Page 1
Service
VP12 /F1S/K1M/N1M/U1M
Manual
VP-12S1
DLP Projector
TABLE OF CONTENTS
SECTION PAG E
1. TECHNICAL SPECIFICATIONS ...................................................................................................1
2. DISASSEMBLE PROCEDURE..................................................................................................... 2
3. ADJUSTMENT PROCEDURE ...................................................................................................... 8
4. UPDATE FIRMWARE AND SUB µ-COM .................................................................................... 16
5. CHECK LIST FOR TROUBLESHOOTING ................................................................................. 24
6. i.LINK .......................................................................................................................................... 28
7. WIRING DIAGRAM ..................................................................................................................... 29
8. BLOCK DIAGRAM ...................................................................................................................... 31
9. PARTS LOCATION...................................................................................................................... 33
10. MICROPROCESSOR AND IC DATA........................................................................................... 43
11. EXPLODED VIEW AND PARTS LIST ......................................................................................... 57
12. ELECTRICAL PARTS LIST......................................................................................................... 61
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
VP-12S1
R
VP-12S1
413V855010 MIT
First Issue 2002.05
Page 2
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components,
Only original
MARANTZ
parts can insure that your
MARANTZ
MARANTZ
product will continue to perform to the specifi cations for which
company has created the ultimate in stereo sound.
it is famous.
Parts for your
MARANTZ
ORDERING PARTS :
equipment are generally available to our National Marantz Subsidiary or Agent.
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specifi ed.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
USA
MARANTZ AMERICA, INC
1100 MAPLEWOOD DRIVE
ITASCA, IL. 60143
USA
PHONE : 630 - 741 - 0300
FAX : 630 - 741 - 0301
AMERICAS
SUPERSCOPE TECHNOLOGIES, INC.
MARANTZ PROFESSIONAL PRODUCTS
2640 WHITE OAK CIRCLE, SUITE A
AURORA, ILLINOIS 60504 USA
PHONE : 630 - 820 - 4800
FAX : 630 - 820 - 8103
EUROPE / TRADING
MARANTZ EUROPE B.V.
P. O. BOX 8744, BUILDING SILVERPOINT
BEEMDSTRAAT 11, 5653 MA EINDHOVEN
THE NETHERLANDS
PHONE : +31 - 40 - 2507844
FAX : +31 - 40 - 2507860
AUSTRALIA
TECHNICAL AUDIO GROUP PTY, LTD
558 DARLING STREET,
BALMAIN, NSW 2041,
AUSTRALIA
PHONE : 61 - 2 - 9810 - 5300
FAX : 61 - 2 - 9810 - 5355
CANADA
LENBROOK INDUSTRIES LIMITED
633 GRANITE COURT,
PICKERING, ONTARIO L1W 3K1
CANADA
PHONE : 905 - 831 - 6333
FAX : 905 - 831 - 6936
HONG KONG
Jolly ProAudio Broadcast Engineering Ltd.
UNIT 2, 10F, WAH HUNG CENTRE,
41 HUNG TO ROAD, KWUN TONG, KLN.,
HONG KONG
PHONE : 852 - 21913660
FAX : 852 - 21913990
AUSTRALIA
QualiFi Pty Ltd,
24 LIONEL ROAD,
MT. WAVERLEY VIC 3149
AUSTRALIA
PHONE : +61 - (0)3 - 9543 - 1522
FAX : +61 - (0)3 - 9543 - 3677
NEW ZEALAND
WILDASH AUDIO SYSTEMS NZ
14 MALVERN ROAD MT ALBERT
AUCKLAND NEW ZEALAND
PHONE : +64 - 9 - 8451958
FAX : +64 - 9 - 8463554
JAPAN
MARANTZ JAPAN, INC.
35- 1, 7- CHOME, SAGAMIONO
SAGAMIHARA - SHI, KANAGAWA
JAPAN 228-8505
PHONE : +81 42 748 1013
FAX : +81 42 741 9190
Technical
THAILAND
MRZ STANDARD CO., LTD
746 - 754 MAHACHAI ROAD.,
WANGBURAPAPIROM, PHRANAKORN,
BANGKOK, 10200 THAILAND
PHONE : +66 - 2 - 222 9181
FAX : +66 - 2 - 224 6795
TAIWAN
PAI- YUING CO., LTD.
6 TH FL NO, 148 SUNG KIANG ROAD,
TAIPEI, 10429, TAIWAN R.O.C.
PHONE : +886 - 2 - 25221304
FAX : +886 - 2 - 25630415
SHOCK, FIRE HAZARD SERVICE TEST :
SINGAPORE
WO KEE HONG DISTRIBUTION PTE LTD
130 JOO SENG ROAD
#03-02 OLIVINE BUILDING
SINGAPORE 368357
PHONE : +65 6858 5535 / +65 6381 8621
FAX : +65 6858 6078
MALAYSIA
WO KEE HONG ELECTRONICS SDN. BHD.
SUITE 8.1, LEVEL 8, MENARA GENESIS,
NO. 33, JALAN SULTAN ISMAIL,
50250 KUALA LUMPUR, MALAYSIA
PHONE : +60 3 - 21457677
FAX : +60 3 - 21458180
KOREA
MK ENTERPRISES LTD.
ROOM 604/605, ELECTRO-OFFICETEL, 16-58,
3GA, HANGANG-RO, YONGSAN-KU, SEOUL
KOREA
PHONE : +822 - 3232 - 155
FAX : +822 - 3232 - 154
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product and
controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied, and
verifi ed before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of diffi culties, do not hesitate to contact the Technical
Department at above mentioned address.
020326MIT
Page 3
1. TECHNICAL SPECIFICATIONS
Optical characteristics
Panel ............................................................... 0.85inch 16:9
........................................................ 1,280 x 720 pixels
....................................... Digital Micromirrory Device
Lamp......................................... Super High Pressure 150 W
Lens..................................................... f: 26.5 to 30.7 / F: 3.0
Projection size .............................................40 to 250 inches
Light output.................................... 700 ANSI LUMEN typical
INPUT/OUTPUT
VIDEO IN..................................................................RCA x 1
............................NTSC-3.58 / PAL-4.43 / SECAM
...................... Composite video 1.0 Vp-p / 75 Ohm
S-VIDEO IN ................................................. S-Connector x 1
.......................NTSC-3.58 / PAL-4.43 / SECAM
............................................................. S-Video
COMPONENT IN......................................................RCA x 3
......................................Y, CB/PB, CR/PR
RGB/HD IN..............................................D-sub M 15 pin x 1
........................................................ Analog RGB
......................................... HD:1080i, 720p, 480p
REMOTE CONTROLLER IN ......................Mini jack type x 1
REMOTE CONTROLLER OUT ..................Mini jack type x 1
AC IN.............................................. 3 Prong Grounding Type
TRIGGER OUT................................................. Mini Jack x 2
.................................Output : DC 12 V or 0 V
RS-232C.................................. RS-232C receptacle plug x 1
AUX. IN ............................. IEEE1394 AV receptacle plug x 1
COAXIAL Digital
AUDIO OUTPUT...........COAXIAL audio data output x 1
OPTICAL Digital
AUDIO OUT .................. OPTICAL audio data output x 1
GENERAL
Power requirement (F).............................AC 100V, 50/60 Hz
(K/N/U)... AC 100-120V / 220-240V, 50/60 Hz
TM
Power consumption ..................................................< 250 W
Standby consumption................................................< 3.3 W
Chassis isolation........................................................Class-1
Safety ....................................................................... UL6500
............................................................... CSA E60065
..................................................................... EN60950
........................................................................ J60065
.................................................................... IEC60950
EMC..................................................... FCC Part-15 Class-B
.......................................................... EN55022 Class-B
........................................................................ EN55024
...............................................................EN61000-3-2,3
Dimensions............................405(W) x 471(D) x 155(H) mm
Net weight..................................................................... 13 kg
Operating Temperature.......................................... 5 to 35 °C
Operating humidity ................................................30 to 85%
Storage Temperature ..........................................-20 to 60 °C
Storage humidity....................................................30 to 85%
Accessories ..................................................... Lens cap x 1
.........................................Remote controller x 1
....................................................... Batteries x 2
...................................................Mains code x 1
................................................... User Guide x 1
........................................ Control Adapter cable
........................................ (Mini jack to RCA) x 1
................................................. Ferrite cores x 2
1
Page 4
2. DISASSEMBLE PROCEDURE
1. Disassemble of the lens ring.
1) Turn the ring (170B) counter clockwise and remove the ring.
2) Remove 3 screws (167B) and remove the focus ring (165B).
3) Remove 3 screws (162B) and remove the zoom ring (160B).
2. Disassemble of the front cover.
1) Remove the cap (154B) with a minus driver, as shown in a
fi gure.
2) Remove 2 screws (152B) and 1 screw (153B) from the front
cover.
3) The front cover is locked by 4 hooks (A to D). The part of
the C, D are strongly pulled to the direction shown and
remove it.
165B
167B
170B
FRONT COVER
150B
160B
162B
162B
167B
Fig.1
A
B
3. Disassemble of the rear panel.
1) Remove 3 screws (120B) from the rear panel.
2) Disconnect 3 connectors (J331, J356 and J357) from rear
panel.
Cautions in disassembling
When removing the rear panel, take care not to damage the
cable for the IR sensor and lights.
Since the IR window(110B) fends to get damaged, the IR
window should not put the IR window downward.
154B
152B
C
D
153B
Fig.2
J357
110B
120B
REAR PANEL
100B
120B
J356
J331
120B
Fig.3
2
Page 5
g
4. Disassemble of the top case.
1) Remove 4 screws (200B), 3 screws (045B) and the screw
(202B) from the top and bottom case.
2) Disconnect the 2 connectors (J334 and J329) from the top
case.
3) Remove the top case (001B) vertically.
Cautions in disassembling
When removing the top case, take care not to damage the
cable for the IR sensor, inside of set the product and key
control.
200B
202B
200B
TOP CASE
001B
J334
J329
045B
045B
045B
200B
5. Disassemble of the bottom case.
1) Remove 2 E-rings (040C) and 2 spring washers (041C).
2) The set is turned over, then turn the lever(arrow A) and
remove the leg (arrow B) vertically.
Cautions
When turning the set over, take care not to damage the
lens shift shaft.
LENS SHIFT SHAFT
LEG
IR SENSOR
B
A
LEVER
200B
Fig.4
040C
041C
Fig.5-1
1) Remove 4 screws. (321G)
321G
321G
321G
321G
.5-2
Fi
3
Page 6
1) Remove 2 screws. (059B)
2) Remove the adjusters (001C) and 4 screws. (045C)
3) Remove the bottom case (050B) vertically.
6. Disassemble of the PCB shield and the duct shield.
(Top case side).
1) Remove 7 screws (217G) and remove the PCB shield
(215G).
2) Remove 2 insulators (338G, 340G).
3) Remove 7 screws (202G) and remove the duct shield
(200G).
001C
050B
217G
338G
045C
215G
Fig.5-3
217G
059B
340G
045C
202G
200G
059B
001C
202G
7. Disassemble of the thermal sensor and lamp bracket.
1) Remove the screw. (308G)
2) Remove the clamp (306G) and remove thermal sensor
(TH02).
3) Remove the 2 screws (180G) and remove lamp bracket
(160G)
202G
Fig.6
308G
202G
306G
SENSOR
TH02
180G
BRACKET LAMP
160G
180G
Fig.7
4
Page 7
g
8. Disassemble of the base of lens.
1) To remove a lens base (UN04), a procedure (Fig.10 -
Fig.13) is required. Because the screw (157G) is hidden by
the duct of the fan for lamp cooling (M703).
2) Remove the 6 screws (157G) and 2 screws (157G), after
the process 1).
3) Remove the 2 screws (153G) for the lamp connector, and
remove the lens base (UN04) vertically.
Cautions
When removing the lens base, please be sure to lift the
lens base main part.
Do NOT touch the lens part.
UN04
LENS BASE
155G
Fig.8
157G
LAMP CASE
150G
157G
155G
153G
9. Disassemble of the POWER SUPPLY UNIT and the
BALLAST UNIT.
1) Remove 6 screws (022G).
2) Disconnect 2 connectors (CN301 and CN300) and remove
the POWER SUPPLY UNIT (UN02).
3) Remove 4 screws (207G) and remove the BALLAST UNIT
(UN01).
Cautions
· When removing the POWER SUPPLY UNIT (UN02),
remove 3 PCBs and the tape adhesion tape that is fi xing
the cables in opposite side main chassis. (See fi g. 12)
Because cables of POWER SUPPLY UNIT (UN02) is fi xed
on opposite side main chassis under the 3 PCBs.
· When removing the BALLAST UNIT (UN01), remove the
lens base before. (See fi g. 8) The lamp connector was fi xed
between the main chassis and the lens base.
POWER SUPPLY UNIT(UN02)
022G
A
CN300
CN301
B
.9
Fi
C
022G
207G
207G
BALLAST UNIT(UN01)
LAMP CONNETOR
D
5
Page 8
10. Disassemble of the shield for PCB of bottom side.
1) Remove 4 screws (311G) and remove the shield(310G) for
PCB.
2) Remove 9 screws (302G) and the shield(300G) for PCB.
11. Disassemble of the FORMATTER PCB and the EXTEND
PCB.
1) Remove 2 screws (135G).
2) Disconnect 3 connectors (J002, J003 and J004) and the
FPC (J005).
3) Remove the FORMATTER PCB (P100) vertically, and
disconnect to EXTEND PCB (P401).
4) Remove 2 screws (133G) and remove the EXTEND PCB
(P401).
311G
310G
302G
FORMATER PCB
133G
P401
EXTEND PCB
P101
135G
Fig.10
J004
302G
302G
300G
J002
J005
J003
Fig.11
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Page 9
12. Disassemble of the SSB2 PCB, the SSB1 PCB and the
IFC PCB.
1) Remove 3 screws (247G) and the screw (250G).
2) Disconnect 2 connectors (A : J321 and J322).
3) Remove the SSB2 PCB (P801) vertically, and disconnect to
SSB1 PCB (P701).
4) Remove the 7 screws (250G).
5) Disconnect the 7 connectors. (B-G : J332, J355, J326,
J325, J341, J342 and J339)
6) Remove the SSB1 PCB (P701) vertically, and disconnect to
IFC PCB (P601).
7) Remove the 6 screws (237G).
8) Disconnect the connector (H : JA01) and remove the IFC
PCB (P601).
250G
247G
SSB2 PCB
B
250G
Fig.12
P801
C
237G
250G
D
250G
A
247G
250G
E
F
P701
SSB1 PCB
G
H
237G
P601
IFC PCB
13. Disassemble of the bracket and the fan for lamp
cooling.
1) Remove 2 screws (232G) and remove the bracket (230G).
2) Remove 3 screws (017G) and the fan for lamp cooling
(M703).
232G
230G
017G
M703
FAN
Fig.13
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3. ADJUSTMENT PROCEDURE
Cases Adjustment is needed
Color Wheel, Bin Voltage Adjustment
When any of P701 PCB Board, Color Wheel, DMD or Engine
is replaced.
Color Temperature Adjustment
When any of P701 PCB Board, Color Wheel, Engine or
Lamp (if needed) is replaced.
Phase Alignment for Color Wheel and Adjusting Bin
Voltage
1. Necessary Equipments
1) PC with the program for adjustment (VPCADJ) installed.
Please copy it from the CD(*VP12S1CDR) to your hard
disk
* VPCADJ is the program to adjust phase(s) of the color
wheel(s) and to set the Bin voltage of DMD.
2) RS-232C cable straight type (9 pin female – 9 pin
female).
3) Luminance Ramp test signal generator (monochrome) .
2. Connections
1) Confi rm that power cord is not connected to VP-12S1.
2) Connect RS-232C terminal on your PC and VP-12S1
with the RS-232C cable.
3) Input the "Luminance Ramp test signal" signal to
VP-12S1’s video input.
* Do not connect the power at this time.
3. Launching the Program and Confi guration
Starting display
* It supposes that shortcut keys for each programs for this
adjustment procedure are set as shown at
below.
1) Launch VPCADJ on the starting display.
Double click VPCADJ
2) Confi gure RS-232C COM Port
* This section is to set the number of the terminal that the
RS-232C cable is connected.
8
Page 11
Call the "RS-232C Settings" window from the select
menu shown at
Put the cursor on Setting.
Click RS-232C Setting.
below.
* This "RS-232C Settings" window is to set the 2 COM
Ports shown below.
1. Luminosity data input port. (Port number for CL-200)
This port is for data input from
Chroma meter for color
temperature adjustment. This port
is not used in this adjustment.
* Select a port number other than the
number used in the next step 2.
2. Control data output port. (Port number for VP-12S1)
This is the port No. of the RC-232C terminal for output
to VP-12S1. Select the COM Port No. of the RS-232C
terminal that is connected to VP-12S1.
Click OK
3) Select Color Wheel Adjustment Program
Select "Color Wheel Adj." from Tool menu.
Put the cursor on Tool.
Click Color Wheel Adj.
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4) Connect power cord to VP-12S1.
* Do NOT turn Power ON.
4. Start Adjustment
1) Click "Adj. Start" to start adjustment.
* Upon this start, VP-12S1 turns on automatically.
Click Adj. Start
*
VP-12S1 turns on power automatically at this moment.
* If VP-12S1 is not turned on after 20 to 30 seconds, click
Exit to terminate the program, disconnect power cord
and do this procedure from 3 - 2) again.
(Confi rm that COM Port number is set correctly.)
2) When the lamp lights on, set VP-12S1’s input to "Video",
and project the "Lamp wave form".
3) Set Bin Voltage.
1. Bin voltage is the reference voltage supplied to DMD
and there are different values for each DMD. The value
is marked at the location shown in the picture at below.
(Remove the top cover of the set to see it.)
2. If "B" is marked in the picture below, click this "B".
4) Color Wheel Phase Adjustment
This is to adjust phase of color of the color wheel and
timing of the mirror on/off of DMD. If the phases are not
coherent, vertical color stripes appear in the all tone
monochrome screen as shown in the pictures below.
A wheel mouse is recommended to use when the color
wheel phase adjustment
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Phases are coherent
Phases are not coherent
* To adjust the phases, set the value at middle of A and B
with seeing the PROJECTED IMAGE.
Color stripes appear Color stripes appear
Cyan magenta
Middle
Minimum value : A B : Maximum value
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1. Seek the maximum value B when color stripes appear
by clicking shown in the picture above.
2. Likewise seek the minimum value A when color stripes
appear by clicking .
This value changes upon clicking the keys.
Click this key to seek max B.
Click this key to seek min A.
3. Set the value at the middle of A and B with and .
5. Finish Adjustment
1) Click Adj. Finish and then click Exit.
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The display returns to the starting display.
2) Click Exit to terminate VPCADJ program.
3) Turn off power.
4) After VP-12S1 is turning into standby mode, disconnect
power cord from VP-12S.
5) Disconnect the RS-232C cable from VP-12S1.
All the adjustment procedure is completed.
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Color Temperature Adjustment Procedure
1. Necessary Equipments
1) PC with the program for adjustment (VPCADJ) installed.
Please copy it from the CD(*VP12S1CDR) to your hard
disk
2) RS-232C cable straight type (9 pin female – 9 pin
female).
3) 100% white signal in 525i(480i) format.
4) Minolta CL-200 Color Luminosity Meter.
5) LAN cable (In case that the cable with CL-200 is not
long enough).
2. Connection
1) Confi rm that power cord is not connected to
VP-12S1.
2) Confi rm that Minolta CL-200 Chroma Meter is
power off.
3) Connect CL-200 and your PC(RS-232C terminal)
with the CL-200’s cable.
4) Connect RS-232C terminal on your PC and
VP-12S1 with the RS-232C cable.
5) Input "100% white signal" to VP-12S1’s component
input.
* Do not connect power cord at this time.
3. Launching the Program and Confi guration
Starting display
* It supposes that shortcut keys for each programs for this
adjustment procedure are set as shown at below.
1) Launch VPCADJ on the starting display.
Double click VPCADJ
2) Confi gure RS-232C COM Port
* This section is to set the number of the terminal that the
RS-232C cable is connected.
CL200
LAN cable
13
Page 16
Call the "RS-232C Settings" window from the select
menu shown at below.
Put the cursor on Setting.
Click RS-232C Setting.
* This "RS-232C Settings" window is to set the 2 COM
Ports shown below.
1. Luminosity data input port. (Port number for CL-200)
This port is for data input from
Chroma meter for color
temperature adjustment.
* Select a port number other than the
number used in the next step 2.
2. Control data output port. (Port number for VP-12S1)
This is the port No. of the RC-232C terminal for output
to VP-12S1. Select the COM Port No. of the RS-232C
terminal that is connected to VP-12S1.
Click OK
4. Setting CL-200
1) Set CL-200 at the center of the project screen.
2) Remove the cap covering the light sensor of CL-200.
3) Set the direction of CL-200’s light sensor towards the
lens.
4) Give enough light to CL-200. Turning on power of
CL-200 with the cap on or in the darkness, CL-200 will
not work properly.
5) Turn on power of CL-200. Using AC adopter is recom-
mended rather than battery.
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Page 17
5. Start Adjustment
1) Connect power cord to VP-12S1.
Start adjustment more than 5 minutes after when the
lamp is lit on.
This adjustment must be done after the color wheel
adjustment.
2) Click Start button to start adjustment.
Click this to start adjustment
3) Be aware not to move CL-200 while adjustment.
4) If adjustment is terminated abnormally, "Adjustment was
not completed." warning dialogue appears.
5) If adjustment is completed successfully, "Color Temp
Adjustment Complete." dialogue appears.
6) After the adjustment, each measured color temperature
for Low, Mid and High will be displayed on the program
window.
7) Click "Exit" button to terminate VPCADJ program.
Click this to terminate VPCADJ.
6. Finish Adjustment
1) After all adjustment is done, press Standby key to turn
off "Soft Power".
2) After VP-12S1 is turning into standby mode, disconnect
power cord from VP-12S.
3) Disconnect RS-232C cable from VP-12S1.
4) Turn off power of CL-200.
5) Disconnect RS-232C cable from CL-200.
All the adjustment procedure is completed.
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Page 18
4. UPDATE FIRMWARE AND SUB µ-Com
PW365 Firmware Upload Procedure
1. Preparation
Copy FlashUpgradeNT.exe from the CD to your hard disk.
(CD : *VP12S1CDR)
Example: C:\VP-12S1\ FlashUpgraderNT.exe
Copy the fi les to upload to your hard disk.
Example : C:\VP-12S1\pwSDk.inf
C:\VP-12S1\confi gdata.hex
C:\VP-12S1\fl ash.hex
C:\VP-12S1\romcode.hex
C:\VP-12S1\gui.hex
2. Connection
Confi rm that power cable is not connected to VP-12S1.
Connect J333 on P701 PCB (VP-12S1) and RS-232C
terminal on your PC with the specialized RS-232C
cable(reset button) that is designed for this task.
Connect power cable to VP-12S1.
3. Entering Writing Mode
Send "Debug" command (RC-5, System:01,
Command:63, Ext:63) to VP-12S1 with a leaning
remote control. All LED (POWER ON , STANDBY and
WARNING) will light up to show it is in the writing mode.
4. Launch the Upload Program
Launch FlashUpgraderNT.exe.
Start display
Select the port the RS-232C cable is connected with in
the COM Port menu.
Set Baud Rate to 115,200 bps.
Click Choose button to select the fi le to be uploaded.
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Page 19
5. Selecting fi le
Select the folder that has the defi ne fi le. Then select
"pwSKD.inf" fi le.
Example: C:\VP-12S1\pwSKD.inf
Click Open button to load the defi ne fi le.
6. Finish Confi guration
Click Flash button to start uploading.
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Page 20
7. Start Uploading
Press the reset button on the specialized RS-232C cable.
8. Uploading
The progress bar is displayed on the right bottom side.
The bar grows upon the progress.
The following 4 fi les will be uploaded continuously.
1. fl ash.hex
2. gui.hex
3. confi gdata.hex
4. romcode.hex
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Page 21
The uploading-completed fi les are displayed reversed in
the window.
9. Uploading Completed
Uploading takes about 1 minute 52 seconds.
When uploading is completed, display returns to just
before uploading started.
Click Close button to terminate the up-grader program.
Press Standby key to turn off the soft power (VP-12S1).
After turning off the soft power, disconnect power cord
from VP-12S1.
Disconnect the RS-232C cable from VP-12S1.
The upload procedure is completed.
To upload to more than two units, you can skip step 3 and 4
for the units second and after.
19
Page 22
Sub µ-Com Writing Procedure
1. Preparation
1) PC with the writing program (VP Write.exe) installed.
Please copy it from the CD(*VP12S1CDR) to your hard
disk
2) RS-232C cable straight type (9 pin female – 9 pin
female)
3) Copy Vp12_frm.mot to the hard disk.
Ex. C:\VP-12S1\H8\VPWriter\Vp12_frm.mot
2. Connection
1) Confi rm that power cord is not connected to VP-12S1.
2) Connect RS-232C terminal on your PC and VP-12S1
with the RS-232C straight cable as shown in the picture
below.
RS-232C cable (straight)
3) Connect power cord to VP-12S1.
* Writing to the sub micro computer is done in standby
mode.
3. Confi guration / Writing
1) Launch VPWrite.exe among the programs shown at
below.
Double click
2) In the starting display shown at above, select the same
COM Port number that the RS-232C cable is connected.
20
Page 23
Start display
Mark the COM Port number
3) Then, click Browse to select the fi le to be written to
the micro computer.
Ex. C:\VP-12S1\H8\VPWriter\Vp12_frm.mot
4) Select the fi le "Vp12_frm.mot".
Click Vp12_frm.mot
Click Open
5) Start writing.
Click Start
Caution:
* Do not disconnect power cord while writing.
(Writing a wrong fi le does not erase the core program
in the set so you can write again. But disconnecting
power while writing can crush the core program. )
* If "Error" is displayed, disconnect the power once
and retry the procedure from the beginning. ( If the
fi rmware program in the sub µ-com is broken due to a
writing failure, STANDBY LED and POWER ON LED
fl ash each other. But there is no problem to write the
program again. )
* POWER ON LED fl ashes fast while writing.
* Writing takes about 1minute 45 seconds.
21
Page 24
6) Writing fi nished.
When writing fi nishes, "Flash Write Success" message
is displayed as shown at below.
Click OK.
7) Display returns to the same display at 4).
* If you want to write to another set, connect RS-232C
cable to the set and click Start button.
* To terminate the program, click Exit.
4. Finish Writing Procedure
1) Disconnect power cord from VP-12S1.
2) Confi rm that all LEDs are not light.
3) Disconnect the RS-232C cable from VP-12S1.
All the fi rmware writing procedure is completed.
22
Page 25
NOTE :
23
Page 26
5. CHECK LIST FOR TROUBLESHOOTING
Symptom Condition check Check Parts and Components
No Power
(Lamp
doesn’t light)
STANDBY LED
lights
Blue POWER ON
LED stays lit
WARNING LED
lights
No LED No power supplied to P903 (Key input PCB) ->J399(P701), J329(P903),
Remote control doesn't work ->P701(Small Signal PCB)
Key input doesn't work ->P903 (Key Input PCB)
->P701(Small Signal PCB),
W014(VSS)cable
Lamp on signal is not output from P701 to P101 ->J324 output connector, W003(VFM)
Lamp on signal is not output in P101 ->P101 (DMD drive PCB)
Color wheel does not rotate ->Color wheel body, W002(VFM)
WARNING LED lights upon power on ->UN02(power unit) temperature high
(Lamp door & high temperature error) ->Lamp temperature high
WARNING LED
lights several seconds after power on
P903 (Key input PCB) malfunction ->P903 (Key Input PCB)
UN01(Balast PCB) malfunction ->UN02(power unit)
Lamp on signal is not
output from P701 to
UN01(Balast PCB)
Lamp circuit malfunction ->Lamp socket out of place
cable
->P701(Small Signal PCB)
cable snap
->P701(Small Signal PCB)
->J325(P701)
->J2(UN01)
->Lamp body
->UN01(Balast PCB)
W014(cable)
Symptom Condition check Check Parts and Components
No Picture No picture for all inputs P701 (Small signal PCB)
P801 (Small signal PCB)
P503 (Input PCB - MAIN)
P501 (Input PCB - SUB)
Bad Picture No picture only for FOCUS and MENU P701 (Small signal PCB)
No picture only for AUX input P601
Vartial stripes on picture P301 (DMD PCB)
P401 (Relay PCB)
P101 (DMD drive PCB)
Picture is green P701 (Small signal PCB)
Block noise for AUX input P601(IEEE-1394 PCB)
Color changes partially (All inputs) P701, W001 (fl exible wire)
Picture disturbed (Picture comes and goes) Low AC power Voltage (Under 90V)
Picture trembles vartically in 480P input P801 (Small signal PCB)
Grid pattern appears on picture (all inputs) P701 (Small signal PCB)
Outline of picture is noisy Color wheel (adjust)
Abnormal color P701 (Small signal PCB)
P101 (DMD drive PCB)
Color wheel (adjust)
Picture fl ickers (luminosity varies) Bad lamp
24
Page 27
Condition check Check point PCB etc Cause
Vartial stripes on picture P301 Bad contact on J013, J014
P401 Bad contact on J011, J012
P101 Bad contact on J009
Lamp doesn't light (Warnig fl ashes) UN01 Balast PCB(UN02) malfunction
Lamp doesn't light (Warnig doesn’t fl ash) P701 Light-on signal is not output to P101
Green picture P701
Block noise on AUX input P601
No picture (sound) for AUX input P601, P501, P503,
No picture for inputs except AUX P701, P801, P502, P503,
Color changes partially (All inputs) P701, W001(VFM)
Key input doesn't work P903, W014(VSS), P701
Remote control doesn't work P903, W015(VIR),
Fan doesn't rotate P201, W022(VOT), FAN
Door error P201, W019(VOT), S701
Temperature error Bad TH02(Sensor),
Picture disturbed (Picture comes and goes) AC power voltage is lower than 80V
Picture trembles vartically in 480P input P801 Check software version (main Ver.1.17 or later)
Color wheel doesn't rotate P701, P601 ASIC NG
Grid pattern appears on picture (all inputs) P701 Bad ICA2
No picture for progressive and RGB inputs P701 Bad IC88
Troubled picture on CVBS(NTSC) P701 Bad IC73
No picture for CVBS & S-Video inputs P701
No picture
Outline of picture is noisy Color wheel Bad color wheel adjustment
Abnormal color P701, P101 Bad color wheel adjustment
Picture fl ickers (luminosity varies) Bad lamp
W002(VDV), W008(VDV)
W009(VSS), W011(VSS)
Bad J339
W016(VIR), S301
not pressed
AC power voltage is lower than 90V
UN02(IC??)
and replace ICG7 to new version
P101 NG
Color wheel, W002(VFM) Bad contact on fl exible wire (W002)
P801 Bad IC88 or ICF2
25
Page 28
5. CHECK LIST FOR TROUBLESHOOTING
26
Page 29
27
Page 30
6. i.LINK
i.LINKTM is the trademark for the world standard IEEE1394 digital transfer protocol. It is a high-speed, high volume wired
network system, capable of transferring all types of digital data among practically all types of digital products. With i.LINK,
you can create a network of interconnected audio/visual products, VAIO computers and peripherals, all sharing movies,
music, photographs, text and control signals back and forth freely and easily.
i.LINK Advantages
Easy to Handle Cable
Data fl ows both ways in an i.LINK network, and one type of cable handles audio, video, text and every other type of digital
data. No more tangled web of cables featured by most other A/V and computer products.
Plug & Play
Setting up an i.LINK network is as easy as plugging in cables: no drivers, controllers or installers are needed.
High Speed
An i.LINK network can send data signals at speeds of 100, 200 and 400Mbps, with even higher speeds planned for the
future. This high speed interface makes i.LINK the ideal interface for 30Mbps Digital Video signals.
Real Time Transfer
i.LINK's special data transfer feature makes it possible to transmit and receive time-critical data such as video and audio
signals in real time, with no time lag.
Secure Network
i.LINK uses copy protection technology licensed by DTLA (The Digital Transmission Licensing Administrator), making it
possible to handle a wide variety of digital video and audio signals while safeguarding copyrights.
The i.LINK Connection
The number of digital products with an i.LINK terminal has already started to grow considerably. Soon it will be possible
to interface practically every digital product in the home, in an integrated Home Network. All devices will recognize one
another and communicate freely (seamless products). Additionally, all content on the network can be accessed from any
product, (seamless content), and the entire network can be controlled from any node, or from a remote location (seamless
environment).
"i.LINK" Logo
is a trademark.
28
Page 31
7. WIRING DIAGRAM
FAN
IN
FAN
CW
FAN
S
FAN
DMD
M701
VOT-W022
/
3
M702
/
3
M703
/
3
M701
/
3
J348J346J347J345J349
P201
FAN CTL
VSS-W017
J344
VFM-W002
J016J350J351
8
VOT-W019
2
VOT-W018
2
VFM-W005
J015
VPS-W007
J343J2
035G
/
CW
COLOR WHEEL
/
TH02
/
TH-PR
/
3
P202
J701
DOOR SW
/
4
/
12
P301
DMD
J013 J014
B to BB to B
J011 J012
P401
EXTEND
J010
B to B
J009
J004
P101
FORMATTER
J003J005
30
50
5
/
/
/
12
VFM-W003
VFM-W001
VSS-W013
VPS-W006
/
P903
KEY
J341
J323 J324
J332 J355
J329
13
VSS-W014
J339
P701
SSB1
VIR-W015
J334J335J358
VIR-W016
VOT-W025
/
6
J326
J353
J400
3
B to B
B to B
/
3
/
/
3
J330
J331
/
J356
3
J357
/
3
CW-SENSOR
P901 IR-F
P902 IR-R
P905 LIGHT
P906 LIGHT
P601
IFC
IEEE1394
JA06
P801
SSB2
J401
UN03
LAMP UNIT
2
UN01
BALLAST UNIT
P904
AC INLET
VSS-W020
VPS-W023
/
J1JB01
2
VOT-W024
/
2
DN306
DN300 DN301
J002
10
/
4
VPS-W004
DN304
UN02
POWER SUPPLY UNIT
J342J325
14 15 12 15 6
VSS-W012
VSS-W011
J313 J314J316
J321J322
VSS-W009
JA02
VDV-W008
J320
JA01
P503
I/O 3
DN303DN305
B to B
J408 J409J410
P502
I/O 2
B to B
P501
I/O 1
VDV-W002
29 30
Page 32
8. BLOCK DIAGRAM
USB
IR SENSOR
IR SENSOR
CLK_1394
YG/CB/CRIEE
HSYNC
VSYNC
FIELD
FAN1ON
FAN2ON
FAN3ON
FAN4ON
TEMP_MES
74HCT04AF
INVERTER
V
ST24FC21
DDC EEPROM
SWITCH
NJM2370
REGULATOR
REGULATOR
NJM2370
BA00ASFP
BA00ASFP
BA00ASFP
BA00ASFP
TC7S02FU
OR
H_VGA
V_VGA
R FROM VGA
D+
D-
TXD
RTS
RXD
CTS
LAMPLIT
TRIGO
R FROM VGA
D+
D-
TXD
RTS RTS_232C
RXD
CTS
FAN
FAN
FAN
FAN
THERMISTOR
ATT
ATT
CB FROM COMP
G FROM VGA
CB FROM COMPCB FROM COMP
CR FROM COMP
G FROM VGA
B FROM VGA
CR FROM COMP
B FROM VGA
G FROM VGA
I2C
LPF
LPF
LPF
LPF
A0_AMP
AD9884A
OPA2680
ELC4093C
CLAMPING
AMP.
ELC4093C
CLAMPING
AMP.
ELC4093C
CLAMPING
AMP.
VCKOUT
ICS551M
I2C
BA7046
SYNC
SEP.
SAA7118E
GRE/GGE/GBE/GRO/GGO/GBO
GCLK
GPEN
GVS
GHS
GSOG
GFBK
GREF
GBLKSPL
GCOAST
GHSFOUT
OPA2680
CVBS
1/2 2/2
ATT
Y FROM S
Y FROM 3D
AD8174
Y FROM COMPY FROM COMP
C FROM S
C FROM 3D
AD8174
AD8174
A1_AMP
Y FROM S
C FROM S
CVBS
ATT
ATT
ATT
OPA2680
1/2
OPA2680
1/2
2/2
OPA2680
I2C
USB_D USB_D8
USBN9604
USB
TXD_232C
uPD4721
RXD_232C RXD_232C
RS232
CTS_232C
TC4W14FU
NOT
TC4W53FU
2FH/1FH_SEL
SECAMZ
C_B_SEL
T2241628-35
uPD64082G
ADS825
ADC
OPA2353
ADS825
ADC
OPA2680
1/2
ADS825
ADC
OPA2680
2/2
8
SECAMZ
8
SECAMZ
8
SECAMZ
VHS
VVS
LPF
F
LPF
CLAMP LEVEL CLAMP PLUSE
74HC4053A
SN74LVTH
541
SN74LVTH
541
SN74LVTH
541
CRDAT
CBDAT
YGDAT
CK_SECAM
TO POWER SUPPLY
OPA2680
1/2
2/2
OPA2680
CK_GRP
CK_1394
OPA2680
1/2
3D/CVBS_SEL
74HC4053
CKIFRA
YGDAT
CBDAT
CRDAT
VCKOUT
TO JTAG
EPROM
SN74CBT
LV3253
EL4581
SYNC
SEP.
T_SHUT
PWR_SHUT
PWR_CTRL
CKSWS0
CKSWS1
OSC
10
10
10
C.SYNC
MAX913 MAX913
FLI2000
20
SN74LV14A
Y/C_CMS
HIFRA
VIFRA
S-814A25
AMC
2.5VReg
BA033FP
3.3VReg
PQ05DZ11
5VReg
MM1385AN
5VReg
TK72150
-5VReg
BA033FP
3.3VReg
I2C
HIFRA
H_VGA
CSYN C
VHS
VIFRA
V_VGA
VHS
/RESET_FE
OTR/YC_SEL
3D/CVBS_SEL
SYNCSEL1
CLK
74HC4052
SYNCSEL0
Y/CB/CRCNP
SW
30
CKOOTR
Y/CB/CRCNP
SDRAM
HOFRB
C_B_SEL
SN74CBT
LV1G125
XC2S150_5F6456C
HPOLZ
VPOLZVPOLZ
CLPFPGAZCLPFPGAZ
CSYNCGAZ
HPOLZ
H
M52347FP
V
+13V
+2.5V DIGITAL
+3.3V DIGITAL
+2.5V ANALOG
+3.3V ANALOG
+5.0V ANALOG
+5.0V ANALOG
-5.0V ANALOG
+3.3V STANDBY
+5.0V STANDBY
2FH/1FH_SEL
SN74AHC
FLI2200 FLI2220
VOFRB
30
YG/CB/CRIEE
1G04
NOT
HIFRB
HSYNC
VIFRB
VSYNC
FIELD
I2C
/RESET_FE
S-80828
ANUP
TEMP_ERR
DOOR_ERR
FAN_ERR
T_SHUT
PWR_SHUT
PWR_CTRL
HREF
VREF
RESET
TXD_232C
RTS_232C
CTS_232C
RC5
CLK
2FH/1FH_SEL
30
Y/CB/CRPRG
SN74CBT
LV1G125
SW
CKO2FH
Y/CB/CRPRG
RST_FPGA
PRG_FPGA
DONEFPGADONEFPGA
RST_FPGA
PRG_FPGA
HD64F3067RVF
ICSSCL
ICSDATA
VFLDO
HOFRC
ICSSTM
ICSSTD
VOFRC
VIFRC
HIFRC
PW_RESET
PW_SHUT
PW_STATE
RXD_PW
TXD_PW
KEY0
KEY1
KEY2
LED_POW
LED_STD
LED_WAN
FAN1ON
FAN2ON
FAN3ON
FAN4ON
TEMP_MES
FWE
MODE 1
TXD
RXD
I2C
MCLK
I2C
/RESET_FE
R/G/BFR
30
CK_REF
R_PW
8
G_PW
8
8
VCK_PW
H_PW_R
V_PW_R
VPEN
CSYNCUPZ
GRE/GGE/GBE/GRO/GGO/GBO
GCLK
GPEN
GVS
GHS
GSOG
GFBK
GREF
GBLKSPL
GCOAST
GHSFOUT
ICSSCL
ICSDATA
ICSSTD
ICSSCL
ICSDATA
ICSSTM
SN74LV14A
TO FAN
RESET
TO WRITER
SN74LVTH
541
SN74LVTH
541
SN74LVTH
541R_PW
SN74LVTH
541
MBM29LV
800TA
FLASH
SRAM
PROMJET
ICS307
ICS307
NOT
PCF8574T
R_PW
8
88G_PW
R_PW
VCK_PW
H_PW_R
V_PW_R
VPEN
FPGA_DAT
FPGA_CLK
FPGA_ENA
48
DCKEXT
MCKEXT
PW_NMI
TC7S00FU
C_B_SEL
2FH/1FH_SEL
NOT IN USE
A1_AMP
A0_AMP
SYNCSEL1
SYNCSEL0
3D/CVBS_SEL
PW365
PW_RESET
PW_SHUT
RXD_PW
PW_STATE
&
KEY0
KEY1
KEY2
LED_POW
LED_STD
LED_WAN
TXD_PW
OR
10
DRE
10
DGE
10
DBE
TO FORMATTER
PIXCLK
VSYNCZ
HSYNC Z
ACTDATA
SN74LVC
10A
NAND
LAMPEN
LAMPLIT
RESETZ
CWINDEX
LAMPSYNC
LAMPFLAG
CWINDEX
LEDLED LED
TO FORMATTER
TO LAMP PS
FROM CW SENSOR
AT24C
128N-2.7
E2PROM
BSN
20
BSN
20
TC7SET08FU
&
CKSWS1
CKSWS0
SECAMZ
TRIGO
/RESET_FE
I2C
TO JTAG
TO WRITER
PWRGOOD
I2C_DATA
I2C_CLK
PW_TDO
PW_TMS
PW_TDI
PW_TCK
RESET
RESET
RXD_PW
TXD_PW
LED
LED
LED
LED
3231
Page 33
9. PARTS LOCATION
P601
ICM1
ICN9
ICN1
ICM2
ICO0
ICN2 ICN5 ICN8 ICN7 ICN6
IC01
IC02
ICM8 ICM7 ICM6
ICM4 ICM5
P903
P601
IC03
IC05
ICM9
ICM03 ICM04
33 34
Page 34
P701
ICC9
ICE0
IC81
IC80
IC77
IC83
IC87
CC86 Q3L2
IC85
ICF4
ICF2
ICF4
IC92
ICE2
IC96
IC88
ICH3
ICG6
ICC6 ICK6 ICK5
ICG7
ICA2
ICH0 ICH1
ICE5 ICE8
Q997 Q998
ICA4 ICG3
ICE4
ICA1
ICE6
ICH5 ICH4
P401
P701
ICH6 Q4N3 Q4N4
ICE9
ICF0
ICG4
ICA6
ICA5
Q6Y2 Q6Y1
Q4M2 A4M1 Q4N2 Q4N2
ICA3
ICH2
ICG9
ICE3
ICC8
IC90 IC89 ICE1
IC95 Q441
IC91
IC94
IC93
IC97
IC98
ICC2
ICF3
IC84
Q3L1 IC78
IC82
P401
3635
Page 35
P801
Q703 Q705 - Q707
ICC5
Q701 Q702
Q712 - Q714
IC67 IC66
IC65 IC68
IC69
ICG1
ICF8
IC74
ICF5
ICF9
IC73
ICG2
IC70
ICF6
ICF7
Q601 Q602
Q393 - Q395
Q391
IC75 IC76
Q392
ICG0
IC72
IC71
P301
P801
P301
37 38
Page 36
P101
Q503
IC25
Q506
IC29
IC06
Q508
IC31
IC01
IC23
Q509
Q512 Q513
IC02 IC08
IC13
IC24
IC03
IC14
IC16 IC19
IC26
IC32
IC17
IC22
IC07
IC12
Q505 Q511
IC04 IC09
Q505
Q510 IC27
IC15
IC05
Q500 Q501
Q502
IC11
IC20 IC21
IC28
IC18
P101
IC50 IC51 IC53
IC55 - IC57
4039
Page 37
P904
P902 P902
P904
P202
P905
P906
P501
P905 Q4W4
P906
Q4W5
P502
Q301
Q302
41
Page 38
P201
P503
Q801 ICJ1
Q802
Q804 ICJ2
Q803
Q807 ICJ4
Q808
Q805 ICJ3
Q806
Q810 ICJ5
Q809
P901
P901
P503
IC61
IC62
Q303 - Q306
42
Page 39
10. MICROPROCESSOR AND IC DATA
ICM6 : P89C51RD2 (LQFP44:plastic low profi le quad fl at package:44 leads)
PIN NO. PORT NAME SYMBOL TYPE FUNCTION
1 P1.5/CEX2 LED_2 I/O Interrupt indicator of frame
2 P1.6/CEX3 I2C_SCL I/O I2C serial clock
3 P1.7/CEX4 I2C_SDA I/O I2C serial data
4 RST I RESET HI=reset
5 P3.0/RxD RXD I INPUT UART
6 NIC No Internal Connection
7 P3.1/TxD TXD O OUTPUT UART
8 P3.2/~INT0 PINT0# I Interrupt FPGA
9 P3.3/~INT1 LINK_INT# I Interrupt 1394LINK
10 P3.4/T0 VID__HS I INPUT NW700 VID_HS
11 P3.5/T1 CONFPGA O OUTPUT FPGA CONF
12 P3.6/~WR PWR# O Write strove output for external memory
13 P3.7/~RD PRD# O Read strove output for external memory
14 XTAL2 O 11.0592MHz
15 XTAL1 I
16 Vss I Ground: 0 V reference.
17 NIC No Internal Connection
18 P2.0/A8 PA8 I/O Address Port (A15 - A8)
19 P2.1/A9 PA9
20 P2.2/A10 PA10
21 P2.3/A11 PA11
22 P2.4/A12 PA12
23 P2.5/A13 PA13
24 P2.6/A14 PA14
25 P2.7/A15 PA15
26 ~PSEN PSEN# O Program Store Enable HI=Programing
27 ALE/~PROG PALE O Output address latch for external memory
28 NIC No Internal Connection
29 ~EA/Vpp I External Access Enable/Programming Supply Voltage
30 P0.7/AD7 PAD7 I/O Address Port (A7 - A0)
31 P0.6/AD6 PAD6
32 P0.5/AD5 PAD5
33 P0.4/AD4 PAD4
34 P0.3/AD3 PAD3
35 P0.2/AD2 PAD2
36 P0.1/AD1 PAD1
37 P0.0/AD0 PAD0
38 Vcc I Power Supply: This is the power supply voltage for
39 NIC No Internal Connection
40 P1.0/T2 FPGADATA I/O FPGA (Data port)
41 P1.1/T2EX FPGACLK I/O FPGA (Clock port)
42 P1.2/ECI STATUS I/O FPGA (Status port)
43 P1.3/CEX0 1394_RST I/O Output Reset for 1394PHY/LINK
44 P1.4/CEX1 LED_1 I/O Main Processing Indicator
Data Port (D7 - D0)
normal, idle, and power-down operation.
43
Page 40
ICE4 : PW365-20U (352 PBGA)
Pin Description
Pin Description I/O Signal PU/PD Active Initial
A1 VSS - GND - - A2 PORTA6 O TRIG0 - H L
A3 PORTA7 O PW_STATE - H L
A4 PORTB3 O CKSWS0 - - H
A5 PORTB6 O RESET_Z - L L
A6 PORTC0 I LAMPEN - H L
A7 PORTC4 O DGE[8] - - A8 MODE1 I MODE1(+3.3V) - - -
A9 VR0 I R_PW[0] - - A10 VR2 I R_PW[2] - - A11 VR6 I R_PW[6] - - A12 VG2 I G_PW[2] - - A13 VG4 I G_PW[4] - - A14 VB0 I B_PW[0] - - A15 VB4 I B_PW[4] - - A16 VB7 I B_PW[7] - - A17 VSS - GND - - A18 VSS - GND - - A19 VSS - GND - - A20 VDD25 - +2.5V - - A21 VLAV I H_PW_V - - A22 VHS I H_PW_V - - A23 GBO3 I GBO[3] - - A24 GBO7 I GBO[7] - - A25 VDD25 - +2.5V - - A26 GBE1 I GBE[1] - - -
B1 PORTA2 O FPGA_DAT PD - -
B2 PORTA3 O FPGA_CLK - - -
B3 PORTA5 I IE3_RST PD H L
B4 PORTB2 O CKSWS1 - - H
B5 PORTB5 I LAMPFLAG - H L
B6 PORTB7 O PWRGOOD - H L
B7 PORTC3 O DBE[9] - - -
B8 PORTC5 O DGE[9] - - -
B9 CPUTCLK I PW_TCLK - - B10 VR1 I R_PW[1] - - B11 VR5 I R_PW[5] - - B12 VG1 I G_PW[1] - - B13 VG3 I G_PW[3] - - B14 VG7 I G_PW[7] - - B15 VB3 I B_PW[3] - - B16 VCLK I VCK_PW PU/PD - B17 CPUTMS I PW_TMS - - B18 VPEN I VPEN - - B19 VSS - GND - - B20 VSS - GND - - B21 VVS I V_PW_V - - B22 GBO1 I GBO[1] - - B23 GBO4 I GBO[4] - - B24 VSS - GND - - B25 GBE0 I GBE[0] - - B26 GBE5 I GBE[5] - - -
C1 PORTA0 I/O SDA_I2C PU - C2 PORTA1 I/O SCL_I2C PU - C3 VDD33 - +3.3V - - C4 VDD25 - +2.5V - - C5 PORTB0 O /RST_FE - L L
C6 PORTB4 O SYNCVAL PD H L
C7 VDD25 - +2.5V - - C8 PORTC2 O DBE[8] - - -
C9 PORTC7 O DRE[9] - - C10 VDD25 - +2.5V - - C11 VR4 I R_PW[4] - - C12 VG0 I G_PW[0] - - C13 VDD33 - +3.3V - - -
C14 VG6 I G_PW[6] - - C15 VB2 I B_PW[2] - - C16 VB6 I B_PW[6] - - C17 VDD25 - +2.5V - - C18 VDD25 - +2.5V - - C19 VDD25 - +2.5V - - C20 VDD25 - +2.5V - - C21 VFIELD I VFLD_PW - - C22 GBO2 I GBO[2] - - C23 GBO6 I GBO[6] - - C24 VDD33 - +3.3V - - C25 GBE4 I GBE[4] - - C26 GBE6 I GBE[6] - - -
D1 RXD I RXD_PW PU - D2 TXD O TXD_PW PU - D3 VSS - GND - - D4 VSS - GND - - D5 PORTA4 O FPGA_ENA - H L
D6 PORTB1 I/O SECAMZ - L H
D7 VSS - GND - - D8 PORTC1 I LAMPLIT -
D9 PORTC6 O DRE[8] - - D10 VSS - GND - - D11 VR3 I R_PW[3] - - D12 VR7 I R_PW[7] - - D13 VSS - GND - - D14 VG5 I G_PW[5] - - D15 VB1 I B_PW[1] - - D16 VB5 I B_PW[5] - - D17 VSS - GND - - D18 VDD25 - +2.5V - - D19 VDD25 - +2.5V - - D20 VSS - GND - - D21 GBO0 I GBO[0] - - D22 GBO5 I GBO[5] - - D23 VSS - GND - - D24 GBE2 I GBE[2] - - D25 GGO1 I GGO[1] - - D26 GGO2 I GGO[2] - - -
E1 RESET I RESET - H H
E2 IRRCVR1 I (N.C.) - - E3 IRRCVR0 I (N.C.) - - -
E4 MODE0 I MODE0(+3.3V) - - E23 GBE3 I GBE[3] - - E24 GBE7 I GBE[7] - - E25 GGO4 I GGO[4] - - E26 GGO5 I GGO[5] - - -
F1 NMI I PW_NMI - H L
F2 CPUEN I +3.3V - - -
F3 UCSRC I +3.3V - - -
F4 WDTEN I +3.3V - - F23 GGO0 I GGO[0] - - F24 GGO3 I GGO[3] - - F25 GGO6 I GGO[6] - - F26 GGO7 I GGO[7] - - -
G1 EXTINT1 I/O GND PD - G2 EXTINT0 I PW_SHUT - H L
G3 VDD25 - +2.5V - - -
G4 VSS - GND - - G23 VSS - GND - - G24 VDD25 - +2.5V - - G25 VDD33 - +3.3V - - G26 GGE1 I GGE[1] - - -
H1 EXTINT2 I/O GND PD - -
H2 D1 I/O PW_D[1] - - -
H3 D0 I/O PW_D[0] - - -
H4 VCC33 +3.3V - - H23 GGE0 I GGE[0] - - -
44
Page 41
H24 VSS - GND - - H25 GGE2 I GGE[2] - - H26 GFBK I/O GFBK - - -
J1 VDD33 - +3.3V - - J2 VSS - GND - - J3 D3 I/O PW_D[3] - - -
J4 D2 I/O PW_D[2] - - J23 GBLKSPL O GBLKSPL - - J24 GCOAST O GCOAST - - J25 GREF O GREF - - J26 GHS I H_PW_G - - -
K1 D4 I/O PW_D[4] - - K2 D5 I/O PW_D[5] - - K3 VDD25 - +2.5V - - -
K4 VSS - GND - - K23 VSS - GND - - K24 VDD25 - +2.5V - - K25 GSOG I GSOG - - K26 GPEN I GPEN - - -
L1 D6 I/O PW_D[6] - - -
L2 D7 I/O PW_D[7] - - -
L3 D8 I/O PW_D[8] - - -
L4 D9 I/O PW_D[9] - - -
L23 PLLCLK I GND - - L24 GCLK I GCLK PU/PD - L25 GVS I V_PW_G - - L26 GFIELD I GND - - -
M1 VDD33 - +3.3V - - M2 VSS - GND - - M3 D10 I/O PW_D[10] - - -
M4 D11 I/O PW_D[11] - - M23 VSS - GND - - M24 GHSFOUT O GHSFOUT - - M25 GCLKOUT O (N.C.) - - M26 GADCCLK O (N.C.) - - -
N1 D12 I/O PW_D[12] - - N2 D13 I/O PW_D[13] - - N3 D14 I/O PW_D[14] - - -
N4 D15 I/O PW_D[15] - - N23 VSS - GND - - N24 VDD33 - +3.3V - - N25 VSS - GND - - N26 VDD25 - +2.5V - - -
P1 RAMWE O RAMWEN - L -
P2 RAMOE O RAMOEN - L -
P3 VDD33 - +3.3V - - -
P4 VSS - GND - - P23 GGE3 I GGE[3] - - P24 GGE4 I GGE[4] - - P25 GGE5 I GGE[5] - - P26 GGE6 I GGE[6] - - -
R1 ROMWE O ROMWEN - L -
R2 ROMOE O ROMOEN - L -
R3 CS0 O (N.C.) - - -
R4 CS1 O (N.C.) - - R23 GGE7 I GGE[7] - - R24 GRO0 I GRO[0] - - R25 GRO1 I GRO[1] - - R26 GRO2 I GRO[2] - - -
T1 CS2 I/O (N.C.) - - T2 CS3 I/O (N.C.) - - T3 RD I/O (N.C.) - - -
T4 WR I/O (N.C.) - - T23 GRO3 I GRO[3] - - T24 GRO4 I GRO[4] - - T25 GRO5 I GRO[5] - - T26 GRO6 I GRO[6] - - -
U1 BHEN I/O BHENN - L -
U2 A0 I/O PW_A[0] - - U3 VDD25 - +2.5V - - -
U4 VSS - GND - - U23 VSS - GND - - U24 VDD25 - +2.5V - - U25 GRO7 I GRO[7] - - U26 GRE0 I GRE[0] - - -
V1 A1 I/O PW_A[1] - - -
V2 A2 I/O PW_A[2] - - -
V3 A4 I/O PW_A[4] - - -
V4 A5 I/O PW_A[5] - - V23 GRE2 I GRE[2] - - V24 GRE1 I GRE[1] - - V25 GRE3 I GRE[3] - - V26 GRE4 I GRE[4] - - -
W1 A3 I/O PW_A[3] - - W2 VDD33 - +3.3V - - W3 A6 I/O PW_A[6] - - -
W4 A7 I/O PW_A[7] - - W23 GRE7 I GRE[7] - - W24 GRE6 I GRE[6] - - W25 GRE5 I GRE[5] - - W26 VSS - GND - - -
Y1 VSS - GND - - Y2 CLKIN I (N.C.) - - Y3 XTALIN I (12.375MHz
X'tal in)
Y4 XTALOUT O (12.375MHz
X'tal out)
Y23 VSS - GND - - Y24 VDD25 - +2.5V - - Y25 DRE0 I/O DRE[0] - - Y26 VDD33 - +3.3V - - -
AA1 A8 I/O PW_A[8] - - AA2 VDD25 - +2.5V - - AA3 A10 I/O PW_A[10] - - -
AA4 VSS - GND - - AA23 DRE5 I/O DRE[5] - - AA24 DRE4 I/O DRE[4] - - AA25 DRE2 I/O DRE[2] - - AA26 DRE1 I/O DRE[1] - - -
AB1 VSS - GND - - -
AB2 A9 I/O PW_A[9] - - -
AB3 A12 I/O PW_A[12] - - -
AB4 A16 I/O PW_A[16] - - AB23 DGE0 I/O DGE[0] - - AB24 VDD33 - +3.3V - - AB25 VSS - GND - - AB26 DRE3 I/O DRE[3] - - -
AC1 A11 I/O PW_A[11] - - -
AC2 VDD33 - +3.3V - - -
AC3 A17 I/O PW_A[17] - - -
AC4 VSS - GND - - -
AC5 MODE2 I GND - - -
AC6 DBO3 I/O (N.C.) - - -
AC7 VSS - GND - - -
AC8 DGO5 I/O (N.C.) - - -
AC9 DGO2 I/O (N.C.) - - AC10 VSS - GND - - AC11 VSS - GND - - AC12 DRO1 I/O (N.C.) - - AC13 VSS - GND - - AC14 VSS - GND - - AC15 DHS O HSYNCZ - - AC16 DENG O DENG - - AC17 VSS - GND - - AC18 VSS - GND - - AC19 VDD25 - +2.5V - - -
---
---
45
Page 42
AC20 VSS - GND - - AC21 VDD33 - +3.3V - - AC22 DGE4 I/O DGE[4] - - AC23 VSS - GND - - AC24 DGE1 I/O DGE[1] - - AC25 DRE7 I/O DRE[7] - - AC26 DRE6 I/O DRE[6] - - -
AD1 A13 I/O PW_A[13] - - AD2 A15 I/O PW_A[15] - - AD3 VDD33 - +3.3V - - AD4 VDD25P - +2.5VP - - AD5 DBO5 I/O (N.C.) - - AD6 VDD33 - +3.3V - - AD7 VDD25 - +2.5V - - AD8 DGO4 I/O (N.C.) - - -
AD9 DGO1 I/O (N.C.) - - AD10 VDD25 - +2.5V - - AD11 VDD33 - +3.3V - - AD12 DRO2 I/O (N.C.) - - AD13 DCLK O PIXCLK - - AD14 VDD33 - +3.3V - - AD15 DVS O VSYNCZ - - AD16 DENB O DENB - - AD17 VDD25 - +2.5V - - AD18 DBE6 I/O DBE[6] - - AD19 VDD25 - +2.5V - - AD20 VDD25 - +2.5V - - AD21 DBE2 I/O DBE[2] - - AD22 VSS - GND - - AD23 DGE3 I/O DGE[3] - - AD24 VDD33 - +3.3V - - AD25 VDD25 - +2.5V - - AD26 DGE2 I/O DGE[2] - - -
AE1 A14 I/O PW_A[14] - - -
AE2 A19 I/O PW_A[19] - - -
AE3 DBO7 I/O (N.C.) - - -
AE4 CPUTDI I CPUTDI PU - -
AE5 DBO4 I/O (N.C.) - - -
AE6 DBO2 I/O (N.C.) - - -
AE7 DBO0 I/O (N.C.) - - -
AE8 VDD33 - +3.3V - - -
AE9 DGO3 I/O (N.C.) - - -
AE10 DRO7 I/O (N.C.) - - -
AE11 DRO5 I/O (N.C.) - - AE12 DRO3 I/O (N.C.) - - AE13 VDD33 - +3.3V - - AE14 VSS - GND - - AE15 MCKEXT I MCKEXT PU/PD - AE16 VDD33 - +3.3V - - AE17 DBE7 I/O DBE[7] - - AE18 DBE5 I/O DBE[5] - - AE19 DBE4 I/O DBE[4] - - AE20 VSS - GND - - AE21 VDD25 - +2.5V - - AE22 DBE3 I/O DBE[3] - - AE23 DBE0 I/O DBE[0] - - AE24 DGE5 I/O DGE[5] - - AE25 VSS - GND - - AE26 VSS - GND - - -
AF1 A18 I/O PW_A[18] - - AF2 CPUTDO O PW_TDO - - AF3 VSS - GND - - AF4 DBO6 I/O (N.C.) - - AF5 VSS - GND - - AF6 DBO1 I/O (N.C.) - - AF7 DGO7 I/O (N.C.) - - AF8 DGO6 I/O (N.C.) - - -
AF9 VSS - GND - - AF10 DGO0 I/O (N.C.) - - AF11 DRO6 I/O (N.C.) - - AF12 DRO4 I/O (N.C.) - - AF13 DRO0 I/O (N.C.) - - AF14 VDD25 - +2.5V - - AF15 DCKEXT I DCKEXT PU/PD - AF16 VSS - GND - - AF17 DENR O DENR - - AF18 VDD25 - +2.5V - - AF19 VDD25 - +2.5V - - AF20 VSS - GND - - AF21 VSS - GND - - AF22 VSS - GND - - AF23 DBE1 I/O DBE[1] - - AF24 DGE7 I/O DGE[7] - - AF25 DGE6 I/O DGE[6] - - AF26 VDD25 - +2.5V - - -
46
Page 43
ICG3 : HD64F3067RVF (100pin QFP)
Pin Description
Pin Description I/O Signal PU/PD Active Initial
1 Vcc - +3.3V - -2 PB0/CS7X/TMO0
/TP8
3 PB1/CS6X
/DREQ0X/TMIO1
/TP9
4 PB2/CS5X
/TMIO2/TP10
5 PB3/CS4X
/DREQ1/TMIO3
/TP11
6 PB4/UCASX
/TP12
7 PB5/SCK2
/LCASX/TP13
8 PB6/TXD2/TP14 O RXD_232C EXT. PU --
9 PB7/RXD2/TP15 I TXD_232C none --
10 RESOX/FWE I FWE EXT. PD -11 VSS - GND - -12 P90/TXD0 O PW_RXD EXT. PU -13 P91/TXD1 O FLASH_TXD EXT. PU -14 P92/RXD0 I PW_TXD EXT. PU -15 P93/RXD1 I FLASH_RXD EXT. PU -16 P94/IRQ4 I FWE_OUT - -17 P95/IRQ5 I N.C EXT. PU -18 P40/D0 O FAN1ON none -19 P41/D1 O FAN2ON none -20 P42/D2 O FAN3ON none -21 P43/D3 O FAN4ON none -22 VSS - GND - -23 P44/D4 O ICSCLK - -24 P45/D5 O ICSDAT - -25 P46/D6 O ICSSTM - -26 P47/D7 O ICSSTD - -27 D8 O PW_SHUT EXT. PD High Low
28 D9 O PW_RESET EXT. PD Low Low
29 D10 I PW_STATE EXT. PD -Low
30 D11 I N.C EXT. PU -31 D12 I N.C EXT. PU -32 D13 I N.C EXT. PU -33 D14 I N.C EXT. PU -34 D15 I N.C EXT. PU -35 VCC - +3.3V - -36 P10/A0 I N.C EXT. PU -37 P11/A1 I N.C EXT. PU -38 P12/A2 I N.C EXT. PU -39 P13/A3 I N.C EXT. PU -40 P14/A4 I N.C EXT. PU -41 P15/A5 I N.C EXT. PU -42 P16/A6 I N.C EXT. PU -43 P17/A7 I N.C EXT. PU -44 VSS - GND - -45 P20/A8 I N.C EXT. PU -46 P21/A9 I N.C EXT. PU -47 P22/A10 I N.C EXT. PU -48 P23/A11 I N.C EXT. PU -49 P24/A12 I N.C EXT. PU -50 P25/A13 I N.C EXT. PU -51 P26/A14 I N.C EXT. PU -52 P27/A15 I N.C EXT. PU -53 P50/A16 I EXT. PU -54 P51/A17 I EXT. PU -55 P52/A18 I N.C EXT. PU -56 P53/A19 I N.C EXT. PU -57 VSS - GND - --
O N.C EXT. PU --
O N.C EXT. PU --
I N.C EXT. PU --
I RC5 none --
O CTS_232C EXT. PU --
I RTS_232C none --
58 P60/WAITX O RST_FPGA - Low High
59 P61/BREQX O PRG_FPGA EXT. PU Low High
60 P42/BACKX I DONEFPGA EXT. PU -61 P67/CLKOUT I N.C EXT. PU -62 STBYX - STBY EXT. PU -63 RESX - RESET - -64 NMI - - EXT. PD -65 VSS - GND - -66 EXTAL - X’tal Out - -67 XTAL - X’tal In - -68 VCC - +3.3V - -69 ASX I N.C EXT. PU -70 RDX I N.C EXT. PU -71 HWRX I N.C EXT. PU -72 LWRX I N.C EXT. PU -73 MD0 - Pull Up
Mode7
setting
74 MD1 - Pull Up
Mode7
setting
75 MD2 - Pull Up Flash
/ Mode7
76 AVCC - +3.3V - -77 VREF - +3.3V - -78 P70/AN0 I KEY0 - -79 P71/AN1 I KEY1 - -80 P72/AN2 I KEY2 - -81 P73/AN3 I N.C EXT. PU -82 P74/AN4 I TEMP_ERR EXT. PU High Low
83 P75/AN5 I DOOR_ERR EXT. PU High Low
84 P76/AN6/DA0 I FAN_ERR - High Low
85 P77/AN7/DA1 I T_SHUT EXT. PU High Low
86 AVSS - GND - -87 P80/IRQ0/RFSHX O PWR_CTRL none Low High
88 P81/IRQ1/CS3X I PWR_SHUT EXT. PU High Low
89 P82/IRQ2/CD2X I N.C EXT. PU -90 P83/IRQ3/CS1X
/ADTRGX
91 P84/CS0X I UNLOCK none Low High
92 VSS - GND - -93 PA0/TEND0X
/TCLKA/TP0
94 PA1/TEND1X
/TCLKB/TP1
95 PA2/TCLKC
/TIOCA0/TP2
96 PA3/TCLKD
/TIOCB0/TP3
97 PA4/A23/TIOCA1
/TP4
98 PA5/A22/TIOCB1
/TP5
99 PA6/A21/TIOCA2
/TP6
100 PA7/A20/TIOCB2
/TP7
I N.C EXT. PU --
I HSYNCUPZ EXT. PU --
I CSYNCUPZ EXT. PU --
I VSYNCUPZ EXT. PU --
I IE3ID0 EXT. PU --
I IE3ID1 EXT. PU --
O LED_PWR - High Low
O LED_STD - High High
O LED_WAN - High Low
EXT. PU --
EXT. PU --
EXT. PU --
47
Page 44
ICG3 : HD64F3067RVF (100pin QFP)
RxD2/TP15/PB
7
TxD2/TP14/PB6
/LCAS/TP13/PB5
SCK
2
UCAS/TP
/DREQ1/TMIO3/TP11/PB3
CS
4
CS
/TMO2/TP10/PB
5
CS6/DREQ0/TMIO1/TP9/PB
CS7/TMO0/TP8/PB
A20/TIOCB2/TP7/PA
A21/TIOCA2/TP6/PA
A22/TIOCB1/TP5/PA
A23/TIOCA1/TP
TCLKD/TIOCB0/TP3/PA
TCLKC/TIOCA0/TP2/PA
TEND1/TCLKB/TP1/PA
TEND0/TCLKA/TP0/PA
DA1/AN7/P7
DA0/AN6/P7
Port B
/PB4
12
2
1
0
7
6
5
Port A
/PA
4
4
3
2
1
0
V
REF
AV
CC
AV
SS
7
6
AN5/P7
5
Port 7
AN4/P7
4
AN3/P7
3
AN2/P7
2
AN1/P7
1
AN0/P7
0
Note: * Functions as RESO in the mask ROM versions, and as FWE in the flash memory and
flash memory R versions.
P9 /TxD
0
0
controller (TPC)
D/A converter
P9 /RxD
P9 /TxD
Programmable
timing pattern
A/D converter
P9 /SCK /IRQ
P9 /SCK /IRQ
P9 /RxD
54321
101
1
0
5
4
ADTRG/CS
RFSH/IRQ
CS
CS
2
1
3
/IRQ
/IRQ
/IRQ
2
3
1
/P8
/P8
0
/P8
/P8
2
3
1
0
Port 8
16-bit timer unit
8-bit timer unit
Serial communication
(SCI) 3 channels
interface
´
(WDT)
CS
0
/P8
4
0
RAM
Watchdog timer
P1 /A
P1 /A
P1 /A
0
0
BREQ/P6
WAIT/P6
1
Port 1
P1 /A
BACK/P6
2
flash memory)
P1 /A
P1 /A
HWR/P6
RD/P6
AS/P6
5
3
4
Port 6
(mask ROM or
ROM
(DMAC)
Bus controller
P1 /A
P1 /A
7654321
7654321
LWR/P6
f /P6
6
7
Interrupt controller
DMA controller
P2 /A
P2 /A
P2 /A
0
8
FWE*/RESO
NMI
Port 2
P2 /A
P2 /A
STBY
RES
Clock pulse
generator
H8/300H CPU
P2 /A
P2 /A
XTAL
P2 /A
7654321
1514131211109
EXTAL
MD
P5 /A
0
16
MD
MD
210
Address bus
Data bus (upper)
Data bus (lower)
Port 5Port 9
P5 /A
P5 /A
P5 /A
321
191817
Port 3 Port 4
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7
15
6
14
5
13
4
12
3
11
2
10
1
9
0
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
ICA2 : AD9884A
Pin Description
Pin Name Function
INPUTS
AIN
R
AIN
G
AIN
B
HSYNC Horizontal Sync Input
COAST Clock Generator Coast Input (optional)
CLAMP External Clamp Input (optional)
SOGIN Sync On Green Slicer Input (optional)
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
High impedance inputs that accepts the RED, GREEN, and BLUE channel graphics signals, respectively. The three channels
are identical, and can be used for any colors, but colors are assigned for convenient reference. They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency refer- ence for
pixel clock generation. The logic sense of this pin is controlled by HSPOL. Only the leading edge of HSYNC is active. When
HSPOL = 0, the falling edge of HSYNC is used. When HSPOL = 1, the rising edge is active. The input includes a Schmitt
trigger for noise immunity, with a nominal input threshold of 1.5 V. Electrostatic Discharge (ESD) protection diodes will
conduct heavily if this pin is driven more than 0.5 V above the 3.3 V power supply (or more than 0.5 V below ground). If a 5 V
signal source is driving this pin, the signal should be clamped or current limited.
This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue pro- ducing a
clock at its present frequency and phase. This is useful when processing sources that fail to produce hori- zontal sync pulses
when in the vertical interval. The COAST signal is generally NOT required for PC-generated signals. The logic sense of this
pin is controlled by CSTPOL. COAST may be asserted at any time. When not used, this pin must be grounded and CSTPOL
programmed to 1. CSTPOL defaults to 1 at power-up.
This logic input may be used to defi ne the time during which the input signal is clamped to ground, establishing a black
reference. It should be exercised when a black signal is known to be present on the analog input channels, typically during the
back porch period of the graphics signal. The CLAMP pin is enabled by setting control bit EXTCLMP to 1 (default power-up
is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from
the trailing edge of the HSYNC input. The logic sense of this pin is controlled by CLAMPOL. When not used, this pin must be
grounded and EXTCLMP programmed to 0.
This input is provided to assist in processing signals with embedded sync, typically on the GREEN channel. The pin is
connected to a high speed comparator with an internally-generated threshold of 0.15 V. When connected to a dc-coupled
graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT that changes state whenever
the input signal crosses 0.15 V. This is usually a composite sync signal, containing both vertical and horizontal sync
information that must be separated before passing the horizontal sync signal to HSYNC.
The SOG slicer comparator continues to operate when the AD9884A is put into a power-down state. When not used, this
input should be grounded.
48
Page 45
CKEXT External Clock Input (optional)
This pin may be used to provide an external clock to the AD9884A, in place of the clock internally-generated from HSYNC.
This input is enabled by programming EXTCLK to 1. When an external clock is used, all other internal functions operate
normally. When unused, this pin should be tied through a 10kohm resistor to GROUND, and EXTCLK programmed to 0. The
clock phase adjustment still operates when an external clock source is used.
CKINV Sampling Clock Inversion (optional)
This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180degrees. This
is in support of Alternate Pixel Sampling mode, wherein higher frequency input signals (up to 280Mpps) may be captured
by fi rst sampling the odd pixels, then capturing the even pixels on the subsequent frame. This pin should be exercised only
during blanking intervals (typically vertical blanking) as it may produce several samples of corrupted data during the phase
shift. CKINV should be grounded when not used.
Pin Name Function
OUTPUTS
RA7-0
D
RB7-0
D
GA7-0
D
GB7-0
D
BA7-0
D
BB7-0
D
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue Channel, Port A
Data Output, Blue Channel, Port B
The main data outputs. Bit 7 is the MSB. Each channel has two ports. When the part is operated in Single Channel mode
(DEMUX = 0), all data are presented to Port A, and Port B is placed in a high impedance state. Programming DEMUX to
1 establishes Dual Channel mode, wherein alternate pixels are presented to Port A and Port B of each channel. These will
appear simultaneously, two pixels presented at the time of every second input pixel, when PAR is set to 1 (parallel mode).
When PAR = 0, pixel data appear alternately on the two ports, one new sample with each incoming pixel (interleaved
mode). In Dual Channel mode, the fi rst pixel sampled after HSYNC is routed to Port A. The second pixel goes to Port B,
the third to A, etc. The delay from pixel sampling time to output is fi xed. When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted as well. The DATACK, DATACK and HSOUT outputs are also moved, so the
timing relationship among the signals is maintained.
DATACK Data Output Clock
DATACK Data Output Clock Complement
Differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They are produced
by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9884A is operated
in Single Channel mode, the output frequency is equal to the pixel sampling frequency. When operating in Dual Channel
mode, the Data Output Clock and the Output Data are presented at one-half the pixel rate. When the sampling time is
changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, DATACK and HSOUT
outputs are all moved, so the timing relationship among the signals is maintained. Either or both signals may be used,
depending on the timing mode and interface design employed.
HSOUT Horizontal Sync Output
A reconstructed and phase-aligned version of the HSYNC input. This signal is always active HIGH. By maintaining
alignment with DATACK, DATACK, and Data, data timing with respect to horizontal sync can always be clearly determined.
SOGOUT Sync On Green Slicer Output
The output of the Sync On Green slicer comparator. When SOGIN is presented with a dc-coupled ground-referenced
analog graphics signal containing composite sync, SOGOUT will produce a digital composite sync signal. This signal gets
no other processing on the AD9884A. The SOG slicer comparator continues to operate when the AD9884A is put into a
power-down state.
CONTROL
SDA Serial Data I/O
Bidirectional data port for the serial interface port.
SCL Serial Interface Clock
Clock input for the serial interface port.
1-0
A
Serial Port Address LSBs
The two least signifi cant bits of the serial port address are set by the logic levels on these pins. Connect a pin to ground to
set the address bit to 0. Tie it HIGH (to VD through 10 kΩ) to set the address bit to 1. Using these pins, the serial address
may be set to any value from 98h to 9Fh. Up to four AD9884As may be used on the same serial bus by appropriately setting
these bits. They can also be used to change the AD9884A address if a confl ict is found with another device on the bus.
PWRDN Power-Down Control Input
Bringing this pin LOW puts the AD9884A into a very low power dissipation mode. The output buffers are placed in a
highimpedance state. The clock generator is stopped. The control register contents are maintained. The Sync On Green
Slicer (SOGOUT) and internal reference continue to function
.
49
Page 46
ICA2 : AD9884A
Pin Name Function
ANALOG INTERFACE
REFOUT Internal Reference Output
Output from the internal 1.25 V bandgap reference. This output is intended to drive relatively light loads. It can drive
the AD9884A Reference input directly, but should be externally buffered if it is used to drive other loads as well.
The absolute accuracy of this output is ±4%, and the temperature coeffi cient is ±50 ppm, which is adequate for
most AD9884A applications. If higher accuracy is required, an external reference may be employed. If an external
reference is used, tie this pin to ground through a 0.1 µF capacitor.
REFIN Reference Input
The reference input accepts the master reference voltage for all AD9884A internal circuitry (+1.25 V ± 10%). It may
be driven directly by the REFOUT pin. Its high impedance presents a very light load to the reference source.
This pin should be bypassed to Ground with a 0.1 µF capacitor.
FILT External Filter Connection
For proper operation, the pixel clock generator PLL requires an external fi lter. Connect the fi lter shown in Figure 10
to this pin. For optimal performance, minimize noise and parasitics on this node.
POWER SUPPLY
V
D Main Power Supply
These pins supply power to the main elements of the circuit. It should be as quiet and fi ltered as possible.
V
DD Digital Output Power Supply
A large number of output pins (up to 52) switching at high speed (up to 140 MHz) generates a lot of power supply
transients (noise). These supply pins are identifi ed separately from the VD pins so special care can be taken to
minimize output noise transferred into the sensitive analog circuitry. If the AD9884A is interfacing with lower voltage
logic, VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility.
D Clock Generator Power Supply
PV
GND Ground
The most sensitive portion of the AD9884A is the clock generation circuitry. These pins provide power to the clock
PLL and help the user design for optimal performance. The designer should provide "quiet," noise-free power to
these pins.
The ground return for all circuitry on chip. It is recommended that the AD9884A be assembled on a single solid
ground plane, with careful attention to ground current paths. See the Design Guide for details.
AD9884A
2
CONTROL
A0A
8
8
8
8
8
PWRDN
1
R
IN
G
IN
B
IN
HSYNC
COAST
CLAMP
CKINV
CKEXT REFIN
CLAMP
CLAMP
CLAMP
CLOCK
GENERATOR
SOGIN
FILT
0.15V
SOGOUT
A/D
A/D
A/D
SDA SCL
8
8
8
8
8
8
REF
REFOUT
R
OUTA
R
OUTB
G
OUTA
G
OUTB
B
OUTA
B
OUTB
DATACK
HSOUT
50
Page 47
IC73 : µPD64082
No. Symbol I/O Level Buffer type
Description
PU/PD [kΩ]
1 DGND - - Digital section ground
2-9 MA7-MA0 O TTL 3-state 1 mA Address output for external EDO memory
10 MCAS O TTL 3-state 1 mA CAS output for external EDO memory (active-low)
11 MWE O TTL 3-state 1 mA WE output for external EDO memory (active-low)
12 MOE O TTL 3-state 1 mA OE output for external EDO memory (active-low)
13-28 MIO15-MIO0 I/O TTL 3-state 1 mA 5 V resistant Data input/output for external EDO memory
29 DGND - - fsc generator digital section ground
30 XI I - fsc generator reference clock input (X’tal is connected.)
31 XO O - fsc generator reference clock inverted output (X’tal is connected.)
32 DVDD - - fsc generator digital section supply voltage
33-36 HO3-HO0 O TTL
3-state
37 HWCK O TTL
3-state
38 HRCK O TTL
3-state
39 HRST O TTL
3-state
1 mA Data output for external fi eld memory (Open when not used.)
HO3 is the MSB, HO0 is the LSB.
3 mA Write clock output for external fi eld memory (Open when not
used.)
3 mA Read clock output for external fi eld memory (Open when not
used.)
1 mA Reset signal output for external fi eld memory (Open when
not used.)
40 DGND - - Digital section ground
41-44 HI3-HI0 I TTL 5 V resistant Input for external fi eld memory (Grounded when not used.)
HI3 is the MSB, HI0 is the LSB.
45 DVDD - - Digital section supply voltage
46 AVDD - - fsc generator DAC section supply voltage
47 FSCO - Analog fsc generator fsc output
48 AGND - - fsc generator DAC section ground
49 AGND - - 8fSC-PLL ground
50 FSCI - Analog 8fSC-PLL fsc input
51 CPLL - - 8fSC-PLL fi lter output (Grounded)
52 RPLL - Schmitt PU:50 Test pin (Grounded)
53 AVDD - - 8fSC-PLL section supply voltage
No. Symbol I/O Level Buffer type
Description
PU/PD [kΩ
54 CKMD I TTL 5 V resistant Clock mode test input ('L' : Normal mode, 'H' : Test mode)
55 DGND - - Digital section ground
56 CLK8 O / I TTL 3-state 3 mA 5 V resistant 8fsc clock output (8fsc clock input when CKMD pin = H )
57 RSTB I Schmitt 5 V resistant
PU:50
58 SLA0 I TTL 5 V resistant PD:50 I
59 SCL I Schmitt 5 V resistant I
60 SDA I / O Schmitt
N-ch open
5 mA
5 V resistant
System reset input (active-low) (Active-low reset pulse is input from the
outside.)
2
C bus slave address selection input ('L' : B8 / B9h, 'H' : BA / BBh)
2
C bus clock input (Connected to system SCL line)
2
I
C bus data input/output (Connected to system SDA line)
drain
61 ST0 O TTL 1 mA Internal signal monitor output 0
62 ST1 O TTL 1 mA Internal signal monitor output 1
63 NSTD O TTL 1 mA Nonstandard signal detection monitor output ('L' : standard, 'H' :
nonstandard)
64 DVDD - - Digital section supply voltage
65-74 DYCO0-
DYCO9
(LSB)(MSB)
I/O TTL 1 mA
5 V resistant
EXADINS=0: Digital YC signal alternate output
EXADINS=1: Digital video data input for external Y-ADC
(Pull down unuse lower bit pins via 100 & resistor) DYCO0 is the LSB,
DYCO9 is the MSB.
75 ALTF O TTL 1 mA EXADINS=0: Digital YC signal alternate fl ag output ('L' : C, 'H' : Y)
EXADINS=1: 4fsc clock output for external Y-ADC
76 CSI I Schmitt 5 V resistant
Composite sync input (active-low)
PD:50
77 TEST I TTL 5 V resistant
PD:50
78 LINE I TTL 5 V resistant
PD:50
79 KIL I TTL 5 V resistant
PD:50
Test pin for IC selection ('L' : Normal mode, 'H' : Test mode)
(Grounded)
Forced inter-line processing selection input
('L' : ordinary processing, 'H' : forced inter-line processing)
External killer input
('L' : ordinary processing, 'H' : forced YC separation stop)
80 DGND - - Digital section ground
81 AVDD - - Y-DAC and C-DAC supply voltage
82 CBPC O Analog C-DAC phase compensation output
51
Page 48
IC73 : µPD64082
83 ACO O Analog C-DAC analog C signal output
84 AYO O Analog Y-DAC analog Y signal output
85 CBPY O Analog Y-DAC phase compensation output
86 AGND - - Y-DAC and C-DAC ground
87 AGND - - Y-ADC ground
No. Symbol I/O Level Buffer type
Description
PU/PD [kΩ]
88 AYI I Analog Y-ADC analog composite signal or Y signal input
89 VCLY O Analog Y-ADC clamp potential output
90 VRBY O Analog Y-ADC bottom reference voltage output
91 VRTY O Analog Y-ADC top reference voltage output
92 AVDD - - Y-ADC supply voltage
93 AVDD - - C-ADC supply voltage
94 VRTC O Analog C-ADC top reference voltage output
95 VRBC O Analog C-ADC bottom reference voltage output
96 ACI I Analog C-ADC analog C signal input
97 AGND - - C-ADC ground
98 MRAS O TTL 3-state 1 mA RAS output for external EDO memory (active-low)
99 MA8 O TTL 3-state 1 mA Address output for external EDO memory
100 DVDD - - Digital section supply voltage
AY I
AC I
MRA S
MCAS
MWE
MOE
MA8-0
MIO15-0
HRST
HWCK
HRCK
HO3-0
HI3-0
CS I
Erro r Det.
Clamp
Bias
EDO
Memo r y
Interface
Field
Memory
Interface
(HH option)
10-bi t
Y-ADC
8-bi t
C-ADC
YCNR
EXADI NS
YCNR
MNNR
HH
HH
Line Comb
Line Comb
Line Comb
Field Comb
Filter (C/HH'
Separ at ion)
H
Separation
Fi lter
Fi lter
Fi lter
HV
Coun t er
Sync
HH De c .
3
C
C3'
HH '
De la y
Ch roma
Mi xer
Motion
Detection
HH
Decoder
WCV- ID
Decoder
Non-standard
Signal
Detection
YCNR
KIL
YCNR
MNNR
YNR
Recurs i ve
Recurs i ve
HH De c .
HH
YNR
CNR
YCNR
Y-High Freq.
Coring
Y-High Freq.
Peak i ng
C-BPF &
De la y
Adjustment
Y-Vertical
Aper ture
Compensation
ID-1
Enc ode r
4f
SC
8f
SC
4f
SC
EXAD INS
10-bit
Y-DAC
10-bit
C-DAC
2
C Bus
I
Interface
8f
SC
PLL
8-bit
SC
-DAC
f
SC
f
Gen er a t or
DYCO9-0
ALTF
AYO
ACO
SDA
SCL
SLA0
RSTB
CLK8
FSCI
BPF
FSCO
XO
XI
52
Page 49
ICF2 : SAA7118
PINNING
SYMBOL
DNC6 1 B2 O do not connect, reser ved for future extensions and for testing
AI41 2 B1 I analog input 41
AGND 3 C2 P analog ground
V
SSA4
AI42 5 D2 I analog input 42
AI4D 6 D3 I differential input for ADC channel 4 (pins AI41 to AI44)
AI43 7 D1 I analog input 43
V
DDA4
V
DDA4A
AI44 10 E1 I analog input 44
AI31 11 E3 I analog input 31
V
SSA3
AI32 13 F2 I analog input 32
AI3D 14 F1 I/O differential input for ADC channel 3 (pins AI31 to AI34)
AI33 15 F3 I analog input 33
V
DDA3
V
DDA3A
AI34 18 G1 I analog input 34
AI21 19 G4 I analog input 21
V
SSA2
AI22 21 G3 I analog input 22
AI2D 22 H1 I differential input for ADC channel 2 (pins AI24 to AI21)
AI23 23 H2 I analog input 23
V
DDA2
V
DDA2A
AI24 26 J3 I analog input 24
AI11 27 J2 I analog input 11
V
SSA1
AI12 29 K1 I analog input 12
AI1D 30 K3 I differential input for ADC channel 1 (pins AI14 to AI11)
AI13 31 K2 I analog input 13
V
DDA1
V
DDA1A
AI14 34 L3 I analog input 14
AGNDA 35 L2 P analog signal ground
AOUT 36 M1 O analog test output (do not connect)
V
DDA0
V
SSA0
PIN
QFP160 BGA156
4 C1 P ground for analog inputs AI4x
8 D4 P analog supply voltage for analog inputs AI4x (3.3 V)
9 E2 P analog supply voltage for analog inputs AI4x (3.3 V)
12 E4 P ground for analog inputs AI3x
16 F4 P analog supply voltage for analog inputs AI3x (3.3 V)
17 G2 P analog supply voltage for analog inputs AI3x (3.3 V)
20 H3 P ground for analog inputs AI2x
24 H4 P analog supply voltage for analog inputs AI2x
25 J1 P analog supply voltage for analog inputs AI2x
28 J4 P ground for analog inputs AI1x
32 K4 P analog supply voltage for analog inputs AI1x (3.3 V)
33 L1 P analog supply voltage for analog inputs AI1x (3.3 V)
37 M3 P analog supply voltage (3.3 V) for internal clock generation circuit
38 M2 P ground for internal Clock Generation Circuit (CGC)
TYPE
(1)
DESCRIPTION
SYMBOL
V
DDD5
ASCLK 74 N11 O audio serial clock output
ALRCLK 75 P12 O/st/pd audio left/right clock output; can be strappedto supply via a 3.3 kΩ resistor
AMXCLK 76 M12 I audio master external clock input
ITRDY 77 N12 I target ready input for image por t data
DNC0 78 P13 I/pu do not connect, reserved for future extensions and for testing: scan input
DNC16 79 N13 NC do not connect, reserved for future extensions and for testing
DNC17 80 N14 NC do not connect, reserved for future extensions and for testing
DNC19 81 − NC do not connect, reser ved for future extensions and for testing
DNC20 82 − NC do not connect, reser ved for future extensions and for testing
FSW 83 M13 I/pd fast switch (blanking) with internal pull-down inserts component inputs into
PIN
QFP160 BGA156
73 D12 P digital supply voltage 5 (peripheral cells)
ICLK 84 M14 I/O clock output signal for image port, or optional asynchronous back-end
IDQ 85 L13 O output data qualier f or image port (optional: gated clock output)
ITRI 86 L12 I/(O) image port output control signal, affects all input port pins inclusive ICLK,
IGP0 87 L14 O general purpose output signal 0; image port (controlled by subaddresses
V
IGP1 89 K13 O general purpose output signal 1; image por t (controlled by subaddresses
88 D11 P digital ground 5 (per ipheral cells)
SSD5
IGPV 90 K14 O multi purpose vertical reference output signal; image port (controlled by
IGPH 91 K12 O multi purpose horizontal reference output signal; image port (controlled by
IPD7 92 K11 O MSB of image port data output
IPD6 93 J13 O MSB − 1 of image port data output
IPD5 94 J14 O MSB − 2 of image port data output
V
V
IPD4 97 H13 O MSB − 3 of image por t data output
IPD3 98 H14 O MSB − 4 of image por t data output
IPD2 99 H11 O MSB − 5 of image por t data output
IPD1 100 G12 O MSB − 6 of image port data output
V
IPD0 102 G14 O LSB of image port data output
95 F12 P digital supply voltage 6 (core)
DDD6
96 F11 P digital ground 6 (core)
SSD6
101 H12 P digital supply voltage 7 (peripheral cells)
DDD7
(1)
TYPE
to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal
pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1);
notes 5 and 7
DESCRIPTION
CVBS signal
clock input
enable and active polarityis under software control (bits IPE in subaddress
87H); output path used for testing: scan output
84H and 85H)
84H and 85H)
subaddresses 84H and 85H)
subaddresses 84H and 85H)
SYMBOL
DNC13 39 N1 NC do not connect, reser ved for future extensions and for testing
DNC14 40 N2 I/pu do not connect, reserved for future extensions and for testing
DNC18 41 P2 I/O do not connect, reserved for future extensions and for testing
DNC15 42 N3 I/pd do not connect, reserved for future extensions and for testing
EXMCLR 43 P3 I/pd external mode clear (with internal pull-down)
CE 44 N4 I/pu chip enable or reset input (with internal pull-up)
V
DDD1
LLC 46 P4 O line-locked system clock output (27 MHz nominal)
V
SSD1
LLC2 48 N5 O line-locked1⁄2clock output (13.5 MHz nominal)
RES 49 P5 O reset output (active LOW)
V
DDD2
V
SSD2
CLKEXT 52 N6 I external clock input intended for analog-to-digital conversion of VSB
ADP8 53 P6 O MSB of direct analog-to-digital converted output data (VSB)
ADP7 54 M6 O MSB − 1 of direct analog-to-digital converted output data (VSB)
ADP6 55 L6 O MSB − 2 of direct analog-to-digital converted output data (VSB)
ADP5 56 N7 O MSB − 3 of direct analog-to-digital converted output data (VSB)
ADP4 57 P7 O MSB − 4 of direct analog-to-digital converted output data (VSB)
ADP3 58 L7 O MSB − 5 of direct analog-to-digital converted output data (VSB)
V
DDD3
ADP2 60 M7 O MSB − 6 of direct analog-to-digital converted output data (VSB)
ADP1 61 P8 O MSB − 7 of direct analog-to-digital converted output data (VSB)
ADP0 62 N8 O LSB of direct analog-to-digital converted output data (VSB)
V
SSD3
INT_A 64 P9 O/od I2C-bus interrupt ag (LO W if any enabled status bit has changed)
V
DDD4
SCL 66 N9 I serial clock input (I2C-bus)
V
SSD4
SDA 68 P10 I/O/od serial data input/output (I2C-bus)
RTS0 69 M10 O real-time status or sync information, controlled by subaddresses
PIN
QFP160 BGA156
45 C5 P digital supply voltage 1 (peripheral cells)
47 D5 P digital ground 1 (peripheral cells)
50 C8 P digital supply voltage 2 (core)
51 D7 P digital ground 2 (core; substrate connection)
59 C9 P digital supply voltage 3 (peripheral cells)
63 D9 P digital ground 3 (peripheral cells)
65 C10 P digital supply voltage 4 (core)
67 D10 P digital ground 4 (core)
RTS1 70 N10 O real-time status or sync information, controlled by subaddresses
RTCO 71 L10 O/st/pd real-time control output; contains information about actual system clock
AMCLK 72 P11 O audio master clock output, up to 50% of crystal clock
TYPE
(1)
DESCRIPTION
signals (36 MHz)
11H and 12H
11H and 12H
frequency, eld rate , odd/even sequence, decoder status, subcarrier
frequency and phase and PAL sequence (see document
, available on request); the RTCO pin is enabled via I2C-bus
Description”
bit RTCE; see notes 5, 6 and Table 35
“RTC Functional
SYMBOL
PIN
QFP160 BGA156
HPD7 103 G13 I/O MSB of host port data I/O, extended CB-CR input for expansion port,
V
104 G11 P digital ground 7 (peripheral cells)
SSD7
HPD6 105 F14 I/O MSB − 1 of host port data I/O, extended CB-CR input for expansion port,
V
106 J12 P digital supply voltage 8 (core)
DDD8
HPD5 107 F13 I/O MSB − 2 of host port data I/O, extended CB-CR input for expansion port,
V
108 J11 P digital ground 8 (core)
SSD8
HPD4 109 E14 I/O MSB − 3 of host por t data I/O, extended CB-CR input for expansion port,
HPD3 110 E12 I/O MSB − 4 of host por t data I/O, extended CB-CR input for expansion port,
HPD2 111 E13 I/O MSB − 5 of host por t data I/O, extended CB-CR input for expansion port,
HPD1 112 E11 I/O MSB − 6 of host por t data I/O, extended CB-CR input for expansion port,
HPD0 113 D14 I/O LSB of host port data I/O, extended CB-CR input for expansion port,
V
114 M4 P digital supply voltage 9 (peripheral cells)
DDD9
DNC1 115 D13 I/pu do not connect, reserved for future extensions and for testing: scan input
DNC2 116 C14 I/pu do not connect, reserved for future extensions and for testing: scan input
DNC7 117 B13 NC do not connect, reserved for future extensions and for testing
DNC8 118 B14 NC do not connect, reserved for future extensions and for testing
DNC11 119 C12 NC do not connect, reserved for future extensions and for testing
DNC12 120 C13 NC do not connect, reserved for future extensions and for testing
DNC21 121 − NC do not connect, reserved for future extensions and for testing
DNC22 122 − NC do not connect, reserved for future extensions and for testing
DNC3 123 A13 I/pu do not connect, reserved for future extensions and for testing: scan input
DNC4 124 B12 O do not connect, reserved for future extensions and for testing: scan output
DNC5 125 A12 I/pu do not connect, reserved for future extensions and for testing: scan input
XTRI 126 B11 I X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH,
XPD7 127 C11 I/O MSB of expansion port data
XPD6 128 A11 I/O MSB − 1 of expansion port data
129 L4 P digital ground 9 (peripheral cells)
V
SSD9
XPD5 130 B10 I/O MSB − 2 of expansion port data
XPD4 131 A10 I/O MSB − 3 of expansion port data
132 M5 P digital supply voltage 10 (core)
V
DDD10
V
133 L5 P digital ground 10 (core)
SSD10
(1)
TYPE
extended C
B-CR
extended C
B-CR
extended C
B-CR
extended C
B-CR
extended C
B-CR
extended C
B-CR
extended C
B-CR
extended C
B-CR
XRV, XDQ and XCLK), enable and active polarity is under software control
(bits XPE in subaddress 83H)
DESCRIPTION
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
53
Page 50
ICF2 : SAA7118
SYMBOL
XPD3 134 B9 I/O MSB − 4 of expansion port data
XPD2 135 A9 I/O MSB − 5 of expansion port data
V
DDD11
V
SSD11
XPD1 138 B8 I/O MSB − 6 of expansion port data
XPD0 139 A8 I/O LSB of expansion port data
XRV 140 D8 I/O vertical reference I/O expansion port
XRH 141 C7 I/O horizontal reference I/O expansion port
V
DDD12
XCLK 143 A7 I/O clock I/O expansion port
XDQ 144 B7 I/O data qualier f or expansion port
V
SSD12
XRDY 146 A6 O task ag or ready signal from scaler , controlled by XRQT
TRST 147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up);
TCK 148 B6 I/pu test clock for boundary scan test; note 2
TMS 149 D6 I/pu test mode select input for boundary scan test or scan test; note 2
TDO 150 A5 O test data output for boundary scan test; note 2
V
DDD13
TDI 152 B5 I/pu test data input for boundary scan test; note 2
V
SSD13
V
SS(xtal)
XTALI 155 B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection
XTALO 156 A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL
V
DD(xtal)
XTOUT 158 A2 O crystal oscillator output signal; auxiliary signal
DNC9 159 C3 NC do not connect, reserved for future extensions and for testing
DNC10 160 C4 NC do not connect, reserved for future extensions and for testing
Notes
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.
2. In accordance with the
pull-up transistor and TDO is a 3-state output pad.
3. For board design without boundary scan implementation connect the
4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit.
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
5. Pin strapping is done by connecting the pin to thesupply via a 3.3 kΩ resistor. During the power-up reset sequence
the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).
PIN
QFP160 BGA156
136 M8 P digital supply voltage 11 (peripheral cells)
137 L8 P digital ground 11 (peripheral cells)
142 M9 P digital supply voltage 12 (core)
145 L9 P digital ground 12 (core)
151 M11 P digital supply voltage 13 (peripheral cells)
153 L11 P digital ground 13 (peripheral cells)
154 A4 P ground for crystal oscillator
157 B3 P supply voltage for crystal oscillator
(1)
TYPE
notes 2, 3 and 4
of external oscillator with TTL compatible square wave clock signal
clock input of XTALI is used
“IEEE1149.1”
standard the pads TDI, TMS, TCK and TRST are input pads with an internal
DESCRIPTION
TRST pin to ground.
TRST can be used to force the Test
FSW
AI11
AI12
AI13
AI14
AI1D
AI21
AI22
AI23
AI24
AI2D
AI31
AI32
AI33
AI34
AI3D
AI41
AI42
AI43
AI44
AI4D
AOUT
AGND
AGNDA
]
ADP[8:0
CLKEXT
AD PORT
ANALOG1
and
ADC1
ANALOG2
and
ADC2
ANALOG3
and
ADC3
ANALOG4
and
ADC4
POWER-ON CONTROL
POWER SUPPLY
V
V
SSA
SSD
V
V
DDD
DDA
RES
DNC0 to DNC5
CONTROL
FAST SWITCH DELAY
R
G
COMPONENTS
PROCESSING
B
C
CROMINANCE
PROCESSING
COMB FILTER
ANALOG INPUT CONTROL
Y
LUMININANCE
S
PROCESSING
SYNCHRONIZATION VIDEO/ TEXT ARBITER
VIDEO
CLOCK
V
LLC2
DD(xtal)
V
SS(xtal)
LLC
I2C-BUS REGISTER MAP
Y
C
B
C
RAW
R
S
C
B
C
R
Y-CB-C
DECODER OUTPUT CONTROL
Y
RAW
S
Y-CB-C
SS
GPO CRYSTAL X PORT
RTS0
RTCO
XTALI
XRDY
RTS1
XTALO
XTOUT
R
R
XPD[7:0
Y-CB-CRS
XCLK
]
FIRST TASK I2C-BUS REGISTER MAP SCALER
SECOND TASK I2C-BUS REGISTER MAP SCALER
SCALER EVENT CONTROLLER
PRESCALER
BCS-SCALER
FIR-PREFILTER
LINE FIFO BUFFER
SAA7118
VBI-DATA SLICER
XDQ
CB-C
XRV
R
XTRIXRH
H PORT
HPD[7:0
CB-C
AMXCLK
]
HORIZONTAL
VERTICAL SCALING
FINE (PHASE) SCALING
R
AUDIO
CLOCK
ALRCLK
AMCLK
ASCLK
TDO
TEXT
FIFO
VIDEO FIFO
BOUNDARY
SCAN
TRST
TDI TCK
INT_ASCLSDACE
IGP1
IGP0
IGPV
IGPH
]
IPD[7:0
ICLK
IDQ
ITRDY
OUTPUT FORMATTER I PORT
ITRI
TMS
54
Page 51
IC96 : FLI2220
Pin Connections and Functions
Pin # Name Description
Power Supply Connections (not shown on Block diagram)
See list V
See list V
72 ISINK Analog current sink return for the video DAC circuits. Connect to the analog ground plane.
74 AV
68 AV
Pin # Name Description
Control Signals
25 RESETB Reset. When this input is set low it will reset all the internal registers to the default states.
139 ENHOFF When this pin is set low the FLI2220 will be in normal enhancement mode. When it is set high
23-21 ADDR
20, 18 MODE
17 SCL I
16 SDA I2C compatible serial control bus data. Data can be written to the control registers via this pin
24 I2CCLK Clock input for the internal I2C circuit. This pin may be connected to the main CLKIN signal
67 CLKIN Master clock input. CLKIN should be driven by the pixel clock of the video input signal. The
Input Signals
66-61, Y/D1IN
58-55 determined by the settings of the DVIMode bits. Refer to the DVIMode description, bits 7-6 in
37-30, Cb/CrCbIN
27-26 the settings of the DVIMode bits. Refer to the DVIMode description, bits 7-6 in register 09H,
54-51, VIN
48-43 DVIMode bits. Refer to the DVIMode description, bits 7-6 in register 09H, for details. When
SS
DD
DD
DD
9-0
Digital ground connections. Connect to the digital ground plane. Pins: 12, 29, 41, 50, 79, 80,
82, 88, 94, 100, 102, 108, 114, 120, 122, 128, 132, 136, 142, 155
Digital power connections. Connect to the digital 3.3 volt power supply and decouple to the
digital ground plane. Pins: 11, 28, 40, 49, 59, 60, 81, 87, 93, 99, 101, 107, 113, 119, 121, 127,
131, 135, 141, 154
Analog power connections for the video DAC circuits. Connect to separately decoupled 3.3
volt power supplies and decouple to the analog ground plane if a separate plane is used.
Analog power connections for the clock PLL circuits. Connect to separately decoupled 3.3 volt
power supplies and decouple to the analog ground plane if a separate plane is used.
Refer to the section on the control registers for details of these states. The device must be reset
after it is powered-up.
all the enhancement functions will be turned off. This overrides the ENHEN register control,
bit 0 in register 20
The settings of ADDR
2-0
conflict with the other I2C devices in the system. ADDR
any of the following values:
Please refer to the section I2C Bus Operation and Protocol for further information.
I2C operating MODE
1-0
allowing it to be driven by an external processor. When MODE
operate in Master mode, allowing it to be connected to an external memory. In this mode the
FLI2200 will automatically load all of its registers from the external memory after a reset.
Other settings of MODE
2
C compatible serial control bus clock. The control port can operate in both slave and master
modes, so that this pin can be an input or an output.
when it is in the input mode and data can be read from the status registers when it is in the
output mode. Refer to the section on the serial port for timing and format details and to the
section on the registers for programming information.
or driven from a separate clock between 4 and 54 MHz. Note that when the I2C bus is put into
Master mode (MODE
maximum frequency of CLKIN is 54 MHz.
10-bit luminance or multiplexed Y/Cb/Cr (D1/ITU BT-R601) signal input bus. The format is
9-0
register 09H, for details. When DVIMode is set to 01 or 10 the Y signal is sampled on the
rising edges of the master clock, CLKIN. When DVIMode is set to 00 the multiplexed
Y/Cb/Cr signal is sampled on the rising edges of the master clock, CLKIN. In this mode the
HREIN, VREFIN and FLDIN inputs are not required since the FLI2200 will derive all timing
information from the input signal.
10-bit non-multiplexed Cb or multiplexed Cb/Cr signal input bus. The format is determined by
9-0
for details. When DVIMode is set to 10 the Cb signal is input on this bus. In this mode the
chroma signal is sampled on alternate rising edges of the CLKIN clock, starting with the first
rising edge following the rising edge of HREFIN. When DVIMode is set to 01 the multiplexed
Cb/Cr signal is input on this bus. In this mode the chroma signals are sampled on the rising
edges of the CLKIN clock, along with Y/D1IN
used and these pins should be tied low. Note that the pins are not sequential on this bus.
10-bit non-multiplexed Cr signal input bus. The mode is determined by the settings of the
DVIMode is set to 10 the Cr signal is input on this bus. In this mode the chroma signal is
sampled on alternate rising edges of the CLKIN clock, starting with the first rising edge
following the rising edge of HREFIN. When DVIMode is set to 00 or 01 this bus is not used
and these pins should be tied low.
.
H
allow the I2C address of the device to be programmed to prevent
2-0
80/81H, 88/89H, 90/91H, 98/99H, C0/C1H, C8/C9H, D0/D1H, D8/D9H.
. When MODE
1-0
will put the FLI2220 into test modes and should not be used.
1-0
= 10) f
1-0
is set to 01 the I2C port will operate in Slave mode,
1-0
will be f
SCL
I2CCLK
9-0
allow the slave address to be set to
2-0
is set to 10 the I2C port will
1-0
/33.
. When DVIMode is set to 00 this bus is not
Pin # Name Description
Input Signals (cont.)
38 HBLANKI Horizontal input blanking signal. This signal goes high during the horizontal blanking interval
39 VBLANKI Vertical input blanking signal. This signal goes high during the vertical blanking interval and
42 FLDIN Odd/Even field designator input. When the input signals are interlaced video, the FLDIN
Analog Output Signals
73 G/Y-ANA Analog output. In the RGB mode this output is the Green signal and in the YUV mode it is the
71 R/Cr-ANA Analog output. In the RGB mode this output is the Red signal and in the YUV mode it is the
75 B/Cb-ANA Analog output. In the RGB mode this output is the Blue signal and in the YUV mode it is the
76 COMP Compensation for video DACs. Should be connected to analog ground via a 10 nF capacitor.
77 RSET Current setting resistor for video DACs. A precision resistor placed between this pin and
78 VREF Voltage reference for video DACs. The on-chip reference can be used or overridden by
Digital Output Signals
83-86, G/YOUT
89-92, YUV mode it is the Y or multiplexed Y/Cb/Cr signal. The color mode is determined by the
95-96 setting of the YUV bit, bit 3 in register 50H. Refer to the CSCCTL register description for
115-118, B/UOUT
123-126, mode it is the Cb or multiplexed Cb/Cr signal. The color mode is determined by the setting of
129-130 the YUV bit, bit 3 in register 50H. Refer to the CSCCTL register description for details. The
and low during active video. The polarity of this signal can be inverted by setting InvBlankI
(bit 7 in register 05H) high.
low during active video fields. The polarity of this signal can be inverted by setting InvBlankI
(bit 7 in register 05
signal should be set low during the odd fields and high during the even fields. When the input
signals are progressive (non-interlaced) scan video, the FLDIN signal should always be low.
Y signal. The color mode is determined by the setting of the YUV bit, bit 3 in register 50
Refer to the CSCCTL register description for details. The signal is clocked out on the rising
edges of the YCLKO clock.
Cr signal. The color mode is determined by the setting of the YUV bit, bit 3 in register 50
Refer to the CSCCTL register description for details. The signal is clocked out on the rising
edges of the YCLKO clock.
Cb signal. The color mode is determined by the setting of the YUV bit, bit 3 in register 50
Refer to the CSCCTL register description for details. The signal is clocked out on the rising
edges of the YCLKO clock.
analog ground sets the full-scale DAC currents. Refer to the DAC Output section for details.
connecting an external reference to this pin. In either case, it should be decoupled to analog
ground. Refer to the DAC Output section for details.
Green or luminance output bus. In the RGB mode this output is the Green signal and in the
9-0
details. The format is determined by the settings of the DVOMode bits. Refer to the
DVOMode register, bits 5-4 in register 09
DVOMode is set to 01 or 10 the Y signal is clocked out on the rising edges of the YCLKO
clock. When DVOMode is set to 00 the output on this bus will be the multiplexed Y/Cb/Cr
signal; this mode is only available when the ITU BT-R601/D1 input mode is selected. The
signal will contain timing information replicated from the input signal.
Blue or Cb chrominance output bus. In the RGB mode this output is the Blue signal, in the YUV
9-0
format is determined by the settings of the DVOMode bits. Refer to the DVOMode register, bit
x in register 09H, description for details. The signal is clocked out on the rising edges of
CCLKO in the 4:2:2 (non-multiplexed chroma) format, when DVOMode is set to 10, and on
the rising edges of the YCLKO clock in the 4:4:4 and multiplexed chroma formats, when
DVOMode is set to 01. When DVOMode is set to 00 this bus is not used.
) high.
H
, description for details. In the YUV mode, when
H
.
H
.
H
.
H
Simplified Block Diagram
HREFI
VREFI
FLDIN
CLKIN
Sync &
Timing
Control
Luma
Larg e-Edge
Enhancer
30
Digital
YUV/
YCrCb
Input
Formatter
Interpolator
Luma
Detail
Enhancer
Line
Memories
SCL
I2C
Interface
Control
Registers
Chroma
Larg e-Edge
Enhancer
SDA
Pin # Name Description
Digital Output Signals (cont.)
97-98, R/VOUT
103-106, mode it is the Cr signal; in the multiplexed Y, Cb/Cr and Y/CrCb modes it is not used. The
109-112 color mode is determined by the setting of the YUV bit, bit 3 in register 50
137 YCLKO Output luma sampling clock. This clock is derived from CLKIN and may be at the same
140 CCLKO Output chroma sampling clock. This clock is derived from CLKIN and may be at the same
133 HBLANKO Horizontal output blanking signal. This signal goes high during the horizontal blanking interval
134 VBLANKO Vertical output blanking signal. This signal goes high during the vertical blanking interval of
138 FLDO Odd/Even field designator input. When the input signals are interlaced video, the FLDO signal
External OSD Interface
144-153 OSDY
156-160, OSDC
1-5 multiplexed chroma signal is input on this bus. The CLKIN signal should be used to drive the
6 OSDSEL External OSD Select input. This signal is used internally to switch between the video and the
Test Inputs (Not shown on block diagram)
70-69, TEST
143
19 TESTB Active low test input. This pin should be tied to V
Test Outputs (Not shown on block diagram)
7-10, TESTO
13-15
Red or Cr chrominance output bus. In the RGB mode this output is the Red signal, in the YUV
9-0
CSCCTL register description for details. The format is determined by the settings of the
DVOMode bits. Refer to the DVOMode register, bits 5-4 in register 09
details. The signal is clocked out on the rising edges of the YCLKO clock in the 4:4:4 mode
and on the rising edges of the CCLKO clock in the 4:2:2 mode. This bus is not used when
DVOMode is set to 00 or 01.
frequency or double the frequency of CLKIN, depending on the setting of, bit 4 in register 02
When this bit is set high, the frequency of YCLKO will be double that of CLKIN, and when it
is set low they will be equal, indicating that the output decimator has been turned on.
frequency or half the frequency of CLKIN, depending on the setting of, bit 4 in register 02
When this bit is set high, the frequency of YCLKO will be equal to that of CLKIN, and when it
is set low it will be at half that frequency, indicating that the output decimator is turned on.
of the output signals and low during active video. The polarity of this signal can be inverted by
setting InvBlankO (bit 7 in register 06
the output signals and low during active video fields. The polarity of this signal can be inverted
by setting InvBlankO (bit 7 in register 06
will go low during the odd fields and high during the even fields. When the input signals are
progressive, or non-interlaced, video, the FLDO signal will always be low. This signal is a
delayed version of FLDIN.
External OSD luma input. When the external OSD mode is used the 10-bit luma signal is input
9-0
on this bus. The CLKIN clock should be used to drive the source of this signal, as shown in the
timing diagrams, unless the video input mode selected is the ITU BT-R601 (multiplexed luma
and chroma) mode, in which case the chroma output clock, CCLKO, should be used instead.
External OSD multiplexed chroma input. When the external OSD mode is used the 10-bit
9-0
source of this signal, as shown in the timing diagrams, unless the video input mode selected is
the ITU BT-R601 (multiplexed luma and chroma) mode. In this case the chroma output clock,
CCLKO, should be used instead.
graphics signals on a pixel by pixel basis. Bit 7 in register 40H must be set high to enable this
function.. When this pin is set high the OSDY
FLI2220 output signals, and when it is set low the video inputs will pass through to the
FLI2220 outputs.
Active high test inputs. These pins should all be tied to VSS for normal operation.
2-0
Test outputs. These pins should all be left unconnected for normal operation.
6-0
) high.
H
) high.
H
and OSDC
9-0
for normal operation.
DD
9-0
, description for
H
signals will pass through to the
. Refer to the
H
Triple
10-b it DAC
Analog
YUV/
RGB
Color-Space
Converter
& Output
Formatter
30
Digital
YUV
YCrCb/
RGB
External
OSD
Decimator
(Optional)
OSD
Engine &
Interface
.
H
.
H
55 56
Page 52
11. EXPLODED VIEW AND PARTS LIST
391G
361Gx4
390G
340G
5128
3X8( U)
x6
5128
3X6( A)
x4
UN02
205Gx2
160B
165B
5182
2X4( U)
x3
5182
2X4( U)
170B
M701
x3
215G
477Gx2
UN01
UN04
5128
3X6( A)
392G
415G
5126
3X10( A)
x7
338G
463G
5128
3X10( A)
x6
460G
154G
5128
3X15( A)
380G
5110
3X6( A)
x2
x2
P904
A
A
306G
TH02
E
C
5128
3X5( U)
305G
262G
260G
5128
3X6( A)
x2
051B
150G
5148
3X8( A)
x2
P503
UN03
(UN03)
(160G)
261G
5128
3X6( A)
x4
(471Gx4)
5128
3X6( A)
x4
220G
P501
P502
185B
(165G)
5128
3X8( U)
x3
224Gx4
P906
106B
x
2
107Bx2
(170G)
115B
902
P
P905
5110
A
3X6(
x3
(175G)
(470G)
(180Gx2)
100B
)
116B
110B
109B
051S
5110
3X8( K)
5128
3X6( U)
x3
001B
130B
145B
053S( N, U ONLY)
053S( K ONLY)
x3
UONLY
058S
135B
350G
C
D
150B
5110
3X8(K)
x2
154B
5110
3X6( A)
5128
2. 6X8( A)
x3
156B
5150
3X8( K)
x4
030Cx2
040Cx2
041Cx2
025Cx2
035Cx2
157B
003B
5128
3X15( A)
x2
001C
x2
5128
3X8( U)
x2
5128
3X5( U)
5128
3X8( K)
x4
x2
B
B
5110
4X10( A)
x4
061B
396G
D
050B
001G
5128
3X8( U)
x2
055B
5128
3X8( K)
395Gx4
5110
3X6( A)
041Bx4
5110
3X6( A)
x4
055S
UONLY
057S
031B
035B
038B
039B
032B
5128
3X8( U)
034B
5128
3X8( U)
x4
5110
4X6( A)
x4
013B
053B
025Bx3
015B
018B
019B
017B
5128
3X6( A)
x5
P901
P903
348Gx2
E
5128
3X6( A)
x7
200G
A
A
344G
345G
346G
B
SYMBOL STY L E
5110
5126
5128
5148
5150
5182
5402
PARTS NAME
+B.H.M.SCREW
+B. H. TAP TI TE SCREWW/ WASHER
+B. H. TAP TI TE SCREW(B T YPE)
+B.H.M.SCREW(W/WASHER)
+F . H. TAP TI TE SCREW(B T YPE)
+P.H.M.SCREW(MINUTE)
FL AT WASHERS
MARK M ATERIA L / FIN ISH
( U) STEEL / BL ACK
( A ) S TEEL / CHROMATE
( K) ST EEL/ NI CKEL
5857
Page 53
5128
3X6( A)
x4
310G
393G
394G
411G
360Gx6
5128
3X6( A)
x9
300G
5128
3X25( U)
x2
M702
5110
3X6( A)
x2
P101
5110
3X6( A)
x2
475Gx2
P401
5128
3X6( A)
x9
5128
3X6( A)
x4
P201
5128
3X20( U)
x2
473Gx4
452G
014G
450G
M701
5128
3X6( A)
x2
332G
451G
462G
461G
5128
3X6( A)
256G
P202
P801
400G
5128
3X6( A)
x6
P601
257Gx6
002G
230G
254G
5110
3X6( A)
x6
245Gx3
P701
255Gx6
5128
3X6( A)
x2
5128
3X8( A)
x6
026G
027Gx2
M703
5128
3X12(A)
035G
105G, 110G
x3
301Gx3
5128
3X6( A)
x3
138Gx3
59
464G
001G
342G
P904
5128
3X6( A)
x2
Page 54
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
001B 413V064010 CASE TOP 413V064010
003B 413V003010 PERFORATED
413V003010
FOR BOTTOM CASE
013B 413V270010 BUTTON MAIN FRAME 413V270010
015B 413V270020 BUTTON KEY TOP PWR 413V270020
025B 413V151010 INTRODUCER LED 413V151010
031B 413V154010 KNOB 3-DIRECTION 413V154010
032B 413V354020 LEVER FOR 030B KNOB 413V354020
035B 413V353010 RING 3-DIRECTION 413V353010
039B 413V115010 SPRING 3DIRECTION KNOB 413V115010
050B 413V064020 CASE BOTTOM 413V064020
053B 413V158010 WINDOW IR FRONT 413V158010
055B 413V057010 LEG FOR CASE BOTTOM 413V057010
100B 413V250010 REAR PANEL I/O TERMINAL 413V250010
107B 183J010010 SCREW FOR IR REAR PCB 183J010010
110B 413V158020 WINDOW IR REAR 413V158020
115B 413V063010 ESCUTCHEON I/O TERMINAL 413V063010
130B 413V257050 LID LAMP 413V257050
135B 413V010020 SCREW LAMP LID 413V010020
150B 413V053010 COVER FRONT 413V053010
154B 413V257060 LID FOR COVER FRONT 413V257060
156B 413V110010 SHIFTER FOR COVER FRONT 413V110010
160B 413V154140 KNOB ZOOM RING 413V154140
165B 413V154130 KNOB FOCUS RING 413V154130
170B 413V063020 ESCUTCHEON FOCUS RING 413V063020
185B 413V154020 KNOB LENS SHIFT 413V154020
001C 413V164510 ADJ LEG ASSY 413V164510
005C 413V064110 CASE ADJ LEG 413V064110
010C 413V102110 LOCK ADJ LEG 413V102110
015C 413V354110 LEVER ADJ LEG 413V354110
020C 413V115110 SPRING ADJ LEG 413V115110
025C 413V112010 SHAFT ADJ. LEG 413V112010
030C 413V353020 RING ADJ. LEG 413V353020
035C 413V057010 LEG ADJ. LEG 413V057010
040C 64000500X0 E-RING LEG SHAFT 64000500X0
014G 413V257090 LID FOR FAN TOTO(M701) 413V257090
026G 413V120390 INSULATOR FOR FAN 413V120390
035G ZK413V0060 COLOR WHEEL UNIT ZK413V0060
105G YJ90014510 JACK CLGA INTERPOSER 252
YJ90014510
CONTACTS
110G YJ90014500 JACK
YJ90014500
CLAMP CLGA INTERPOSER
115G 413V104040 RETAINER DMD HEAT SINK 413V104040
120G 413V010030 SCREW FIX DMD MODULE 413V010030
130G 413V005010 CLAMPER DMD HEAT SINK 413V005010
138G 4220005030 CLAMPER FOR WIRE 4220005030
150G 413V064030 CASE LAMP HOUSE 413V064030
165G 413V116010 LEAF SPRING LAMP FIX 413V116010
170G 413V257040 LID LAMP CARTRIDGE 413V257040
180G 413V010020 SCREW LAMP BRACKET 413V010020
224G 396B010030 SCREW D-SUB TERMINAL 396B010030
M701 MM01200370 D.C MOTOR
MM01200370
FAN MOTOR FBA06T12L
M702 MM01200390 D.C MOTOR
MM01200390
SCILOCCO FAN TYF300J06
M703 MM01200360 D.C MOTOR
MM01200360
SILOCCO FAN FAL6F12LLS
M704 MM01200120 D.C MOTOR
MM01200120
FRONT FAN FBL06A12H
P101 ZZ413V1000 FORMATTER PCB ASS’Y ZZ413V1000
P301 ZZ413V3000 DMD PCB ASS’Y ZZ413V3000
P601 ZZ413V6000 IFC PCB ASS’Y ZZ413V6000
P701 ZZ413V7000 SSB1 PCB ASS’Y ZZ413V7000
P801 ZZ413V8000 SSB2 PCB ASS’Y ZZ413V8000
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
TH02 FR30090010 CIRCUIT BREAKER 67L110 FR30090010
UN01 ZK413V0020 UNIT KIT
ZK413V0020
BALLAST PS-213-LC-170-SS
UN02 ZK413V0030 UNIT KIT
ZK413V0030
POWER SUPPLY NZ01
UN03 ZK413V0040 UNIT KIT LAMP SHP ZK413V0040
UN04 ZK413V0070 UNIT KIT OPTICAL ENGINE ZK413V0070
W001 YU50045510 JUMPER LEAD FFC 50P
YU50045510
(J005-J323)
W002 YU08200520 JUMPER LEAD FFC 8P
YU08200520
1.0MM 200MM
PACKING
001T F USER GUIDE 413V851110
001T K USER GUIDE 413V851350
001T N 413V851310 USER GUIDE 413V851310
001T U USER GUIDE 413V851250
001Z ZK413V0010 REMOTE CONTROLLER RC05
ZK413V0010
RC12VP-S1
035Z 413V067010 CAP PROJECTION LENS 413V067010
040Z U MAINS CORD 3P 10A 125V AC ZC01802110
043Z N ZC02003190 MAINS CORD 3P 10A 250V AC ZC02003190
045Z K MAINS CORD 3P 10A 250V ZC01804100
047Z F MAINS CORD 3P 7A 125V ZC01801070
NOT STANDARD
SPEAR PARTS
010S 413V809010 CUSHION LEFT 413V809010
015S 413V809020 CUSHION RIGHT 413V809020
035S 413V801010 PACKING CASE 413V801010
60
Page 55
12. ELECTRICAL PARTS LIST
ASSIGNMENT OF COMMON PARTS CODES.
RESISTORS
R : 1) GD05 × × × 140, Carbon film fixed resistor, ±5% 1/4W
R : 2) GD05 × × × 160, Carbon film fixed resistor, ±5% 1/6W
Examples ;
Resistance value
➀
0.1 Ω.... 001 10 Ω .... 100 1 kΩ .... 102 100 kΩ .... 104
0.5 Ω.... 005 18 Ω .... 180 2.7 kΩ .... 272 680 kΩ .... 684
1 Ω .... 010 100 Ω .... 101 10 kΩ .... 103 1 MΩ.... 105
6.8 Ω.... 068 390 Ω .... 391 22 kΩ .... 223 4.7 MΩ .... 475
Note : Please distinguish 1/4W from 1/6W by the shape of parts
used actually.
CAPACITORS
C : CERAMIC CAP.
3) DD1 × × × × 370, Ceramic capacitor
Examples ;
Tolerance (Capacity deviation)
➁
±0.25 pF .... 0
Tolerance of COMMON PARTS handled here are as follows :
C : CERAMIC CAP.
Examples ;
C : 5) ELECTROLY CAP. ( ), 6) FILM CAP. ( )
Examples ;
0.5 pF 5 pF .... ±0.25 pF
Capacity value
➂
0.5 pF ....005 3 pF .... 030 100 pF .... 101
1.5 pF ....015 47 pF .... 470 560 pF .... 561
4) DK16 × × × 300, High dielectric constant ceramic
Capacity value
➃
100 pF .... 101 1000 pF .... 102 10000 pF .... 103
470 pF .... 471 2200 pF .... 222
5) EA × × × × × × 10, Electrolytic capacitor
Capacity value
➄
0.1 µF....104 4.7 µF .... 475 100 µF ....107
0.33 µF....334 10 µF ....106 330 µF ....337
Working voltage
➅
{
➂
{
{
➅
Resistance value
Disc type
Temp.coeff.P350 N1000, 50V
Capacity value
Tolerance
capacitor
Disc type
Temp.chara. 2B4, 50V
Capacity value
One-way lead type, Tolerance ±20%
Working voltage
Capacity value
2200 µF ....228
➀
{
➁
±0.5 pF .... 1
±5% .... 5
6 pF 10 pF .... ±0.5 pF
12 pF 560 pF .... ±5%
1 pF .... 010 10 pF .... 100 220 pF .... 221
➃
{
➄
1 µF....105 22 µF .... 226 1100 µF ....118
6.3V....006 25V ....025
10V ....010 35V .... 035
16V ....016 50V .... 050
NOTE ON SAFETY FOR FUSIBLE RESISTOR :
The suppliers and their type numbers of fusible resistors
are as follows;
1. KOA Corporation
Part No. (MJI) Type No. (KOA) Description
NH05 × × × 140 RF25S × × × × ΩJ(±5% 1/4W)
NH05 × × × 120 RF50S × × × × ΩJ(±5% 1/2W)
NH85 × × × 110 RF73B2A × × × × ΩJ(±5% 1/10W)
NH95 × × × 140 RF73B2E × × × × ΩJ(±5% 1/4W)
2. Matsushita Electronic Components Co., Ltd
Part No. (MJI) Type No. (MEC) Description
NF05 × × × 140 ERD-2FCJ × × × (±5% 1/4W)
RF05 × × × 140
NF02 × × × 140
RF02 × × × 140
Examples ;
{
Resistance value
ERD-2FCG
{
Resistance value
Resistance value
0.1 Ω.... 001 10 Ω .... 100 1 kΩ .... 102 100 kΩ .... 104
0.5 Ω.... 005 18 Ω .... 180 2.7 kΩ .... 272 680 kΩ .... 684
1 Ω .... 010 100 Ω .... 101 10 kΩ .... 103 1 MΩ.... 105
6.8 Ω.... 068 390 Ω .... 391 22 kΩ .... 223 4.7 MΩ .... 475
{
Resistance value
(0.1 Ω − 10 kΩ)
× × × (±2% 1/4W)
{
Resistance value
ABBREVIATION AND MARKS
ANT. : ANTENNA BATT. : BATTERY
CAP. : CAPACITOR CER. : CERAMIC
CONN. : CONNECTING DIG. : DIGITAL
HP : HEADPHONE MIC. : MICROPHONE
µ-PRO : MICROPROCESSOR REC. : RECORDING
RES. : RESISTOR SPK : SPEAKER
SW : SWITCH TRANSF. : TRANSFORMER
TRIM. : TRIMMING TRS. : TRANSISTOR
VAR. : VARIABLE X’TAL : CRYSTAL
NOTE ON FUSE :
Regarding to all parts of parts code FS20xxx2xx, replace
only with Wickmann-Werke GmbH, Type 372 non glass type
fuse.
6) DF15 × × × 350 Plastic film capacitor
DF15 × × × 310 One-way type, Mylar ±5% 50V
DF16 × × × 310 Plastic film capacitor
Examples ;
Capacity value
➆
0.001 µF (1000 pF) ....... 102 0.1 µF ....104
0.0018 µF ........................ 182 0.56 µF....564
0.01 µF........................ 103 1 µF .... 105
0.015 µF ........................ 153
: 1) The above CODES ( R , R , C , C and
NOTE
C ) are omitted on the schematic diagram in some
case.
2) On the occasion, be confirmed the common parts on
the parts list.
3) Refer to “Common Parts List” for the other common
parts (RI05, DD4, DK4).
➆
{
One-way type, Mylar ±10% 50V
Capacity value
NOTE ON SAFETY :
Symbol Fire or electrical shock hazard. Only original
parts should be used to replaced any part marked with
symbol . Any other component substitution (other
than original type), may increase risk of fire or electrical
shock hazard.
010728MIT
61
Page 56
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
P101-FORMATTER
CIRCUIT BOARD
P101 ZZ413V1000 P101-FORMATTER
ZZ413V1000
CIRCUIT BOARD ASS’Y
P201-FAN
CIRCUIT BOARD
P201-CAPACITORS
C801 DK5610520R CER. CHIP 1µF 16V ±10% B DK5610520R
C802 EY47601620 ELECT. CHIP 47µF 16V EY47601620
C803 DK5610520R CER. CHIP 1µF ±10% B 16V DK5610520R
C804 EY47601620 ELECT. CHIP 47µF 16V EY47601620
C805 DK5610520R CER. CHIP 1µF ±10% B 16V DK5610520R
C806 EY47601620 ELECT. CHIP 47µF 16V EY47601620
C807 EY47403530 TANTL. CHIP 0.47µF 35V EY47403530
C808 EY47601620 ELECT. CHIP 47µF 16V EY47601620
C809 EY47403530 TANTL. CHIP 0.47µF 35V EY47403530
C810 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C811 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C812 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C813 EY10701620 ELECT. CHIP 100µF 16V EY10701620
C814 nsp CER. CHIP 0.47µF +80%-20% DK98474200
C815
nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C818
P201-RESISTORS
Ω
R801 nsp CHIP 2.2k
R802 nsp CHIP 33k
R803 nsp CHIP 2.2k
R804 nsp CHIP 47k
R805 nsp CHIP 4.7k
R806 nsp CHIP 2.2k
R807 nsp CHIP 22k
R808 nsp CHIP 2.2k
R810 nsp CHIP 4.7k
R811 nsp CHIP 2.2k
R812 nsp CHIP 47k
R813 nsp CHIP 2.2k
R815 nsp CHIP 4.7k
R816 nsp CHIP 2.2k
R817 nsp CHIP 22k
R818 nsp CHIP 2.2k
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05333610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05472610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05223610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05472610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05472610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05223610
Ω
±5% 1/16W NN05222610
R820 nsp CHIP 4.7k
R821 nsp CHIP 100k
R823 nsp CHIP 2.2k
R824 nsp CHIP 1k
R826 nsp CHIP 22k
R827 nsp CHIP 27k
R831 nsp CHIP 15k
R832 nsp CHIP 15k
R833 nsp CHIP 15k
R834 nsp CHIP 15k
R835 nsp CHIP 33k
R836 nsp CHIP 33k
R837 nsp CHIP 33k
R838 nsp CHIP 22k
R839 nsp CHIP 10k
Ω
±5% 1/16W NN05472610
Ω
±5% 1/16W NN05104610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05102610
Ω
±5% 1/16W NN05223610
Ω
±5% 1/16W NN05273610
Ω
±5% 1/16W NN05153610
Ω
±5% 1/16W NN05153610
Ω
±5% 1/16W NN05153610
Ω
±5% 1/16W NN05153610
Ω
±5% 1/16W NN05333610
Ω
±5% 1/16W NN05333610
Ω
±5% 1/16W NN05333610
Ω
±5% 1/16W NN05223610
Ω
±5% 1/16W NN05103610
P201-SEMICONDUCTORS
D801 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D802 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D803 HZ 21105000 CHIP DIODE 1SS361 DAN222 HZ21105000
D804 HZ20032050 CHIP DIODE U1BC44 HZ20032050
D805 HZ20032050 CHIP DIODE U1BC44 HZ20032050
D806 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D807 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D808 HZ 21105000 CHIP DIODE 1SS361 DAN222 HZ21105000
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
D809 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D810 HZ20032050 CHIP DIODE U1BC44 1A HZ20032050
D811 HZ31303050 CHIP DIODE 02CZ3.0X HZ31303050
ICJ1
HC91915210 IC BA00ASFP HC91915210
ICJ4
ICJ5 HC10174990 IC OPA2353 HC10174990
Q801 BA21107000 DIG. TRS. DTC114YE BA21107000
Q802 BA12107000 DIG. TRS. DTA114YE BA12107000
Q803 BA21107000 DIG. TRS. DTC114YE BA21107000
Q804 BA12107000 DIG. TRS. DTA114YE BA12107000
Q805 BA21107000 DIG. TRS. DTC114YE BA21107000
Q806 BA12107000 DIG. TRS. DTA114YE BA12107000
Q807 BA21107000 DIG. TRS. DTC114YE BA21107000
Q808 BA12107000 DIG. TRS. DTA114YE BA12107000
Q809 HX346172A0 CHIP TRS. 2SC4617 Q R HX346172A0
Q810 BA21107000 DIG. TRS. DTC114YE BA21107000
P201-MISCELLANEOU
J016 YJ07026380 JACK CFP0508-0201 FFC YJ07026380
M701 MM01200370 D.C MOTOR
MM01200370
FAN MOTOR FBA06T12L
P202-LEAF SW
CIRCUIT BOARD
S701 SC01010570 SWITCH SPPB6A0400 SC01010570
P301-DMD
CIRCUIT BOARD
P301 ZZ413V30 00 P301-DMD
ZZ413V3000
CIRCUIT BOARD ASS’Y
P401-EXTEND
CIRCUIT BOARD
J010 YP06902270 PLUG 1-353284-0 YP06902270
J011 YJ06031710 JACK 100R-JMDSS YJ06031710
J012 YJ06031710 JACK 100R-JMDSS YJ06031710
P501-IO1
CIRCUIT BOARD
P501-CAPACITORS
C326 nsp CER. CHIP 1µF 10V F DK98105200
C329 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C330 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C331 nsp CER. CHIP 1µF 10V F DK98105200
P501-RESISTORS
R321 nsp CHIP 220
R327 nsp CHIP 0
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05000610
P501-MISCELLANEOUS
J301 YT03040440 TERMINAL UV31413-M1 YT03040440
J303 YT02010610 TERMINAL YKB11-0736 YEL YT02010610
J304 YJ11000670 JACK YKF51-5527 YJ11000670
J305 YT02030690 TERMINAL YKC21-5870 YT02030690
J307 YP11000210 PLUG DZ11AA1-B2 YP11000210
J319 YJ15000210 OPT. CONNECTOR JFJ300 YJ15000210
J410 YP06021730 PLUG 50PS-JMDSS-G-1-TF YP06021730
L301
FM31101020 EMI FILTER FM31101020
L314 NFM2012R03C101R
S302 SP01011610 PUSH SWITCH SKHHLRA010 SP01011610
62
Page 57
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
P502-IO2
CIRCUIT BOARD
P502-CAPACITORS
C309 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C310 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C324 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C325 EY10601070 TANTL. CHIP 10µF 10V EY10601070
C328 EY10601070 TANTL. CHIP 10µF 10V EY10601070
P502-RESISTORS
Ω
R312 nsp CHIP 47
R314 nsp CHIP 47k
R315 nsp CHIP 100k
R316 nsp CHIP 2.2k
R317 nsp CHIP 10k
R319 nsp CHIP 47
R320 nsp CHIP 33
R323 nsp CHIP 10k
±5% 1/16W NN05470610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05104610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05103610
Ω
±5% 1/16W NN05470610
Ω
±5% 1/16W NN05330610
Ω
±5% 1/16W NN05103610
P502-SEMICONDUCTORS
D323 HZ20018050 CHIP DIODE 1SS302 HZ20018050
D324 HZ20028050 CHIP DIODE 1SS301 HZ20028050
Q301 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
Q302 BA10016050 DIG. TRS. RN2305 BA10016050
P502-MISCELLANEOUS
J308 YP11000220 PLUG DZ101A1-B2 YP11000220
J309 YJ01004730 JACK LGY6502-0600 YJ01004730
J310 YJ01004730 JACK LGY6502-0600 YJ01004730
J311 YJ01004730 JACK LGY6502-0600 YJ01004730
J312 YJ01004730 JACK LGY6502-0600 YJ01004730
J318 YT02011720 TERMINAL YKB11-0969 YT02011720
J408 YP06021720 PLUG 20PS-JMDSS-G-1-TF YP06021720
L315
FM31101020 EMI FILTER FM31101020
L318 FM31101020 NFM2012R03C101R FM31101020
L321 TP41042030 PULSE TRANSF.
TP41042030
TPS247MN-0386AN
S301 SS02021690 SLIDE SWITCH SSSF12 2-2 SS02021690
S303 SS02021690 SLIDE SWITCH SSSF12 2-2 SS02021690
P503-IO BASE
CIRCUIT BOARD
P503-CAPACITORS
C301
nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C305
C306 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C307 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C308 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C311 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C312 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C313 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C314 nsp CER. CHIP 0.01µF ±10% 50V DK96103300
C315 nsp CER. CHIP 100pF ± 5% CH 50V DD95101300
C316 nsp CER. CHIP 100pF ± 5% CH 50V DD95101300
C317 EY10702560 TANTL. CHIP 100µF 25V EY10702560
C318 EY10601070 TANTL. CHIP 10µF 10V EY10601070
C319 EY10701620 TANTL. CHIP 100µF 16V EY10701620
C320 EY10701620 ELECT. CHIP 100µF 16V EY10701620
C321 EY10601070 TANTL. CHIP 10µF 10V EY10601070
C322 EY10701620 ELECT. CHIP 100µF 16V EY10701620
C323 EY10701620 ELECT. CHIP 100µF 16V EY10701620
P503-RESISTORS
R301 nsp CHIP 2.2k
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
Ω
±5% 1/16W NN05222610
VERS.
POS.
COLOR
NO
R302 nsp CHIP 47k
PART NO.
(FOR EUR)
DESCRIPTION
Ω
±5% 1/16W NN05473610
PART NO.
(MJI)
R303
nsp CHIP 100Ω ±5% 1/16W NN05101610
R306
R307 nsp CHIP 2.2k
R308 nsp CHIP 2.2k
R309 nsp CHIP 22
R310 nsp CHIP 100
R311 nsp CHIP 22
R313 nsp CHIP 22k
R318 nsp CHIP 22k
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05220610
Ω
±5% 1/16W NN05101610
Ω
±5% 1/16W NN05220610
Ω
±5% 1/16W NN05223610
Ω
±5% 1/16W NN05223610
P503-SEMICONDUCTORS
D301
HZ2001 8050 CHIP DIODE 1SS302 HZ20018050
D306
D307 HZ20028050 CHIP DIODE 1SS301 HZ20028050
D308
HZ2001 8050 CHIP DIODE 1SS302 HZ20018050
D314
D315
HZ 30022050 CHIP DIODE 02CZ24-Y HZ30022050
D322
D325 HZ20032050 CHIP DIODE U1BC44 HZ20032050
D326 HZ20032050 CHIP DIODE U1BC44 HZ20032050
IC61 HC700405Q0 IC 74HCT04AF HC700405Q0
IC62 HC10180990 IC AT24C21-10SC-2.5 HC10180990
IC63 HC10219090 IC NJM2370 HC10219090
IC64 HC10219090 IC NJM2370 HC10219090
Q303 BA12107000 DIG. TRS. DTA114YE BA12107000
Q304 BA21107000 DIG. TRS. DTC114YE BA21107000
Q305 BA12107000 DIG. TRS. DTA114YE BA12107000
Q306 BA21107000 DIG. TRS. DTC114YE BA21107000
P503-MISCELLANEOUS
J411 YJ06031720 JACK 20R-JMDSS-G-1-TF YJ06031720
J412 YJ06031730 JACK 50R-JMDSS-G-1-TF YJ06031730
L319 LU17103010 CHIP INDUCTANCE 10µH
LU17103010
NLC322522T-101K
L320 LU17103010 CHIP INDUCTANCE 10µH
LU17103010
NLC322522T-101K
P601-IFC
CIRCUIT BOARD
P601 ZZ413V6000 P601-IFC
ZZ413V6000
CIRCUIT BOARD ASS’Y
P701-SSB 1
CIRCUIT BOARD
P701 ZZ413V7000 P701-SSB 1
ZZ413V7000
CIRCUIT BOARD ASS’Y
P801-SSB 2
CIRCUIT BOARD
P801 ZZ413V8000 P801-SSB 2
ZZ413V8000
CIRCUIT BOARD ASS’Y
P901-IR-F
CIRCUIT BOARD
C851 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C852 EY47601030 TANTL. CHIP 47µF 10V EY47601030
D851 HW10004210 PHOTO UNIT RPM6936-V4 HW10004210
R851 nsp CHIP 22
R852 nsp CHIP 100
Ω
±5% 1/16W NN05220610
Ω
±5% 1/16W NN05101610
63
Page 58
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
P902-IR-R
CIRCUIT BOARD
C853 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C854 EY47601030 TANTL. CHIP 47µF 10V EY47601030
D852 HW10004210 PHOTO UNIT RPM6936-V4 HW10004210
Ω
R853 nsp CHIP 22
R854 nsp CHIP 100
±5% 1/16W NN05220610
Ω
±5% 1/16W NN05101610
P903-KEY
CIRCUIT BOARD
P903-CAPACITORS
C4W1 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C4W2 EY10501610 TANTL. CHIP 1µF 16V EY10501610
C4W4 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C4W5 EY10501610 TANTL. CHIP 1µF 16V EY10501610
C4W7 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C4W8 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C4W9 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C4X0 EY10501610 TANTL. CHIP 1µF 16V EY10501610
P903-RESISTORS
Ω
R451 nsp CHIP 1.5k
R452 nsp CHIP 1k
R453 nsp CHIP 1.5k
R456 nsp CHIP 1.5k
R457 nsp CHIP 1k
R458 nsp CHIP 1.5k
R459 nsp CHIP 1.5k
R460 nsp CHIP 1k
R461 nsp CHIP 1.5k
R462 nsp CHIP 220
R463 nsp CHIP 220
R464 nsp CHIP 220
R465 nsp CHIP 2.2k
R471 nsp CHIP 47k
R473 nsp CHIP 10k
R474 nsp CHIP 2.2k
R475 nsp CHIP 2.2k
R476 nsp CHIP 47k
R477 nsp CHIP 47k
R478 nsp CHIP 10k
R479 nsp CHIP 10k
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05102610
Ω
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05102610
Ω
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05102610
Ω
±5% 1/16W NN05152610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05103610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05222610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05473610
Ω
±5% 1/16W NN05103610
Ω
±5% 1/16W NN05103610
P903-SEMICONDUCTORS
D4W1 HZ20018050 CHIP DIODE 1SS302 HZ20018050
D4W2 HZ20018050 CHIP DIODE 1SS302 HZ20018050
D4W3 HZ20018050 CHIP DIODE 1SS302 HZ20018050
D4W4 HI10042080 L.E.D. SECU1E01C HI10042080
D4W9 HI10107210 L.E.D. SML-010VT HI10107210
D4X0 HI 10107210 L.E.D. SML-010VTT86 HI10107210
ICK1 HC700805I0 IC TC7SET08FU H C700805I0
Q4W1 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
Q4W2 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
Q4W3 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
P903-MISCELLANEOUS
S4W1
SP01012120 PUSH SWITCH SKQGADE010 SP01012120
S4W5
S4W6
SP01013810 PUSH SWITCH SKHUPFE010 SP01013810
S4W9
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
P904-INLET
CIRCUIT BOARD
EN01 YJ04002540 JACK FN9226-3-02 YJ04002540
P905-LED L
CIRCUIT BOARD
C855 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C856 EY10501610 TANTL. CHIP 1µF 16V EY10501610
D880 HI10002980 L.E.D. NSCW100 HI10002980
D881 HI10002980 L.E.D. NSCW100 HI10002980
Q4W4 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
Ω
R855 CHIP 47k
R860 nsp CHIP 100
R861 nsp CHIP 220
R862 nsp CHIP 100
R863 nsp CHIP 220
±5% 1/16W
Ω
±5% 1/16W NN05101610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05101610
Ω
±5% 1/16W NN05221610
nsp NN05473610
P906-LED R
CIRCUIT BOARD
C857 nsp CER. CHIP 0.1µF ±10% B 10V DK96104200
C858 EY10501610 TANTL. CHIP 1µF 16V EY10501610
D882 HI10002980 L.E.D. NSCW100 HI10002980
D883 HI10002980 L.E.D. NSCW100 HI10002980
Q4W5 HX341161C0 CHIP TRS. 2SC4116GR HX341161C0
Ω
R864 nsp CHIP 100
R865 nsp CHIP 220
R866 nsp CHIP 100
R867 nsp CHIP 220
R872 nsp CHIP 47k
±5% 1/16W NN05101610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05101610
Ω
±5% 1/16W NN05221610
Ω
±5% 1/16W NN05473610
64
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