Datasheet L10C11PC20, L10C11JC15, L10C11PC15, L10C11JC20 Datasheet (LOGIC)

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DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

❑❑

❑ Variable Length 4 or 8-bit Wide

Shift Register

❑❑

❑ Selectable Delay Length from 3 to

18 Stages

❑❑

❑ Low Power CMOS Technology ❑❑

❑❑

❑ Replaces Fairchild TMC2011 ❑❑

❑❑

❑ Load, Shift, and Hold Instructions ❑❑

❑❑

❑ Separate Data In and Data Out Pins ❑❑

❑❑

❑ Package Styles Available:

• 24-pin Plastic DIP

• 28-pin Plastic LCC, J-Lead

FEATURES DESCRIPTION

L10C11

4/8-bit Variable Length Shift Register

DEVICES INCORPORATED

The L10C11 is a high-speed, low power CMOS variable length shift register. The L10C11 consists of two 4-bit wide, adjustable length shift registers. These registers share control signals and a common clock. Both shift registers can be programmed together to any length from 3 to 18 stages inclusive, or one register can be fixed at 18 stages of delay while the other is variable. The configuration implemented is determined by the Length Code (L3-0) and the MODE control line as shown in Table 1.

Each input is applied to a chain of registers which are clocked on the rising edge of the common CLK input. These registers are numbered R1 through R17 and R1’ through R17’, corresponding to the D3-0 and D7-4 data fields respectively. A multiplexer serves to route the contents of any of registers R2 through R17 to the output register, denoted R18. A similar multiplexer operates on the contents of R2’ through R17’ to load

R18’. Note that the minimum-length path from data inputs to outputs is R1 to R2 to R18, consisting of three stages of delay.

The MODE input determines whether one or both of the internal shift registers have variable length. When MODE = 0, both D3-0 and D7-4 are delayed by an amount which is controlled by L3-0. When MODE = 1, the D7-4 field is delayed by 18 stages independent of L3-0.

The Length Code (L3-0) controls the number of stages of delay applied to the D inputs as shown in Table 1. When the Length Code is 0, the inputs are delayed by 3 clock periods. When the Length Code is 1, the delay is 4 clock periods, and so forth. The Length Code and MODE inputs are latched on the rising edge of CLK. Both the Length Code and MODE values may be changed at any time without affecting the contents of registers R1 through R17 or R1’ through R17’.

L10C11 BLOCK DIAGRAM

L REGISTER

3-0

7-4

3-0

MODE

CLK

R17 R16 R15

R4 R3 R2

MUX

3-0

7-4

R17’ R16’ R15’

R4’ R3’ R2’

MUX

DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

Length Code Mode = 0 Mode = 1

Delay Delay

L3 L2 L1 L0 Y3-0 Y7-4 Y3-0 Y7-4

0000 33 318 0001 44 418 0010 55 518 0011 66 618 0100 77 718 0101 88 818 0110 99 918 0 1 1 1 1010 1018 1 0 0 0 1111 1118 1 0 0 1 1212 1218 1 0 1 0 1313 1318 1 0 1 1 1414 1418 1 1 0 0 1515 1518 1 1 0 1 1616 1618 1 1 1 0 1717 1718 1 1 1 1 1818 1818

TABLE 1. CONTROL ENCODING

Storage temperature ..................................................... –65°C to +150°C

Operating ambient temperature..................................... –55°C to +125°C

VCC supply voltage with respect to ground...................... –0.5 V to +7.0 V

Input signal with respect to ground .................................. –3.0 V to +7.0 V

Signal applied to high impedance output ......................... –3.0 V to +7.0 V

Output current into low outputs....................................................... 25 mA

Latchup current ......................................................................... > 400 mA

MAXIMUM RATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

OPERATING CONDITIONS

To meet specified electrical and switching characteristics

Symbol Parameter Test Condition Min Typ Max Unit

VOH Output High Voltage VCC = Min., IOH = –12 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 24 mA 0.5 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 10 20 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA

ELECTRICAL CHARACTERISTICS

Over Operating Conditions (Note 4)

Mode Temperature Range Supply Voltage

Active Operation, Com. 0°C to +70°C 4.75 V £ VCC £ 5.25 V

Active Operation, Mil. –55°C to +125°C 4.50 V £ VCC £ 5.50 V

DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

1234567890123456789012345678901212345678901234

23456789012345678901234567890121234567890123

1234567890123456789012345678901212345678901234

L10C11–

Symbol Parameter Min Max Min Max Min Max

tPD Output Delay 30 25 20 tPW Clock Pulse Width 15 12 12 tSD Data Setup Time 25 10 10 tHD Data Hold Time 2 2 0 tSL L3-0, MODE Setup Time 25 10 10 tHL L3-0, MODE Hold Time 2 2 0

1234567890123456

23456789012345

1234567890123456

L10C11–

20 15

Symbol Parameter Min Max Min Max Min Max

tPD Output Delay 25 20 15 tPW Clock Pulse Width 15 12 10 tSD Data Setup Time 20 10 8 tHD Data Hold Time 2 0 0 tSL L3-0, MODE Setup Time 20 10 8 tHL L3-0, MODE Hold Time 2 0 0

COMMERCIAL OPERATING RANGE (0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

MILITARY OPERATING RANGE (–55°C to +125°C)

Notes 9, 10 (ns)

SWITCHING WAVEFORMS

tSL

CLK

tSD tHD

tHL

tPW

tPD

D7-0

L3-0

Y7-0

MODE

2345678901234567890123

*DISCONTINUED SPEED GRADE

DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability.

2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values.

3. This device provides hard clamping of transient undershoot and overshoot. Input levels below ground or above VCC will be clamped beginning at –0.6 V and

VCC + 0.6 V. The device can withstand

indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA.

4. Actual test conditions may vary from those designated but operation is guaranteed as specified.

5. Supply current for a given application can be accurately approximated by:

where

N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency

6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate.

7. Tested with all inputs within 0.1 V of VCC or Ground, no load.

8. These parameters are guaranteed but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except

tDIS test), and input levels of nominally

0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed.

This device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended:

a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common.

b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers.

c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin.

10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time.

11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.

12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V 1.5 V

3.5V Vth

1.5 V

0V Vth

VOL*

Measured V

with IOH = –10mA and IOL = 10mA

Measured V

with IOH = –10mA and IOL = 10mA

FIGURE B. THRESHOLD LEVELS

FIGURE A. OUTPUT LOADING CIRCUIT

DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

23456789012345678901234567890121234567890123456

Plastic DIP

(P2)

L10C11PC20 L10C11PC15

24-pin — 0.3" wide

ORDERING INFORMATION

24-pin — 0.6" wide

0°C to +70°C — COMMERCIAL SCREENING

Speed

20 ns 15 ns

–55°C to +125°C — MIL-STD-883 COMPLIANT

–55°C to +125°C — COMMERCIAL SCREENING

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

CLK

GND MODE Y

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

CLK

GND MODE Y

Plastic DIP

(P1)

Discontinued Package

DEVICES INCORPORATED

L10C11

4/8-bit Variable Length Shift Register

Pipeline Registers

03/27/2000–LDS.11-L

Plastic J-Lead Chip Carrier

(J4)

L10C11JC20 L10C11JC15

28-pin

Speed

20 ns 15 ns

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING

–55°C to +125°C — MIL-STD-883 COMPLIANT

–55°C to +125°C — COMMERCIAL SCREENING

5 6 7 8 9 10 11

25 24 23 22 21 20 19

Top

View

12 17 18

28312

13 14 15 16

NC L

GND GND MODE NC

CLK

D5D6D

7Y7Y6Y5Y4

D2D1D0Y0Y1Y2Y

Datasheet L10C11PC20, L10C11JC15, L10C11PC15, L10C11JC20 Datasheet (LOGIC)

Specifications and Main Features

Frequently Asked Questions

User Manual