Datasheet LTC3568 Datasheet (LINEAR TECHNOLOGY)

LTC3568

1.8A, 4MHz, Synchronous

Step-Down DC/DC Converter

FEATURES

■

Uses Tiny Capacitors and Inductor

■

High Frequency Operation: Up to 4MHz

■

Low R

■

High Effi ciency: Up to 96%

■

Stable with Ceramic Capacitors

■

Current Mode Operation for Excellent Line

Internal Switches: 0.110Ω

DS(ON)

and Load Transient Response

■

Short-Circuit Protected

■

Low Dropout Operation: 100% Duty Cycle

■

Low Shutdown Current: IQ ≤ 1μA

■

Low Quiescent Current: 60μA

■

Output Voltages from 0.8V to 5V

■

Selectable Burst Mode® Operation

■

Sychronizable to External Clock

■

Small 3mm × 3mm, 10-Lead DFN Package

APPLICATIONS

■

Notebook Computers

■

Digital Cameras

■

Cellular Phones

■

Handheld Instruments

■

Board Mounted Power Supplies

DESCRIPTION

The LTC®3568 is a constant frequency, synchronous
step- down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user confi gurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. The output voltage
is adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 2.4A peak current ratings provide
high effi ciency. The LTC3568’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.

The LTC3568 can be confi gured for automatic power sav­ing Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer­ence, the SYNC/MODE pin can be confi gured to skip pulses
or provide forced continuous operation.

To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle)
with a low quiescent current of 60μA. In shutdown, the
device draws <1μA.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst
Mode is a registered trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners. Protected by U.S. Patents including 5481178,
6580258, 6304066, 6127815, 6611131.

TYPICAL APPLICATION

V

2.5V TO 5.5V

SYNC/MODEV

IN

PGOOD

I

TH

SHDN/R

13k

1000pF

NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE

324k

T

Figure 1. Step-Down 1.8A Regulator

LTC3568

PV

IN

SV

IN

SW

V

FB

PGNDSGND

IN

22μF

L1

2μH

887k

412k

3568 F01

V

OUT

2.5V/1.8A

22μF + 10μF

EFFICIENCY (%)

Effi ciency vs Load Current

100

95

90

85

80

75

70

1 100 100001000

EFFICIENCY

POWER LOSS

10

LOAD CURRENT (mA)

VIN = 3.3V

= 2.5V

V

OUT

= 1MHz

f

O

Burst Mode
OPERATION

3568 TA01

1000

POWER LOSS (mW)

100

10

1

3568f

1

LTC3568

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

PVIN, SVIN Voltages .................................... –0.3V to 6V

, ITH, SHDN/RT Voltages ......... –0.3V to (VIN + 0.3V)

V

FB

SYNC/MODE Voltage .................... –0.3V to (V

SW Voltage ................................. –0.3V to (V

+ 0.3V)

IN

+ 0.3V)

IN

PGOOD Voltage ........................................... –0.3V to 6V

SHDN/R

SYNC/MODE

SGND

SW

PGND

TOP VIEW

10

9

8

7

6

I

TH

V

FB

PGOOD

SV

IN

PV

IN

1

T

2

11

3

4

5

Operating Ambient Temperature Range

(Note 2) ...............................................–40°C to 85°C

Junction Temperature (Notes 5, 8) ...................... 125°C

Storage Temperature Range ................... –65°C to 125°C

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

DD PACKAGE

= 125°C, θJA = 43°C/W, θJC = 3°C/W

ORDER PART NUMBER DD PART MARKING

LTC3568EDD LCSG

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specifi ed. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

FB

V

FB

ΔV

LINEREG

ΔV

LOADREG

g

m(EA)

I

S

V

SHDN/RT

f

OSC

f

SYNC

I

LIM

R

DS(ON)

I

SW(LKG)

V

UVLO

Operating Voltage Range 2.25 5.5 V

Feedback Pin Input Current (Note 3) ±0.1 μA

Feedback Voltage (Note 3)

●

0.784 0.8 0.816 V

Reference Voltage Line Regulation VIN = 2.25V to 5V 0.04 0.2 %/V

Output Voltage Load Regulation ITH = 0.36, (Note 3)

I

= 0.84, (Note 3)

TH

●

●

0.02

–0.02

0.2

–0.2

%
%

Error Amplifi er Transconductance ITH Pin Load = ±5μA (Note 3) 800 μS

Input DC Supply Current (Note 4)
Active Mode
Sleep Mode
Shutdown

Shutdown Threshold High
Active Oscillator Resistor

Oscillator Frequency RT = 324k

V

= 0.75V, SYNC/MODE = 3.3V

FB

V

SYNC/MODE

V

SHDN/RT

= 3.3V, VFB = 1V

= 3.3V

(Note 7)

240

62

0.1

VIN – 0.6

324k

350
100

1

VIN – 0.4

1M

0.85 1 1.15
4

μA
μA
μA

Ω

MHz
MHz

Synchronization Frequency (Note 7) 0.4 4 MHz

Peak Switch Current Limit ITH = 1.3 2.4 3 4 A

Top Switch On-Resistance (Note 6) VIN = 3.3V 0.11 0.15

Bottom Switch On-Resistance (Note 6) V

Switch Leakage Current VIN = 6V, V

= 3.3V 0.11 0.15

IN

= 0V, VFB = 0V 0.01 1 μA

ITH/RUN

Ω

Ω

Undervoltage Lockout Threshold VIN Ramping Down 2 2.25 V

V

2

3568f

LTC3568

ELECTRICAL CHARACTERISTICS

The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T

PGOOD Power Good Threshold VFB Ramping Up, SHDN/RT = 1V

RPGOOD Power Good Pull-Down On-Resistance 118 200

= 25°C. VIN = 3.3V, RT = 324k unless otherwise specifi ed. (Note 2)

A

6.8

V

Ramping Down, SHDN/RT = 1V

FB

–7.6

%
%

Ω

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3568 is guaranteed to meet specifi ed performance from
0°C to 85°C. Specifi cations over the –40°C to 85°C operating ambient
termperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3568 is tested in a feedback loop which servos V
midpoint for the error amplifi er (V

= 0.6V).

ITH

to the

FB

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Note 5: T

is calculated from the ambient TA and power dissipation PD

J

according to the following formula:

= TA + (PD • 43°C/W)

T

J

Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.

Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).

Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.

TYPICAL PERFORMANCE CHARACTERISTICS

Burst Mode Operation Pulse Skipping Mode Forced Continuous Mode

V

OUT

10mV/

DIV

S

2V/DIV

V

OUT

10mV/

DIV

S

W

2V/DIV

W

V

OUT

10mV/

DIV

S

2V/DIV

W

500mA/

DIV

I

L

VIN = 3.3V
V
I

LOAD

OUT

= 2.5V

= 100mA

10μs/DIV

3568 G01

200mA/

DIV

I

L

Effi ciency vs Load Current Effi ciency vs V

100

Burst Mode

OPERATION

95

90

85

EFFICIENCY (%)

80

PULSE SKIP

75

70

1 100 1000 10000

FORCED CONTINUOUS

VIN = 3.3V
V

OUT

CIRCUIT OF FIGURE 7

10

LOAD CURRENT (mA)

= 2.5V

3568 G04

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

2.5 3.5 4.5 5.53.0 4.0 5.0 6.0

VIN = 3.3V

= 2.5V

V

OUT

= 100mA

I

LOAD

I

= 500mA

OUT

I

= 1.8A

OUT

V

= 2.5V

OUT

CIRCUIT OF FIGURE 7

2μs/DIV

IN

VIN (V)

3568 G02

3568 G05

500mA/

DIV

V

OUT

100mV/

DIV

1A/
DIV

I

L

VIN = 3.3V

= 2.5V

V

OUT

= 100mA

I

LOAD

Load Step

I

L

VIN = 3.3V

= 2.5V

V

OUT

= 180mA TO 1.8A

I

LOAD

2μs/DIV

50μs/DIV

3568 G03

3568 G06

3568f

3

LTC3568

TYPICAL PERFORMANCE CHARACTERISTICS

Load Regulation Line Regulation Frequency vs V

0.6

0.5

0.4

0.3
PULSE SKIP

0.2

0.1

ERROR (%)

0

OUT

CONTINUOUS

V

–0.1

–0.2

–0.3

–0.4

1 10 100 1000 10000

Burst Mode
OPERATION

FORCED

LOAD CURRENT (mA)

VIN = 3.3V
V

= 1.8V

OUT

3568 G07

0.20
V

= 1.8V

OUT

0.15

0.10

I

= 1.8A

0.05

0

ERROR (%)

–0.05

OUT

V

–0.10

–0.15

–0.20

2.0 3.0 4.0 5.02.5 3.5 4.5 5.5 6.0

OUT

VIN (V)

I

OUT

= 500mA

3568 G08

10

V

OUT

8

I

OUT

= 25°C

T

A

6

4

2

0

–2

–4

FREQUENCY VARIATION (%)

–6

–8

–10

2 3 4 5 6

Frequency Variation
vs Temperature Effi ciency vs Frequency

10

8

6

4

2

0

–2

–4

REFERENCE VARIATION (%)

–6

–8

–10

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

3568 G10

100

95

EFFICIENCY (%)

90

85

0

12

FREQUENCY (MHz)

IN

= 1.8V

= 1.25A

VIN (V)

VIN = 3.3V

= 2.5V

V

OUT

= 500mA

I

OUT

= 25°C

T

A

34

3568 G11

3568 G09

4

R

vs V

DS(ON)

120

TA = 25°C

115

110

(mΩ)

105

DS(ON)

R

100

95

90

2.5 3 3.5 4 4.5 5 5.5 6

IN

SYNCHRONOUS SWITCH

MAIN SWITCH

VIN (V)

3568 G12

R

vs Temperature

DS(ON)

160

150

140

130

120

110

DS(ON)

R

100

VIN = 3.3V

90

80

70

60

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

VIN = 2.5V

VIN = 5V

MAIN SWITCH
SYNCHRONOUS SWITCH

3568 G13

3568f

PIN FUNCTIONS

LTC3568

SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing
this pin to SV

causes the device to be shut down. In

IN

shutdown all functions are disabled.

SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op­eration of the device. When tied to SV

or SGND, Burst

IN

Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SV

, the forced

IN

continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.

SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be con­nected to this ground (see Board Layout Considerations).

SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV

to PGND.

IN

PGND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of C

(Pin 6): Main Supply Pin. Must be closely decoupled

PV

IN

, and (–) terminal of CIN.

OUT

to PGND.

(Pin 7): The Signal Power Pin. All active circuitry

SV

IN

is powered from this pin. Must be closely decoupled to
SGND. SV

must be greater than or equal to PVIN.

IN

PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within ±7.5% of regulation.

(Pin 9): Receives the feedback voltage from the ex-

V

FB

ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.

(Pin 10): Error Amplifi er Compensation Point. The cur-

I

TH

rent comparator threshold increases with this control volt­age. Nominal voltage range for this pin is 0V to 1.5V.

Exposed Pad (Pin 11): Thermal Ground. Connect to SGND
and solder to the PCB for rated thermal performance.

BLOCK DIAGRAM

9

V

FB

0.74V

0.86V

8

PGOOD

0.8V

SV

IN

7

VOLTAGE

REFERENCE

+

–

+

–

+

–

SGND

3

ERROR
AMPLIFIER

I

TH

10

PMOS CURRENT

SLOPE

COMPENSATION

NMOS

REVERSE

COMPARATOR

+

–

+

–

–

+

I

TH

LIMIT

BCLAMP

–

+

V

B

BURST
COMPARATOR
HYSTERESIS = 80mV

OSCILLATOR

1

SHDN/R

T

LOGIC

2

SYNC/MODE

COMPARATOR

COMPARATOR

PV

IN

6

SW

4

5

PGND

3568 BD

3568f

5

LTC3568

OPERATION

The LTC3568 uses a constant frequency, current mode
architecture. The operating frequency is determined by
the value of the R
external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise
for effi ciency.

The output voltage is set by an external divider returned
to the V

pin. An error amplfi er compares the divided

FB

output voltage with a reference voltage of 0.8V and adjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output
low if the output voltage is not within ±7.5%.

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V

FB

The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor fl ows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the voltage on

pin, which is the output of the error amplifi er.This

the I

TH

amplifi er compares the V
When the load current increases, the V
slightly below the reference. This decrease causes the er­ror amplifi er to increase the I
inductor current matches the new load current.

The main control loop is shut down by pulling the SHDN/R
pin to SV

. A digital soft-start is enabled after shutdown,

IN

which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whichever is fi rst. Soft-start can be lengthened by ramping
the voltage on the I
section).

resistor or can be synchronized to an

T

voltage is below the the reference voltage.

pin to the 0.8V reference.

FB

voltage decreases

FB

voltage until the average

TH

T

pin (see Applications Information

TH

To optimize effi ciency, the Burst Mode

operation can be
selected. When the load is relatively light, the LTC3568
automatically switches into Burst Mode

operation in which
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses
of the power MOSFETs are minimized. The main control
loop is interrupted when the output voltage reaches the
desired regulated value. The hysteretic voltage comparator
B trips when I

is below 0.24V, shutting off the switch and

TH

reducing the power. The output capacitor and the inductor
supply the power to the load until I

/RUN exceeds 0.31V,

TH

turning on the switch and the main control loop which
starts another cycle.

For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3568
continues to switch at a constant frequency down to
very low currents, where it will eventually begin skipping
pulses.

Finally, in forced continuous mode, the inductor current
is constantly cycled which creates a fi xed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to fi lter out. Another advan­tage of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.

Low Supply Operation

Low Current Operation

Three modes are available to control the operation of the
LTC3568 at low currents. All three modes automatically
switch from continuous operation to to the selected mode
when the load current is low.

6

The LTC3568 incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 2V.

3568f

APPLICATIONS INFORMATION

LTC3568

A general LTC3568 application circuit is shown in
Figure 5. External component selection is driven by the load
requirement, and begins with the selection of the inductor
L1. Once L1 is chosen, C

and C

IN

can be selected.

OUT

Operating Frequency

Selection of the operating frequency is a tradeoff between
effi ciency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves effi ciency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.

The operating frequency, f
by an external resistor that is connected between the R

, of the LTC3568 is determined

O

T

pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator and can be calculated
by using the following equation:

−

.

Rf

=

978 10

.•

TO

11

108

()Ω()

or can be selected using Figure 2.

The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:

f

O(MAX)

≈ 6.67 • (V

OUT

/ V

IN(MAX)

) (MHz)

The minimum frequency is limited by leakage and noise
coupling due to the large resistance of R

.

T

Inductor Selection

Although the inductor does not infl uence the operat­ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔI
with higher inductance and increases with higher V

:

V

OUT

V

I

L

OUT

fL

•

O

Δ= −

⎛

•1

⎜
⎝

V

OUT

V

IN

⎞
⎟

⎠

decreases

L

or

IN

Accepting larger values of ΔIL allows the use of low induc­tances, but results in higher output voltage ripple, greater
core losses, and lower output current capability.

A reasonable starting point for setting ripple current is

= 0.4 • I

ΔI

L

rent. The largest ripple current ΔI

, where I

OUT

is the maximum output cur-

OUT

occurs at the maximum

L

input voltage. To guarantee that the ripple current stays
below a specifi ed maximum, the inductor value should be
chosen according to the following equation:

V

OUT

L

=

fIVV

OL

⎛

−

1

•

⎜

Δ

•

⎝

IN MAX

⎞

OUT

⎟
⎠

()

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in effi ciency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.

4.5

= 25°C

T

A

4.0

3.5

3.0

2.5

2.0

1.5

FREQUENCY (MHz)

1.0

0.5

0

0

500 1500

Figure 2. Frequency vs R

RT (kΩ)

1000

3568 F02

T

Inductor Core Selection

Different core materials and shapes will change the size/cur­rent and price/current relationship of an inductor. Toroid or
shielded pot cores in ferrite or permalloy materials are small
and don’t radiate much energy, but generally cost more than
powdered iron core inductors with similar electrical char­acteristics. The choice of which style inductor to use often
depends more on the price vs size requirements and any
radiated fi eld/EMI requirements than on what the LTC3568
requires to operate. Table 1 shows some typical surface

3568f

7

LTC3568

APPLICATIONS INFORMATION

mount inductors that work well in LTC3568 applications.

Table 1. Representative Surface Mount Inductors

MANU­FACTURER PART NUMBER VALUE

Toko A914BYW-2R2M (D52LC) 2.2μH 2.05A 49mΩ 2mm

Toko A915Y-2R0M (D53LC-A) 2μH 3.3A 22mΩ 3mm

Toko A918CY-2R0M (D62LCB) 2μH 2.33A 24mΩ 2mm

Coilcraft D01608C-222 2.2μH 2.3A 70mΩ 3mm

Sumida CDRH2D18/HP1R7 1.7μH 1.8A 35mΩ 2mm

Sumida CDRH4D282R2 2.2μH 2.04A 23mΩ 3mm

Sumida CDC5D232R2 2.2μH 2.16A 30mΩ 2.5mm

TDK VLCF4020T-1R8N1R9 1.8μH 1.97A 46mΩ 2mm

Taiyo Yuden N06DB2R2M 2.2μH 3.2A 29mΩ 3.2mm

Taiyo Yuden N05DB2R2M 2.2μH 2.9A 32mΩ 2.8mm

Cooper SD14-2R0 2μH 2.37A 45mΩ 1.45mm

MAX DC

CURRENT DCR HEIGHT

Catch Diode Selection

A catch diode is not necessary.

Input Capacitor (C

) Selection

IN

In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V

OUT/VIN

.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:

VVV

II

≈

RMS MAX

OUT IN OUT

where the maximum average output current I

−()

V

IN

MAX

equals

the peak current minus half the peak-to-peak ripple cur-

= I

rent, I

MAX

This formula has a maximum at V

= I

I

RMS

OUT

– ΔIL/2.

LIM

= 2V

IN

, where

OUT

/2. This simple worst case is commonly used
to design because even signifi cant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur­rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional

0.1μF to 1μF ceramic capacitor is also recommended on
for high frequency decoupling, when not using an all

V

IN

ceramic capacitor solution.

Output Capacitor (C

The selection of C

) Selection

OUT

is driven by the required ESR to

OUT

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfi ed, the capacitance
is adequate for fi ltering. The output ripple (ΔV

OUT

) is

determined by:

⎛

Δ≈Δ +

V I ESR

OUT L

⎜
⎝

8

fC

O OUT

where f = operating frequency, C
and ΔI

= ripple current in the inductor. The output ripple

L

is highest at maximum input voltage since ΔI
with input voltage. With ΔI

= 0.4 • I

L

will be less than 100mV at maximum V

⎞

1

⎟
⎠

= output capacitance

OUT

the output ripple

OUT

and fO = 1MHz

IN

increases

L

with:

ESRC

Once the ESR requirements for C
RMS current rating generally far exceeds the I

< 130mΩ

OUT

have been met, the

OUT

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail­able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalums, avalable in case heights ranging
from 2mm to 4mm. Aluminum electrolytic capacitors have
a signifi cantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.

3568f

8

APPLICATIONS INFORMATION

LTC3568

Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coeffi cient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to signifi cant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.

In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3568 in parallel with the
main capacitors for high frequency decoupling.

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now be­coming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR generates
a loop “zero” at 5kHz to 50kHz that is instrumental in giving
acceptable loop phase margin. Ceramic capacitors remain
capacitive to beyond 300kHz and ususally resonate with
their ESL before ESR becomes effective. Also, ceramic
caps are prone to temperature effects which requires the
designer to check loop stability over the operating tem­perature range. To minimize their large temperature and
voltage coeffi cients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK and Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V

pin. At best, this ringing can

IN

couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfi ll a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com­ponents and the output capacitor size. Typically, 3 to 4

cycles are required to respond to a load step, but only in
the fi rst cycle does the output drop linearly. The output
droop, V

, is usually about 2 to 3 times the linear

DROOP

drop of the fi rst cycle. Thus, a good place to start is with
the output capacitor size of approximately:

I

C

≈Δ25.

OUT

OUT

fV

•

O DROOP

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 22μF ceramic capacitor is
usually enough for these conditions.

Setting the Output Voltage

The LTC3568 develops a 0.8V reference voltage between
the feedback pin, V

, and the signal ground as shown in

FB

Figure 5. The output voltage is set by a resistive divider
according to the following formula:

R

2

VV

≈+

OUT

⎛

08 1

.

⎜
⎝

⎞
⎟

⎠

R

1

Keeping the current small (<5μA) in these resistors maxi­mizes effi ciency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-for ward capaci-

may also be used. Great care should be taken to

tor C

F

route the V

line away from noise sources, such as the

FB

inductor or the SW line.

Shutdown and Soft-Start

The SHDN/R

pin is a dual purpose pin that sets the oscil-

T

lator frequency and provides a means to shut down the
LTC3568. This pin can be interfaced with control logic in
several ways, as shown in Figure 3(a) and Figure 3(b).

The I

pin is primarily for loop compensation, but it can

TH

also be used to increase the soft-start time. Soft start
reduces surge currents from V

by gradually increasing

IN

the peak inductor current. Power supply sequencing can
also be accomplished using this pin. The LTC3568 has an

3568f

9

LTC3568

APPLICATIONS INFORMATION

SHDN/R

T

R

T

RUN

(3a) (3b)

RUN OR VINI

R1

Figure 3. SHDN/RT Pin Interfacing and External Soft-Start

RUN

TH

D1

C1 C

(3c)

SHDN/R

R

C

C

3568 F03

SV

T

IN

R

1M

T

internal digital soft-start which steps up a clamp on ITH
over 1024 clock cycles, as can be seen in Figure 4.

The soft-start time can be increased by ramping the volt­age on I
the voltage on I

during start-up as shown in Figure 3(c). As

TH

ramps through its operating range the

TH

internal peak current limit is also ramped at a proportional
linear rate.

V

IN

5V/DIV

V

OUT

1V/DIV

I

L

1A/DIV

VIN = 3.3V

= 2.5V

V

OUT

= 1.8A

I

LOAD

Figure 4. Digital Soft-Start

400μs/DIV

3568 F04

Mode Selection and Frequency Synchronization

The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect­ing this pin to V

enables Burst Mode operation, which

IN

provides the best low current effi ciency at the cost of a
higher output voltage ripple. When this pin is connected

to ground, pulse skipping operation is selected which
provides the lowest output voltage and current ripple
at the cost of low current effi ciency. Applying a voltage
between SV

– 1V and 1V, results in forced continuous

IN

mode, which creates a fi xed output ripple and is capable
of sinking some current (about 1/2ΔI

). Since the switch-

L

ing noise is constant in this mode, it is also the easiest to
fi lter out. In many cases, the output voltage can be simply
connected to the SYNC/MODE pin, giving the forced con­tinuous mode, except at startup.

The LTC3568 can also be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre­quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the rising
edge of the external clock.

Checking Transient Response

The OPTI-LOOP compensation allows the transient
response to be optimized for a wide range of loads and
output capacitors. The availability of the I

pin not only

TH

allows optimization of the control loop behavior but also
provides a DC-coupled and AC fi ltered closed loop response
test point. The DC step, rise time and settling at this test
point truly refl ects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.

The I

external components shown in the Figure 1 circuit

TH

will provide an adequate starting point for most applica­tions. The series R-C fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs
to 10μs will produce output voltage and I

pin waveforms

TH

3568f

10

APPLICATIONS INFORMATION

LTC3568

that will give a sense of the overall loop stability without
breaking the feedback loop.

Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
mediately shifts by an amount equal to ΔI
ESR is the effective series resistance of C
begins to charge or discharge C

generating a feedback

OUT

• ESR, where

LOAD

. ΔI

OUT

error signal used by the regulator to return V
steady-state value. During this recovery time, V

OUT

LOAD

OUT

OUT

im-

also

to its

can
be monitored for overshoot or ringing that would indicate
a stability problem.

The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor

can be added to improve the high frequency response,

C

F

as shown in Figure 5. Capacitor C

provides phase lead by

F

creating a high frequency zero with R2 which improves
the phase margin.

The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.

Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V

drops toward V

IN

, the load step capability

OUT

does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil­ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.

In some applications, a more severe transient can be caused
by switching in loads with large (>1uF) input capacitors.
The discharged input capacitors are effectively put in paral­lel with C

, causing a rapid drop in V

OUT

. No regulator

OUT

can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifi cally
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.

Effi ciency Considerations

The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:

%Effi ciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent­age of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of

V

2.5V

TO 5.5V

IN

SGND

PGND

+

C6

PGND

C

ITH

SGND SGND SGND SGNDGND

R6

C

IN

C8

SGND

R

C

C

C

Figure 5. LTC3568 General Schematic

SV

PV

IN

LTC3568

SYNC/MODE
I

TH

SGND PGND

IN

PGOOD

SW

V

SHDN/R

R5

PGOOD

V

L1

C

F

FB

T

R

T

R2

R1

+

C

OUT

PGND PGND

OUT

C5

3568 F05

3568f

11

LTC3568

APPLICATIONS INFORMATION

the losses in LTC3568 circuits: 1) LTC3568 VIN current,

2

2) switching losses, 3) I

1) The V

current is the DC supply current given in the

IN

R losses, 4) other losses.

electrical characteristics which excludes MOSFET driver
and control currents. V
that increases with V

current results in a small loss

IN

, even at no load.

IN

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V
ground. The resulting dQ/dt is a current out of V

IN

that is

IN

to

typically much larger than the DC bias current. In continu­ous mode, I

GATECHG

= fO(QT + QB), where QT and QB are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V

IN

and thus their effects will be more pronounced at higher
supply voltages.

2

R Losses are calculated from the DC resistances of

3) I
the internal switches, R

, and external inductor, RL. In

SW

continuous mode, the average output current fl owing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance look­ing into the SW pin is a function of both top and bottom
MOSFET R

R

The R

= (R

SW

DS(ON)

and the duty cycle (DC) as follows:

DS(ON)

TOP)(DC) + (R

DS(ON)

BOT)(1 – DC)

DS(ON)

for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

2

curves. Thus, to obtain I

2

R losses = I

I

OUT

R losses:

2(RSW + RL)

4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

IN

charge storage and very low ESR at the switching frequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3568 does not dis­sipate much heat due to its high effi ciency. However, in
applications where the LTC3568 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.

To avoid the LTC3568 from exceeding the maximum junc­tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:

RISE

= PD • θ

JA

T

where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.

The junction temperature, T

T

J

= T

RISE

+ T

AMBIENT

, is given by:

J

As an example, consider the case when the LTC3568 is in
dropout at an input voltage of 3.3V with a load current of

1.8A with a 70°C ambient temperature. From the Typical
Performance Characteristics graph of Switch Resistance,
the R

resistance of the P-channel switch is 0.125Ω.

DS(ON)

Therefore, power dissipated by the part is:

P

D

= I2 • R

DS(ON)

= 405mW

The DFN package junction-to-ambient thermal resistance,

is 43°C/W. Therefore, the junction temperature of

θ

JA

the regulator operating in a 70°C ambient temperature is
approximately:

= 0.405 • 43 + 70 = 87.4°C

T

J

Remembering that the above junction temperature is
obtained from an R
the junction temperature based on a higher R

at 70°C, we might recalculate

DS(ON)

DS(ON)

since
it increases with temperature. However, we can safely as­sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.

3568f

12

APPLICATIONS INFORMATION

LTC3568

Design Example

As a design example, consider using the LTC3568 in a typical
application with V

= 5V. The load requires a maximum

IN

of 1.8A in active mode and 10mA in standby mode. The
output voltage is V

= 2.5V. Since the load still needs

OUT

power in standby, Burst Mode operation is selected for
good low load effi ciency.

First, calculate the timing resistor:

−

.

RMHzk

=

9 78 10 1 323 8

.• .

T

11

()

108

=

Use a standard value of 324k. Next, calculate the inductor
value for about 40% ripple current at maximum V

25

.

L

1 720

MHz mA

V

•

25

.

V

5

V

⎞

=μ

17

.

⎟

⎠

H=−

⎛

1

•

⎜

⎝

IN

:

Choosing the closest inductor from a vendor of 2μH,
results in a maximum ripple current of:

25

.

V

12

•

MHz

μ

Δ=

L

For cost reasons, a ceramic capacitor will be used. C

25

.

⎛

•

⎜

⎝

V

1

−

⎞

625

=I

⎟

⎠

5

V

mA

OUT

selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

A

18

C

≈=μ25

OUT

MHz V

1525

.

•( %• . )

F

36.

The closest standard value is 22μF plus 10μF. Since the
supply’s output impedance is very low, C
22μF. In noisy environments, decoupling SV

is typically a

IN

from PVIN

IN

with an R6/C8 fi lter of 1Ω/0.1μF may help, but is typically
not needed.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high effi ciency, the
current in these resistors should be kept small. Choosing
2μA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.

The compensation should be optimized for these compo­nents by examining the load step response but a good place
to start for the LTC3568 is with a 13kΩ and 1000pF fi lter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.

The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.

Figure 1 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3568. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:

C

IN

V

IN

C

PV

IN

SV

R5

C4

R3R1R2

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 6. LTC3568 Layout Diagram (See Board Layout Checklist)

IN

LTC3568

PGOODPGOOD
V

FB

I

TH

C3

PGND

SW

SGND

SYNC/MODE

SHDN/R

L1

V

IN

T

BMPS

R

T

OUT

V

OUT

3568 F06

3568f

13

LTC3568

APPLICATIONS INFORMATION

1. Does the capacitor CIN connect to the power VIN (Pin

6) and power GND (Pin 5) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.

2. Are the C
returns current to PGND and the (–) plate of CIN.

C

OUT

and L1 closely connected? The (–) plate of

OUT

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of C
near SGND (Pin 3). The feedback signal V

and a ground line terminated

OUT

should be

FB

routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.

TYPICAL APPLICATIONS

V

IN

2.5V TO

5.5V

C1

22μF

PGND

RS1
1M

BM

FC

PS

RS2

1M

R3

13k

SGND SGND

NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A915AY-2ROM (D53LC SERIES)

SGND

PV

IN

SV

IN

SYNC/MODE V
I

TH

C3
1000pF

PGOOD PGOOD

LTC3568

SHDN/R

PGNDSGND

GND

SW

FB

T

4. Keep sensitive components away from the SW pin. The
input capacitor C

and all the resistors R1, R2, RT, and RC should be

C

ITH

, the compensation capacitor CC and

IN

routed away from the SW trace and the inductor L1.

5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.

6. Flood all unused areas on all layers with copper. Flood­ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PV

R5
100k

3.3V 2.5V 1.8V

R4

R1A

324k

280k

R1B
412k

R1C
698k

L1

2μH

R2 887K

C4 22pF

PGND

, PGND, SVIN or SGND.

IN

V

OUT

1.8V/2.5V/3.3V
AT 1.8A

C2
22μF
x2

3568 F07a

14

Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors

Effi ciency vs Load Current

100

Burst Mode
OPERATION

95

90

85

EFFICIENCY (%)

80

PULSE SKIP

75

70

1 100 1000 10000

FORCED CONTINUOUS

VIN = 3.3V
V

OUT

CIRCUIT OF FIGURE 7

10

LOAD CURRENT (mA)

= 2.5V

3568 F07b

3568f

TYPICAL APPLICATIONS

LTC3568

V

IN

2.5V

TO 5.5V

SGND

C1

22μF

PGND

R

S1

1M

BM

FC

PS

R

S2

1M

C3

1000pF

C1: TAIYO YUDEN JMK325BJ226MM
C2: TAIYO YUDEN JMK325BJ476MM
L1: SUMIDA CDRH2D18/HP1R7

R3

13k

PV

SV

SYNC/MODE

I

TH

SGND PGND

IN

PGOOD PGOOD

SHDN/R

SW

V

FB

T

R4

324k

IN

LTC3568

GND

1.7μH

SGND

PACKAGE DESCRIPTION

0.675 ±0.05

Low Output Voltage, 2mm Height Buck Regulator Effi ciency vs Load Current

R5
100k

L1

1.8V

R1A
316k

R1B
453k

C4 47pF

1.2V1.5V

R1C
787k

R2

402k

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

3568 TA04

V

OUT

1.2V/1.5V/1.8V
AT 1.8A

C2
47μF
x2

95

V

= 1.8V

OUT

90

85

V

= 1.2V

OUT

80

EFFICIENCY (%)

75

70

V

= 1.5V

OUT

VIN = 3.3V
Burst Mode OPERATION

= 1MHz

f

O

1 100 1000 10000

10

LOAD CURRENT (mA)

R = 0.115

TYP

106

3568 TA05

0.38 ± 0.10

3.50 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50
BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

3.00 ±0.10

(4 SIDES)

0.75 ±0.05

1.65 ± 0.10

(2 SIDES)

0.00 – 0.05

15

0.25 ± 0.05

0.50 BSC

2.38 ±0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

(DD) DFN 1103

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3568f

15

LTC3568

TYPICAL APPLICATION

1mm Height, 2MHz, Li-Ion to 1.8V Converter Effi ciency vs Load Current

95

90

85

80

75

EFFICIENCY (%)

70

65

V
f

60

1 100 1000 10000

OUT

= 2MHz

O

VIN = 4.2V

= 1.8V

VIN = 2.7V

VIN = 3.6V

10

LOAD CURRENT (mA)

2.5V

TO 4.2V

V

IN

C1
10μF
x2

C7

47pF

C3

1000pF

C1, C2: MURATA GRM319R60J106KE01B
L1: COOPER SD10-1R0

10k

PV
SV

SYNC/MODE
I

R3

SGND PGND

R5

SW

V

100k

L1

C4 22pF

1μH

FB

T

R4
154k

R1
698k

R2

887k

C2
10μF
x3

V

OUT

1.8V
AT 1.8A

3568 TA02

IN

IN

TH

PGOOD PGOOD

LTC3568

SHDN/R

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I

= 20μA, ISD <1μA, ThinSOT Package

Q

95% Effi ciency, VIN: 2.5V to 5.5V, V
I

= 40μA, ISD <1μA, MS10E and DFN Packages

Q

I

= 26μA, ISD <1μA, SC70 Package

Q

I

= 60μA, ISD <1μA, MS10 and DFN Packages

Q

I

= 62μA, ISD <1μA, TSSOP-16E and QFN Packages

Q

I

= 16μA, ISD <1μA, ThinSOT and DFN Packages

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5.25V, I

= 35μA, ISD <1μA, MS10 and DFN Packages

Q

I

= 26μA, ISD <1μA, DFN Package

Q

95% Effi ciency, V
I

= 70μA, ISD <1μA, QFN Package

Q

: 2.5V to 5.5V, V

IN

IQ = 40μA, ISD <1μA, DFN Package

), 2.25MHz, Synchronous Step-Down

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OUT

95% Effi ciency, VIN: 2.5V to 5.5V, V
I

= 40μA, ISD <1μA, MS10E and DFN Packages

Q

I

= 16μA, ISD <1μA, ThinSOT Package

Q

3568 TA03

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

= 0.6V,

= 0.6V,

= 0.8V,

= 0.8V,

= 0.8V,

: 2V to 5V,

: 2.4V to

= 0.6V,

= 0.8V,

= 0.6V,

= 0.6V,

= 0.6V,

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3568f

LT 0407 • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2007