LINEAR TECHNOLOGY LTC3423, LTC3424 Technical data

FEATURES

LTC3423/LTC3424

Low Output Voltage,

3MHz Micropower Synchronous

Boost Converters

U

DESCRIPTIO

■

1.5V to 5.5V Adjustable Output Voltage

■

Synchronous Rectification: Up to 95% Efficiency

■

1A Switch Current (LTC3423) or
2A Switch Current (LTC3424)

■

Fixed Frequency Operation Up to 3MHz

■

Wide Input Range: 0.5V to 5.5V (Operating)

■

Very Low Quiescent Current: 38µA (Burst Mode

®

Operation)

■

No External Schottky Diode Required

■

Synchronizable Switching Frequency

■

Burst Mode Enable Control

■

OPTI-LOOP® Compensation

■

Very Low Shutdown Current: <1µA

■

Small 10-Pin MSOP Package

U

APPLICATIO S

■

Pagers

■

Handheld Instruments

■

Cordless Phones

■

Wireless Handsets

■

GPS Receivers

■

Battery Backup

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

The LTC®3423 and LTC3424 are high efficiency, fixed
frequency, step-up DC/DC converters that can regulate
output voltages as low as 1.5V from a single cell. An
applied voltage of at least 2.7V to the VDD pin is required
to power the internal control circuitry.

The devices include a 0.16Ω N-channel MOSFET switch
and a 0.21Ω P-channel synchronous rectifier. The LTC3423
is intended for applications requiring less than 0.75W of
output power and the LTC3424 for 1.5W or less. Switching
frequencies up to 3MHz are programmed with an external
timing resistor and the oscillator can be synchronized to
an external clock.

Quiescent current is only 38µA in Burst Mode operation,
maximizing battery life in portable applications. Burst
Mode operation is user controlled and can be enabled by
driving the MODE/SYNC pin high. If the MODE/SYNC pin
has either a clock or is driven low then the operation is at
constant fixed frequency.

Other features include a 1µA shutdown, thermal shutdown
and current limit. The LTC3423 and LTC3424 are available
in the 10-lead MSOP package. For applications requiring
an output voltage greater than 2.6V, the LTC3401 and
LTC3402 are recommended without the need of a separate
voltage for the VDD pin.

TYPICAL APPLICATIO

1-Cell to 1.8V at 600mA Step-Up Converter

V

2.2µF

DD

C1

VDD = 2.7V TO 5.5V

= 0.9V TO 1.5V

V

IN

+

1
CELL

–

C2

10µF

0 = FIXED FREQ

1 = Burst Mode OPERATION

L1

2.2µH

LTC3424

6

V

10

SHDN

3

V

2

MODE/SYNC

1

R

R

t

30.1k

SW

DD

V

OUT

IN

t

FB

V

C

GND

C1: TAIYO YUDEN JMK212BJ225MG
C2: TAIYO YUDEN JMK212BJ106MM
C3: TAIYO YUDEN JMK325BJ226MM
L1: SUMIDA CD43-2R2M

4

7

8

9

5

U

C4
470pF

RC
82k

C5

4.7pF

R1
110k

R2
249k

V

OUT

1.8V
600mA

C3
44µF
(2× 22µF)

3423/24 TA01

100

90

OPERATION

80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.1 10 100 10001

Efficiency

VIN = 1.5V

Burst Mode

VDD = 3.3V

= 1.8V

V

OUT

WITH MBRM120T3 SCHOTTKY

OUTPUT CURRENT (mA)

VIN = 1.2V

VIN = 0.9V

3223/24 TA02

34234f

1

LTC3423/LTC3424

PACKAGE/ORDER I FOR ATIO

UU

W

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

VIN, V

SW Voltage ................................................. –0.5V to 6V

VC, Rt Voltages ......................... –0.5V to (V

SHDN, FB, MODE Voltages ......................... –0.5V to 6V

Operating Temperature Range (Note 2) .. –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)..................300°C

, VDD Voltages.............................. –0.5V to 6V

OUT

OUT

+ 0.3V)

ORDER PART

TOP VIEW

10

1

R

t

MODE

2

V

3

IN

SW

4

GND

5

MS PACKAGE

10-LEAD PLASTIC MSOP

T

= 125°C

JMAX

= 130°C/W 1 LAYER BOARD

θ

JA

= 100°C/W 4 LAYER BOARD

θ

JA

Consult LTC Marketing for parts specified with wider operating temperature ranges.

SHDN

9

V

C

FB

8

V

7

OUT

V

6

DD

NUMBER

LTC3423EMS
LTC3424EMS

MS PART MARKING

LTQM

LTQN

ELECTRICAL CHARACTERISTICS

The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 1.2V, VDD = 3.3V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Input Voltage Range ● 2.7 5.5 V
VIN Operating Voltage Range (Note 4) ● 0.5 5.5 V
Output Voltage Adjust Range ● 1.5 5.5 V
Feedback Voltage ● 1.22 1.25 1.28 V
Feedback Input Current VFB = 1.25V 1 50 nA
Quiescent Current—Burst Mode Operation VC = 0V, MODE/SYNC = 3.3V (Note 3) 38 65 µA
Quiescent Current—SHDN SHDN = 0V, Not Including Switch Leakage 0.1 1 µA
Quiescent Current—Active VC = 0V, MODE/SYNC = 0V, Rt = 300k (Note 3) 440 800 µA
NMOS Switch Leakage 0.1 5 µA
PMOS Switch Leakage 0.1 10 µA
NMOS Switch On Resistance 0.16 Ω
PMOS Switch On Resistance 0.21 Ω
NMOS Current Limit LTC3423 ● 1 1.6 A

Maximum Duty Cycle Rt = 15k ● 80 85 %
Minimum Duty Cycle ● 0%
Frequency Accuracy Rt = 15k ● 1.6 2 2.4 MHz
MODE/SYNC Input High 1.4 V
MODE/SYNC Input Low 0.4 V
MODE/SYNC Input Current V
Error Amp Transconductance ∆I = –5µA to 5µA, VC = V

= 1.8V, unless otherwise noted.

OUT

LTC3424

MODE/SYNC

● 2 2.8 A

= 5.5V 0.01 1 µA

FB

85 µmhos

2

34234f

LTC3423/LTC3424

ELECTRICAL CHARACTERISTICS

The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 1.2V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

SHDN Input High V
SHDN Input Low 0.4 V
SHDN Input Current V

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3423/LTC3424 are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.

= 3.3V unless otherwise noted.

OUT

= VIN = V

SHDN

= 5.5V 0.01 1 µA

SHDN

OUT

Note 3: Current is measured into V
bootstrapped to the V

pin. The outputs are not switching.

DD

1V

since the supply current is

DD

Note 4: Once the output is started, the IC is not dependant upon the V
supply.

IN

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Transient Response

Switching Waveform on SW Pin

150mA to 450mA

SW

0.5V/DIV

V

OUT

100mV/DIV

AC COUPLED

SW

1V/DIV

0V

I

= 500mA 100ns/DIV 3423/24 G01

LOAD

V

1.8V

OUT

Burst Mode Operation
at 500µA Load

= 1.2V 1ms/DIV 3423/24 G03

V

IN

V

= 1.8V

OUT

= 44µF

C

OUT

MODE/SYNC PIN = HIGH

V

OUT

100mV/DIV

AC COUPLED

450mA

I

OUT

150mA

V

OUT

100mV/DIV

AC COUPLED

SW

1V/DIV

C

= 44µF 200µs/DIV 3423/24 G02

OUT

L = 2.2µH

= 1MHz

f

OSC

Burst Mode Operation
at 10mA Load

V

= 1.2V 500µs/DIV 3423/24 G04

IN

V

= 1.8V

OUT

= 44µF

C

OUT

MODE/SYNC PIN = HIGH

34234f

3

LTC3423/LTC3424

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Converter Efficiency 1.2V to 1.8V

100

90

Burst Mode

80

OPERATION

70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.1 10 100 1000

300MHz

1MHz

WITH MBRM120T3 SCHOTTKY

1
OUTPUT CURRENT (mA)

EA FB Voltage

1.28

1.27

1.26

1.25

VOLTAGE (V)

1.24

1.23

3MHz

3223/24 G05

LTC3424 Current Limit

3.4

3.2

3.0

2.8

2.6

CURRENT (A)

2.4

2.2

2.0
–15 25 105

–55

TEMPERATURE (°C)

Oscillator Frequency Accuracy

2.10
= 15k

R

T

2.05

2.00

FREQUENCY (MHz)

1.95

LTC3423 Current Limit

1.80

1.75

1.70

1.65

1.60

1.55

CURRENT (A)

1.50

1.45

RESISTANCE (Ω)

1.40

0.30

0.25

0.20

0.15

0.10

–15 25 105

–55

TEMPERATURE (°C)

NMOS R

DS(ON)

V

= 1.8V

OUT

= 3.3V

V

DD

65

125

3423/24 G07

65

125

3423/24 G06

1.22
–55

–15 25 105

TEMPERATURE (°C)

0.40

0.35

0.30

0.25

RESISTANCE (Ω)

0.20

0.15

65

3423/24 G08

PMOS R

–55

DS(ON)

V

= 1.8V

OUT

= 3.3V

V

DD

–15 25 105

TEMPERATURE (°C)

125

1.90
–15 25 105

–55

TEMPERATURE (°C)

65

125

3423/24 G09

0.05
–15 25 105

–55

TEMPERATURE (°C)

65

125

3423/24 G10

Efficiency Loss Without Schottky
vs Frequency

14

T

= 25°C

A

12

10

8

6

4

EFFICIENCY LOSS (%)

2

65

125

3423/24 G11

0

0.2

0.6 1.0
FREQUENCY (MHz)

1.8 2.6 3.0

1.4 2.2

3423/24 G12

34234f

4

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3423/LTC3424

Shutdown Threshold

1.10

1.05

1.00

0.95

0.90

0.85

0.80

VOLTAGE (V)

0.75

0.70

0.65

0.60

U

–15 25 105

–55

TEMPERATURE (°C)

UU

65

125

3423/24 G13

PI FU CTIO S

Rt (Pin 1): Timing Resistor to Program the Oscillator
Frequency.

10

•

f

OSC

MODE/SYNC (Pin 2): Burst Mode Select and Oscillator
Synchronization.

MODE/SYNC = High. Enable Burst Mode operation. The
inductor peak inductor current will be 400mA and
return to zero current on each cycle. During Burst Mode
operation the operation is variable frequency, providing
a significant efficiency improvement at light loads. It is
recommended the Burst Mode operation only be en­tered once the part has started up.

MODE/SYNC = Low. Disable Burst Mode operation and
maintain low noise, constant frequency operation.

MODE/SYNC = External CLK. Synchronization of the
internal oscillator and Burst Mode operation disable. A
clock pulse width of 100ns to 2µs is required to
synchronize.

VIN (Pin 3): Voltage Sense for Internal Circuitry.

310

=

Hz

R

t

Burst Mode Operation Current

44

42

40

38

36

CURRENT (µA)

34

32

30

–15 25 105

–55

TEMPERATURE (°C)

65

125

3423/24 G14

SW (Pin 4): Switch Pin. Connect inductor and optional
Schottky diode here. Minimize trace length to keep EMI
down.

GND (Pin 5): Signal and Power Ground for the IC.
VDD (Pin 6): Power Source for the IC. Typically derived

from a higher voltage power converter. Requires an input
of 2.7V to 5.5V. A 2.2µF ceramic bypass capacitor is
recommended as close to the pins as possible.

V

(Pin 7): Output of the Synchronous Rectifier.

OUT

FB (Pin 8): Feedback Pin. Connect resistor divider tap

here. The output voltage can be adjusted from 1.5V to

5.5V. The feedback reference voltage is typically 1.25V.
VC (Pin 9): Error Amp Output. A frequency compensation

network is connected to this pin to compensate the loop.
See the section “Compensating the Feedback Loop” for
guidelines.

SHDN (Pin 10): Shutdown. Grounding this pin shuts down
the IC. Tie to >1V to enable (VDD or digital gate output).
During shutdown the output voltage will hold up to V

IN

minus a diode drop due to the body diode of the PMOS
synchronous switch. If the application requires a com­plete disconnect during shutdown then refer to section
“Output Disconnect”.

34234f

5

LTC3423/LTC3424

W

BLOCK DIAGRA

+

1V TO
V

+ 0.3

OUT

OPTIONAL

V

2.7V TO 5.5V

V

IN

3

SHDN SHUTDOWN

10

GND

5

DD

V

6

DD

ANTICROSS
CONDITION

CURRENT

LIMIT

PWM

LOGIC

SLEEP

SW

4

N

+

–

1.6A TYP (LTC3423)

2.8A TYP (LTC3424)

–

CURRENT

COMP

+

+

I

SENSE

AMP

–

+–

Σ

10mV

P

V

OUT

7

V

OUT

1.5V TO 5.5V

+

+

–

I

ZERO

AMP

+

1.25V

ERROR

AMP

–

FB

8

V

9

R1

C

Burst Mode

CONTROL

R

t

1

OSC

SYNC

SLOPE COMP

MODE/SYNC

2

3423/24 BD

R2

34234f

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APPLICATIO S I FOR ATIO

LTC3423/LTC3424

DETAILED DESCRIPTION

The LTC3423/LTC3424 provides high efficiency, low noise
power for applications such as portable instrumentation
and are ideal for applications that require an output voltage
between 1.5V and 2.6V from a single cell. These products
are an addition to the LTC3401 and LTC3402 family of
synchronous boost converters, with the differences being
the omission of the power good function (PGOOD) and the
addition of a VDD input to provide internal power. The IC
will not start up until the applied voltage on the VDD pin is
above 2.7V.

The current mode architecture with adaptive slope
compensation provides ease of loop compensation with
excellent transient load response. The low R
gate charge synchronous switches provides the pulse
width modulation control at high efficiency.

Low Noise Fixed Frequency Operation
Oscillator. The frequency of operation is set through a

resistor from the Rt pin to ground where f = 3 • 1010/Rt. An
internally trimmed timing capacitor resides inside the IC.
The oscillator can be synchronized with an external clock
inserted on the MODE/SYNC pin. When synchronizing the
oscillator, the free running frequency must be set to
approximately 30% lower than the desired synchronized
frequency. Keeping the sync pulse width below 2µs will
ensure that Burst Mode operation is disabled.

DS(ON)

, low

Zero Current Amp. The zero current amplifier monitors the
inductor current to the output and shuts off the synchro­nous rectifier once the current is below 50mA, preventing
negative inductor current.

Burst Mode Operation

Burst Mode operation is when the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
38µA. In this mode, the output ripple has a variable
frequency component with load current and the steady
state ripple will be typically below 3%.

During the period where the device is delivering energy to
the output, the peak current will be equal to 400mA and the
inductor current will terminate at zero current for each cycle.
In this mode the maximum output current is given by:

V

I

OUT MAXBURST

()

Burst Mode operation is user controlled by driving the
MODE/SYNC pin high to enable and low to disable. It is
recommended that Burst Mode operation be entered after
the part has started up.

COMPONENT SELECTION

Inductor Selection

IN

Amps

•≈6

V

OUT

Current Sensing. Lossless current sensing converts the
peak current signal to a voltage to sum in with the internal
slope compensation. This summed signal is compared to
the error amplifier output to provide a peak current control
command for the PWM. The slope compensation in the IC
is adaptive to the input and output voltage. Therefore, the
converter provides the proper amount of slope compensa­tion to ensure stability and not an excess causing a loss of
phase margin in the converter.

Error Amp. The error amplifier is a transconductance
amplifier with gm = 85µmhos. A simple compensation
network is placed from the VC pin to ground.

Current Limit. The current limit amplifier will shut the
NMOS switch off once the current exceeds its threshold.
The current amplifier delay to output is typically 50ns.

The high frequency operation of the LTC3423/LTC3424
allows the use of small surface mount inductors. The
minimum inductance value is proportional to the operat­ing frequency and is limited by the following constraints:

VV V

k

L

where

H and L

>µ >

f

k = 3 for LTC3423, 2 for LTC3424
f = Operating Frequency (Hz)
Ripple = Allowable Inductor Current Ripple (A)
V
V

= Minimum Input Voltage (V)

IN(MIN)
OUT(MAX)

= Maximum Output Voltage (V)

IN MIN OUT MAX IN MIN

•–

() ( ) ()

()

f Ripple V

••

OUT MAX

()

H

34234f

7

LTC3423/LTC3424

WUUU

APPLICATIO S I FOR ATIO

The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.

For high efficiency, choose an inductor with a high fre­quency core material, such as ferrite, to reduce core
losses. The inductor should have low ESR (equivalent
series resistance) to reduce the I2R losses and must be
able to handle the peak inductor current at full load without
saturating. Molded chokes or chip inductors usually do
not have enough core to support the peak inductor cur­rents in the 1A to 2A region. To minimize radiated noise,
use a toroid, pot core or shielded bobbin inductor. See
Table 1 for a list of component suppliers.

Table 1. Inductor Vendor Information

SUPPLIER PHONE FAX WEBSITE

Coilcraft [phone] [phone] www.coilcraft.com
Coiltronics [phone] [phone] www.coiltronics.com
Murata [phone] [phone] www.murata.com

[phone]

Sumida

USA: [phone] [phone] www.japanlink.com

Japan: 81-3-3607-5111 81-3-3607-5144 sumida

where

IL = Average Inductor Current
IP = Peak Inductor Current

The ESR is usually the most dominant factor for ripple in
most power converters. The ripple due to capacitor ESR is
simply given by:

VR

CESR

= IP • R

ESR

Volts

where

R

= Capacitor Series Resistance

ESR

Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors and Sanyo POSCAP or Taiyo­Yuden ceramic capacitors are recommended. For through­hole applications Sanyo OS-CON capacitors offer low ESR
in a small package size. See Table 2 for a list of component
suppliers.

In some layouts it may be required to place a 1µF low ESR
capacitor as close to the V

and GND pins as possible.

OUT

SHDN

R

t

MODE
V
SW
GND

V

OUT

Figure 1. Recommended Component Placement. Traces
Carrying High Current Are Direct. Trace Area FB and VC Pins
Are Kept Low. Lead Length to Battery Should be Kept Short

V

C

FB

IN

V

OUT

V

DD

VDD IN

2.7V
TO 5.5V

3423/24 F01

Output Capacitor Selection

The output voltage ripple has several components. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The max ripple due
to charge is given by:

IVV V

•( –)

VR

BULK

L IN OUT IN

=

CVVf

•••

OUT OUT OUT

Volts

Table 2. Capacitor Vendor Information

SUPPLIER PHONE FAX WEBSITE

AVX [phone] [phone] www.avxcorp.com
Sanyo [phone] [phone] www.sanyovideo.com
Taiyo Yuden [phone] [phone] www.t-yuden.com

Input Capacitor Selection

The input filter capacitor reduces peak currents drawn from
the input source and reduces input switching noise. In most
applications a 3.3µF is sufficient.

Output Diode

The Schottky diode across the synchronous PMOS switch
is not required, but provides a lower drop during the break­before-make time (typically 20ns) of the NMOS to PMOS
transition. The addition of the Schottky diode will improve
peak efficiency (see graph “Efficiency Loss Without
Schottky vs Frequency”). Use of a Schottky diode such as
a MBRM120T3, 1N5817 or equivalent. Since slow recov­ery times will compromise efficiency, do not use ordinary
rectifier diodes.

34234f

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APPLICATIO S I FOR ATIO

LTC3423/LTC3424

Operating Frequency Selection

There are several considerations in selecting the operat­ing frequency of the converter. The first is determining the
sensitive frequency bands that cannot tolerate any spec­tral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz. In this
case, converter frequencies up to 3MHz may be em­ployed.

The second consideration is the physical size of the
converter. As the operating frequency goes up, the induc­tor and filter caps go down in value and size. The trade off
is in efficiency since the switching losses due to gate
charge are going up proportional with frequency.

Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimum on time of the converter cannot support the duty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
applications where physical size is the main criterion then
running the converter in this mode is acceptable. In
applications where it is preferred not to enter this mode,
then the maximum operating frequency is given by:

130mA/100mV, and the LTC3424 is typically 170mA/
100mV, so the amount of signal injected is proportional to
the anticipated change of inductor current with load. The
outer voltage loop performs the remainder of the correc­tion, but because of the load feed forward signal, the range
over which it must slew is greatly reduced. This results in
an improved transient response. A logic level feed forward
signal, VFF, is coupled through components C5 and R6.
The amount of feed forward signal is attenuated with
resistor R6 and is given by the following relationship:

R

6

where ∆I

V

IN

V

DD

IN



VRV

515

•• •.

FF IN



VI



OUT

•–∆

OUT OUT

= load current change.

LTC3423/LTC3424

6

V

DD

10

SHDN

3

V

IN

2

MODE/SYNC

1

R

t

V

GND

SW

OUT



R

5≈





V

OUT

4

7

8

FB

9

V

C

5

C3

VV

–

f

MAX NOSKIP

where t

ON(MIN)

= minimum on time = 140ns

OUT IN

=

Vt

•

OUT ON MIN_()

Hz

Reducing Output Capacitance with a Load Feed
Forward Signal

In many applications the output filter capacitance can be
reduced for the desired transient response by having the
device commanding the change in load current, (i.e.
system microcontroller), inform the power converter of
the changes as they occur. Specifically, a “load feed
forward” signal coupled into the VC pin gives the inner
current loop a head start in providing the change in output
current. The transconductance of the LTC3423 converter
at the VC pin with respect to the inductor current is typically

R5

C5

LOAD FEED

FORWARD

SIGNAL

V

FF

Figure 2

3.3nF

R6

3423/24 F02

Closing the Feedback Loop

The LTC3423/LTC3424 uses current mode control with
internal adaptive slope compensation. Current mode con­trol eliminates the 2nd order filter due to the inductor and
output capacitor exhibited in voltage mode controllers,
and simplifies it to a single-pole filter response. The
product of the modulator control to output DC gain plus
the error amp open-loop gain equals the DC gain of the
system.

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9

LTC3423/LTC3424

WUUU

APPLICATIO S I FOR ATIO

GDC = G

G

CONTROL

CONTROLOUTPUT

2•

=

I

OUT

• G

V

IN

, GEA ≈ 2000

EA

The output filter pole is given by:

I

f

FILTERPOLE

where C

=

is the output filter capacitor.

OUT

OUT

VC

π••

OUT OUT

Hz

The output filter zero is given by:

f

FILTERZERO

where R

=

2• • •π

is the capacitor equivalent series resistance.

ESR

1

RC

ESR OUT

Hz

A troublesome feature of the boost regulator topology is
the right half plane zero (RHP) and is given by:

2

VR

=

2••••π

IN O

LV

Hz

2

O

f

RHPZ

At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.

The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:

f

POLE

≈

1

22010

•• • •

1

π

6

Hz

C

C

1

whichisextremelyclosetoDC

f

ZERO

f

POLE

=

1

2

≈

2

1

RC

•• •

π

ZC

1

RC

•• •

π

2

ZC

Hz

1

Hz

2

Refer to Application Note AN76 for more closed loop
examples.

V

OUT

R1

R2

C

C2

3423/24 F03

ERROR

AMP

+

–

1.25V

FB

8

V

C

9

Figure 3

C

C1

R

Z

TYPICAL APPLICATIO

1 = Burst Mode OPERATION

10

U

Typical Application with Output Disconnect

VIN = 0.9V TO 1.5V

LTC3423/LTC3424

3

V

IN

10

SHDN

2

MODE/SYNC

6

V

DD

V

DD

1

R

t

* SET RB TO FORCE BETA OF ≤100; RB =

0 = FIXED FREQ

V

GND

SW

OUT

ZETEX

FMMT717

4

7

8

FB

9

V

C

5

– V

INMIN

I

OUTMAX

– 0.7V) • 100

(V

OUT

RB*

3423/24 TA03

V

C5
1µF

OUT

34234f

TYPICAL APPLICATIO

V

DD

IN

C1

2.2µF

U

Single Cell to 1.8V at 300mA, 1.8mm High

VDD = 2.7V TO 5.5V

= 0.9V TO 1.5V

V

IN

+

1
CELL

–

C2

4.7µF

6

V

10

SHDN

3

V

2

MODE/SYNC

1

R

R

t

30.1k

DD

IN

t

f

OSC

L1

4.7µH

LTC3423

= 1MHz

V

GND

SW

OUT

4

7

8

FB

9

V

C

5

LTC3423/LTC3424

D1

C4
470pF

C5

R
82k

4.7pF

C

R1
110k

R2
249k

V

OUT

1.8V
300mA

C3
22µF

PACKAGE DESCRIPTIO

5.23

(.206)

MIN

3.05 ± 0.38

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

GAUGE PLANE

0.18

(.007)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0 = FIXED FREQ

1 = Burst Mode OPERATION

U

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889

(.035 ± .005)

3.2 – 3.45

(.126 – .136)

(.0197)

DETAIL “A”

0.254
(.010)

° – 6° TYP

0

DETAIL “A”

MS Package

± 0.127

0.50

BSC

0.53 ± 0.01

(.021 ± .006)

C1: TAIYO YUDEN JMK212BJ225MG
C2: TAIYO YUDEN JMK212BJ475MM
C3: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120T3
L1: SUMIDA CDRH3D16-4R7M

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

4.88 ± 0.10

(.192 ± .004)

12

1.10

(.043)

MAX

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

0.50

(.0197)

TYP

3423/24 TA04

0.497 ± 0.076

7

6

45

(.0196 ± .003)

REF

3.00 ± 0.102

(.118 ± .004)

NOTE 4

0.86

(.034)

REF

0.13 ± 0.05

(.005 ± .002)

MSOP (MS) 1001

34234f

8910

3

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

LTC3423/LTC3424

TYPICAL APPLICATIO

U

Triple Output Converter

V

DD

IN

2.2µF

C1

VDD = 2.7V TO 5.5V

= 0.9V TO 1.5V

V

IN

+

1
CELL

–

C2

10µF

0 = FIXED FREQ

1 = Burst Mode OPERATION

6

V

DD

10

SHDN

3

V

IN

2

MODE/SYNC

1

R

t

R

t

30.1k

D2 D3

0.1µF 0.1µF 0.1µF

L1

2.2µH

LTC3423

= 1MHz

f

OSC

4

SW

7

V

OUT

8

FB

9

V

C

5

GND

C1: TAIYO YUDEN JMK212BJ225MG
C2: TAIYO YUDEN JMK212BJ106MM
C3: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120T3
D2 TO D7: ZETEX FMND7000 DUAL DIODE
L1: SUMIDA CD43-2R2M

D1

RC
82k

D4 D5

C4
470pF

C5

4.7pF

R1
110k

R2
249k

4.7µF

0.1µF

V

OUT

1.8V
700mA

C3
44µF
(2× 22µF)

3423/24 TA05

3.6V
2mA

D6

4.7µF

D7

–1.1V
1mA

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ThinSOT is a trademark of Linear Technology Corporation.

Linear Technology Corporation

12

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

TM

VIN As Low As 1.1V, 3V at 30mA from Single Cell

≤ 5V

OUT

LT/TP 0302 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORP ORATION 2001

34234f