LINEAR TECHNOLOGY LTC3421 Technical data

FEATURES

■

Synchronous Rectification: Up to 96% Efficiency

■

True Output Disconnect

■

Inrush Current Limiting

■

Very Low Quiescent Current: 12µA

■

Up to 1.5A Continuous Output Current

■

Fixed Frequency Operation Up to 3MHz

■

0.5V to 4.5V Input Range

■

2.4V to 5.25V Adjustable Output Voltage

■

Guaranteed 1V Start-Up

■

Programmable Current Limit

■

Programmable Soft-Start

■

Synchronizable Oscillator

■

Manual or Automatic Burst Mode® Operation

■

Low-Battery Comparator

■

<1µA Shutdown Current

■

1.22V Reference Output Voltage

■

Small (4mm × 4mm) Thermally Enhanced QFN
Package

U

APPLICATIO S

■

Handheld Computers

■

Cordless Phones

■

GPS Receivers

■

Battery Backup Supplies

LTC3421

3A, 3MHz Micropower

Synchronous Boost Converter

with Output Disconnect

U

DESCRIPTIO

The LTC®3421 is a high efficiency, current mode, fixed
frequency, step-up DC/DC converter with true output dis­connect and inrush current limiting. The device includes a

0.10Ω N-channel MOSFET switch and a 0.14Ω P-channel
synchronous rectifier. This product has the ability to sim­ply program the output voltage, switching frequency, cur­rent limit, soft-start, Burst Mode threshold and loop
compensation with external passive components.

Quiescent current is only 12µA during Burst Mode opera-
tion, maximizing battery life in portable applications. The
oscillator frequency can be programmed up to 3MHz and
can be synchronized to an external clock applied to the
SYNC pin. An open-drain uncommitted low-battery com­parator is included. The part maintains operation in
applications with a secondary cell powering the output
voltage during shutdown.

Other features include: 1µA shutdown, antiringing control,
thermal limit and reference output.

The LTC3421 is available in a small 4mm × 4mm QFN
package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

V

IN

1.8V TO 3V

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM

2
CELLS

C1*

4.7µF

45.3k

0.1µF

221141516

V

SHDN

REF

LIM

SS R

IN

GND

T

28k

4

ENB

3

V

23

LBI

22

LBO

7

SYNC

8

I

U

L1

4.7µH

SW SW

SW

18

V

OUTS

17

V

OUT

19

V

OUT

20

LTC3421

PGND PGNDPGND

C5: TAIYO YUDEN JMK325BJ226MM
L1: TDK RLF7030T-4R7M3R4

V

OUT

BURST

FB
V

C

1312111056

0.1µF

1
24
9

470pF

20k

100k

340k

200k

C5*
22µF

3421 TA01

V

3.3V

1.2A

OUT

2-Cell to 3.3V Efficiency

100

Burst Mode OPERATION

90
80
70
60
50
40

EFFICIENCY (%)

30
20

V

10

f

0

0.1 10 100 1000

= 3.3V

OUT

= 1MHz

OSC

1
OUTPUT CURRENT (mA)

VIN = 3V

VIN = 2.4V

VIN = 2V

3421 G02

3421f

1

LTC3421

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

VIN, V
BURST, SHDN, SS, ENB, SW,

LBO, LBI, SYNC Voltages .......................... –0.3V to 6V

Operating Temperature Range

(Notes 2, 5)............................................. –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

OUT

, V

Voltage ............................ –0.3V to 6V

OUTS

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

LBO

VINV

25

10 11 12

GND

BURST

OUTVOUT

18

V

OUTS

V

17

OUT

SW

16

SW

15

SW

14
13

PGND

PGND

PGND

LTC3421EUF

VCLBI

24 23 22 21 20 19

FB

1

SHDN

2

V

3

REF

ENB

4

R

5

T

SS

6

7 8 9

LIM

I

SYNC

24-LEAD (4mm × 4mm) PLASTIC QFN

T

JMAX

= 35°C/W 4 LAYER BOARD, θJC = 2.6°C/W

θ

JA

EXPOSED PAD IS GND (PIN 25) MUST BE SOLDERED TO PCB

UF PACKAGE

= 125°C, θJA = 40°C/W 1 LAYER BOARD,

ORDER PART NUMBER

UF PART MARKING 3421

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum VIN Start-Up Voltage I
Minimum VIN Operating Voltage (Note 4) ● 0.5 V
Output Voltage Adjust Range 2.25 5.25 V

Feedback Voltage ● 1.196 1.220 1.244 V
Feedback Input Current VFB = 1.22V 1 50 nA
Quiescent Current—Burst Mode Operation VC = 0V, ENB = 0V (Note 3) 12 20 µA

Quiescent Current—Shutdown SHDN = 0V, ENB = 0V 0.1 1 µA

Quiescent Current—Active (Note 3) 0.6 1.1 mA
NMOS Switch Leakage 0.1 5 µA
PMOS Switch Leakage 0.1 10 µA
NMOS Switch On Resistance 0.1 Ω
PMOS Switch On Resistance 0.14 Ω
NMOS Current Limit I

Max Duty Cycle ● 84 91 %
Min Duty Cycle ● 0%

LOAD

V

= 0V, ENB = 2V (Note 3) 23 50 µA

C

SHDN = 0V, ENB > 1.4V 0.2 2 µA

Resistor = 105k ● 1 1.5 A

LIM

I

Resistor = 36.5k ● 3 4.2 A

LIM

The ● denotes the specifications which apply over the full operating

= 3.3V, RT = 28k, unless otherwise noted.

OUT

< 1mA 0.88 1 V

● 2.40 5.25 V

2

3421f

LTC3421

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Frequency Accuracy ● 0.85 1 1.15 MHz
SYNC Input High ● 2.2 V
SYNC Input Low ● 0.8 V
SYNC Input Current ● 0.01 1 µA
ENB Input High ● 1.2 V
ENB Input Low ● 0.4 V
ENB Input Current ● 1 µA
SHDN Input High V

SHDN Input Low 0.25 V
SHDN Input Current ● 0.01 1 µA
REF Output Voltage ● 1.183 1.22 1.257 V
REF Output Current Range –100 8 µA
Error Amp Transconductance 45 µs
LBI Threshold Falling Edge ● 0.58 0.6 0.62 V
LBI Input Current ● 0.01 1 µA
LBO Low Voltage VIN = 0V, I

LBO Leakage V
SS Current Source VSS = 1V 1.2 2.4 5 µA
BURST Threshold Voltage Falling Edge 0.87 0.97 1.07 V

OUT

V

OUT

V

IN

PGOOD

= 0V, I

The ● denotes the specifications which apply over the full operating

= 3.3V, RT = 28k, unless otherwise noted.

OUT

= 0V (Initial Start-Up) 1.00 V
> 2.4V 0.65 V

= 1mA 12.0 50 mV

SINK

= 20mA 0.25 0.5 V

SINK

= 5.5V 0.01 1 µA

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3421E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: Current is measured into the V
bootstrapped to the output. The current will reflect to the input supply by
(V

) • Efficiency. The outputs are not switching.

OUT/VIN

pin since the supply current is

OUTS

Note 4: Once V
supply.

Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

is greater than 2.4V, the IC is not dependent on the V

OUT

IN

3421f

3

LTC3421

OUTPUT CURRENT (mA)

0

START VOLTAGE (V)

1.00

1.05

1.10

200

3421 G09

0.95

0.90

0.80
50

100

150

0.85

1.20

1.15

UW

TYPICAL PERFOR A CE CHARACTERISTICS

(TA = 25°C, unless otherwise specified)

Single Cell to 3.3V Efficiency

100

Burst Mode OPERATION

90
80
70
60
50
40

EFFICIENCY (%)

30
20

V

= 3.3V

10

OUT

= 1MHz

f

OSC

0

0.1 10 100 1000

1
OUTPUT CURRENT (mA)

VIN = 1.2V

Burst Mode Operation Load Transient Response Inrush Current Control

V

OUT

50mV/DIV

AC COUPLED

SW

INDUCTOR

CURRENT

0.5A/DIV

VIN = 1.5V

VIN = 1V

3421 G01

2-Cell to 3.3V Efficiency Li-Ion to 5V Efficiency

100

Burst Mode OPERATION

90
80
70
60
50
40

EFFICIENCY (%)

30
20

V

10

OUT

f

OSC

0

0.1 10 100 1000

V

OUT

100mV/DIV

AC COUPLED

600mA

I

OUT

50mA

VIN = 3V

= 3.3V

= 1MHz

1
OUTPUT CURRENT (mA)

VIN = 2.4V

VIN = 2V

3421 G02

100

90

Burst Mode

80

OPERATION

70
60
50
40

EFFICIENCY (%)

30
20

V

= 5V

10

OUT

= 1MHz

f

OSC

0

0.1 10 100 1000

V

OUT

1V/DIV

INDUCTOR

CURRENT

0.5A/DIV

1
OUTPUT CURRENT (mA)

VIN = 4.2V

= 3.6V

V

IN

= 2.7V

V

IN

3421 G03

100

90
80
70
60

50
40

EFFICIENCY (%)

30
20
10

0

4

2.5µs/DIV

3421 G04

= 2.4V 2.5ms/DIV 3421 G05

V

IN

V

= 3.3V

OUT

= 44µF

C

OUT

Efficiency vs Frequency Efficiency vs V

100

f = 300kHz

f = 3MHz

f = 1MHz

1

10 100 1000

OUTPUT CURRENT (mA)

VIN = 2.4V
V

OUT

= 3.3V

3421 G07

90
80
70
60
50
40

EFFICIENCY (%)

30
20

10

0

1

1.5 2.5

2

INPUT VOLTAGE (V)

IN

PMOS LDO MODE

3

3.5

V

OUT

I

OUT

VIN > V

4

= 3.3V

= 200mA

OUT

4.5

3421 G08

= 0V TO 2.4V 500µs/DIV 3421 G06

V

IN

C

= 44µF

OUT

Start-Up Voltage vs Output Current

5

3421f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3421

(TA = 25°C, unless otherwise specified)

Burst Mode Threshold vs R

180

160

140

120

100

80

60

OUTPUT CURRENT (mA)

40

20

INTO BURST

0

20

OUT OF BURST

70

R

BURST

BURST

120

(kΩ)

3421 G10

FB Voltage Frequency Accuracy

1.24

1.23

1.22

VOLTAGE (V)

1.21

1.20
–45

–30 –15 0 15

TEMPERATURE (°C)

30 45 60 75 90

3421 G11

Burst Mode Quiescent Current Current Limit Accuracy R

20

15

10

CURRENT (µA)

5

0

–45

–30 –15 0 15

TEMPERATURE (°C)

30 45 60 75 90

3421 G13

1.70

R

LIM

1.65

1.60

1.55

1.50

1.45

1.40

CURRENT (A)

1.35

1.30

1.25

1.20

–30 0

–45

= 105k

–15

TEMPERATURE (°C)

30 90

45

15

60

75

3421 G14

1.03

1.01

0.99

FREQUENCY (MHz)

0.97

0.95
–45

–30 –15 0 15

DS(ON)

0.20

0.18

0.16

0.14

0.12

0.10

0.08

RESISTANCE (Ω)

0.06

0.04

0.02

0

–30 0

–15

–45

TEMPERATURE (°C)

TEMPERATURE (°C)

30 45 60 75 90

PMOS

NMOS

30 90

45

15

3421 G12

60

75

3421 G15

UUU

PI FU CTIO S

FB (Pin 1): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to

5.25V. The feedback reference voltage is typically 1.220V.
SHDN (Pin 2): Shutdown Pin. Less than 0.25V on this pin

shuts down the IC. The IC is enabled when the SHDN
voltage is greater than 1V. Once V
hysteresis is applied to the pin (–500nA out of the pin)
allowing it to operate at a logic high while the battery can
drop to 0.5V.

V

(Pin 3): Buffered 1.22V Reference Output. This pin

REF

can source up to 100µA and sink up to 8µA. This pin must
be decoupled with a 0.1µF capacitor for stability.

is above 2.2V,

OUT

ENB (Pin 4): Reference Output (V
Comparator Enable. When ENB = Low, the V

) and Low-Battery

REF

output and

REF

low-battery comparator are disabled, which lowers the
quiescent current by 5µA. When ENB = High, the V

REF

output and the low-battery comparator are enabled. Dur­ing shutdown, if the ENB = High and the output voltage is
pulled up to greater than 2.5V from a secondary source
such as a coin cell through a Schottky diode, the V

REF

output and low-battery comparator becomes powered
from the output voltage and enabled.

3421f

5

LTC3421

UUU

PI FU CTIO S

RT (Pin 5): Connect a resistor to ground to program the
oscillator frequency according to the formula:

OSC

28 100,

=

R

T

is in kHz and RT is in kΩ.

OSC

f

where f
SS (Pin 6): Soft-Start Pin. Connect a capacitor from this

pin to ground to set the soft-start time according to the
formula:

t(ms) = CSS(µF) • 320

The nominal soft-start charging current is 2.5µA. The
active range of SS is from 0.8V to 1.6V.

SYNC (Pin 7): Oscillator Synchronization Pin. A clock
pulse width of 100ns to 2µs is required to synchronize the
internal oscillator. If not used SYNC should be grounded.

I

(Pin 8): Current Limit Adjust Pin. Connect a resistor

LIM

from this pin to ground to set the peak current limit thresh­old for the N-channel MOSFET according to the formula
(note that this is the peak current in the inductor):

GND (Pin 10): Signal Ground Pin. Connect to ground plane
near the RT resistor, error amp compensation compo­nents and feedback divider.

PGND (Pins 11 to 13): Source Terminal of Power Internal
N-Channel MOSFET.

SW (Pins 14 to 16): Switch Pin for Inductor Connection.
For applications where V
SW to V

or to a snubber circuit is required to maintain

OUT

> 4.3V, a Schottky diode from

OUT

absolute maximum rating for SW. (see Application Cir­cuits for 5V).

V

(Pins 17, 19 and 20): The output of the synchronous

OUT

rectifier and bootstrapped power source for the IC. A
ceramic bypass capacitor is required to be very close to
the V

V

OUTS

and PGND pins of the IC.

OUT

(Pin 18): V

Sense Pin. Connect V

OUT

OUTS

directly to
an output filter capacitor. The top of the feedback divider
network should also be tied to this point.

VIN (Pin 21): Input Supply Pin. Connect this pin to the
input supply and decouple with at least a 4.7µF ceramic
capacitor.

LIM

150

=

R

I

where I is in amps and R is in kΩ.
BURST (Pin 9): Burst Mode Threshold Adjust Pin. A

resistor/capacitor combination from this pin to ground
programs the average load current at which automatic
Burst Mode operation is entered, according to the formula:

R

BURST

where R

C

BURST

where C

BURST

BURST(MIN)

2

=

I

BURST

is in kΩ and I

CV

•

OUT OUT

≥

,10 000

and C

BURST

are in µF.

OUT

is in amps.

For manual control of Burst Mode operation, ground the
BURST pin to force Burst Mode operation or connect it to
V

to force fixed frequency PWM mode. Note that the

OUT

BURST pin must not be pulled higher than V

OUT

.

LBO (Pin 22): Open-Drain Output. This pin pulls low when
the LBI input is below 0.6V. The open-drain output can
sink up to 20mA. During Burst Mode operation LBO is only
active during the time the IC wakes up to service the
output.

LBI (Pin 23): Low-Battery Comparator Input. Typical
threshold voltage is 0.6V with 30mV hysteresis. This
function is enabled when the ENB pin is high. The low­battery comparator will operate off VIN or V

, whichever

OUT

is greater.
VC (Pin 24): Error Amp Output. A frequency compensation

network is connected from this pin to ground to compen­sate the loop. See the section Compensating the Feedback
Loop for guidelines.

Exposed Pad (Pin 25): Ground. This pin must be soldered
to the PCB and is typically connected through the power
GND plane.

3421f

6

BLOCK DIAGRA

W

+

LTC3421

1V TO 4.5V

21

V

IN

ANTIRING

VINV

ANTICROSS

CONDUCTION

CURRENT

LIMIT

SHDN

ENB

V

REF

SHUTDOWN

1.22V REF
2%

THERMAL

REG/SHDN

PWM

LOGIC

2

V

4

OUT

3

14

15

16

SW

SW

DD

NMOS

SW

I

SENSE

AMP

PMOS

V

IN

WELL
SWITCH

+

–

I

ZERO

AMP

V

18

OUTS

V

OUT

17

V

OUT

19

V

OUT

20

R1

V

OUT

2.40V TO 5.25V

+

I

LIM

BURST

8

SS

6

FB

1

V

C

24

9

R

C1

C

SS

R2

C

P

R

Z

SLEEP

OFF

–

–

CURRENT

COMP

+

++

Σ

Burst Mode

CONTROL

1%

ERROR

AMP

I

LIMIT

150k/R

+

–

=

C1

1.22V

I/3000

+

SYNC

R1

R2

0.97V/1.05V

–

LBO

22

13

3421 BD

3421f

EXPOSED

PAD

25

–

+

–3%

BURST

COMP

+

3%

–

PGND

PGND12PGND

11

R

T

SYNC

LBI

0.6V/

OSC

V

–

+

INVOUT

ENB

SLOPE COMP

GND

10

5

7

IN

23

0.63V

UV

OV

7

LTC3421

OPERATIO

U

LOW VOLTAGE START-UP

The LTC3421 includes an independent start-up oscillator
designed to start-up at input voltages of 0.85V typical. The
frequency and peak current limit during start-up are inter­nally controlled. The device can start-up under some load
(see graph of Start-Up Current vs Input Voltage). Soft­start and inrush current limiting are provided during start­up as well as normal mode. The same soft-start capacitor
is used for each operating mode.

When either VIN or V
normal operating mode. Once the output voltage exceeds
the input by 0.3V, the IC powers itself from V
of VIN. At this point the internal circuitry has no depen­dency on the VIN input voltage, eliminating the require­ment for a large input capacitor. The input voltage can drop
as low as 0.5V without affecting circuit operation. The
limiting factor for the application becomes the availability
of the power source to supply sufficient energy to the
output at the low voltages and the maximum duty cycle,
which is clamped at 91% typical.

exceeds 2.25V, the IC enters

OUT

instead

OUT

Oscillator

The frequency of operation is set through a resistor from
the RT pin to ground. An internally trimmed timing capaci­tor resides inside the IC. The oscillator can be synchro­nized with an external clock applied to the SYNC pin. When
synchronizing the oscillator, the free running frequency
must be set to an approximately 30% lower frequency
than the desired synchronized frequency.

Current Sensing

Lossless current sensing converts the peak current signal
to a voltage to sum in with the internal slope compensa­tion. This summed signal is compared to the error ampli­fier output to provide a peak current control command for
the PWM. The slope compensation in the IC is adaptive to
the input voltage and output voltage. Therefore, the con­verter provides the proper amount of slope compensation
to ensure stability, but not an excess to cause a loss of
phase margin in the converter.

Error Amplifier

LOW NOISE FIXED FREQUENCY OPERATION

Shutdown

The part is shut down by pulling SHDN below 0.3V, and
activated by pulling the pin initially above 1V and maintain­ing a high state down to 0.5V. Note that the SHDN pin can
be driven above VIN or V
than the absolute maximum rating.

Soft-Start

The soft-start time is programmed with an external capaci­tor to ground on the SS pin. An internal current source
charges it with a nominal 2.5µA. The voltage on the SS pin
(in conjunction with the external resistor on the I
is used to control the peak current limit until the voltage on
the capacitor exceeds 1.6V, at which point the external
resistor sets the peak current. In the event of a com­manded shutdown or a thermal shutdown, the capacitor is
discharged automatically. Note that Burst Mode operation
is inhibited during the soft-start time.

as long as it is limited to less

OUT

LIM

pin)

The error amplifier is a transconductance amplifier, with
its positive input internally connected to the 1.22V refer­ence and its negative input connected to FB. A simple
compensation network is placed from COMP to ground.
Internal clamps limit the minimum and maximum error
amplifier output voltage for improved large-signal tran­sient response. During sleep (in Burst Mode operation),
the compensation pin is high impedance; however, clamps
limit the voltage on the external compensation network,
preventing the compensation capacitor from discharging
to zero during the sleep time.

Current Limit

The programmable current limit circuit sets the maximum
peak current. This clamp level is programmed with a
resistor from I
current limit is automatically set to a nominal value of 0.6A
peak for optimal efficiency.

LIM

150

=

I

to ground. In Burst Mode operation, the

LIM

R

t(ms) = CSS(µF) • 320

8

where I is in amps and R is in kΩ.

3421f

OPERATIO

LTC3421

U

Zero Current Amplifier

The zero current amplifier monitors the inductor current to
the output and shuts off the synchronous rectifier once the
current is below 50mA typical, preventing negative induc­tor current.

Antiringing Control

The antiringing control places a resistor across the
inductor to damp the ringing on the SW pin in discontinu­ous conduction mode. The LCSW ringing (L = inductor,
CSW = capacitance on SW pin) is low energy, but can
cause EMI radiation.

V

REF

The internal 1.22V reference is buffered and brought out
to REFOUT. It is active when the ENB pin is pulled high
(above 1.4V). For stability, a minimum of a 0.1µF capacitor
must be placed on the pin. The output can source up to
100µA and sink up to 8µA. For the lowest possible quies-
cent current in Burst Mode operation, the reference output
should be disabled by grounding the ENB pin.

increasing the output capacitance. Another method of
reducing Burst Mode ripple is to place a small feed­forward capacitor across the upper resistor in the V
feedback divider network.

During Burst Mode operation, the VC pin is disconnected
from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on VC during Burst Mode opera­tion. This minimizes the transient experienced when a
heavy load is suddenly applied to the converter after being
in Burst Mode operation for an extended period of time.

For automatic operation, an RC network should be con­nected from BURST to ground. The value of the resistor
will control the average load current (I
Burst Mode operation will be entered and exited (there is
hysteresis to prevent oscillation between modes). The
equation given for the capacitor on BURST is for the
minimum value to prevent ripple on BURST from causing
the part to oscillate in and out of Burst Mode operation at
the current where the mode transition occurs.

BURST

) at which

OUT

Burst Mode OPERATION

Burst Mode operation can be automatic or user controlled.
In automatic operation, the IC will automatically enter
Burst Mode operation at light load and return to fixed
frequency PWM mode for heavier loads. The user can
program the average load current at which the mode
transition occurs using a single resistor.

The oscillator is shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current and the off time is determined
by the time it takes for the inductor current to return to
zero.

In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12µA of quiescent current. In this mode, the output ripple
has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent
losses. Burst Mode ripple can be reduced slightly by

R

BURST

where R

where C
In the event that a sudden load transient causes FB to

deviate by more than 4% from the regulation value, an
internal pull-up is applied to BURST, forcing the part
quickly out of Burst Mode operation. For optimum tran­sient response when going between Burst Mode operation
and PWM mode, the mode should be controlled manually
by the host. This way PWM mode can be commanded
before the load step occurs, minimizing output voltage
droop. For manual control of Burst Mode operation, the
RC network can be eliminated. To force fixed frequency
PWM mode, BURST should be connected to V
force Burst Mode operation, BURST should be grounded.

C

BURST

BURST

BURST(MIN)

2

=

I

BURST

is in kΩ and I

CV

•

OUT OUT

≥

,10 000

and C

BURST

are in µF.

OUT

is in amps.

OUT

. To

3421f

9

LTC3421

OPERATIO

U

Simplified Diagram of Automatic Burst Mode Control Circuit

V

CC

1mA I

–

V

REF

–4%

FB

1

+

–

REF

+

V
±1%

UV

ERROR AMP/
SLEEP COMP

24

SSDONE

V

C

R

COMP

C

COMP

TO
MODULATOR

CLAMP

0.5V TO 1V

9

0.9V/

1.1V

BURST

R

B

/3000

OUT

SSDONE

–

+

C

B

SLEEP

MODE
1 = Burst Mode
OPERATION
0 = PWM MODE

3421 TA03

The circuit connected to BURST should be able to sink or
source up to 2mA. Note that Burst Mode operaton is
inhibited during start-up and soft-start.

Note that if VIN is above V

– 0.3V, the part will exit Burst

OUT

Mode operation and the synchronous rectifier will be
disabled.

Note that if the load applied during forced Burst Mode
operation exceeds the current that can be supplied, the
output voltage will start to droop and the part will auto­matically come out of Burst Mode operation and enter fixed
frequency mode, raising V

. The maximum current that

OUT

can be supplied in Burst Mode operation is given by:

10

I

O MAX

()

=

2

055

VV

+

1

•

–

()

OUT IN

V

IN

in amps

.

OUTPUT DISCONNECT AND INRUSH LIMITING

The LTC3421 is designed to allow true output disconnect
by eliminating body diode conduction of the internal
P-channel MOSFET rectifier. This allows V

to go to zero

OUT

volts during shutdown without drawing any current from
the input source. It also allows for inrush current limiting
at turn-on, minimizing surge currents seen by the input
supply. Note that to obtain the advantages of output

3421f

OPERATIO

LTC3421

U

disconnect, there must not be any external Schottky
diodes connected between the SW pins and V

OUT

.

Note: Board layout is extremely critical to minimize volt­age overshoot on the SW pins due to stray inductance.
Keep the output filter capacitors as close as possible to the

WUUU

APPLICATIO S I FOR ATIO

COMPONENT SELECTION

V

24 23 22 21 20 19

LBI LBO VINV

V

C

FB

1

2

SHDN

3

V

REF

4

ENB

R

5

T

SS

6

I

LIM

SYNC

BURST GND PGND PGND

7 8 9 10 11 12

OUTVOUT

V

OUTS

V

PGND

OUT

SW

SW

SW

V

OUT

18

17

16

15

14

13

3421 F01

Figure 1. Recommended Component Placement. Traces Carrying
High Current are Direct (PGND, SW, V

). Trace Area at FB and

OUT

VC are Kept Low. Lead Length to Battery Should be Kept Short.
VIN and V

Ceramic Capacitors Should be as Close to the IC

OUT

Pins as Possible

Inductor Selection

The high frequency operation of the LTC3421 allows the
use of small surface mount inductors. The minimum
inductance value is proportional to the operating fre­quency and is limited by the following constraints:

3

L

and L

>>

VV V

IN MIN OUT MAX IN MIN

f

•–

()

() ( ) ()

••

f Ripple V

OUT MAX

()

IN

GND

MULTIPLE VIAS
TO GROUND
PLANE

V

pins and use very low ESR/ESL ceramic capacitors,

OUT

tied to a good ground plane. In V
a Schottky diode is required from the switch nodes to V

> 4.3V applications,

OUT

OUT

to limit the peak switch voltage to less than 6V unless
some form of external snubbing is employed. (See 5V
Applications section.)

where

f = Operating Frequency in MHz
Ripple = Allowable Inductor Current Ripple (Amps

Peak-Peak)
V
V

= Minimum Input Voltage

IN(MIN)
OUT(MAX)

= Maximum Output Voltage

The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.

For high efficiency, choose an inductor with high fre­quency core material, such as ferrite, to reduce core loses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I2R losses and must be able to
handle the peak inductor current without saturating. Molded
chokes or chip inductors usually do not have enough core
to support peak inductor currents in the 1A to 4A region.
To minimize radiated noise, use a toroidal or shielded
inductor. See Table 1 for suggested inductor suppliers and
Table 2 for a list of capacitor suppliers.

Table 1. Inductor Vendor Information

SUPPLIER PHONE FAX WEB SITE

Coilcraft [phone] [phone] www.coilcraft.com
Coiltronics [phone] [phone]
Murata USA: USA: www.murata.com

[phone] [phone]
[phone]

Sumida USA: USA: www.sumida.com

[phone] [phone]
Japan: Japan:

81-3-3607-5111 81-3-3607-5144
TDK [phone] [phone] www.component.tdk.com
TOKO [phone] [phone] www.toko.com

3421f

11

LTC3421

WUUU

APPLICATIO S I FOR ATIO

Output Capacitor Selection

The output voltage ripple has two components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple due to charge is given by:

IV

•

V

RBULK

=

PIN

CVf

••

OUT OUT

where IP = peak inductor current.
The ESR (equivalent series resistance) is usually the most

dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:

V

where C

RCESR

ESR

= IP • C

ESR

= capacitor series resistance.

Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors, Sanyo POSCAP or Taiyo Yuden
ceramic capacitors are recommended. For through-hole
applications, Sanyo OS-CON capacitors offer low ESR in a
small package size.

In some layouts it may be necessary to place a 1µF low ESR
ceramic capacitor as close to the V

and GND pins as

OUT

possible.

Input Capacitor Selection

The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated, the demand on the input capacitor is
much less. In most applications 1µF per amp of peak input
current is recommended. Taiyo Yuden offers very low ESR
ceramic capacitors, for example the 1µF in a 0603 case
(JMK107BJ105MA).

Table 2. Capacitor Vendor Information

SUPPLIER PHONE FAX WEB SITE

AVX [phone] [phone] www.avxcorp.com
Sanyo [phone] [phone] www.sanyovideo.com
TDK [phone] [phone] www.component.tdk.com
Murata USA: USA: www.murata.com

[phone] [phone]
[phone]

Taiyo Yuden [phone] [phone] www.t-yuden.com

Operating Frequency Selection

There are several considerations in selecting the operating
frequency of the converter. The first is, which are the sen­sitive frequency bands that cannot tolerate any spectral
noise? The second consideration is the physical size of the
converter. As the operating frequency goes up, the induc­tor and filter capacitors go down in value and size. The trade
off is in efficiency since the switching losses due to gate
charge are going up proportional with frequency.

Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimum on time of the converter cannot support the duty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
applications where physical size is the main criterion,
running the converter in this mode is acceptable. In appli­cations where it is preferred not to enter this mode, the
maximum operating frequency is given by:

f

MAX NOSKIP

where t

ON(MIN)

=

•

Vt

OUT ON MIN_()

Hz

= minimum on time = 120ns.

–

VV

OUT IN

Thermal Considerations

To deliver the power that the LTC3421 is capable of, it is
imperative that a good thermal path be provided to
dissipate the heat generated within the package. This can
be accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that mul­tiple vias in the printed circuit board be used to conduct
heat away from the IC and into a copper plane with as much
area as possible. In the event that the junction tempera­ture gets too high, the peak current limit will automatically
be decreased. If the junction temperature continues to rise,
the part will go into thermal shutdown, and all switching
will stop until the temperature drops.

VIN > V

Operation

OUT

The LTC3421 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
by terminating the switching on the synchronous PMOS
and applying VIN statically on the gate. This will ensure the

3421f

12

WUUU

f

V

IL

RHPZ

IN

OUT

=

π

2

2• • •

APPLICATIO S I FOR ATIO

LTC3421

volts • seconds of the inductor will reverse during the time
current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output
current is limited in order to maintain an acceptable
junction temperature.

–

125

T

I

OUT MAX

()

=

•.–

40 1 5

VV

()

()

IN OUT

A

+

where TA = ambient temperature.
For example at VIN = 4.5V and V

= 3.3V, the maximum

OUT

output current is 370mA.

Short Circuit

The LTC3421 output disconnect feature allows output short
circuit while maintaining a maximum set current limit. The
IC has incorporated internal features such as current limit
and thermal shutdown for protection from an excessive
overload or short circuit. In applications that require a pro­longed short circuit, it is recommended to limit the power
dissipation in the IC to maintain an acceptable junction
temperature. The circuit in Figure 2 will limit the maximum
current during a prolonged short by reducing the current
limit value in a short circuit by disconnecting R2 with the
N-channel MOSFET switch. R3 and C1 provide a soft-start
function after a short circuit. Resistor R1 lowers the cur­rent limit value as VIN rises, maintaining a relatively con­stant power. The current limit equation for the circuit in
Figure 2 is given by:

Closing the Feedback Loop

The LTC3421 uses current mode control with internal
adaptive slope compensation. Current mode control elimi­nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim­plifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:

V

GG

=

G

DC EA

G

CONTROL

CONTROL_OUTPUT

V

•,2

I

OUT

IN

=≈

••

G

EA

2000

V

REF

OUT

The output filter pole is given by:

I

f

FILTER POLE

where C

=

_

is the output filter capacitor.

OUT

OUT

••

π

VC

OUT OUT

The output filter zero is given by:

f

FILTER ZERO

where R

_

ESR

=

•• •

2

is the capacitor equivalent series resistance.

1

RC

π

ESR OUT

A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:

I

LIMIT

where I



06 06

=





R

is in Amps; R

LIMIT

Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions

.

LIM

I

LIM

8

R

LIM

100k

V

–

VN2222

IN

TO V



–.

R

1

IN

R1
1M

R2
50k

250

•





and R1 are in kΩ.

LIM

R3

10k

C1

0.1µF

3421 F02

TO V

OUT

At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.

The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:

f

POLE

f

ZERO

f

POLE

≈

1

2206

≈

1

2

≈

2

2

1

π

•• •

eC

1

π

•• •

RC

ZC

1

π

•• •

RC

ZC

which is extremely close to DC

C

1

1

2

3421f

13

LTC3421

WUUU

APPLICATIO S I FOR ATIO

U

TYPICAL APPLICATIO

5V Applications

ERROR

AMP

+

–

1.22V

FB

1

V

C

24

Figure 3

V

OUT

R1

R2

C

R

Z

C

C1

C2

3421 F03

When the output voltage is programmed above 4.3V it is
necessary to add a Schottky diode either from SW to
V

, or to a snubber network in order to maintain an

OUT

acceptable peak voltage on SW. The Schottky to the

V

2.7V TO

4.2V

Li-Ion

IN

C1*
10µF

+

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM

23
22

R1
60k

C2

0.1µF

SHDN

4

ENB

3

V

REF

LBI
LBO

7

SYNC

8

I

LIM

SS R

L1

3µH

221141516

SW SW

V

IN

LTC3421

GND

T

PGND PGNDPGND

R2
28k

SW

V

BURST

D1: MOTOROLA MBR0520L
L1: SUMIDA CDRH6D28-3R0
M1: ZETEX ZXM61P025

OUTS

V

OUT

V

OUT

V

OUT

FB
V

C

1312111056

0.1µF

D1*

18
17
19
20
1
24
9

C3

C4

470pF

R3
10k

R4

100k

output will provide a peak efficiency improvement but will
negate the output disconnect feature. If output disconnect
is required, the Schottky to an active snubber network is
suggested as shown in Figure 4.

M1

R5

1.13M

R6
365k

C6*

1µF

C5*
22µF
×2

3421 F04

100

V

OUT

5V
1A

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

Li-Ion to 5V Efficiency

Burst Mode

OPERATION

V

= 5V

OUT

= 1MHz

f

OSC

0.1 10 100 1000

1
OUTPUT CURRENT (mA)

VIN = 4.2V

= 3.6V

V

IN

= 2.7V

V

IN

3421 G03

14

Figure 4. Lithium-Ion to 5V at 1A Application with an Active Snubber Circuit

3421f

PACKAGE DESCRIPTIO

LTC3421

U

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

0.70 ±0.05

4.50 ± 0.05

3.10 ± 0.05

2.45 ± 0.05

(4 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

4.00 ± 0.10

(4 SIDES)

PIN 1
TOP MARK
(NOTE 5)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

0.75 ± 0.05

2.45 ± 0.10

(4-SIDES)

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

0.23 TYP

(4 SIDES)

24

23

0.38 ± 0.10

1
2

(UF24) QFN 0603

0.25 ± 0.05

0.50 BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3421f

15

LTC3421

TYPICAL APPLICATIO

U

Single Cell to 3.3V at 500mA with Secondary Cell Backup During Shutdown. LOWBAT and V

L1

R2
28k

V

IN

LTC3421

GND

4.7µH

SW SW

SW

V

OUTS

V

V

V

BURST

PGND PGNDPGND

OUT

OUT

OUT

FB
V

1312111056

0.1µF

18
17
19
20

1
24

C

9

C3

470pF

R3
40k

V

IN

1V TO 1.5V

1 CELL

PRIMARY CELL

C1*

4.7µF

301k

+

604k

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM

0.1µF

LOW BAT

OUTPUT

R1
60k

0.1µF

221141516

SHDN

4

ENB

3

V

REF

23

LBI

22

LBO

7

SYNC

8

I

LIM

SS R

T

C2

C5: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A916CY-4R7M

D1

+

C4

REF

3V
SECONDARY CELL

R4
100k

Single Cell to 3.3V Efficiency

100

Burst Mode OPERATION

90
80
70
60
50
40

EFFICIENCY (%)

30
20

V

= 3.3V

10

OUT

= 1MHz

f

OSC

0

0.1 10 100 1000

1
OUTPUT CURRENT (mA)

VIN = 1.5V

VIN = 1.2V

VIN = 1V

3421 G01

Output are Enabled

V

OUT

3.3V
500mA

R5
340k

C5*
22µF

R6
200k

3421 TA05

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Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

: 35V/42V, IQ: 4mA, ISD: <12µA,

OUT(MAX)

OUT(MAX)

OUT(MAX)

 LINEAR TECHNOLOGY CORPORATION 2003

: 5V, IQ: 19µA/300µA,

OUT(MAX)

: 5.5V, IQ: 38µA,

: 5.5V, IQ: 38µA,

: 5.25V, IQ: 12µA,

OUT(MAX)

LT/TP 1103 1K PRINTED IN USA

3421f