LINEAR TECHNOLOGY LTC2283 Technical data

LTC2283

www.BDTIC.com/LINEAR

Dual 12-Bit, 125Msps

Low Power 3V ADC

FEATURES

n

Integrated Dual 12-Bit ADCs

n

Sample Rate: 125Msps

n

Single 3V Supply (2.85V to 3.4V)

n

Low Power: 790mW

n

70.2dB SNR, 88dB SFDR

n

110dB Channel Isolation at 100MHz

n

Flexible Input: 1V

n

640MHz Full Power Bandwidth S/H

n

Clock Duty Cycle Stabilizer

n

Shutdown and Nap Modes

n

Data Ready Output Clock

n

Pin Compatible Family

P-P

to 2V

P-P

Range

125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

n

64-Pin (9mm × 9mm) QFN Package

APPLICATIONS

DESCRIPTION

The LTC®2283 is a 12-bit 125Msps, low power dual 3V
A/D converter designed for digitizing high frequency,
wide dynamic range signals. The LTC2283 is perfect for
demanding imaging and communications applications
with AC performance that includes 70.1dB SNR and 82dB
SFDR for signals at the Nyquist frequency.

Typical DC specs include ±0.4LSB INL, ±0.2LSB DNL. The
transition noise is a low 0.32LSB

A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.

A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor­mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.

RMS

.

n

Wireless and Wired Broadband Communication

n

Imaging Systems

n

Spectral Analysis

n

Portable Instrumentation

TYPICAL APPLICATION

ANALOG
INPUT A

CLK A

CLK B

ANALOG
INPUT B

+

INPUT

S/H

–

CLOCK/DUTY CYCLE

CONTROL

CLOCK/DUTY CYCLE

CONTROL

+

INPUT

S/H

–

12-BIT
PIPELINED
ADC CORE

12-BIT
PIPELINED
ADC CORE

OUTPUT

DRIVERS

OUTPUT

DRIVERS

2283 TA01

OV

DD

D11A

•

•

•

D0A

OGND

OF

MUX

CLKOUT

OV

DD

D11B

•

•

•

D0B

OGND

SNR vs Input Frequency,

–1dB, 2V Range

73

72

71

70

69

SNR (dBFS)

68

67

66

65

50 100 200

0

150

INPUT FREQUENCY (MHz)

250 300 350

2283 TA01b

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LTC2283

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OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ..................................................4V

Digital Output Ground Voltage (OGND) ........–0.3V to 1V

Analog Input Voltage (Note 3) .......–0.3V to (V

Digital Input Voltage ......................–0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

Power Dissipation .............................................1500mW

Operating Temperature Range

LTC2283C ................................................ 0°C to 70°C

LTC2283I.............................................. –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

DD
DD
DD

+ 0.3V)
+ 0.3V)
+ 0.3V)

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

TOP VIEW

DD

64 GND

63 VDD62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OF

56 DA11

55 DA10

54 DA9

53 DA8

52 DA7

51 DA6

50 OGND

49 OV

A

INA

A

INA

REFHA 3
REFHA 4
REFLA 5
REFLA 6

V

DD

CLKA 8
CLKB 9
V

DD

REFLB 11
REFLB 12
REFHB 13
REFHB 14

–

A

INB

+

A

INB

+

1

–

2

7

65

10

15
16

48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
41 NC
40 CLKOUT
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5

18

DD

V

GND 17

SENSEB 19

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

T

NC 24

OEB 23

MUX 21

VCMB 20

SHDNB 22

UP PACKAGE

= 150°C, θJA = 20°C/W

JMAX

NC 25

DB0 26

DB1 27

DB2 28

DB3 29

DB4 30

OGND 31

32

DD

OV

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2283CUP#PBF LTC2283CUP#TRPBF LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2283IUP#PBF LTC2283IUP#TRPBF LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2283CUP LTC2283CUP#TR LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2283IUP LTC2283IUP#TR LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

The l denotes the specifi cations which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes)

Integral Linearity Error Differential Analog Input (Note 5)

Differential Linearity Error Differential Analog Input

Offset Error (Note 6)

Gain Error External Reference

Offset Drift ±10 μV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°C

Gain Matching External Reference ±0.3 %FS

2

12 Bits

●

–2 ±0.4 2 LSB

●

–0.9 ±0.2 0.9 LSB

●

–12 ±2 12 mV

●

–2.5 ±0.5 2.5 %FS

●

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LTC2283

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The l denotes the specifi cations which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise specifi cations are at T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Offset Matching ±2 mV

Transition Noise SENSE = 1V 0.32 LSB

ANALOG INPUT

The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

V

IN

V

IN,CM

I

IN

I

SENSE

I

MODE

t

AP

t

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Analog Input Range (A

Analog Input Common Mode (A

Analog Input Leakage Current 0V < A

SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V

MODE Input Leakage Current 0V < MODE < V

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

Full Power Bandwidth Figure 8 Test Circuit 640 MHz

–

–A

IN

) 2.85V < V

IN

+

–

+A

IN

IN

= 25°C. (Note 4)

A

< 3.4V (Note 7)

DD

)/2 Differential Input Drive (Note 7)

Single Ended Input Drive (Note 7)

+

–

, A

< V

IN

IN

DD

DD

●

●

●

●

●

●

±0.5V to ±1V V

1

0.5

–1 1 μA

–3 3 μA

–3 3 μA

1.5

1.5

RMS

1.9
2

RMS

V
V

DYNAMIC ACCURACY

The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 70.2 dB

30MHz Input 70.1 dB

68 70 dB

●

70 82 dB

●

77 90 dB

●

67 69.6 dB

●

SFDR Spurious Free Dynamic Range

SFDR Spurious Free Dynamic Range

S/(N+D) Signal-to-Noise Plus Distortion Ratio

I

MD

2nd or 3rd Harmonic

4th Harmonic or Higher

Intermodulation Distortion fIN = 40MHz, 41MHz 85 dB

Crosstalk f

70MHz Input

140MHz Input 69.6 dB

5MHz Input 88 dB

30MHz Input 85 dB

70MHz Input

140MHz Input 78 dB

5MHz Input 90 dB

30MHz Input 90 dB

70MHz Input

140MHz Input 90 dB

5MHz Input 69.8 dB

30MHz Input 69.7 dB

70MHz Input

140MHz Input 69.5 dB

= 100MHz –110 dB

IN

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LTC2283

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INTERNAL REFERENCE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage I

V

CM

Output Tempco ±25 ppm/°C

V

CM

Line Regulation 2.85V < VDD < 3.4V 3 mV/V

V

CM

Output Resistance

V

CM

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the specifi cations which apply over the

= 0 1.475 1.500 1.525 V

OUT

|

I

|

< 1mA

OUT

(Note 4)

4Ω

full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)

V

IH

V

IL

I

IN

C

IN

LOGIC OUTPUTS

= 3V

OV

DD

C

OZ

I

SOURCE

I

SINK

V

OH

V

OL

= 2.5V

OV

DD

V

OH

V

OL

= 1.8V

OV

DD

V

OH

V

OL

High Level Input Voltage VDD = 3V

Low Level Input Voltage VDD = 3V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10μA

Low Level Output Voltage IO = 10μA

High Level Output Voltage IO = –200μA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200μA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

OUT

OUT

I

= –200μA

O

I

= 1.6mA

O

DD

= 0V 50 mA

= 3V 50 mA

2V

●

●

–10 10 μA

●

2.995

2.7

●

●

2.99

0.005

0.09 0.4

0.8 V

V
V

V
V

4

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LTC2283

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The l denotes the specifi cations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

OV

DD

IV

DD

P

DISS

P

SHDN

P

NAP

The l denotes the specifi cations which apply over the full operating temperature

TIMING CHARACTERISTICS

Analog Supply Voltage (Note 9)

Output Supply Voltage (Note 9)

Supply Current Both ADCs at f

Power Dissipation Both ADCs at f
Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW
Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

range, otherwise specifi cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

s

t

L

t

H

t

AP

t

D

t

C

t

MD

Pipeline Latency 5 Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V

Note 4: V
drive, unless otherwise noted.

DD

Sampling Frequency (Note 9)

CLK Low Time Duty Cycle Stabilizer Off (Note 7)

CLK High Time Duty Cycle Stabilizer Off (Note 7)

Sample-and-Hold Aperture Delay 0 ns

CLK to DATA Delay CL = 5pF (Note 7)

CLK to CLKOUT Delay CL = 5pF (Note 7)

DATA to CLKOUT Skew (t

MUX to DATA Delay CL = 5pF (Note 7)
Data Access Time After OE↓ C

BUS Relinquish Time (Note 7)

= 3V, f

= 125MHz, input range = 2V

SAMPLE

= 25°C. (Note 8)

A

without latchup.

DD

with differential

P-P

S(MAX)

S(MAX)

Duty Cycle Stabilizer On (Note 7)

Duty Cycle Stabilizer On (Note 7)

– tC) (Note 7)

D

= 5pF (Note 7)

L

Note 5: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code fl ickers between 0000 0000 0000 and 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test.

, they

DD

Note 8: V
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.

Note 9: Recommended operating conditions.

DD

= 3V, f

2.85 3 3.4 V

●

0.5 3 3.6 V

●

●

●

1 125 MHz

●

3.8

●

3

●

3.8

●

3

●

1.4 2.7 5.4 ns

●

1.4 2.7 5.4 ns

●

–0.6 0 0.6 ns

●

1.4 2.7 5.4 ns

●

●

●

= 125MHz, input range = 1V

SAMPLE

263 305 mA

790 915 mW

4

500

4

500

4

500

4

500

4.3 10 ns

3.3 8.5 ns

with differential

P-P

ns
ns

ns
ns

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LTC2283

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TYPICAL PERFORMANCE CHARACTERISTICS

Crosstalk vs Input Frequency Typical INL, 2V Range, 125Msps Typical DNL, 2V Range, 125Msps

–100

–105

–110

–115

CROSSTALK (dB)

–120

–125

–130

0

20 40 60 80

INPUT FREQUENCY (MHz)

100

2283 G01

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

1024 2048 4096

CODE

3072

2283 G02

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

1024 2048 4096

CODE

3072

2283 G03

8192 Point FFT, f
–1dB, 2V Range, 125Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0

10 20 30 40 50

FREQUENCY (MHz)

8192 Point FFT, f
–1dB, 2V Range, 125Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0

10 20 30 40 50

FREQUENCY (MHz)

= 5MHz,

IN

= 140MHz,

IN

60

2283 G04

60

2283 G07

8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range, 125Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0

10 20 30 40 50

FREQUENCY (MHz)

8192 Point 2-Tone FFT,

= 28.2MHz and 26.8MHz,

f

IN

–1dB, 2V Range, 125Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0

10 20 30 40 50

FREQUENCY (MHz)

60

2283 G05

60

2283 G08

8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, 125Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0

10 20 30 40 50

FREQUENCY (MHz)

Grounded Input
Histogram, 125Msps

70000

4249

2045

58717

2046
CODE

60000

50000

40000

COUNT

30000

20000

10000

00

0

2044

2562

2047

60

2283 G06

2048

2283 G09

6

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TYPICAL PERFORMANCE CHARACTERISTICS

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LTC2283

SNR vs Input Frequency,
–1dB, 2V Range, 125Msps

73

72

71

70

69

SNR (dBFS)

68

67

66

65

50 100 200

0

150

INPUT FREQUENCY (MHz)

SNR vs Input Level,

= 70MHz, 2V Range, 125Msps

f

IN

80

70

60

50

40

30

SNR (dBc AND dBFS)

20

10

0

–50 –40

–60

dBFS

dBc

–30

INPUT LEVEL (dBFS)

250 300 350

2283 G10

–20

–10

2283 G13

0

SFDR vs Input Frequency,
–1dB, 2V Range, 125Msps

95

90

85

80

SFDR (dBFS)

75

70

65

0

50 100

INPUT FREQUENCY (MHz)

200 300 350

150 250

SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps

110

100

90

80

70

60

50

40

SFDR (dBc AND dBFS)

30

20

10

0

–60

dBFS

dBc

–40 –20–50 –30 –10

INPUT LEVEL (dBFS)

2283 G11

2283 G14

(mA)

I

0

SNR and SFDR vs Sample Rate,
2V Range, f

90

80

70

SNR AND SFDR (dBFS)

60

50

0

20 40 60 80

I

vs Sample Rate,

VDD

= 5MHz, –1dB

IN

SFDR

SNR

SAMPLE RATE (Msps)

100 120 140 160

5MHz Sine Wave Input, –1dB

290

280

270

260

VDD

250

240

230

220

210

200

190

2V RANGE

1V RANGE

20

0

60

40

SAMPLE RATE (Msps)

80

100 120

2283 G12

140

2283 G15

I

vs Sample Rate, 5MHz Sine

OVDD

Wave Input, –1dB, 0VDD = 1.8V SNR vs SENSE, fIN = 5MHz, –1dB

16

14

12

10

(mA)

8

OVDD

I

6

4

2

0

20 40 80

0

60

SAMPLE RATE (Msps)

100 120 140

2283 G16

72

71

70

69

68

SNR (dBFS)

67

66

65

64

0.4

0.5 0.6 0.8

0.7

SENSE PIN (V)

0.9 1.0 1.1

2283 G17

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LTC2283

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PIN FUNCTIONS

+

A

(Pin 1): Channel A Positive Differential Analog

INA

Input.

–

A

(Pin 2): Channel A Negative Differential Analog

INA

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short to­gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short to­gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.

(Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

V

DD

GND with 0.1μF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by­pass to Pins 13, 14 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.

and a ±0.5V input range. V

selects the internal reference

DD

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input
range of ±V

(Pin 20): Channel B 1.5V Output and Input Common

V

CMB

. ±1V is the largest valid input range.

SENSEB

Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to V

CMA

.

MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA11; Channel B
comes out on DB0-DB11. If MUX is Low, the output bus­ses are swapped and Channel A comes out on DB0-DB11;
Channel B comes out on DA0-DA11. To multiplex both
channels onto a single output bus, connect MUX, CLKA
and CLKB together. (This is not recommended at clock
frequencies above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V

results in normal operation

DD

with the outputs at high impedance. Connecting SHDNB
to V
outputs at high impedance. Connecting SHDNB to V
and OEB to V

and OEB to GND results in nap mode with the

DD

results in sleep mode with the outputs

DD

DD

at high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

NC (Pins 24, 25, 41, 42): Do not connect these pins.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by­pass to Pins 11, 12 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.

–

A

(Pin 15): Channel B Negative Differential Analog

INB

Input.

+

A

(Pin 16): Channel B Positive Differential Analog

INB

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to V

selects the internal reference

CMB

8

DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

(Pins 32, 49): Positive Supply for the Output Drivers.

OV

DD

Bypass to ground with 0.1μF ceramic chip capacitor.

CLKOUT (Pin 40): Data Ready Clock Output. Latch data
on the falling edge of CLKOUT. CLKOUT is derived from
CLKB. Tie CLKA to CLKB for simultaneous operation.

DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.

OF (Pin 57): Overfl ow/Underfl ow Output. High when an
overfl ow or underfl ow has occurred on either Channel A
or Channel B.

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