LINEAR TECHNOLOGY LTC2283 Technical data

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LTC2283

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Dual 12-Bit, 125Msps

Low Power 3V ADC

FEATURES

Integrated Dual 12-Bit ADCs

Sample Rate: 125Msps

Single 3V Supply (2.85V to 3.4V)

Low Power: 790mW

70.2dB SNR, 88dB SFDR

110dB Channel Isolation at 100MHz

Flexible Input: 1V

640MHz Full Power Bandwidth S/H

Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Data Ready Output Clock

Pin Compatible Family

P-P

to 2V

P-P

Range

125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit) 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

64-Pin (9mm × 9mm) QFN Package

APPLICATIONS

DESCRIPTION

The LTC®2283 is a 12-bit 125Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2283 is perfect for demanding imaging and communications applications with AC performance that includes 70.1dB SNR and 82dB SFDR for signals at the Nyquist frequency.

Typical DC specs include ±0.4LSB INL, ±0.2LSB DNL. The transition noise is a low 0.32LSB

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. A data ready output clock (CLKOUT) can be used to latch the output data.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

RMS

Wireless and Wired Broadband Communication

Imaging Systems

Spectral Analysis

Portable Instrumentation

TYPICAL APPLICATION

ANALOG INPUT A

CLK A

CLK B

ANALOG INPUT B

INPUT

S/H

–

CLOCK/DUTY CYCLE

CONTROL

CLOCK/DUTY CYCLE

CONTROL

INPUT

S/H

–

12-BIT PIPELINED ADC CORE

OUTPUT

DRIVERS

OUTPUT

DRIVERS

2283 TA01

D11A

•

D0A

OGND

MUX

CLKOUT

D11B

•

D0B

OGND

SNR vs Input Frequency,

–1dB, 2V Range

SNR (dBFS)

50 100 200

150

INPUT FREQUENCY (MHz)

250 300 350

2283 TA01b

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OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ..................................................4V

Digital Output Ground Voltage (OGND) ........–0.3V to 1V

Analog Input Voltage (Note 3) .......–0.3V to (V

Digital Input Voltage ......................–0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

Power Dissipation .............................................1500mW

Operating Temperature Range

LTC2283C ................................................ 0°C to 70°C

LTC2283I.............................................. –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

DD DD DD

+ 0.3V) + 0.3V) + 0.3V)

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

TOP VIEW

64 GND

63 VDD62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OF

56 DA11

55 DA10

54 DA9

53 DA8

52 DA7

51 DA6

50 OGND

49 OV

INA

REFHA 3 REFHA 4 REFLA 5 REFLA 6

CLKA 8 CLKB 9 V

REFLB 11 REFLB 12 REFHB 13 REFHB 14

–

INB

–

15 16

48 DA5 47 DA4 46 DA3 45 DA2 44 DA1 43 DA0 42 NC 41 NC 40 CLKOUT 39 DB11 38 DB10 37 DB9 36 DB8 35 DB7 34 DB6 33 DB5

GND 17

SENSEB 19

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

NC 24

OEB 23

MUX 21

VCMB 20

SHDNB 22

UP PACKAGE

= 150°C, θJA = 20°C/W

JMAX

NC 25

DB0 26

DB1 27

DB2 28

DB3 29

DB4 30

OGND 31

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2283CUP#PBF LTC2283CUP#TRPBF LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2283IUP#PBF LTC2283IUP#TRPBF LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2283CUP LTC2283CUP#TR LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C

LTC2283IUP LTC2283IUP#TR LTC2283UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁ cations which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes)

Integral Linearity Error Differential Analog Input (Note 5)

Differential Linearity Error Differential Analog Input

Offset Error (Note 6)

Gain Error External Reference

Offset Drift ±10 μV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°C

Gain Matching External Reference ±0.3 %FS

12 Bits

●

–2 ±0.4 2 LSB

●

–0.9 ±0.2 0.9 LSB

●

–12 ±2 12 mV

●

–2.5 ±0.5 2.5 %FS

●

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The l denotes the speciﬁ cations which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Offset Matching ±2 mV

Transition Noise SENSE = 1V 0.32 LSB

ANALOG INPUT

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN,CM

SENSE

MODE

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Analog Input Range (A

Analog Input Common Mode (A

Analog Input Leakage Current 0V < A

SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V

MODE Input Leakage Current 0V < MODE < V

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

Full Power Bandwidth Figure 8 Test Circuit 640 MHz

–

–A

) 2.85V < V

–

= 25°C. (Note 4)

< 3.4V (Note 7)

)/2 Differential Input Drive (Note 7)

Single Ended Input Drive (Note 7)

–

, A

< V

●

±0.5V to ±1V V

0.5

–1 1 μA

–3 3 μA

1.5

RMS

1.9 2

RMS

V V

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 70.2 dB

30MHz Input 70.1 dB

68 70 dB

●

70 82 dB

●

77 90 dB

●

67 69.6 dB

●

SFDR Spurious Free Dynamic Range

S/(N+D) Signal-to-Noise Plus Distortion Ratio

2nd or 3rd Harmonic

4th Harmonic or Higher

Intermodulation Distortion fIN = 40MHz, 41MHz 85 dB

Crosstalk f

70MHz Input

140MHz Input 69.6 dB

5MHz Input 88 dB

30MHz Input 85 dB

70MHz Input

140MHz Input 78 dB

5MHz Input 90 dB

30MHz Input 90 dB

70MHz Input

140MHz Input 90 dB

5MHz Input 69.8 dB

30MHz Input 69.7 dB

70MHz Input

140MHz Input 69.5 dB

= 100MHz –110 dB

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INTERNAL REFERENCE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage I

Output Tempco ±25 ppm/°C

Line Regulation 2.85V < VDD < 3.4V 3 mV/V

Output Resistance

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over the

= 0 1.475 1.500 1.525 V

OUT

< 1mA

OUT

(Note 4)

4Ω

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN, MUX)

LOGIC OUTPUTS

= 3V

SOURCE

SINK

= 2.5V

= 1.8V

High Level Input Voltage VDD = 3V

Low Level Input Voltage VDD = 3V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10μA

Low Level Output Voltage IO = 10μA

High Level Output Voltage IO = –200μA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200μA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

OUT

= –200μA

= 1.6mA

= 0V 50 mA

= 3V 50 mA

●

–10 10 μA

●

2.995

2.7

●

2.99

0.005

0.09 0.4

0.8 V

V V

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LTC2283

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The l denotes the speciﬁ cations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise speciﬁ cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DISS

SHDN

NAP

The l denotes the speciﬁ cations which apply over the full operating temperature

TIMING CHARACTERISTICS

Analog Supply Voltage (Note 9)

Output Supply Voltage (Note 9)

Supply Current Both ADCs at f

Power Dissipation Both ADCs at f Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pipeline Latency 5 Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V

Note 4: V drive, unless otherwise noted.

Sampling Frequency (Note 9)

CLK Low Time Duty Cycle Stabilizer Off (Note 7)

CLK High Time Duty Cycle Stabilizer Off (Note 7)

Sample-and-Hold Aperture Delay 0 ns

CLK to DATA Delay CL = 5pF (Note 7)

CLK to CLKOUT Delay CL = 5pF (Note 7)

DATA to CLKOUT Skew (t

MUX to DATA Delay CL = 5pF (Note 7) Data Access Time After OE↓ C

BUS Relinquish Time (Note 7)

= 3V, f

= 125MHz, input range = 2V

SAMPLE

= 25°C. (Note 8)

without latchup.

with differential

P-P

S(MAX)

Duty Cycle Stabilizer On (Note 7)

– tC) (Note 7)

= 5pF (Note 7)

Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code ﬂ ickers between 0000 0000 0000 and 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test.

, they

Note 8: V drive. The supply current and power dissipation are the sum total for both channels with both channels active.

Note 9: Recommended operating conditions.

= 3V, f

2.85 3 3.4 V

●

0.5 3 3.6 V

●

1 125 MHz

●

3.8

●

3.8

●

1.4 2.7 5.4 ns

●

1.4 2.7 5.4 ns

●

–0.6 0 0.6 ns

●

1.4 2.7 5.4 ns

●

= 125MHz, input range = 1V

SAMPLE

263 305 mA

790 915 mW

500

4.3 10 ns

3.3 8.5 ns

with differential

P-P

ns ns

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TYPICAL PERFORMANCE CHARACTERISTICS

Crosstalk vs Input Frequency Typical INL, 2V Range, 125Msps Typical DNL, 2V Range, 125Msps

–100

–105

–110

–115

CROSSTALK (dB)

–120

–125

–130

20 40 60 80

INPUT FREQUENCY (MHz)

100

2283 G01

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1024 2048 4096

CODE

3072

2283 G02

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1024 2048 4096

CODE

3072

2283 G03

8192 Point FFT, f –1dB, 2V Range, 125Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

10 20 30 40 50

FREQUENCY (MHz)

8192 Point FFT, f –1dB, 2V Range, 125Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

10 20 30 40 50

FREQUENCY (MHz)

= 5MHz,

= 140MHz,

2283 G04

2283 G07

8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 125Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

10 20 30 40 50

FREQUENCY (MHz)

8192 Point 2-Tone FFT,

= 28.2MHz and 26.8MHz,

–1dB, 2V Range, 125Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

10 20 30 40 50

FREQUENCY (MHz)

2283 G05

2283 G08

8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 125Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

10 20 30 40 50

FREQUENCY (MHz)

Grounded Input Histogram, 125Msps

70000

4249

2045

58717

2046 CODE

60000

50000

40000

COUNT

30000

20000

10000

2044

2562

2047

2283 G06

2048

2283 G09

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TYPICAL PERFORMANCE CHARACTERISTICS

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LTC2283

SNR vs Input Frequency, –1dB, 2V Range, 125Msps

SNR (dBFS)

50 100 200

150

INPUT FREQUENCY (MHz)

SNR vs Input Level,

= 70MHz, 2V Range, 125Msps

SNR (dBc AND dBFS)

–50 –40

–60

dBFS

dBc

–30

INPUT LEVEL (dBFS)

250 300 350

2283 G10

–20

–10

2283 G13

SFDR vs Input Frequency, –1dB, 2V Range, 125Msps

SFDR (dBFS)

50 100

INPUT FREQUENCY (MHz)

200 300 350

150 250

SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps

110

100

SFDR (dBc AND dBFS)

–60

dBFS

dBc

–40 –20–50 –30 –10

INPUT LEVEL (dBFS)

2283 G11

2283 G14

(mA)

SNR and SFDR vs Sample Rate, 2V Range, f

SNR AND SFDR (dBFS)

20 40 60 80

vs Sample Rate,

VDD

= 5MHz, –1dB

SFDR

SNR

SAMPLE RATE (Msps)

100 120 140 160

5MHz Sine Wave Input, –1dB

290

280

270

260

VDD

250

240

230

220

210

200

190

2V RANGE

1V RANGE

SAMPLE RATE (Msps)

100 120

2283 G12

140

2283 G15

vs Sample Rate, 5MHz Sine

OVDD

Wave Input, –1dB, 0VDD = 1.8V SNR vs SENSE, fIN = 5MHz, –1dB

(mA)

OVDD

20 40 80

SAMPLE RATE (Msps)

100 120 140

2283 G16

SNR (dBFS)

0.4

0.5 0.6 0.8

0.7

SENSE PIN (V)

0.9 1.0 1.1

2283 G17

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PIN FUNCTIONS

(Pin 1): Channel A Positive Differential Analog

INA

Input.

–

(Pin 2): Channel A Negative Differential Analog

INA

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

(Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

GND with 0.1μF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

and a ±0.5V input range. V

selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input range of ±V

(Pin 20): Channel B 1.5V Output and Input Common

CMB

. ±1V is the largest valid input range.

SENSEB

Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor. Do not connect to V

CMA

MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA11; Channel B comes out on DB0-DB11. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB11; Channel B comes out on DA0-DA11. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. (This is not recommended at clock frequencies above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to V

results in normal operation

with the outputs at high impedance. Connecting SHDNB to V outputs at high impedance. Connecting SHDNB to V and OEB to V

and OEB to GND results in nap mode with the

results in sleep mode with the outputs

at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

NC (Pins 24, 25, 41, 42): Do not connect these pins.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.

–

(Pin 15): Channel B Negative Differential Analog

INB

Input.

(Pin 16): Channel B Positive Differential Analog

INB

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to V

selects the internal reference

CMB

DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital Outputs. DB11 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

(Pins 32, 49): Positive Supply for the Output Drivers.

Bypass to ground with 0.1μF ceramic chip capacitor.

CLKOUT (Pin 40): Data Ready Clock Output. Latch data on the falling edge of CLKOUT. CLKOUT is derived from CLKB. Tie CLKA to CLKB for simultaneous operation.

DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital Outputs. DA11 is the MSB.

OF (Pin 57): Overﬂ ow/Underﬂ ow Output. High when an overﬂ ow or underﬂ ow has occurred on either Channel A or Channel B.

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PIN FUNCTIONS

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LTC2283

OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function.

SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to V

results in normal operation

with the outputs at high impedance. Connecting SHDNA to V outputs at high impedance. Connecting SHDNA to V and OEA to V

and OEA to GND results in nap mode with the

results in sleep mode with the outputs

at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V

selects offset binary output format and turns the

FUNCTIONAL BLOCK DIAGRAM

clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. V

selects 2’s complement output format and turns

the clock duty cycle stabilizer off.

(Pin 61): Channel A 1.5V Output and Input Common

CMA

Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor. Do not connect to V

CMB

SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to V and a ±0.5V input range. V

selects the internal reference

CMA

selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input range of ±V

. ±1V is the largest valid input range.

SENSEA

GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground.

2.2μF

SENSE

INPUT

S/H

–

1.5V

REFERENCE

RANGE

SELECT

FIRST PIPELINED

ADC STAGE

REF BUF

SECOND PIPELINED

ADC STAGE

DIFF REF AMP

REFH

1μF 1μF

THIRD PIPELINED

0.1μF

2.2μF

ADC STAGE

REFL

INTERNAL CLOCK SIGNALSREFH REFL

FOURTH PIPELINED

CLOCK/DUTY

CYCLE

CONTROL

CLK

FIFTH PIPELINED

CONTROL

LOGIC

SHDN

ADC STAGE

OEMODE

ADC STAGE

*OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS.

SIXTH PIPELINED

ADC STAGE

SHIFT REGISTER

AND CORRECTION

OUTPUT DRIVERS

OGND

2283 F01

•

OF*

D11

CLKOUT*

Figure 1. Functional Block Diagram (Only One Channel is Shown)

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TIMING DIAGRAMS

ANALOG

INPUT

CLKA = CLKB

D0-D11, OF

CLKOUT

Dual Digital Output Bus Timing

(Only One Channel is Shown)

N + 2

N + 1

N – 5 N

N – 4 N – 3 N – 2 N – 1

N + 3

N + 4

N + 5

2283 TD01

ANALOG

INPUT A

ANALOG

INPUT B

CLKA = CLKB = MUX

D0A-D11A

D0B-D11B

CLKOUT

Multiplexed Digital Output Bus Timing

APA

B – 4

A – 4

A + 2

B + 2

APB

A – 5

B – 5

A – 5

A + 1

B + 1

A – 4

B – 4

A – 3

B – 3

A – 3

A + 3

B + 3

A – 2

B – 2

A – 2

A + 4

B + 4

A – 1

B – 1

2283 TD02

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APPLICATIONS INFORMATION

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LTC2283

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the ﬁ rst ﬁ ve harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is deﬁ ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal.

Input Bandwidth

The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

THD= 20log (V22+ V32+ V42+ ...Vn2)/V1

where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the ﬁ fth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are

 

 

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNR

Crosstalk

Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal).

CONVERTER OPERATION

As shown in Figure 1, the LTC2283 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value ﬁ ve cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly

= –20log (2π • fIN • t

JITTER

)

2283fb

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worse harmonic distortion. The CLK input is single-ended. The LTC2283 has two phases of operation, determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue ampliﬁ er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is ampliﬁ ed and output by the residue ampliﬁ er. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the Block Diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H ampliﬁ er which drives the ﬁ rst pipelined ADC stage. The ﬁ rst stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the ﬁ rst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the

third stage. An identical process is repeated for the third, fourth and ﬁ fth stages, resulting in a ﬁ fth stage residue that is sent to the sixth stage ADC for ﬁ nal evaluation.

Each ADC stage following the ﬁ rst has additional range to accommodate ﬂ ash and ampliﬁ er offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2283 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C

SAMPLE

) through NMOS transistors. The capacitors shown attached to each input (C

PARASITIC

) are the summation of all other capacitance

associated with each input.

During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected

LTC2283

15Ω

CLK

15Ω

–

Figure 2. Equivalent Input Circuit

C 1pF

PARASITIC

SAMPLE

3.5pF

SAMPLE

3.5pF

2283 F02

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from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, A

–

should be driven with the input signal and A connected to 1.5V or V

should be

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The V to provide the common mode bias level. V

output pin may be used

can be tied

directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The V

pin must be bypassed to ground

close to the ADC with a 2.2μF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic performance of the LTC2283 can be inﬂ uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can inﬂ uence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when

CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F

ENCODE

); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2283 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with V

, setting the ADC input

signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

2.2μF

ANALOG

INPUT

0.1μF T1 1:1

T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

Figure 3. Single-Ended to Differential Conversion Using a Transformer

25Ω

0.1μF

25Ω

12pF

LTC2283

–

2283 F03

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2.2μF

12pF

LTC2283

–

2283 F04

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

–

25Ω

Figure 4. Differential Drive with an Ampliﬁ er

2.2μF

12pF

LTC2283

–

2283 F05

ANALOG

INPUT

0.1μF

25Ω

0.1μF

Figure 5. Single-Ended Drive

Figure 4 demonstrates the use of a differential ampliﬁ er to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.

Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required.

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.

For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a ﬂ ux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.

2.2μF

ANALOG

INPUT

0.1μF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

12Ω

0.1μF

12Ω

8pF

–

Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz

2.2μF

ANALOG

INPUT

0.1μF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1μF

–

Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz

2.2μF

ANALOG

0.1μF

INPUT

0.1μF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE

25Ω

0.1μF

8.2nH

8.2nH A

Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz

–

LTC2283

2283 F06

LTC2283

2283 F07

LTC2283

2283 F08

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Reference Operation

Figure 9 shows the LTC2283 reference circuitry consisting of a 1.5V bandgap reference, a difference ampliﬁ er and switching and control circuit. The internal voltage reference can be conﬁ gured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to V pin to V

selects the 1V range.

selects the 2V range; tying the SENSE

The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference ampliﬁ er to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, V

. This provides a high

frequency low impedance path to ground for internal and external circuitry.

LTC2283

4Ω

TIE TO V

RANGE = 2 • V

0.5V < V

1.5V

FOR 2V RANGE; FOR 1V RANGE;

1μF

SENSE

FOR

< 1V

2.2μF

SENSE

REFH

1.5V BANDGAP REFERENCE

1V 0.5V

RANGE DETECT

AND

CONTROL

BUFFER

INTERNAL ADC HIGH REFERENCE

The difference ampliﬁ er generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges.

Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1μF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB.

1.5V

12k

0.75V

12k

Figure 10. 1.5V Range ADC

2.2μF

SENSE

1μF

LTC2283

2283 F10

Input Range

2.2μF

1μF

0.1μF

REFL

DIFF AMP

INTERNAL ADC LOW REFERENCE

2283 F09

Figure 9. Equivalent Reference Circuit

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 4dB. See the Typical Performance Characteristics section.

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11).

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CLEAN

BEAD

0.1μF

CLK

SUPPLY

LTC2283

2283 F11

4.7μF

FERRITE

50Ω

0.1μF

NC7SVU04

SINUSOIDAL

CLOCK

INPUT

Figure 11. Sinusoidal Single-Ended CLK Drive Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

The noise performance of the LTC2283 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, ﬁ lter the CLK signal to reduce wideband noise and distortion products generated by the source.

CLEAN

FERRITE

BEAD

0.1μF

CLK

0.1μF

SUPPLY

LTC2283

CLK

FERRITE

BEAD

2283 F12

LTC2283

2283 F13

4.7μF

100Ω

IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR

ETC1-1T

5pF-30pF

DIFFERENTIAL

CLOCK

INPUT

Figure 13. LVDS or PECL CLK Drive Using a Transformer

It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact.

The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass ﬁ lter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reﬂ ections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2283 is 125Msps. The lower limit of the LTC2283 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on

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small valued capacitors. Junction leakage will discharge the capacitors. The speciﬁ ed minimum operating frequency for the LTC2283 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V

or 2/3VDD

using external resistors.

This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock.

For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output buffer. Each buffer is powered by OV

and OGND, isolated

from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2283 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation the capacitive load should be kept under 10pF.

Lower OV

voltages will also help reduce interference

from the digital outputs.

LTC2283

0.5V

OGND

TO 3.6V

0.1μF

TYPICAL DATA OUTPUT

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overﬂ ow bit. Note that OF is high when an overﬂ ow or underﬂ ow has occurred on either Channel A or Channel B.

Table 1. Output Codes vs Input Voltage

(2V Range) OF

>+1.000000V

+0.999512V +0.999024V

+0.000488V

0.000000V –0.000488V –0.000976V

–0.999512V –1.000000V

<–1.000000V

–

– A

1 0 0

0 0 0 0

0 0 1

D11 – D0

(Offset Binary)

1111 1111 1111 1111 1111 1111 1111 1111 1110

1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110

0000 0000 0001 0000 0000 0000 0000 0000 0000

D11 – D0

(2’s Complement)

0111 1111 1111 0111 1111 1111 0111 1111 1110

0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110

1000 0000 0001 1000 0000 0000 1000 0000 0000

2283 F14

Figure 14. Digital Output Buffer

Data Format

Using the MODE pin, the LTC2283 parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3V output format. Connecting MODE to 2/3V

selects offset binary

or VDD selects

2’s complement output format. An external resistor divider can be used to set the 1/3V

or 2/3VDD logic values.

Table 2 shows the logic states for the MODE pin.

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Table 2. MODE Pin Function

MODE PIN OUTPUT FORMAT

0 Offset Binary Off

1/3V

2/3V

Offset Binary On

2’s Complement On

2’s Complement Off

CLOCK DUTY

CYCLE STABILIZER

Overﬂ ow Bit

When OF outputs a logic high the converter is either overranged or underranged on channel A or channel B. Note that both channels share a common OF pin, which is not the case for slower pin compatible parts such as the LTC2282 or LTC2294. OF is disabled when channel A is in sleep or nap mode.

Output Clock

The ADC has a delayed version of the CLKB input available as a digital output, CLKOUT. The falling edge of the CLKOUT pin can be used to latch the digital output data. CLKOUT is disabled when channel B is in sleep or nap mode.

Output Driver Power

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to V

and OE to VDD results

in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to V

and OE

to GND results in nap mode, which typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA, SHDNB). Channel A is controlled by SHDNA and OEA, and channel B is controlled by SHDNB and OEB. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OV

, should be tied

to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OV

should be tied to that same

1.8V supply.

can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OV will swing between OGND and OV

. The logic outputs

Output Enable

The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Channels A and B have independent output enable pins (OEA, OEB).

Digital Output Multiplexer

The digital outputs of the LTC2283 can be multiplexed onto a single data bus if the sample rate is 80Msps or less. The MUX pin is a digital input that swaps the two data busses. If MUX is High, channel A comes out on DA0-DA11; channel B comes out on DB0-DB11. If MUX is Low, the output busses are swapped and channel A comes out on DB0-DB11; channel B comes out on DA0-DA11. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together (see the Timing Diagram for the multiplexed mode). The multiplexed data is available on either data bus — the unused data bus can be disabled with its OE pin.

Grounding and Bypassing

The LTC2283 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care

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should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the V tors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2μF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2283 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2283 is transferred from the die through the bottom-side Exposed Pad and package leads onto the printed circuit board. For good electrical and thermal performance, the Exposed Pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufﬁ cient area.

Clock Sources for Undersampling

Undersampling is especially demanding on the clock source, and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that

, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not ﬁ lter the clock signal with a narrow band ﬁ lter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.

The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a ﬁ lter close to the ADC may be beneﬁ cial. This ﬁ lter should be close to the ADC to both reduce roundtrip reﬂ ection times, as well as reduce the susceptibility of the traces between the ﬁ lter and the ADC. If the circuit is sensitive to closein phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing ﬂ ip-ﬂ op as well as the oscillator should be close to the ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

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QDV

Evaluation Circuit Schematic of the LTC2283

3579111315171921232527293133353739

EDGE-CON-100

246

101214161820222426283032343638

R42

20191817161514

FXLH42245MPX

CCB

CCA

124 23

3456789

JP1 MODE

2/3V

R11kR21kR3

JP2 SENSEA

B5B4B6

PAD

EXPOSED

A3A2A4A5A6A7OE

2.2μF

GND

1/3V

EXT REF

T/R

GND GND GNDGND

0.1μF

C44

0.1μF

EXT

REF A

CCINVSS

SCL

R34

B5B4B6

PAD

μF

0.01

GND

C48

C47

C41

C40

3VE5PWR

C45

R25

C36

100μF

4.7k

QDV

105k

GND

0.1μF

4.7μF

6.3V

OPT

R37

4.99k

R36

4.99k

24LC025

C46

0.1μF

R35

100k

C24

0.1μF

NC7SV86P5X

T/R

GND GND GNDGND

11 12 13 25

C50

10μF

6.3V

QDV

R40

105k

C49

ADJ

BYP

OUT

U13

LT1761ES5-BYP

1μF

C51

C55

0.1μF

C54

0.1μF

QDV

C53

0.1μF

C52

0.1μF

GND

876

A0A1A2

123

μF

0.01

GND

QDV

R33

4.7k

CCIN

VSSSCL

SDA

ENABLE

41434547495153555759616365676971737577

42444648505254565860626466687072747678

20191817161514

FXLH42245MPX

CCB

QDV

CCB

CCA

124 23

11 12 13 25

CMA

ANALOG

0.1μF

OPT

INPUT A

123

3456789

0.1μF

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

0.1μF

24.9Ω

••

24.9Ω

B5B4B6

PAD

EXPOSED

A3A2A4A5A6A7OE

484746454443424140393837363534

OGND DA8 DA9

DA10 DA11 DA12 DA13

OEA

VCMA

GND

123456789

DA7

SHDNA

MODE

0.1μF

INA

51Ω

DA6

SENSEA

–

INA

C9 1μF

CMA

C12

DA5

REFHA

4.7μF

0.1μF

DA4

REFHA

C11

C10

6.3V

BEAD

0.1μF

DA3

REFLA

2.2μF

DA2

DA1

REFLA

VDDCLKA

C13 1μF

C14

T/R

GND GND GNDGND

DA0

DB13

CLKOUT

LTC2283

CLKB

VDDREFLB

10111213141516

C18 1μF

0.1μF

C15

0.1μF

R10

C19

CLOCK

U10

FXLH42245MPX

QDV

124 23

11 12 13 25

DB9

DB12

DB11

DB10

–

REFLB

REFHB

C21

0.1μF

C20

2.2μF

C17

0.1μF

R15

0.1μF R14

INPUT

20191817161514

CCB

CCA

3456789

DB8

DB7

OGND

DB6

DB5

DB4

DB3

DB2

DB1

DB0

OEB

SHDNB

MUX

VCMB

SENSEB

GND

INB

C23 1μF

R39

R32

OPT

NC7SVU04

49.9Ω

B5B4B6

PAD

EXPOSED

A3A2A4A5A6A7OE

C25

0.1μF

C27

0.1μF

R18

C29

R17

ANALOG

7981838587899193959799

808284868890929496

U11

R22

••

QDV

24.9Ω

20191817161514

FXLH42245MPX

CCB

CCA

124 23

3456789

U12

LT1761ES5-BYP

C35

EXT REF

CMB

EXT

R24

C34

R23

51Ω

CMB

C33

0.1μF

OPT

T/R

C28

CMB

INPUT B

GND GND GNDGND

2.2μF

JP3 SENSEB

C31

R20

24.9Ω

123

11 12 13 25

100

EXPOSED

A3A2A4A5A6A7OE

C37

10μF

6.3V

R25

105k

C38

ADJ

BYP

OUT

1μF

C39

0.1μF

REF B

0.1μF

R38

4.99k

SCL

R41

100k

*VERSION TABLE

2283 AI01

SDA

< 70MHz

< 140MHz

INPUT FREQUENCY

1MHz < A

70MHz < A

T1, T2

MABAES0060

MABA-007159-000000

8pF

12pF

C6, C31

24.9Ω

12.4Ω

R5, R9, R18, R24

125

Msps

1012141012

BITS

LTC2281IUP

LTC2283IUP

LTC2285IUP

LTC2281IUP

DC1098A-A

DC1098A-B

DC1098A-C

DC1098A-D

ASSEMBLY TYPE

< 140MHz

70MHz < A

MABA-007159-000000

8pF

12.4Ω

125

LTC2283IUP

LTC2285IUP

DC1098A-F

DC1098A-E

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APPLICATIONS INFORMATION

www.BDTIC.com/LINEAR

LTC2283

Silkscreen Top

Top Side

2283fb

LTC2283

www.BDTIC.com/LINEAR

APPLICATIONS INFORMATION

Inner Layer 2 GND Inner Layer 3 Power

Bottom Side

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PACKAGE DESCRIPTION

www.BDTIC.com/LINEAR

LTC2283

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 ±0.05

7.15 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9 .00 ± 0.10

(4 SIDES)

PIN 1 TOP MARK (SEE NOTE 5)

7.50 REF

(4 SIDES)

8.10 ±0.05 9.50 ± 0.05

PACKAGE OUTLINE

0.75 ± 0.05 R = 0.10

TYP

7.50 REF

(4-SIDES)

R = 0.115

7.15 ± 0.10

TYP

PIN 1

CHAMFER

C = 0.35

6463

0.40 ± 0.10

1 2

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.200 REF

0.00 – 0.05

7.15 ± 0.10

(UP64) QFN 0406 REV C

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

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LTC2283

www.BDTIC.com/LINEAR

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package

LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR

LTC1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain

LTC1994 Low Noise, Low Distortion Fully Differential Input/Output

Ampliﬁ er/Driver

LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN Package

LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package

LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN Package

LTC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN Package

LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN Package

LTC2255 14-Bit, 125Msps ADC, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN Package

LTC2280 10-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 320mW, 61.6dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2282 12-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN Package

LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN Package

LTC2286 10-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2287 10-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2288 10-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package

LTC2289 10-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 422mW, 61.6dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2290 12-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk 120mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2291 12-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2292 12-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2293 12-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2294 12-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 422mW, 70.6dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2295 14-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk 120mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2296 14-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk 150mW, 74.5dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2297 14-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk 235mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2298 14-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk 400mW, 74.3dB SNR, 90dB SFDR, 64-Pin QFN Package

LTC2299 14-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk 444mW, 73dB SNR, 90dB SFDR, 64-Pin QFN Package

LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

LT5514 Ultralow Distortion IF Ampliﬁ er/ADC Driver with Digitally

Controlled Gain

LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator

LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator

LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,

Low Distortion: –94dB at 1MHz

450MHz to 1dB BW, 47dB OIP3, Digital Gain Control

10.5dB to 33dB in 1.5dB/Step

50Ω Single Ended RF and LO Ports

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

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LT 1207 REV B • PRINTED IN USA

LINEAR TECHNOLOGY LTC2283 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual