LINEAR TECHNOLOGY LTC1407, LTC1407A Technical data

FEATURES

■

3Msps Sampling ADC with Two Simultaneous
Differential Inputs

■

1.5Msps Throughput per Channel

■

Low Power Dissipation: 14mW (Typ)

■

3V Single Supply Operation

■

2.5V Internal Bandgap Reference with External
Overdrive

■

3-Wire Serial Interface

■

Sleep (10µW) Shutdown Mode

■

Nap (3mW) Shutdown Mode

■

80dB Common Mode Rejection at 100kHz

■

0V to 2.5V Unipolar Input Range

■

Tiny 10-Lead MS Package

U

APPLICATIO S

■

Telecommunications

■

Data Acquisition Systems

■

Uninterrupted Power Supplies

■

Multiphase Motor Control

■

I & Q Demodulation

■

Industrial Control

LTC1407/LTC1407A

Serial 12-Bit/14-Bit, 3Msps

Simultaneous Sampling

ADCs with Shutdown

U

DESCRIPTIO

The LTC®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs
with two 1.5Msps simultaneously sampled differential
inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10µW.
The combination of speed, low power and tiny package
makes the LTC1407/LTC1407A suitable for high speed,
portable applications.

The LTC1407/LTC1407A contain two separate differential
inputs that are sampled simultaneously on the rising edge
of the CONV signal. These two sampled inputs are then
converted at a rate of 1.5Msps per channel.

The 80dB common mode rejection allows users to elimi­nate ground loops and common mode noise by measuring
signals differentially from the source.

The devices convert 0V to 2.5V unipolar inputs differen­tially. The absolute voltage swing for CH0
and CH1– extends from ground to the supply voltage.

The serial interface sends out the two conversion results in
32 clocks for compatibility with standard serial interfaces.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6084440, 6522187.

+

, CH0–, CH1

+

BLOCK DIAGRA

+

10µF

CH0

CH0

CH1

CH1

–

+

–

1

2

4

5

3

6

11

+

S & H

–

+

S & H

–

V

REF

GND

EXPOSED PAD

MUX

REFERENCE

W

2.5V

3Msps

14-BIT ADC

3V10µF

7

V

DD

14-BIT LATCH14-BIT LATCH

LTC1407A

THREE-

STAT E

SERIAL

OUTPUT

PORT

TIMING

LOGIC

10

8

9

1407A BD

SDO

CONV

SCK

–44

–50

–56

–62

–68

–74

–80

THD, 2nd, 3rd (dB)

–86

–92

–98

–104

THD, 2nd and 3rd

vs Input Frequency

0.1

110100

FREQUENCY (MHz)

THD

2nd

3rd

1407 G02

1407fa

1

LTC1407/LTC1407A

1
2
3
4
5

CH0

+

CH0

–

V

REF

CH1

+

CH1

–

10
9
8
7
6

CONV
SCK
SDO
V

DD

GND

TOP VIEW

11

MSE PACKAGE

10-LEAD PLASTIC MSOP

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UU

W

(Notes 1, 2)

Supply Voltage (VDD) ................................................. 4V

Analog Input Voltage

(Note 3) ................................... – 0.3V to (V

Digital Input Voltage .................... – 0.3V to (V

Digital Output Voltage .................. – 0.3V to (V

Power Dissipation.............................................. 100mW

Operation Temperature Range

LTC1407C/LTC1407AC ............................ 0°C to 70°C

LTC1407I/LTC1407AI ......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

T

= 125°C, θJA = 150°C/ W

EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO PCB

JMAX

ORDER PART NUMBER MSE PART MARKING

LTC1407CMSE
LTC1407IMSE
LTC1407ACMSE
LTC1407AIMSE

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTBDQ
LTBDR
LTAFE
LTAFF

U

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes)
Integral Linearity Error (Notes 5, 17)
Offset Error (Notes 4, 17)

Offset Match from CH0 to CH1 (Note 17) –5 ±0.5 5 –10 ±110 LSB
Gain Error (Notes 4, 17)

Gain Match from CH0 to CH1 (Note 17) –5 ±1 5 –10 ±210 LSB
Gain Tempco Internal Reference (Note 4) ±15 ±15 ppm/°C

A

The ● denotes the specifications which apply over the full operating

= 25°C. With internal reference, VDD = 3V.

LTC1407 LTC1407A

●

12 14 Bits

●

–2 ± 0.25 2 –4 ± 0.5 4 LSB

●

–10 ±1 10 –20 ±220 LSB

●

–30 ±5 30 –60 ±10 60 LSB

External Reference ±1 ±1 ppm/°C

UU

A ALOG I PUT

otherwise specifications are at T

The ● denotes the specifications which apply over the full operating temperature range,

= 25°C. With internal reference, VDD = 3V.

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

V

CM

I

IN

C

IN

t

ACQ

t

AP

t

JITTER

t

SK

CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V –60 dB

2

Analog Differential Input Range (Notes 3, 9) 2.7V ≤ VDD ≤ 3.3V 0 to 2.5 V

Analog Common Mode + Differential 0 to V
Input Range (Note 10)

Analog Input Leakage Current

Analog Input Capacitance 13 pF

Sample-and-Hold Acquisition Time (Note 6)

Sample-and-Hold Aperture Delay Time 1 ns

Sample-and-Hold Aperture Delay Time Jitter 0.3 ps

Sample-and-Hold Aperture Skew from CH0 to CH1 200 ps

fIN = 100MHz, VIN = 0V to 3V –15 dB

●

●

DD

1 µA

39 ns

1407fa

V

LTC1407/LTC1407A

U

W

DY A IC ACCURACY

otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

SINAD Signal-to-Noise Plus 100kHz Input Signal 70.5 73.5 dB

Distortion Ratio 750kHz Input Signal

THD Total Harmonic 100kHz First 5 Harmonics 87 –90 dB

Distortion 750kHz First 5 Harmonics

SFDR Spurious Free 100kHz Input Signal 87 90 dB

Dynamic Range 750kHz Input Signal 83 86 dB

IMD Intermodulation 1.25V to 2.5V 1.40MHz into CH0+, 0V to 1.25V, –82 –82 dB

Distortion 1.56MHz into CH0

Code-to-Code V
Transition Noise

Full Power Bandwidth VIN = 2.5V
Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz

= 25°C. With internal reference, VDD = 3V.

A

100kHz Input Signal, External V
750kHz Input Signal, External V

The ● denotes the specifications which apply over the full operating temperature range,

LTC1407 LTC1407A

●

68 70.5 70 73.5 dB

= 3.3V, VDD ≥ 3.3V 72.0 76.3 dB

REF

= 3.3V, VDD ≥ 3.3V 72.0 76.3 dB

REF

●

–

. Also Applicable to CH1+ and CH1

= 2.5V (Note 17) 0.25 1 LSB

REF

, SDO = 11585LSB

P-P

(–3dBFS) (Note 15) 50 50 MHz

P-P

–

83 –77 –86 –80 dB

RMS

UU U

I TER AL REFERE CE CHARACTERISTICS

TA = 25°C. VDD = 3V.

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

Output Voltage I

REF

V

Output Tempco 15 ppm/°C

REF

V

Line Regulation VDD = 2.7V to 3.6V, V

REF

V

Output Resistance Load Current = 0.5mA 0.2 Ω

REF

V

Settling Time 2ms

REF

= 0 2.5 V

OUT

= 2.5V 600 µV/V

REF

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

I

IN

C

IN

V

OH

V

OL

I

OZ

C

OZ

I

SOURCE

I

SINK

High Level Input Voltage VDD = 3.3V

Low Level Input Voltage VDD = 2.7V

Digital Input Current VIN = 0V to V

Digital Input Capacitance 5pF

High Level Output Voltage VDD = 3V, I

Low Level Output Voltage VDD = 2.7V, I

= 2.7V, I

V

DD

Hi-Z Output Leakage D

Hi-Z Output Capacitance D

Output Short-Circuit Source Current V

Output Short-Circuit Sink Current V

OUT

OUT

V

OUT

OUT

OUT

= 25°C. VDD = 3V.

A

DD

= –200µA

OUT

OUT
OUT

= 0V to V

= 0V, VDD = 3V 20 mA

= VDD = 3V 15 mA

DD

The ● denotes the specifications which apply over the

●

2.4 V

●

●

●

2.5 2.9 V

= 160µA 0.05 V
= 1.6mA

●

●

0.10 0.4 V

1pF

0.6 V

± 10 µA

± 10 µA

1407fa

3

LTC1407/LTC1407A

WU

POWER REQUIRE E TS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

I

DD

PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW

Supply Voltage 2.7 3.6 V

Supply Current Active Mode, f

A

The ● denotes the specifications which apply over the full operating temperature

= 25°C. With internal reference, VDD = 3V.

= 1.5Msps
Nap Mode
Sleep Mode (LTC1407) 2.0 15 µA
Sleep Mode (LTC1407A) 2.0 10 µA

SAMPLE

●

●

4.7 7.0 mA

1.1 1.5 mA

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SAMPLE(MAX)

t

THROUGHPUT

t

SCK

t

CONV

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

12

Maximum Sampling Frequency per Channel
(Conversion Rate)

Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period (Note 16)

Conversion Time (Note 6) 32 34 SCLK cycles
Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns
CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns

SCK Before CONV (Note 6) 0 ns
Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns

SCK to Sample Mode (Note 6) 4 ns
CONV to Hold Mode (Notes 6, 11) 1.2 ns
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns

Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
SCK to Hi-Z at SDO (Notes 6, 12) 6 ns

Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
V

Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms

REF

= 25°C. VDD = 3V.

A

The ● denotes the specifications which apply over the full operating temperature

●

1.5 MHz

●

●

19.6 10000 ns

667 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V

clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V

Note 4: Offset and range specifications apply for a single-ended CH0

+

input with CH0– or CH1– grounded and using the internal 2.5V

CH1
reference.

Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.

Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference

between CH0
Note 9: The absolute voltage at CH0

within this range.

+

and CH0– or CH1+ and CH1–.

without latchup.

DD

+

, CH0–, CH1+ and CH1– must be

, they will be

DD

+

or

4

Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the

1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the

32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code

swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A is measured and specified with 14-bit Resolution

(1LSB = 152µV) and the LTC1407 is measured and specified with 12-bit
Resolution (1LSB = 610µV).

input sine wave.

P-P

1407fa

UW

FREQUENCY (kHz)

MAGNITUDE (dB)

–60

–30

–20

1407 G05

–70

–80

–120

–100

0

–10

–40

–50

–90

–110

0

200 400100 300 600500 700

1.5Msps

FREQUENCY (MHz)

0.1

68

SFDR (dB)

56

44

1 10 100

1407 G19

80

74

62

50

86

92

98

104

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1407/LTC1407A

= 3V, TA = 25°C (LTC1407A)

V

DD

ENOBs and SINAD
vs Input Sinewave Frequency

12.0

11.5

11.0

10.5

10.0

9.5

ENOBs (BITS)

9.0

8.5

8.0

0.1

1 10 100

FREQUENCY (MHz)

SNR vs Input Frequency

74

71

68

65

62

SNR (dB)

59

56

53

50

0.1

1 10 100

FREQUENCY (MHz)

1407 G01

1407 G03

74

71

68

65

62

59

56

53

50

SINAD (dB)

THD, 2nd and 3rd
vs Input Frequency

–44

–50

–56

–62

–68

–74

–80

THD, 2nd, 3rd (dB)

–86

–92

–98

–104

0.1

1 10 100

FREQUENCY (MHz)

98kHz Sine Wave 4096 Point
FFT Plot

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dB)

–80

–90

–100

–110

–120

0

200 400100 300 600500 700

FREQUENCY (kHz)

THD

SFDR vs Input Frequency

2nd

3rd

1407 G02

748kHz Sine Wave 4096 Point
FFT Plot

1.5Msps

1407 G04

1403kHz Input Summed with
1563kHz Input IMD 4096 Point
FFT Plot

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dB)

–80

–90

–100

–110

–120

0

200 400100 300 600500 700

FREQUENCY (kHz)

1.5Msps

1407 G06

Differential Linearity for CH0 with
Internal 2.5V Reference

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

DIFFERENTIAL LINEARITY (LSB)

–0.8

–1.0

0

4096

8192

OUTPUT CODE

12288

1407 G15

16384

Integral Linearity End Point Fit for
CH0 with Internal 2.5V Reference

2.0

1.6

1.2

0.8

0.4

0

–0.4

–0.8

INTEGRAL LINEARITY (LSB)

–1.2

–1.6

–2.0

0

4096

8192

OUTPUT CODE

12288

16384

1407 G16

1407fa

5

LTC1407/LTC1407A

FREQUENCY (Hz)

110

–50

PSRR (dB)

–45

–40

–35

–30

100 1k 10k 100k 1M

1407 G11

–55

–60

–65

–70

–25

FREQUENCY (Hz)

–70

CROSSTALK (dB)

–50

–20

–80

–60

–40

–30

100 1k 10k 100k 1M 10M

1407 G09

–90

CH0 TO CH1

CH1 TO CH0

UW

TYPICAL PERFOR A CE CHARACTERISTICS

VDD = 3V, TA = 25°C (LTC1407A)

Differential Linearity for CH1 with
Internal 2.5V Reference

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

DIFFERENTIAL LINEARITY (LSB)

–0.8

–1.0

0

4096

8192

OUTPUT CODE

VDD = 3V, TA = 25°C (LTC1407/LTC1407A)

Full-Scale Signal Frequency
Response

12

6

0

–6

–12

–18

AMPLITUDE (dB)

–24

–30

–36

1M 10M 100M 1G

FREQUENCY (Hz)

1407 G07

Integral Linearity End Point Fit for
CH1 with Internal 2.5V Reference

2.0

1.6

1.2

0.8

0.4

0

–0.4

–0.8

INTEGRAL LINEARITY (LSB)

–1.2

–1.6

–2.0

12288

16384

1407 G17

0

4096

8192

OUTPUT CODE

12288

CMRR vs Frequency Crosstalk vs Frequency

0

–20

–40

–60

CMRR (dB)

–80

–100

–120

100 1k

CH0 CH1

10k 100k 1M 10M 100M

FREQUENCY (Hz)

1407 G08

16384

1407 G18

3.0

2.6

2.2

1.8

6

1.4

1.0

0.6

ANALOG INPUTS (V)

0.2

–0.2

–0.6

Simultaneous Input Steps at CH0
and CH1 from 25Ω

CH0
CH1

10

0

5

15 30

TIME (ns)

20

25

1407 G10

PSSR vs Frequency

1407fa

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage vs V

2.4902

DD

2.4902

LTC1407/LTC1407A

VDD = 3V, TA = 25°C (LTC1407/LTC1407A)

Reference Voltage
vs Load Current

2.4900

2.4898

(V)

2.4896

REF

V

2.4894

2.4892

2.4890

2.6 3.6

U

2.8 3.0 3.2 3.4

UU

VDD (V)

1407 G12

PI FU CTIO S

CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates fully
differentially with respect to CH0
differential swing and a 0 to V

–

CH0

(Pin 2): Inverting Channel 0. CH0– operates fully

differentially with respect to CH0
differential swing and a 0 to V

V

(Pin 3): 2.5V Internal Reference. Bypass to GND and

REF

a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Can be
overdriven by an external reference voltage ≥2.55V and
≤V

.

DD

+

(Pin 4): Noninverting Channel 1. CH1+ operates fully

CH1

differentially with respect to CH1
differential swing and a 0 to V

–

(Pin 5): Inverting Channel 1. CH1– operates fully

CH1

differentially with respect to CH1
differential swing and a 0 to V

GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these connections.

–

with a 0V to 2.5V

absolute input range.

DD

+

with a –2.5V to 0V

absolute input range.

DD

–

with a 0V to 2.5V

absolute input range.

DD

+

with a –2.5V to 0V

absolute input range.

DD

2.4900

2.4898

(V)

2.4896

REF

V

2.4894

2.4892

2.4890

(Pin 7): 3V Positive Supply. This single power pin

V

DD

0.4 0.8 1.2 1.6
LOAD CURRENT (mA)

2.00.20 0.6 1.0 1.4 1.8

1407 G13

supplies 3V to the entire chip. Bypass to GND pin and solid
analog ground plane with a 10µF ceramic capacitor (or
10µF tantalum) in parallel with 0.1µF ceramic. Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.

SDO (Pin 8): Three-state Serial Data Output. Each pair of
output data words represent the two analog input chan­nels at the start of the previous conversion.

SCK (Pin 9): External Clock Input. Advances the conver­sion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts Nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts Sleep mode.

1407fa

7

LTC1407/LTC1407A

W

BLOCK DIAGRA

+

10µF

CH0

CH0

CH1

CH1

–

+

–

1

2

4

5

V

3

GND

6

11

+

–

+

–

REF

EXPOSED PAD

S & H

S & H

MUX

2.5V

REFERENCE

3Msps

14-BIT ADC

3V10µF

7

V

DD

14-BIT LATCH14-BIT LATCH

LTC1407A

THREE-

STAT E

SERIAL

OUTPUT

PORT

TIMING

LOGIC

8

10

9

SDO

CONV

SCK

1407A BD

8

1407fa