Step-Down Switching Regulator
with 100µA Quiescent Current
FEATURES
■
Wide Input Range: 3.3V to 60V
■
3A Peak Switch Current
■
Burst Mode® Operation: 100µA Quiescent Current**
■
Low Shutdown Current: IQ < 1µA
■
Power Good Flag with Programmable Threshold
■
Load Dump Protection to 60V
■
500kHz Switching Frequency
■
Saturating Switch Design: 0.1Ω On-Resistance
■
Peak Switch Current Maintained Over
Full Duty Cycle Range*
■
1.25V Feedback Reference Voltage
■
Easily Synchronizable
■
Soft-Start Capability
■
Small 16-Pin Thermally Enhanced TSSOP Package
U
APPLICATIO S
■
High Voltage Power Conversion
■
14V and 42V Automotive Systems
■
Industrial Power Systems
■
Distributed Power Systems
■
Battery-Powered Systems
■
USB Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. *Protected by U.S. Patents including 6498466
**See Burst Mode Operation section for conditions.
LT3435
High Voltage 3A, 500kHz
U
DESCRIPTIO
The LT
regulator that accepts input voltages up to 60V. A high
efficiency 3A, 0.1Ω switch is included on the die along with
all the necessary oscillator, control and logic circuitry.
Current mode topology is used for fast transient response
and good loop stability.
Innovative design techniques along with a new high voltage process achieve high efficiency over a wide input
range. Efficiency is maintained over a wide output current
range by employing Burst Mode operation at low currents,
utilizing the output to bias the internal circuitry, and by
using a supply boost capacitor to fully saturate the power
switch. Patented circuitry maintains peak switch current
over the full duty cycle range.* Shutdown reduces input
supply current to less than 1µA. External synchronization
can be implemented by driving the SYNC pin with logic-level
inputs. A single capacitor from the C
provides a controlled output voltage ramp (soft-start). The
device also has a power good flag with a programmable
threshold and time-out and thermal shutdown protection.
The LT3435 is available in a 16-pin TSSOP package with an
exposed pad leadframe for low thermal resistance.
®
3435 is a 500kHz monolithic buck switching
pin to the output
SS
TYPICAL APPLICATIO
14V to 3.3V Step-Down Converter with
100µA No Load Quiescent Current
4700pF
10k
V
IN
1µF
4.7µF
100V
CER
470pF
V
IN
SHDN
V
C
C
T
SYNC
GND
LT3435
BOOST
SW
C
V
BIAS
PGFB
0.33µF
0.1µF
SS
27pF
FB
PG
15µH
B360A
U
165k
100k
Efficiency and Power Loss
vs Load CurrentSupply Current vs Input Voltage
3435 TA02
10
10
1
0.1
0.01
0.001
3435fa
POWER LOSS (W)
60
100
VIN = 12V
90
80
V
OUT
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.0001
= 5V
EFFICIENCY
V
= 3.3V
OUT
0.001
LOAD CURRENT (A)
0.01
TYPICAL
POWER LOSS
0.1 1
150
V
OUT
3.3V
4148
1%
1%
2A
100µF
+
10V
TANT
3435 TA01
125
100
75
50
SUPPLY CURRENT (µA)
25
0
10
0
20
INPUT VOLTAGE (V)
30 40
V
= 3.3V
OUT
= 25°C
T
A
50
3435 TA03
1
LT3435
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
NC
SW
V
IN
V
IN
SW
BOOST
C
T
GND
PGOOD
SHDN
SYNC
PGFB
FB
V
C
BIAS
C
SS
17
WW
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
VIN, SHDN, BIAS, PGOOD, SW ............................... 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, CSS, PGFB, FB................................................ 6V
Operating JunctionTemperature Range
(Note 2) ........................................... – 40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
UUW
PACKAGE/ORDER I FOR ATIO
T
= 125°C, θJA = 45°C/W, θ
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO GND (PIN 8)
JMAX
ORDER PART NUMBER
LT3435EFE
LT3435IFE
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
= 10°C/W
JC(PAD)
FE PART MARKING
3435EFE
3435IFE
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
J
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
SHDN
I
SHDN
I
VINS
I
VIN
I
BIASS
I
BIAS
V
REF
I
FB
2
SHDN Threshold 1.15 1.3 1.45 V
SHDN Input Current SHDN = 12V
Minimum Input Voltage (Note 3)
Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 µA
Supply Sleep Current (Note 4) BIAS = 0V, FB = 1.35V
FB = 1.35V
Supply Quiescent Current BIAS = 0V, FB = 1.15V 3.3 7 mA
BIAS = 5V, FB = 1.15V 2.6 6 mA
Minimum BIAS Voltage (Note 5)
BIAS Sleep Current (Note 4)
BIAS Quiescent Current SYNC = 3.3V 700 900 µA
Minimum Boost Voltage (Note 6) ISW = 1.5A 1.8 V
Input Boost Current (Note 7) ISW = 3A 65 85 mA
Reference Voltage (V
FB Input Bias Current 75 200 nA
EA Voltage Gain (Note 8) 900 V/V
EA Voltage g
m
) 3.3V < V
REF
dI(VC)= ±10µA 400 650 900 µMho
VIN
< 60V
●
●
●
●
●
●
●
1.225 1.25 1.275 V
520 µA
2.4 3 V
170 250 µA
45 75 µA
2.7 3.1 V
125 180 µA
3435fa
LT3435
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
J
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
EA Source Current FB = 1.15V 20 40 55 µA
EA Sink Current FB = 1.35V 15 30 40 µA
I
PK
I
CSS
I
PGFB
V
PGFB
I
CT
V
CT
VC to SW g
VC High Clamp FB = 1.15V 2.1 2.2 2.4 V
SW Current Limit
Switch On Resistance (Note 9)
Switching Frequency
Maximum Duty Cycle 86 92 %
Minimum SYNC Amplitude 1.5 2.0 V
SYNC Frequency Range 575 700 kHz
SYNC Input Impedance 45 kΩ
CSS Current Threshold (Note 10) FB = 0V 7 13 20 µA
PGFB Input Current 25 100 nA
PGFB Voltage Threshold (Note 11)
CT Source Current (Note 11) 2 3.6 5.5 µA
CT Sink Current (Note 11) 1 2 mA
CT Voltage Threshold (Note 11) 1.16 1.2 1.26 V
PG Leakage (Note 11) 0.1 1 µA
PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 100 200 µA
m
●
3 5.2 6.5 A
●
●
425 500 575 kHz
●
88 90 92 %
6A/V
0.1 0.25 Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3435EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3435IFE is guaranteed and tested over the full –40°C to 125°C
operating junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT3435. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT3435 will be provided by the V
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
currents.
pin. With the
IN
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the
pin held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V
Note 9: Switch on resistance is calculated by dividing V
the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 10: The C
pin which results in an increase in sink current from the VC pin.
the C
SS
See the Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V
which causes the current source output of the C
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C
be set active low with a current sink capability of 200µA.
threshold is defined as the value of current sourced into
SS
swing from 1.15V to 750mV.
C
to SW voltage by
IN
pin to change from
T
pin rises until it is clamped
T
clamp is inactive the PG pin will
T
REF
BIAS
voltage
is
3435fa
3
LT3435
UW
TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage Oscillator Frequency SHDN Threshold
1.30
1.29
1.28
1.27
1.26
1.25
1.24
VOLTAGE (V)
1.23
1.22
1.21
1.20
–50 0
–25
50
25
TEMPERATURE (°C)
100
125
3435 G01
75
550
540
530
520
510
500
490
FREQUENCY (kHz)
480
470
460
450
–50
–25
50
25
0
TEMPERATURE (°C)
1.40
1.35
1.30
1.25
1.20
VOLTAGE (V)
0.15
1.10
1.05
100
125
3435 G02
75
1.00
–50 0
–25
TEMPERATURE (°C)
50
25
75
100
125
3435 G03
SHDN Pin Current
5.5
TJ = 25°C
5.0
4.5
4.0
3.5
3.0
2.5
CURRENT (µA)
2.0
1.5
1.0
0
10
0
Bias Sleep Current
200
180
160
140
120
100
80
CURRENT (µA)
60
40
20
0
–50 0
–25
30 40
20
SHDN VOLTAGE (V)
50
25
TEMPERATURE (°C)
Shutdown Supply Current Sleep Mode Supply Current
25
20
15
10
CURRENT (µA)
5
0
50
60
3435 G04
–50 0
VIN = 42V VIN = 12V
–25
TEMPERATURE (°C)
VIN = 60V
50
25
75
100
125
3435 G05
PGFB Threshold
1.20
1.18
1.16
1.14
1.12
1.10
1.08
VOLTAGE (V)
1.06
1.04
1.02
1.00
100
125
3435 G07
75
–50 0
–25
TEMPERATURE (°C)
50
25
75
100
125
3435 G08
200
180
160
140
120
100
80
CURRENT (µA)
60
40
20
0
–50 0
–25
PG Sink Current
250
200
150
100
CURRENT (µA)
50
0
–50 0
–25
V
= 0V
BIAS
V
= 5V
BIAS
50
25
TEMPERATURE (°C)
50
25
TEMPERATURE (°C)
100
100
125
3435 G06
125
3435 G09
75
75
4
3435fa
UW
FB VOLTAGE (V)
0
0
NORMALIZED FREQUENCY (%)
20
30
40
50
60
70
80
90
10
0.25 0.50 0.75
3435 G12
1.00
100
1.25
SWITCH CURRENT (mA)
0
0
BOOST CURRENT (mA)
10
30
2000
70
60
3435 G18
20
1000
500
2500
1500 3000
40
50
TYPICAL PERFOR A CE CHARACTERISTICS
LT3435
Switch Peak Current Limit
6.0
5.5
5.0
4.5
4.0
PEAK SWITCH CURRENT (A)
3.5
3.0
–25 –0 25 50
–50
TEMPERATURE (°C)
Switch On Voltage (V
500
450
400
350
300
250
200
VOLTAGE (mV)
150
100
50
0
0.5
1.0 2.0 3.0
1.5
LOAD CURRENT (A)
Soft-Start Current Threshold
vs FB Voltage
50
TJ = 25°C
45
40
35
30
25
20
CURRENT (µA)
15
10
5
0
0
START-UP
0
0.2
RUNNING
START-UP
RUNNING
0.5
75 100 125
3435 G10
) Minimum Input Voltage
CESAT
TJ = 125°C
TJ = 25°C
TJ = –40°C
2.5
3435 G13
8.0
7.5
7.0
6.5
6.0
5.5
5.0
INPUT VOLTAGE (V)
4.5
4.0
3.5
3.0
0.6 0.8
0.4
FB VOLTAGE (V)
V
= 5V
OUT
V
OUT
1.0
1.5 3.0
LOAD CURRENT (A)
2.0
SOFT-START
DEFEATED
1.0
3435 G11
= 3.3V
2.5
3435 G15
1.2
1000
900
800
700
600
500
400
300
LOAD CURRENT (mA)
200
100
Oscillator Frequency
vs FB Voltage
Burst Mode Threshold vs Input
Voltage
V
= 3.3V
0
5
OUT
L = 15µH
= 100µF
C
OUT
= 25°C
T
A
BURST MODE EXIT
(INCREASING LOAD)
BURST MODE ENTER
(DECREASING LOAD)
10 20
INPUT VOLTAGE (V)
15
3435 G16
Minimum On-Time for Continuous
Mode Operation
600
LOAD CURRENT = 1A
550
500
450
400
350
300
ON TIME (ns)
250
200
150
100
–50
–25
50
25
0
TEMPERATURE (°C)
Maximum Synchronization
Frequency vs Temperature Boost Current vs Switch Current
1000
950
900
850
800
750
700
FREQUENCY (kHz)
650
600
550
500
100
125
3435 G17
75
–50
0
–25
TEMPERATURE (°C)
50
25
75
100
125
3435 G14
3435fa
5
LT3435
UW
TYPICAL PERFOR A CE CHARACTERISTICS
4.0
3.5
3.0
2.5
2.0
1.5
OUTPUT VOLTAGE (V)
1.0
0.5
V
OUT
50mV/DIV
AC-COUPLED
I
SW
500mA/DIV
Dropout Operation Dropout Operation
6
V
V
= 3.3V
OUT
BOOST DIODE = DIODES INC DFLS160
LOAD CURRENT = 2.5A
LOAD CURRENT = 250mA
0
2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT VOLTAGE (V)
Burst Mode Operation
3435 G19
V
OUT
200mV/DIV
AC-COUPLED
I
OUT
1A/DIV
= 5V
OUT
BOOST DIODE = DIODES INC DFLS160
5
4
3
2
OUTPUT VOLTAGE (V)
1
0
2 2.5 3 3.5 4 4.5 5 5.5 6.5 7 7.56
LOAD CURRENT = 250mA
INPUT VOLTAGE (V)
No Load 2A Step Response Step Response
LOAD CURRENT = 2.5A
3435 G20
V
OUT
50mV/DIV
AC-COUPLED
I
SW
500mA/DIV
V
OUT
200mV/DIV
AC-COUPLED
I
OUT
1A/DIV
Burst Mode Operation
V
= 12V 10ms/DIV
IN
V
= 3.3V
OUT
3435 G21
V
V
= 12V 10µs/DIV
IN
V
= 3.3V
OUT
U
3435 G22
UU
= 12V 500µs/DIV
IN
V
= 3.3V
OUT
= 100µF
C
OUT
PI FU CTIO S
NC (Pin 1): No Connection.
SW (Pins 2, 5): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum negative switch voltage allowed is –0.8V.
(Pins 3, 4): This is the collector of the on-chip power
V
IN
NPN switch. V
a voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
powers the internal control circuitry when
IN
3435 G23
= 12V 500µs/DIV
V
IN
V
= 3.3V
OUT
C
= 100µF
OUT
= 500mA
I
LOAD(DC)
3435 G24
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.1Ω FET
structure.
CT (Pin 7): A capacitor on the CT pin determines the amount
of delay time between the PGFB pin exceeding its threshold (V
) and the PG pin set to a high impedance state.
PGFB
3435fa
6
LT3435
U
UU
PI FU CTIO S
When the PGFB pin rises above V
from the C
pin into the external capacitor. When the volt-
T
age on the external capacitor reaches an internal clamp
(V
), the PG pin becomes a high impedance node. The
CT
resultant PG delay time is given by t = C
voltage on the PGFB pin drops below V
discharged rapidly to 0V and PG will be active low with a
200µA sink capability. If the C
pin is clamped (Power Good
T
condition) during normal operation and SHDN is taken low,
the C
pin will be discharged and a delay period will occur
T
when SHDN is returned high. See the Power Good section
in Applications Information for details.
GND (Pins 8, 17): The GND pin connection acts as the
reference for the regulated output, so load regulation will
suffer if the “ground” end of the load is not at the same
voltage as the GND pin of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pin and the load ground. Keep the
path between the GND pin and the load ground short and
use a ground plane when possible. The GND pin also acts
as a heat sink and should be soldered (along with the
exposed leadframe) to the copper ground plane to reduce
thermal resistance (see Applications Information).
CSS (Pin 9): A capacitor from the CSS pin to the regulated
output voltage determines the output voltage ramp rate
during start-up. When the current through the C
tor exceeds the C
the output is limited. The C
threshold (I
SS
threshold is proportional to
SS
the FB voltage (see Typical Performance Characteristics)
and is defeated for FB voltage greater than 0.9V (typical).
See Soft-Start section in Applications Information for
details.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency especially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
(Pin 11): The VC pin is the output of the error amplifier
V
C
and the input of the peak switch current comparator. It is
, current is sourced
PGFB
• VCT/ICT. If the
CT
, CCT will be
PGFB
SS
), the voltage ramp of
CSS
capaci-
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. V
sits
C
at about 0.45V for light loads and 2.2V at maximum load.
During the sleep portion of Burst Mode operation, the V
C
pin is held at a voltage slightly below the burst threshold
for better transient response. Driving the V
pin to ground
C
will disable switching and place the IC into sleep mode.
FB (Pin 12): The feedback pin is used to determine the
output voltage using an external voltage divider from the
output that generates 1.25V at the FB pin . When the FB pin
drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the C
pin. See the Feedback section in
SS
Applications Information for details.
PGFB (PIN 13): The PGFB pin is the positive input to a
comparator whose negative input is set at V
PGFB is taken above V
the C
pin starting the PG delay period. When the voltage
T
on the PGFB pin drops below V
, current (I
PGFB
PGFB
) is sourced into
CSS
, the CT pin is rapidly
PGFB
. When
discharged resetting the PG delay period. The PGFB voltage is typically generated by a resistive divider from the
regulated output or input supply. See Power Good section
in Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between 5%
and 75% duty cycle. The synchronizing range is equal to
maximum initial operating frequency up to 700kHz. When
the voltage on the FB pin is below 0.9V the SYNC function
is disabled. See the Synchronizing section in Applications
Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1µA. The
SHDN pin requires a voltage above 1.3V with a typical
source current of 5µA to take the IC out of the shutdown
state.
PG (Pin 16): The PG pin is functional only when the SHDN
pin is above its threshold, and is active low when the
internal clamp on the C
pin is below its clamp level and
T
high impedance when the clamp is active. The PG pin has
a typical sink capability of 200µA. See the Power Good
section in Applications Information for details.
3435fa
7
LT3435
BLOCK DIAGRA
V
IN
4
BIAS
10
SYNC
14
SHDN
15
+
SHDN
COMP
–
1.3V
INTERNAL REF
UNDERVOLTAGE
W
LOCKOUT
THERMAL
SHUTDOWN
2.4V
SLOPE
COMP
500kHz
OSCILLATOR
ANTISLOPE
COMP
Σ
CURRENT
COMP
R
S
+
–
SWITCH
LATCH
Q
DRIVER
CIRCUITRY
BOOST
SW
6
2
C
SS
9
FB
12
1.25V
V
C
11
PGFB
13
1.12V
C
T
7
SOFT-START
FOLDBACK
DETECT
–
ERROR
AMP
+
+
PG
COMP
–
BURST MODE
DETECT
V
C
CLAMP
1.2V C
T
CLAMP
GND
PGND
PG
16
17
8
3435 BD
Figure 1. LT3435 Block Diagram
The LT3435 is a constant frequency, current mode buck
converter. This means that there is an internal clock and two
feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS latch to turn the switch on. When
switch current reaches a level set by the current comparator the latch is reset and the switch turns off. Output voltage control is obtained by using the output of the error
amplifier to set the switch current trip point. This technique
means that the error amplifier commands current to be
8
delivered to the output rather than voltage. A voltage fed
system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt
180° shift will occur. The current fed system will have 90°
phase shift at a much lower frequency, but will not have the
additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response.
Most of the circuitry of the LT3435 operates from an
internal 2.4V bias line. The bias regulator normally draws
3435fa
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