LINEAR TECHNOLOGY LT3435 Technical data

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Step-Down Switching Regulator

with 100µA Quiescent Current

FEATURES

■

Wide Input Range: 3.3V to 60V

■

3A Peak Switch Current

■

Burst Mode® Operation: 100µA Quiescent Current**

■

Low Shutdown Current: IQ < 1µA

■

Power Good Flag with Programmable Threshold

■

Load Dump Protection to 60V

■

500kHz Switching Frequency

■

Saturating Switch Design: 0.1Ω On-Resistance

■

Peak Switch Current Maintained Over Full Duty Cycle Range*

■

1.25V Feedback Reference Voltage

■

Easily Synchronizable

■

Soft-Start Capability

■

Small 16-Pin Thermally Enhanced TSSOP Package

APPLICATIO S

■

High Voltage Power Conversion

■

14V and 42V Automotive Systems

■

Industrial Power Systems

■

Distributed Power Systems

■

Battery-Powered Systems

■

USB Powered Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 6498466 **See Burst Mode Operation section for conditions.

LT3435

High Voltage 3A, 500kHz

DESCRIPTIO

The LT regulator that accepts input voltages up to 60V. A high efficiency 3A, 0.1Ω switch is included on the die along with all the necessary oscillator, control and logic circuitry. Current mode topology is used for fast transient response and good loop stability.

Innovative design techniques along with a new high voltage process achieve high efficiency over a wide input range. Efficiency is maintained over a wide output current range by employing Burst Mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. Patented circuitry maintains peak switch current over the full duty cycle range.* Shutdown reduces input supply current to less than 1µA. External synchronization can be implemented by driving the SYNC pin with logic-level inputs. A single capacitor from the C provides a controlled output voltage ramp (soft-start). The device also has a power good flag with a programmable threshold and time-out and thermal shutdown protection.

The LT3435 is available in a 16-pin TSSOP package with an exposed pad leadframe for low thermal resistance.

3435 is a 500kHz monolithic buck switching

pin to the output

TYPICAL APPLICATIO

14V to 3.3V Step-Down Converter with

100µA No Load Quiescent Current

4700pF

10k

1µF

4.7µF 100V CER

470pF

SHDN

SYNC GND

LT3435

BOOST

BIAS

PGFB

0.33µF

0.1µF

27pF

15µH

B360A

165k

100k

Efficiency and Power Loss

vs Load CurrentSupply Current vs Input Voltage

3435 TA02

0.1

0.01

0.001

3435fa

POWER LOSS (W)

100

VIN = 12V

OUT

EFFICIENCY (%)

0.0001

= 5V

EFFICIENCY

= 3.3V

OUT

0.001 LOAD CURRENT (A)

0.01

TYPICAL POWER LOSS

0.1 1

150

OUT

3.3V

4148

100µF

10V TANT

3435 TA01

125

100

SUPPLY CURRENT (µA)

INPUT VOLTAGE (V)

30 40

= 3.3V

OUT

= 25°C

3435 TA03

LT3435

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

BOOST

GND

PGOOD

SHDN

SYNC

PGFB

BIAS

ABSOLUTE AXI U RATI GS

(Note 1)

VIN, SHDN, BIAS, PGOOD, SW ............................... 60V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage ................................................. 68V

SYNC, CSS, PGFB, FB................................................ 6V

Operating JunctionTemperature Range

(Note 2) ........................................... – 40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

UUW

PACKAGE/ORDER I FOR ATIO

= 125°C, θJA = 45°C/W, θ

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO GND (PIN 8)

JMAX

ORDER PART NUMBER

LT3435EFE LT3435IFE

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

= 10°C/W

JC(PAD)

FE PART MARKING

3435EFE 3435IFE

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SHDN

VINS

VIN

BIASS

BIAS

REF

SHDN Threshold 1.15 1.3 1.45 V

SHDN Input Current SHDN = 12V

Minimum Input Voltage (Note 3)

Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 µA

Supply Sleep Current (Note 4) BIAS = 0V, FB = 1.35V

FB = 1.35V

Supply Quiescent Current BIAS = 0V, FB = 1.15V 3.3 7 mA

BIAS = 5V, FB = 1.15V 2.6 6 mA

Minimum BIAS Voltage (Note 5)

BIAS Sleep Current (Note 4)

BIAS Quiescent Current SYNC = 3.3V 700 900 µA

Minimum Boost Voltage (Note 6) ISW = 1.5A 1.8 V

Input Boost Current (Note 7) ISW = 3A 65 85 mA

Reference Voltage (V

FB Input Bias Current 75 200 nA

EA Voltage Gain (Note 8) 900 V/V

EA Voltage g

) 3.3V < V

REF

dI(VC)= ±10µA 400 650 900 µMho

VIN

< 60V

●

1.225 1.25 1.275 V

520 µA

2.4 3 V

170 250 µA

45 75 µA

2.7 3.1 V

125 180 µA

3435fa

LT3435

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

EA Source Current FB = 1.15V 20 40 55 µA

EA Sink Current FB = 1.35V 15 30 40 µA

CSS

PGFB

VC to SW g

VC High Clamp FB = 1.15V 2.1 2.2 2.4 V

SW Current Limit

Switch On Resistance (Note 9)

Switching Frequency

Maximum Duty Cycle 86 92 %

Minimum SYNC Amplitude 1.5 2.0 V

SYNC Frequency Range 575 700 kHz SYNC Input Impedance 45 kΩ

CSS Current Threshold (Note 10) FB = 0V 7 13 20 µA

PGFB Input Current 25 100 nA

PGFB Voltage Threshold (Note 11)

CT Source Current (Note 11) 2 3.6 5.5 µA

CT Sink Current (Note 11) 1 2 mA

CT Voltage Threshold (Note 11) 1.16 1.2 1.26 V

PG Leakage (Note 11) 0.1 1 µA

PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 100 200 µA

●

3 5.2 6.5 A

●

425 500 575 kHz

●

88 90 92 %

6A/V

0.1 0.25 Ω

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LT3435EFE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3435IFE is guaranteed and tested over the full –40°C to 125°C operating junction temperature range.

Note 3: Minimum input voltage is defined as the voltage where switching starts. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information.

Note 4: Supply input current is the quiescent current drawn by the input pin. Its typical value depends on the voltage on the BIAS pin and operating state of the LT3435. With the BIAS pin at 0V, all of the quiescent current required to operate the LT3435 will be provided by the V BIAS voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the BIAS pin. Supply sleep current is defined as the quiescent current during the “sleep” portion of Burst Mode operation. See Applications Information for determining application supply currents.

pin. With the

Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I sourced into the pin.

Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch.

Note 7: Boost current is the current flowing into the BOOST pin with the pin held 3.3V above input voltage. It flows only during switch on time.

Note 8: Gain is measured with a V Note 9: Switch on resistance is calculated by dividing V

the forced current (3A). See Typical Performance Characteristics for the graph of switch voltage at other currents.

Note 10: The C

pin which results in an increase in sink current from the VC pin.

the C

See the Soft-Start section in Applications Information. Note 11: The PGFB threshold is defined as the percentage of V

which causes the current source output of the C sinking (below threshold) to sourcing current (above threshold). When sourcing current, the voltage on the C internally. When the clamp is activated, the output of the PG pin will be set to a high impedance state. When the C be set active low with a current sink capability of 200µA.

threshold is defined as the value of current sourced into

swing from 1.15V to 750mV.

to SW voltage by

pin to change from

pin rises until it is clamped

clamp is inactive the PG pin will

REF

BIAS

voltage

3435fa

LT3435

TYPICAL PERFOR A CE CHARACTERISTICS

FB Voltage Oscillator Frequency SHDN Threshold

1.30

1.29

1.28

1.27

1.26

1.25

1.24

VOLTAGE (V)

1.23

1.22

1.21

1.20 –50 0

–25

TEMPERATURE (°C)

100

125

3435 G01

550

540

530

520

510

500

490

FREQUENCY (kHz)

480

470

460

450

–50

–25

TEMPERATURE (°C)

1.40

1.35

1.30

1.25

1.20

VOLTAGE (V)

0.15

1.10

1.05

100

125

3435 G02

1.00 –50 0

–25

TEMPERATURE (°C)

100

125

3435 G03

SHDN Pin Current

5.5 TJ = 25°C

5.0

4.5

4.0

3.5

3.0

2.5

CURRENT (µA)

2.0

1.5

1.0

Bias Sleep Current

200

180

160

140

120

100

CURRENT (µA)

–50 0

–25

30 40

SHDN VOLTAGE (V)

TEMPERATURE (°C)

Shutdown Supply Current Sleep Mode Supply Current

CURRENT (µA)

3435 G04

–50 0

VIN = 42V VIN = 12V

–25

TEMPERATURE (°C)

VIN = 60V

100

125

3435 G05

PGFB Threshold

1.20

1.18

1.16

1.14

1.12

1.10

1.08

VOLTAGE (V)

1.06

1.04

1.02

1.00

100

125

3435 G07

–50 0

–25

TEMPERATURE (°C)

100

125

3435 G08

200

180

160

140

120

100

CURRENT (µA)

–50 0

–25

PG Sink Current

250

200

150

100

CURRENT (µA)

–50 0

–25

= 0V

BIAS

= 5V

BIAS

TEMPERATURE (°C)

100

125

3435 G06

125

3435 G09

3435fa

FB VOLTAGE (V)

NORMALIZED FREQUENCY (%)

0.25 0.50 0.75

3435 G12

1.00

100

1.25

SWITCH CURRENT (mA)

BOOST CURRENT (mA)

2000

3435 G18

1000

500

2500

1500 3000

TYPICAL PERFOR A CE CHARACTERISTICS

LT3435

Switch Peak Current Limit

6.0

5.5

5.0

4.5

4.0

PEAK SWITCH CURRENT (A)

3.5

3.0

–25 –0 25 50

–50

TEMPERATURE (°C)

Switch On Voltage (V

500

450

400

350

300

250

200

VOLTAGE (mV)

150

100

0.5

1.0 2.0 3.0

1.5

LOAD CURRENT (A)

Soft-Start Current Threshold vs FB Voltage

TJ = 25°C

CURRENT (µA)

START-UP

0.2

RUNNING

START-UP

RUNNING

0.5

75 100 125

3435 G10

) Minimum Input Voltage

CESAT

TJ = 125°C

TJ = 25°C

TJ = –40°C

2.5

3435 G13

8.0

7.5

7.0

6.5

6.0

5.5

5.0

INPUT VOLTAGE (V)

4.5

4.0

3.5

3.0

0.6 0.8

0.4 FB VOLTAGE (V)

= 5V

OUT

1.0

1.5 3.0

LOAD CURRENT (A)

2.0

SOFT-START DEFEATED

1.0

3435 G11

= 3.3V

2.5

3435 G15

1.2

1000

900

800

700

600

500

400

300

LOAD CURRENT (mA)

200

100

Oscillator Frequency vs FB Voltage

Burst Mode Threshold vs Input Voltage

= 3.3V

OUT

L = 15µH

= 100µF

OUT

= 25°C

BURST MODE EXIT (INCREASING LOAD)

BURST MODE ENTER (DECREASING LOAD)

10 20

INPUT VOLTAGE (V)

3435 G16

Minimum On-Time for Continuous Mode Operation

600

LOAD CURRENT = 1A

550

500

450

400

350

300

ON TIME (ns)

250

200

150

100

–50

–25

TEMPERATURE (°C)

Maximum Synchronization Frequency vs Temperature Boost Current vs Switch Current

1000

950

900

850

800

750

700

FREQUENCY (kHz)

650

600

550

500

100

125

3435 G17

–50

–25

TEMPERATURE (°C)

100

125

3435 G14

3435fa

LT3435

TYPICAL PERFOR A CE CHARACTERISTICS

4.0

3.5

3.0

2.5

2.0

1.5

OUTPUT VOLTAGE (V)

1.0

0.5

OUT

50mV/DIV

AC-COUPLED

500mA/DIV

Dropout Operation Dropout Operation

= 3.3V

OUT

BOOST DIODE = DIODES INC DFLS160

LOAD CURRENT = 2.5A

LOAD CURRENT = 250mA

2 2.5 3 3.5 4 4.5 5 5.5 6

INPUT VOLTAGE (V)

Burst Mode Operation

3435 G19

OUT

200mV/DIV

AC-COUPLED

OUT

1A/DIV

= 5V

OUT

BOOST DIODE = DIODES INC DFLS160

OUTPUT VOLTAGE (V)

2 2.5 3 3.5 4 4.5 5 5.5 6.5 7 7.56

LOAD CURRENT = 250mA

INPUT VOLTAGE (V)

No Load 2A Step Response Step Response

LOAD CURRENT = 2.5A

3435 G20

OUT

50mV/DIV

AC-COUPLED

500mA/DIV

OUT

200mV/DIV

AC-COUPLED

OUT

1A/DIV

Burst Mode Operation

= 12V 10ms/DIV

= 3.3V

OUT

3435 G21

= 12V 10µs/DIV

= 3.3V

OUT

3435 G22

= 12V 500µs/DIV

= 3.3V

OUT

= 100µF

OUT

PI FU CTIO S

NC (Pin 1): No Connection.

SW (Pins 2, 5): The SW pin is the emitter of the on-chip

power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the SW pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is –0.8V.

(Pins 3, 4): This is the collector of the on-chip power

NPN switch. V a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the path short from the VIN pin through the input bypass capacitor, through the catch diode back to SW. All trace

powers the internal control circuitry when

3435 G23

= 12V 500µs/DIV

= 3.3V

OUT

= 100µF

OUT

= 500mA

LOAD(DC)

3435 G24

inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN.

BOOST (Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.1Ω FET structure.

CT (Pin 7): A capacitor on the CT pin determines the amount of delay time between the PGFB pin exceeding its threshold (V

) and the PG pin set to a high impedance state.

PGFB

3435fa

LT3435

PI FU CTIO S

When the PGFB pin rises above V from the C

pin into the external capacitor. When the volt-

age on the external capacitor reaches an internal clamp (V

), the PG pin becomes a high impedance node. The

resultant PG delay time is given by t = C voltage on the PGFB pin drops below V discharged rapidly to 0V and PG will be active low with a 200µA sink capability. If the C

pin is clamped (Power Good

condition) during normal operation and SHDN is taken low, the C

pin will be discharged and a delay period will occur

when SHDN is returned high. See the Power Good section in Applications Information for details.

GND (Pins 8, 17): The GND pin connection acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground. Keep the path between the GND pin and the load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the copper ground plane to reduce thermal resistance (see Applications Information).

CSS (Pin 9): A capacitor from the CSS pin to the regulated output voltage determines the output voltage ramp rate during start-up. When the current through the C tor exceeds the C the output is limited. The C

threshold (I

threshold is proportional to

the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltage greater than 0.9V (typical). See Soft-Start section in Applications Information for details.

BIAS (Pin 10): The BIAS pin is used to improve efficiency when operating at higher input voltages and light load current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V.

(Pin 11): The VC pin is the output of the error amplifier

and the input of the peak switch current comparator. It is

, current is sourced

PGFB

• VCT/ICT. If the

, CCT will be

PGFB

), the voltage ramp of

CSS

capaci-

normally used for frequency compensation, but can also serve as a current clamp or control loop override. V

sits

at about 0.45V for light loads and 2.2V at maximum load. During the sleep portion of Burst Mode operation, the V

pin is held at a voltage slightly below the burst threshold for better transient response. Driving the V

pin to ground

will disable switching and place the IC into sleep mode.

FB (Pin 12): The feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25V at the FB pin . When the FB pin drops below 0.9V, switching frequency is reduced, the SYNC function is disabled and output ramp rate control is enabled via the C

pin. See the Feedback section in

Applications Information for details.

PGFB (PIN 13): The PGFB pin is the positive input to a comparator whose negative input is set at V PGFB is taken above V the C

pin starting the PG delay period. When the voltage

on the PGFB pin drops below V

, current (I

PGFB

) is sourced into

CSS

, the CT pin is rapidly

PGFB

. When

discharged resetting the PG delay period. The PGFB voltage is typically generated by a resistive divider from the regulated output or input supply. See Power Good section in Applications Information for details.

SYNC (Pin 14): The SYNC pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 5% and 75% duty cycle. The synchronizing range is equal to maximum initial operating frequency up to 700kHz. When the voltage on the FB pin is below 0.9V the SYNC function is disabled. See the Synchronizing section in Applications Information for details.

SHDN (Pin 15): The SHDN pin is used to turn off the regulator and to reduce input current to less than 1µA. The SHDN pin requires a voltage above 1.3V with a typical source current of 5µA to take the IC out of the shutdown state.

PG (Pin 16): The PG pin is functional only when the SHDN pin is above its threshold, and is active low when the internal clamp on the C

pin is below its clamp level and

high impedance when the clamp is active. The PG pin has a typical sink capability of 200µA. See the Power Good section in Applications Information for details.

3435fa

LT3435

BLOCK DIAGRA

BIAS

SYNC

SHDN

SHDN COMP

–

1.3V

INTERNAL REF

UNDERVOLTAGE

LOCKOUT

THERMAL

SHUTDOWN

2.4V

SLOPE

COMP

500kHz

OSCILLATOR

ANTISLOPE

COMP

CURRENT

COMP

–

SWITCH

LATCH

DRIVER

CIRCUITRY

BOOST

1.25V

PGFB

1.12V

SOFT-START

FOLDBACK

DETECT

–

ERROR

AMP

COMP

–

BURST MODE

DETECT

CLAMP

1.2V C

CLAMP

GND

PGND

3435 BD

Figure 1. LT3435 Block Diagram

The LT3435 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS latch to turn the switch on. When switch current reaches a level set by the current comparator the latch is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be

delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response.

Most of the circuitry of the LT3435 operates from an internal 2.4V bias line. The bias regulator normally draws

3435fa

BLOCK DIAGRA

LT3435

power from the VIN pin, but if the BIAS pin is connected to an external voltage higher than 3V bias power will be drawn from the external source (typically the regulated output voltage). This improves efficiency.

High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing switch to be saturated. This boosted voltage is generated with an external capacitor and diode.

WUUU

APPLICATIO S I FOR ATIO

FEEDBACK PIN FUNCTIONS

The feedback (FB) pin on the LT3435 is used to set output voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage and the remaining part talks about frequency foldback and soft-start features. Please read both parts before committing to a final design.

Referring to Figure 2, the output voltage is determined by a voltage divider from V

1.25V at the FB pin. Since the output divider is a load on the output care must be taken when choosing the resistor divider values. For light load applications the resistor values should be as large as possible to achieve peak efficiency in Burst Mode operation. Extremely large values for resistor R1 will cause an output voltage error due to the 50nA FB pin input current. The suggested value for the output divider resistor (see Figure 2) from FB to ground (R2) is 100k or less. A formula for R1 is shown below. A table of standard 1% values is shown in Table 1 for common output voltages.

to ground which generates

OUT

To further optimize efficiency, the LT3435 automatically switches to Burst Mode operation in light load situations. In Burst Mode operation, all circuitry associated with controlling the output switch is shut down reducing the input supply current to 45µA.

The LT3435 contains a power good flag with a programmable threshold and delay time. A logic-level low on the SHDN pin disables the IC and reduces input suppy current to less than 1µA.

Table 1

OUTPUT R1 OUTPUT

VOLTAGE R2 NEAREST (1%) ERROR

(V) (kΩ, 1%) (kΩ)(%)

2.5 100 100 0

3 100 140 0

3.3 100 165 0.38

5 100 301 0.25

6 100 383 0.63

8 100 536 – 0.63

10 100 698 – 0.25

12 100 866 0.63

LT3435

OSCILLATOR

500kHz

SOFT-START

FOLDBACK

DETECT

OUT

=+•

125 2 50

.•

125

–.

OUT

RnA

More Than Just Voltage Feedback

The FB pin is used for more than just output voltage sensing. It also reduces switching frequency and controls the soft-start voltage ramp rate when output voltage is below the regulated level (see the Frequency Foldback

–

ERROR

AMP

1.25V

Figure 2. Feedback Network

3435 F02

3435fa

LT3435

WUUU

APPLICATIO S I FOR ATIO

and Soft-Start Current graphs in Typical Performance Characteristics).

Frequency foldback is done to control power dissipation in both the IC and in the external diode and inductor during short-circuit conditions. A shorted output requires the switching regulator to operate at very low duty cycles. As a result the average current through the diode and inductor is equal to the short-circuit current limit of the switch (typically 4.7A for the LT3435). Minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 500kHz, so frequency is reduced by about 4:1 when the FB pin voltage drops below 0.4V (see Frequency Foldback graph). In addition, if the current in the switch exceeds 1.5 times the current limitations specified by the V LT3435 will skip the next switch cycle. As the feedback voltage rises, the switching frequency increases to 500kHz with 0.95V on the FB pin. During frequency foldback, external syncronization is disabled to prevent interference with foldback operation. Frequency foldback does not affect operation during normal load conditions.

In addition to lowering switching frequency the soft-start ramp rate is also affected by the feedback voltage. Large capacitive loads or high input voltages can cause a high input current surge during start-up. The soft-start function reduces input current surge by regulating switch current via the VC pin to maintain a constant voltage ramp rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from the C dV/dt. When the feedback voltage is below 0.4V, the V will rise, resulting in an increase in switch current and output voltage. If the dV/dt of the output causes the current through the CSS capacitor to exceed I reduced resulting in a constant dV/dt at the output. As the feedback voltage increases I increased dV/dt until the soft-start function is defeated with 0.9V present at the FB pin. The soft-start function does not affect operation during normal load conditions. However, if a momentary short (brown out condition) is present at the output which causes the FB voltage to drop below 0.9V, the soft-start circuitry will become active.

pin to the output determines the maximum output

pin, due to minimum switch on time, the

the VC voltage is

CSS

increases, resulting in an

CSS

INPUT CAPACITOR

Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT3435 and force the switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:

RIPPLE RMS

Ceramic capacitors are ideal for input bypassing. At 500kHz switching frequency input capacitor values in the range of

4.7µF to 20µF are suitable for most applications. If opera- tion is required close to the minimum input required by the LT3435 a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operating voltage resulting in erratic operation.

Input voltage transients caused by input voltage steps or by hot plugging the LT3435 to a pre-powered source such as a wall adapter can exceed maximum V sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. This energy will cause the input voltage to swing above the DC level of input power source and it may exceed the maximum voltage rating of the input capacitor and LT3435. All input voltage transient sequences should be observed at the V the LT3435 to ensure that absolute maximum voltage ratings are not violated.

The easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low ESR input capacitor. The selected capacitor needs to have the right amount of ESR to critically damp the resonant circuit formed by the input lead inductance and the input capacitor. The typical values of ESR will fall in the range of 0.5Ω to 2Ω and capacitance will fall in the range of 5µF to 50µF.

If tantalum capacitors are used, values in the 22µF to 470µF range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be

OUT

VVV

OUT IN OUT()

–=

()

ratings. The

pin of

3435fa

VVV

VLf

OUT IN OUT

P-P

()

()()()

–

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APPLICATIO S I FOR ATIO

LT3435

taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge rated AVX recommends derating capacitor operating voltage by 2:1 for high surge applications.

OUTPUT CAPACITOR

The output capacitor is normally chosen by its effective series resistance (ESR) because this is what determines output ripple voltage. To get low ESR takes volume, so physically smaller capacitors have higher ESR. The ESR range for typical LT3435 applications is 0.05Ω to 0.2Ω. A typical output capacitor is an AVX type TPS, 100µF at 10V, with a guaranteed ESR less than 0.1Ω. This is a “D” size surface mount solid tantalum capacitor. TPS capacitors are specially constructed and tested for low ESR, so they give the lowest ESR for a given volume. The value in microfarads is not particularly critical and values from 22µF to greater than 500µF work well, but you cannot cheat Mother Nature on ESR. If you find a tiny 22µF solid tantalum capacitor, it will have high ESR and output ripple voltage could be unacceptable. Table 2 shows some typical solid tantalum surface mount capacitors.

Table 2. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current

E CASE SIZE ESR MAX (Ω) RIPPLE CURRENT (A)

AVX TPS 0.1 to 0.3 0.7 to 1.1

D CASE SIZE

AVX TPS 0.1 to 0.3 0.7 to 1.1

C CASE SIZE

AVX TPS 0.2 0.5

Unlike the input capacitor RMS, ripple current in the output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular with a typical value of 200mA to calculate this is:

Output capacitor ripple current (RMS)

VVV

029

.–

OUT IN OUT

RIPPLE RMS

CERAMIC CAPACITORS

Higher value, lower cost ceramic capacitors are now becoming available. They are generally chosen for their good high frequency operation, small size and very low ESR (effective series resistance). Low ESR reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capacitors. To compensate for this a resistor R with the V must be taken however since this resistor sets the high frequency gain of the error amplifier including the gain at the switching frequency. If the gain of the error amplifier is high enough at the switching frequency output ripple voltage (although smaller for a ceramic output capacitor) may still affect the proper operation of the regulator. A filter capacitor C with a small feedforward capacitor C control possible ripple at the V

OUTPUT RIPPLE VOLTAGE

()

compensation capacitor CC (Figure 10). Care

()( )

LfV

()()( )

in parallel with the RC/CC network, along

can be placed in series

pin.

. The formula

RMS

P-P

, is suggested to

Many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. This is historically true and type TPS capacitors are specially tested for surge capability but surge ruggedness is not a critical issue with the output capacitor. Solid tantalum capacitors fail during very high turn-on surges which do not occur at the output of regulators. High discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors.

Figure 3 shows a typical output ripple voltage waveform for the LT3435. Ripple voltage is determined by the impedance of the output capacitor and ripple current through the inductor. Peak-to-peak ripple current through the inductor into the output capacitor is:

3435fa

LT3435

VVV

LfV

OUT MAX PK

OUT IN OUT

()

–

–=

()( )

()()( )

-P

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APPLICATIO S I FOR ATIO

OUT

20mV/DIV AC-COUPLED C

= 100µF

OUT

TANTALUM

ESR 100mΩ

OUT

20mV/DIV AC-COUPLED

= 100µF

OUT

CERAMIC

5V/DIV

= 12V 500ns/DIV

= 3.3V

OUT

= 1A

LOAD

L = 15µH

Figure 3. LT3435 Ripple Voltage Waveform

3435 F03

For high frequency switchers the ripple current slew rate is also relevant and can be calculated from:

didtV

Peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times ESR and a square wave created by parasitic inductance (ESL) and ripple current slew rate. Capacitive reactance is assumed to be small compared to ESR or ESL.

V I ESR ESL

RIPPLE

Example: with V

P-P

()( )

= 12V, V

()

= 3.3V, L = 15µH, ESR =

OUT

0.08Ω, ESL = 10nH:

33 12 33

.–.

P-P

()( )

12 15 6 500 3

()

−

()()

0 319

does not fall off at high duty cycles. Most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. This is due to the effects of slope compensation required to prevent subharmonic oscillations in current mode converters. (For detailed analysis, see Application Note 19.)

The LT3435 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides.

Maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. The following formula assumes continuous mode operation, implying that the term on the right (I

/2) is less than I

P-P

OUT

Discontinuous operation occurs when:

OUT DIS

()

For V

OUT

OUT MAX()

VVV

OUT IN OUT

≤

= 5V, V

–

–. .

3 0 125 2 875

–

()

LfV

()()( )

= 8V and L = 15µH:

–

58 5

()( )

–

2 15 6 500 3 8

()()()

dt e

RIPPLE

–

15 6

= (0.319A)(0.08) + (10e – 9)(0.8e6)

= 0.026 + 0.008 = 34mV

MAXIMUM OUTPUT LOAD CURRENT

Maximum load current for a buck converter is limited by the maximum switch current rating (I rating for the LT3435 is 3A. Unlike most current mode converters, the LT3435 maximum switch current limit

08 6

Note that there is less load current available at the higher input voltage because inductor ripple current increases. At

= 15V, duty cycle is 33% and for the same set of

conditions:

P-P

–

515 5

OUT MAX()

). The current

–

–. .

3 0 22 2 88

()( )

–

2 15 6 500 3 15

()()()

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LT3435

To calculate actual peak switch current in continuous mode with a given set of conditions, use:

VVV

SW PK OUT

()

OUT IN OUT

–

()

LfV

()()( )

If a small inductor is chosen which results in discontinous mode operation over the entire load range, the maximum load current is equal to:

IfLV

PK IN

()

OUT MAX

()( )( )

VVV

OUT IN OUT

()( )

–

CHOOSING THE INDUCTOR

For most applications the output inductor will fall in the range of 5µH to 33µH. Lower values are chosen to reduce physical size of the inductor. Higher values allow more output current because they reduce peak current seen by the LT3435 switch, which has a 3A limit. Higher values also reduce output ripple voltage and reduce core loss.

When choosing an inductor you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault current in the inductor, saturation and of course cost. The following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements.

1. Choose a value in microhenries such that

the maximum load current plus half of the inductor ripple current is less than the minimum peak switch current (IPK). Choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the LT3435 is designed to work well in either mode.

Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maximum load current is 1A, for instance, a 1A inductor may not survive a continuous 4A overload condition.

Table 3. Inductor Selection Criteria

VENDOR/ VALUE I

PART NO. (

Sumida

CDRH104R-4R7 4.7 6 0.013 4

CDRH104R-100 10 4.4 0.035 4

CDRH104R-150 15 3.6 0.050 4

CDRH104R-220 22 2.9 0.073 4

CDRH104R-330 33 2.3 0.093 4

CDRH124-4R7 4.7 5.7 0.015 4.5

CDRH124-100 10 4.5 0.026 4.5

CDRH124-220 22 2.9 0.066 4.5

CDRH124R-330 33 2.7 0.097 4.5

CDRH127-330 33 3.0 0.065 8

CEI122-220 22 2.3 0.085 34

Coiltronics

UP3B-4R7 4.7 6.5 0.0083 6.8

UP3B-4R7 10 4.3 0.026 6.8

UP3B-330 33 3 0.069 6.8

H) (Amps) (Ohms) (mm)

DC(MAX)

DCR HEIGHT

For applications with a duty cycle above 50%, the inductor value should be chosen to obtain an inductor ripple current of less than 40% of the peak switch current.

2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so don’t omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions.

PEAK OUT

VVV

OUT IN OUT

–

()

fLV

()( )( )

VIN = maximum input voltage

f = switching frequency, 500kHz

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3. Decide if the design can tolerate an “open” core geometry like a rod or barrel, which have high magnetic field radiation, or whether it needs a closed core like a toroid to prevent EMI problems. This is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem.

4. After making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. Use the experts in the Linear Technology’s applications department if you feel uncertain about the final choice. They have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc.

Short-Circuit Considerations

The LT3435 is a current mode controller. It uses the V

node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the V

node, nominally 2.2V, then acts as an output switch peak current limit. This action becomes the switch current limit specification. The maximum available output power is then determined by the switch current limit.

A potential controllability problem could occur under short-circuit conditions. If the power supply output is short circuited, the feedback amplifier responds to the low output voltage by raising the control voltage, V

, to its

peak current limit value. Ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by VC. However, there is finite response time involved in both the current comparator and turn-off of the output switch. These result in a minimum on time t

ON(MIN).

When combined with the large ratio of VIN to

+ I • R), the diode forward voltage plus inductor I • R voltage drop, the potential exists for a loss of control. Expressed mathematically the requirement to maintain control is:

VIR

•≤+

•

where:

f = switching frequency

= switch on time

VF = diode forward voltage VIN = Input voltage I • R = inductor I • R voltage drop

If this condition is not observed, the current will not be limited at I

but will cycle-by-cycle ratchet up to some

higher value. Using the nominal LT3435 clock frequency of 500kHz, a V maximum t

of 12V and a (VF + I • R) of say 0.7V, the

to maintain control would be approximately

116ns, an unacceptably short time.

The solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently low value such that the current doesn’t continue to ratchet higher. When the FB pin voltage is abnormally low thereby indicating some sort of short-circuit condition, the oscillator frequency will be reduced. Oscillator frequency is reduced by a factor of 4 when the FB pin voltage is below

0.4V and increases linearly to its typical value of 500kHz at a FB voltage of 0.95V (see Typical Performance Characteristics). In addition, if the current in the switch exceeds 1.5

• IPK current demanded by the VC pin, the LT3435 will skip the next on cycle effectively reducing the oscillator frequency by a factor of 2. These oscillator frequency reductions during short-circuit conditions allow the LT3435 to maintain current control.

SOFT-START

For applications where [V

/(V

+ VF)] ratios > 10 or

OUT

large input surge currents can’t be tolerated, the LT3435 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit thereby adding additional control over peak inductor current. The soft-start function limits the switch current via the V

pin to maintain a

constant voltage ramp rate (dV/dt) at the output capacitor. A capacitor (C1 in Figure 2) from the C

pin to the

regulated output voltage determines the output voltage

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LT3435

ramp rate. When the current through the CSS capacitor exceeds the C

threshold (I

output capacitor is limited by reducing the V The C

threshold is proportional to the FB voltage (see

), the voltage ramp of the

CSS

pin voltage.

Typical Performance Characteristics) and is defeated for FB voltages greater than 0.9V (typical). The output dV/dt can be approximated by:

dVdtI

CSS

but actual values will vary due to start-up load conditions, compensation values and output capacitor selection.

= 1000pF

CSS

= 0.01µF

CSS

OUT

1V/DIV

= 12V 1ms/DIV

= 3.3V

OUT

= 500mA

Figure 4. V

OUT

CSS

dV/dt

= 0.1µF

3435 F04

Burst Mode OPERATION

To enhance efficiency at light loads, the LT3435 automatically switches to Burst Mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. During Burst Mode operation, the LT3435 delivers short bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. In addition, V

and BIAS quiescent

currents are reduced to typically 45µA and 125µA respec- tively during the sleep time. As the load current decreases towards a no load condition, the percentage of time that the LT3435 operates in sleep mode increases and the average input current is greatly reduced resulting in higher efficiency.

The minimum average input current depends on the VIN to

ratio, VC frequency compensation, feedback divider

OUT

network and Schottky diode leakage. It can be approximated by the following equation:

III

IN AVG VINS SHDN

≅ ++

()

⎛ ⎜

⎝

⎞

BIASS FB S

()

OUT

⎟

⎠

()

III

where

= input pin current in sleep mode

VINS

= output voltage

OUT

input voltage

IN =

= BIAS pin current in sleep mode

BIASS

IFB = feedback network current IS = catch diode reverse leakage at V

OUT

η = low current efficiency (non Burst Mode operation)

Example: For V

45 5

IAA

IN AVG()

=µ+µ+

=µ+µ+µ=µ

45 5 44 99

150

125

100

SUPPLY CURRENT (µA)

During the sleep portion of the Burst Mode Cycle, the V

= 3.3V, VIN = 12V

OUT

⎞

⎛

3312125 12 5 0 5

.( . . )

⎜ ⎝

µ+ µ+ µ

AAA

⎟ ⎠

AA A A

OUT

Figure 5. I

30 40

INPUT VOLTAGE (V)

vs V

(.)

= 3.3V

= 25°C

3435 F05

pin voltage is held just below the level need for normal operation to improve transient response. See the Typical Performance Characteristics section for burst and transient response waveforms.

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If a no load condition can be anticipated, the supply current can be further reduced by cycling the SHDN pin at a rate higher than the natural no load burst frequency. Figure 6 shows Burst Mode operation with the SHDN pin. V

OUT

burst ripple is maintained while the average supply current drops to 15µA. The PG pin will be active low during the “on” portion of the SHDN waveform due to the C

capaci-

tor discharge when SHDN is taken low. See the Power Good section for further information.

OUT

50mV/DIV

AC-COUPLED

SHDN

2V/DIV

1A/DIV

VIN = 12V 100ms/DIV V

= 3.3V

OUT

= 15µA

Figure 6. Burst Mode with Shutdown Pin

3435 F06

CATCH DIODE

The catch diode carries load current during the SW off time. The average diode current is therefore dependent on the switch duty cycle. At high input to output voltage ratios the diode conducts most of the time. As the ratio approaches unity the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is short circuited. Under this condition the diode must safely handle I

at maximum duty cycle.

PEAK

To maximize high and low load current efficiency a fast switching diode with low forward drop and low reverse leakage should be used. Low reverse leakage is critical to maximize low current efficiency since its value over temperature can potentially exceed the magnitude of the LT3435 supply current. Low forward drop is critical for high current efficiency since the loss is proportional to forward drop.

These requirements result in the use of a Schottky type diode. DC switching losses are minimized due to its low forward voltage drop and AC behavior is benign due to its

Table 4. Catch Diode Selection Criteria

IQ at 125°C EFFICIENCY

LEAKAGE V

= 3.3V VF AT 1A V

OUT

DIODE 25°C 125°C25°C 125°CIL = 0A IL = 1A

IR 10BQ100 0.0µA59µA 0.72V 0.58V 125µA 74.7%

Diodes Inc. 0.1µA 242µA 0.48V 0.41V 215µA 81.7% B260SMA

Diodes Inc. 0.2µA 440µA 0.45V 0.36V 270µA 82.4% B360SMB

IR 1µA 1.81mA 0.42V 0.34V 821µA 82.7% MBRS360TR

IR 30BQ100 1.7µA 2.64mA 0.40V 0.32V 1088µA 81.1%

=12V VIN =12V

= 3.3 V

OUT

= 3.3V

lack of a significant reverse recovery time. Schottky diodes are generally available with reverse voltage ratings of 60V and even 100V and are price competitive with other types.

The effect of reverse leakage and forward drop on efficiency for various Schottky diodes is shown in Table 4. As can be seen these are conflicting parameters and the user must weigh the importance of each specification in choosing the best diode for the application.

The use of so-called “ultrafast” recovery diodes is generally not recommended. When operating in continuous mode, the reverse recovery time exhibited by “ultrafast” diodes will result in a slingshot type effect. The power internal switch will ramp up V

current into the diode in an

attempt to get it to recover. Then, when the diode has finally turned off, some tens of nanoseconds later, the V

node voltage ramps up at an extremely high dV/dt, perhaps 5V to even 10V/ns! With real world lead inductances the V

node can easily overshoot the VIN rail. This can

result in poor RFI behavior and, if the overshoot is severe enough, damage the IC itself.

BOOST PIN

For most applications the boost components are a 0.33µF capacitor and a MMSD914 diode. The anode is typically connected to the regulated output voltage to generate a voltage approximately V

above VIN to drive the output

OUT

stage (Figure 7a). However, the output stage discharges the boost capacitor during the on time of the switch. The output driver requires at least 2.5V of headroom throughout this period to keep the switch fully saturated. If the

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output voltage is less than 3.3V it is recommended that an alternate boost supply is used. The boost diode can be connected to the input (Figure 7b) but care must be taken to prevent the boost voltage (V

= VIN • 2) from

BOOST

exceeding the BOOST pin absolute maximum rating. The additional voltage across the switch driver also increases power loss and reduces efficiency. If available, an independent supply can be used to generate the required BOOST voltage (Figure 7c). Tying BOOST to V

or an

independent supply may reduce efficiency but it will reduce the minimum V

required to start-up with light

loads. If the generated BOOST voltage dissipates too much power at maximum load, the BOOST voltage the LT3435 sees can be reduced by placing a Zener diode in series with the BOOST diode (Figure 7a option).

OPTIONAL

BOOST

BOOST(MAX)

LT3435

– VSW = V

= VIN + V

BOOST

LT3435

SWGND

OUT

(7a)

SWGND

OUT

A 0.33µF boost capacitor is recommended for most appli- cations. Almost any type of film or ceramic capacitor is suitable but the ESR should be <1Ω to ensure it can be fully recharged during the off time of the switch. The capacitor value is derived from worst-case conditions of 1700ns on time, TBD boost current and 0.7V discharge ripple. The boost capacitor value could be reduced under less demanding conditions but this will not improve circuit operation or efficiency. Under low input voltage and low load conditions a higher value capacitor will reduce discharge ripple and improve start-up operation.

SHUTDOWN FUNCTION AND UNDERVOLTAGE LOCKOUT

The SHDN pin on the LT3435 controls the operation of the IC. When the voltage on the SHDN pin is below the 1.2V shutdown threshold the LT3435 is placed in a “zero” supply current state. Driving the SHDN pin above the shutdown threshold enables normal operation. The SHDN pin has an internal sink current of 3µA.

In addition to the shutdown feature, the LT3435 has an undervoltage lockout function. When the input voltage is below 2.4V, switching will be disabled. The undervoltage lockout threshold doesn’t have any hysteresis and is mainly used to insure that all internal voltages are at the correct level before switching is enabled. If an undervoltage lockout function with hysteresis is needed to limit input current at low V

to V

ratios refer to Figure 8 and

OUT

the following:

– VSW = V

BOOST

BOOST(MAX)

Figure 7. BOOST Pin Configurations

BOOST

BOOST(MAX)

LT3435

– VSW = V

= 2V

BOOST

SWGND

= VDC + V

IN IN

(7b)

(7c)

3435 F07

⎛

OUT

=++

UVLO

HYST

SHDN SHDN

⎜

⎝

OUT

()

⎞

SHDN SHDN

⎟ ⎠

R1 should be chosen to minimize quiescent current during normal operation by the following equation:

–

SHDN MAX

()( )

()

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Example:

12 2

–

155

()

513

()

= Ω

Ω

= ΩΩ

(Nearest 1% 6.49M )

R2 =

7 – 1.3

1.3M 408

1.3 13

649

Ω

––

Ω

(Nearest 1% 412k)

See the Typical Performance Characteristics section for graphs of SHDN and V

LT3435

OUT

SHDN

3µA

Figure 8. Undervoltage Lockout

currents verses input voltage.

COMP

–

2.4V

SHDN COMP

–

1.3V

ENABLE

3435 F08

SYNCHRONIZING

Oscillator synchronization to an external input is achieved by connecting a TTL logic-compatible square wave with a duty cycle between

and

75%

to the LT3435 SYNC pin. The synchronizing range is equal to initial operating frequency up to

700kHz

. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency ( ating frequency of

300kHz

synchronizing above

575kHz

), not the typical oper-

. Caution should be used when

575kHz

because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation.

If the FB pin voltage is below 0.9V (power-up or output short-circuit conditions) the sync function is disabled. This allows the frequency foldback to operate to avoid and hazardous conditions for the SW pin.

If the synchronization signal is present during Burst Mode operation, synchronization will occur during the burst portion of the output waveform. Synchronizing the LT3435 during Burst Mode operation may alter the natural burst frequency which can lead to jitter and increased ripple in the burst waveform.

If no synchronization is required this pin should be connected to ground.

POWER GOOD

The LT3435 contains a power good block which consists of a comparator, delay timer and active low flag that allows the user to generate a delayed signal after the power good threshold is exceeded.

Referring to Figure 2, the PGFB pin is the positive input to a comparator whose negative input is set at V PGFB is taken above V the C

pin starting the delay period. When the voltage on

the PGFB pin drops below V

, current (I

PGFB

) is sourced into

CSS

the CT pin is rapidly

PGFB

. When

discharged resetting the delay period. The PGFB voltage is typically generated by a resistive divider from the regulated output or input supply.

The capacitor on the C

pin determines the amount of

delay time between the PGFB pin exceeding its threshold (V When the PGFB pin rises above V (I

) and the PG pin set to a high impedance state.

PGFB

current is sourced

PGFB

) from the CT pin into the external capacitor. When the

voltage on the external capacitor reaches an internal clamp (V

), the PG pin becomes a high impedance node. The

resultant PG delay time is given by t = C the voltage on the PGFB pin drops below its V

•(VCT)/(ICT). If

, CCT will

PGFB

be discharged rapidly and PG will be active low with a 200µA sink capability. If the SHDN pin is taken below its

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threshold during normal operation, the CT pin will be discharged and PG inactive, resulting in a non Power Good cycle when SHDN is taken above its threshold. Figure 9 shows the power good operation with PGFB connected to FB and the capacitance on C

= 0.1µF. The PGOOD pin has

a limited amount of drive capability and is susceptible to noise during start-up and Burst Mode operation. If erratic

OUT

500mV/DIV

100k TO V

500mV/DIV

SHDN

2V/DIV

TIME (10ms/DIV)

Figure 9. Power Good

PG at 80% V

LT3435

PGFB

OUT

with 100ms Delay

200k

153k

12k

100k

0.27µF

3435 F09

= 3.3V

OUT

operation occurs during these conditions a small filter capacitor from the PGOOD pin to ground will ensure proper operation. Figure 10 shows several different configurations for the LT3435 Power Good circuitry. Figure 10 shows several different configurations for the LT3435 Power Good circuitry.

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted the high speed switching current path, shown in Figure 11, must be kept as short as possible. This is implemented in the suggested layout of Figure 12. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this

PG at VIN > 4V with 100ms Delay

LT3435

PGFB

511k

200k

0.27µF

200k

165k

100k

= 3.3V

OUT

Disconnect at 80% V

OUT

with 100ms Delay

LT3435

PGFB

200k

0.27µF

153k

12k

100k

OUT

= 3.3V

OUT

Figure 10. Power Good Circuits

Disconnect 3.3V Logic Signal

with 100µs Delay

LT3435

PGFB

200k

OUT

866k

100k

270pF

3435 F10

= 12V

OUT

3435fa

LT3435

RI V

tIVf

SW OUT OUT

EFF OUT IN

()( )

()( )()()

12/

WUUU

APPLICATIO S I FOR ATIO

parasitic inductance produces a flyback spike across the LT3435 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT3435 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise.

The V

and FB components should be kept as far away as

possible from the switch and boost nodes. The LT3435 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation.

Board layout also has a significant effect on thermal resistance. Pin 8 and the exposed die pad, Pin 17, are a

LT3435

HIGH

FREQUENCY

CIRCULATION

PATH

OUT

LOAD

continuous copper plate that runs under the LT3435 die. This is the best thermal path for heat out of the package. Reducing the thermal resistance from Pin 8 and exposed pad onto the board will reduce die temperature and increase the power capability of the LT3435. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple solder filled feedthroughs under and around this pad to an internal ground plane will also help. Similar treatment to the catch diode and coil terminations will reduce any additional heating effects.

THERMAL CALCULATIONS

Power dissipation in the LT3435 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents.

Switch loss:

GND

Figure 11. High Speed Switching Path

OUT

GND

C2 D2

MINIMIZE

D1-C3

LOOP

CONNECT PIN 8 GND TO THE

PIN 17 EXPOSED PAD GND

PLACE VIA's UNDER EXPOSED

PAD TO A BOTTOM PLANE TO

ENHANCE THERMAL

BOOST

GND

CONDUCTIVITY

PGOOD

SHDN

LT3435

SYNC

PGFB

BIAS

Figure 12. Suggested Layout

3435 F11

Boost current loss:

()

KELVIN SENSE

FEEDBACK

TRACE AND

KEEP SEPARATE

FROM BIAS TRACE

BOOST

Quiescent current loss:

= VIN (0.0026) + V

= switch resistance (≈0.15 when hot )

= effective switch current/voltage overlap time

EFF

(tr + tf + tIR + tIF) tr = (VIN/1.2)ns

OUT OUT

46/

()

(0.001)

OUT

tf = (VIN/1.7)ns tIR = tIF = (I

OUT

/0.2)ns

f = switch frequency

3435 F12

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APPLICATIO S I FOR ATIO

LT3435

Example: with VIN = 25V, V

= 5V and I

OUT

= 2A:

increase in internal dissipation is of insufficient time duration to raise die temperature significantly.

015 2 5

Pee

( )()()

.. .

012 0962 108

BOOST

40 0 0026 5 0 001 0 11

()

Total power dissipation is:

= 1.08 + 0.03+ 0.11 = 1.22W

TOT

Thermal resistance for the LT3435 package is influenced

–

5240

()

77 12 2 25 500 3

()

003

()( )( )

()

...

()

A second consideration is controllability. A potential limitation occurs with a high step-down ratio of V as this requires a correspondingly narrow minimum switch on time. An approximate expression for this (assuming continuous mode operation) is given as follows:

ON(MIN)

where:

= input voltage

= output voltage

OUT

VF = Schottky diode forward drop

by the presence of internal or backside planes. With a full

= switching frequency

plane under the FE16 package, thermal resistance will be about 45°C/W. No plane will increase resistance to about 150°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature:

= TA + QJA (P

With the FE16 package (Q

TOT

)

= 45°C/W) at an ambient

temperature of 70°C:

= 70 + 45(1.22) = 125°C

Input Voltage vs Operating Frequency Considerations

OSC

A potential controllability problem arises if the LT3435 is called upon to produce an on time shorter than it is able to produce. Feedback loop action will lower then reduce the V

control voltage to the point where some sort of cycle-

skipping or Burst Mode behavior is exhibited.

In summary:

1. Be aware that the simultaneous requirements of high V

, high I

practice due to internal dissipation. The Thermal Considerations section offers a basis to estimate internal power. In questionable cases a prototype supply should

The absolute maximum input supply voltage for the LT3435

be built and exercised to verify acceptable operation.

is specified at 60V. This is based solely on internal semiconductor junction breakdown effects. Due to internal power dissipation the actual maximum V

achievable in a

particular application may be less than this.

2. The simultaneous requirements of high V high f

OSC

switch on time. Cycle skipping and/or Burst Mode behavior will result causing an increase in output voltage

A detailed theoretical basis for estimating internal power

ripple while maintaining the correct output voltage.

loss is given in the section Thermal Considerations. Note that AC switching loss is proportional to both operating frequency and output current. The majority of AC switching loss is also proportional to the square of input voltage.

For example, while the combination of V 5V at 2A and f multaneously raising V

= 500kHz may be easily achievable, si-

OSC

to 60V and f

= 40V, V

to 700kHz is not

OSC

OUT

possible. Nevertheless, input voltage transients up to 60V can usually be accommodated, assuming the resulting

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency response the following should be remembered—the worse

the board layout, the more difficult the circuit will be to stabilize. This is true of almost all high frequency analog circuits. Read the Layout Considerations section first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or

to V

OUT

= V

+ VF/VIN(f

OUT

and high f

OUT

)

OSC

may not be achievable in

OSC

, low V

OUT

and

can result in an unacceptably short minimum

3435fa

LT3435

WUUU

APPLICATIO S I FOR ATIO

catch diode and connecting the VC compensation to a ground track carrying significant switch current. In addition the theoretical analysis considers only first order nonideal component behavior. For these reasons, it is important that a final stability check is made with production layout and components.

The LT3435 uses current mode control. This alleviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 12. The LT3435 can be considered as two gm blocks, the error amplifier and the power stage.

Figure 13 shows the overall loop response with a 330pF V

capacitor and a typical 100µF tantalum output capacitor. The response is set by the following terms:

Error amplifier: DC gain is set by g

and RO:

Ω

EA Gain = 650µ • 1.5M = 975

The pole set by CF and RL:

EA Pole = 1/(2π • 1.5M • 470pF) = 220Hz

Unity gain frequency is set by C

and gm:

EA Unity Gain Frequency = 650µF/(2π • 470pF)

= 220kHz

Powerstage: DC gain is set by gm and RL (assume 10Ω):

PS DC Gain = 6 • 10 = 60

LT3435

CURRENT MODE

POWER STAGE

Ω

= 6

gm = 650µ

1.5MR

Ω

ERROR

AMP

–

OUTPUT

ESR

1.25V

3435 F13

OUT

Figure 13. Model for Loop Response

capacitor. As the value of R

is increased, transient re-

sponse will generally improve but two effects limit its value. First, the combination of output capacitor ESR and a large RC may stop loop gain rolling off altogether. Second, if the loop gain is not rolled off sufficiently at the switching frequency output ripple will perturb the V

pin enough to cause unstable duty cycle switching similar to subharmonic oscillation. This may not be apparent at the output. Small-signal analysis will not show this since a continuous time system is assumed.

When checking loop stability the circuit should be operated over the application’s full voltage, current and temperature range. Any transient loads should be applied and the output voltage monitored for a well-damped behavior.

Pole set by C

OUT

and RL:

PS Pole = 1/(2π • 100µF • 10) = 159Hz

Unity gain set by C

OUT

and gm:

PS Unity Gain Freq = 6/(2π • 100µF) = 94kHz.

Tantalum output capacitor zero is set by C

OUT

and C

OUT

ESR

Output Capacitor Zero = 1/(2π • 100µF • 0.1) = 15.9kHz

The zero produced by the ESR of the tantalum output capacitor is very useful in maintaining stability. If better transient response is required, a zero can be added to the loop using a resistor (R

) in series with the compensation

100

GAIN (dB)

–40

–80

100 1k 10k 100k

OUT

= 470pF

= 10k

= 4700pF

LOAD

FREQUENCY (Hz)

= 3.3V = 100µF, 0.1Ω

= 1A

Figure 14. Overall Loop Response

3435 F14

1M10

180

160

PHASE (DEG)

120

3435fa

PACKAGE DESCRIPTIO

(.141)

3.58

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

4.90 – 5.10* (.193 – .201)

3.58

(.141)

16 1514 13 12 11

LT3435

10 9

6.60 ±0.10

4.50 ±0.10

RECOMMENDED SOLDER PAD LAYOUT

0.09 – 0.20

(.0035 – .0079)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

0.65 BSC

4.30 – 4.50* (.169 – .177)

0.50 – 0.75

(.020 – .030)

MILLIMETERS

(INCHES)

(.116)

0.45 ±0.05

2.94

1.05 ±0.10

1345678

0.25 REF

0° – 8°

0.65

(.0256)

BSC

0.195 – 0.30

(.0077 – .0118)

TYP

4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE

2.94

(.116)

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

FE16 (BC) TSSOP 0204

6.40

(.252)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3435fa

LT3435

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OUT

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< 10µA, DD5/7, TO220-5/7

< 2.5µA, S8

< 25µA, TSSOP16/E

< 30µA, N8, S8

TSSOP16

), 1.1MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, V

OUT

< 25µA, TSSOP16/E

MS8E

), 1.5MHz, High Efficiency Step-Down DC/DC VIN: 2.5V to 5.5V, V

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TSSOP16E

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OUT

TSSOP20E

< 30µA, TSSOP16E

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OUT

QFN-32, SSOP-28

= 2.21V, IQ = 8.5mA,

OUT(MIN)

= 2.21V, IQ = 8.5mA,

OUT(MIN)

= 1.24V, IQ = 3.2mA,

OUT(MIN)

= 1.20V, IQ = 1mA, I

OUT(MIN)

= 1.20V, IQ = 2.5mA,

OUT(MIN)

= 1.20V, IQ = 1mA, I

OUT(MIN)

= 1.24V, IQ = 3.2mA,

OUT(MIN)

= 0.8V, IQ = 15µA, ISD < 1µA,

OUT(MIN)

= 1.2V, IQ = 3.8mA, MS10

OUT(MIN)

= 1.20V, IQ = 2.5mA,

OUT(MIN)

= 1.28V, IQ = 30µA, ISD < 1µA,

OUT(MIN)

= 0.6V, IQ = 40µA, MS10

OUT(MIN)

= 0.8V, IQ = 60µA, ISD < 1µA,

OUT(MIN)

= 0.8V, IQ = 64µA, ISD < 1µA,

OUT(MIN)

= 1.20V, IQ = 2.5mA,

OUT(MIN)

= 1.20V, IQ = 2.5mA,

OUT(MIN)

: 3.3V to 20V, IQ = 100µA, TSSOP-16E

OUT

= 0.8V, IQ = 670µA, ISD < 20µA,

OUT(MIN)

< 15µA,

< 6µA,

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

3435fa

LT 0306 REV A • PRINTED IN USA

LINEAR TECHNOLOGY LT3435 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual