LINEAR TECHNOLOGY LT3430, LT3430-1 Technical data

LT3430/LT3430-1

High Voltage, 3A,

200kHz/100kHz Step-Down

Switching Regulators

FEATURES

■

Wide Input Range: 5.5V to 60V

■

3A Peak Switch Current over All Duty Cycles

■

Constant Switching Frequency:
200kHz (LT3430)
100kHz (LT3430-1)

■

0.1Ω Switch Resistance

■

Current Mode

■

Effective Supply Current: 2.5mA

■

Shutdown Current: 30µA

■

1.2V Feedback Reference Voltage

■

Easily Synchronizable

■

Cycle-by-Cycle Current Limiting

■

Small, 16-Pin Thermally Enhanced TSSOP Package

APPLICATIONS

■

Industrial and Automotive Power Supplies

■

Portable Computers

■

Battery Chargers

■

Distributed Power Systems

DESCRIPTION

The LT®3430/LT3430-1 are monolithic buck switching
regulators that accept input voltages up to 60V. A high ef­fi ciency 3A, 0.1Ω switch is included on the die along with
all the necessary oscillator, control and logic circuitry. A
current mode architecture provides fast transient response
and excellent loop stability.

Special design techniques and a new high voltage process
achieve high effi ciency over a wide input range. Effi ciency
is maintained over a wide output current range by using
the output to bias the circuitry and by utilizing a supply
boost capacitor to saturate the power switch. Patented
circuitry* maintains peak switch current over the full duty
cycle range. A shutdown pin reduces supply current to
30µA and a SYNC pin can be externally synchronized with
a logic level input from 228kHz to 700kHz for the LT3430
or from 125kHz to 250kHz for the LT3430-1.

The LT3430/LT3430-1 are available in a thermally enhanced
16-pin TSSOP package.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
*US Patent # 6498466

TYPICAL APPLICATION

5V, 2A Buck Converter

V

IN

5.5V*

TO 60V

4.7µF
100V

ONOFF

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY
** SEE LT3430-1 CIRCUIT IN APPLICATIONS INFORMATION SECTION

V

IN

SHDN

SYNC

GND

0.022µF

BOOST

LT3430**

3.3k

SW

BIAS

V

FB

C

220pF

3430 TA01

0.68µF

30BQ060

MMSD914TI

22µH

15.4k

4.99k

+

V

OUT

5V
2A

100µF 10V
SOLID
TANTALUM

Effi ciency vs Load Current

100

= 5V

V

OUT

90

80

70

EFFICIENCY (%)

60

50

0.5

0

1.0

LOAD CURRENT (A)

VIN = 12V

VIN = 42V

LT3430-1 L = 68µH
LT3430 L =27µH

1.5

2.0

2.5

3430 TA02

34301fa

1

LT3430/LT3430-1

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Input Voltage (VIN) .................................................. 60V

BOOST Pin Above SW (Note 11) .............................. 35V

BOOST Pin Voltage ................................................. 68V

SYNC Voltage ............................................................. 7V

⎯S⎯H⎯D⎯

N Voltage ............................................................ 6V

BIAS Pin Voltage ..................................................... 30V

FB Pin Voltage/Current .................................. 3.5V/2mA

Operating Junction Temperature Range

LT3430EFE (Notes 8, 10) .................. –40°C to 125°C

LT3430IFE (Notes 8, 10) .................. –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

PACKAGE/ORDER INFORMATION

TOP VIEW

1

GND

2

SW

3

V

IN

4

V

IN

SW

BOOST

NC

GND

16-LEAD PLASTIC TSSOP

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

5

6

7

8

FE PACKAGE

17

ORDER PART NUMBER FE PART MARKING

LT3430EFE
LT3430IFE
LT3430EFE-1
LT3430IFE-1

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

GND

16

SHDN

15

SYNC

14

NC

13

FB

12

V

11

C

BIAS

10

GND

9

3430EFE

3430IFE

3430EFE-1

3430IFE-1

ELECTRICAL CHARACTERISTICS

The
temperature range, otherwise specifi cations are at T

= 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit,

J

●

denotes the specifi cations which apply over the full operating

SW = Open Circuit, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Voltage (V

FB Input Bias Current

Error Amp Voltage Gain (Note 2) 200 400 V/V

Error Amp g

to Switch g

V

C

EA Source Current FB = 1V

EA Sink Current FB = 1.4V

VC Switching Threshold Duty Cycle = 0 0.9 V

High Clamp

V

C

Switch Current Limit V

Switch On Resistance I

Maximum Switch Duty Cycle (LT3430) FB = 1V

m

m

)V

REF

+ 0.2 ≤ VC ≤ VOH – 0.2

OL

5.5V ≤ V

dl (VC) = ±10µA

⎯S⎯H⎯D⎯

C

–40°C ≤ T
T

J

SW

≤ 60V

IN

N = 1V 2.1 V

Open, Boost = VIN + 5V, FB = 1V

≤ 25°C

J

= 125°C (Note 9)

= 2.5A, Boost = VIN + 5V (Note 7) 0.1 0.14

1.204

●

1.195

●

1650

●

1000

●

125 225 450 µA

●

100 225 500 µA

2.5

93

●

90

3

1.219 1.234

–0.2 –1.5 µA

2200 3300

3.4 A/V

96 %

1.243

4200

5
4

6.5

5.5

0.18

µMho
µMho

34301fa

V

A
A

Ω
Ω

%

2

LT3430/LT3430-1

ELECTRICAL CHARACTERISTICS

The
temperature range, otherwise specifi cations are at T

= 25°C. VIN = 15V, VC = 1.5V, ⎯S⎯H⎯D⎯N = 1V, BOOST = Open Circuit,

J

SW = Open Circuit, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Maximum Switch Duty Cycle (LT3430-1)

Switch Frequency (LT3430) V

Switch Frequency (LT3430-1)

f

Line Regulation 5.5V ≤ VIN ≤ 60V

SW

Shifting Threshold Df = 10kHz 0.8 V

f

SW

Minimum Input Voltage (Note 3)

Minimum Boost Voltage (Note 4) I

Boost Current (Note 5) Boost = V

Input Supply Current (I

Bias Supply Current (I

) (Note 6) V

VIN

) (Note 6) V

BIAS

Shutdown Supply Current

Lockout Threshold VC Open

Shutdown Threshold V

Minimum SYNC Amplitude 1.5 V

SYNC Frequency Range (LT3430) 228 700 kHz

SYNC Frequency Range (LT3430-1) 125 250 kHz

SYNC Input Resistance 20 kΩ

Set to Give DC = 50%

C

Boost = V

⎯S⎯H⎯D⎯

N = 0V, VIN ≤ 60V, SW = 0V, VC Open

Open, Shutting Down

C

V

Open, Starting Up

C

●

denotes the specifi cations which apply over the full operating

96

●

94

184

●

172

88

●

85

●

●

≤ 2.5A

SW

+ 5V, ISW = 0.75A

IN

+ 5V, ISW = 2.5A

IN

= 5V 1.5 2.2 mA

BIAS

= 5V 3.1 4.2 mA

BIAS

●

●

●

98 %

200
200

100
100

216
228

115
120

0.05 0.15 %/V

4.6 5.5 V

1.8 3 V

25
75

50

120

30 100

●

●

2.3 2.42 2.53 V

●

0.15

●

0.25

0.37

0.42

200

0.58

0.60

kHz
kHz

kHz
kHz

mA
mA

µA
µA

%

V
V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: Gain is measured with a V

swing equal to 200mV above the low

C

clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is defi ned as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.

Note 5: Boost current is the current fl owing into the BOOST pin with the
pin held 5V above input voltage. It fl ows only during switch on time.

Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held
at 5V. Total input referred supply current is calculated by summing input
supply current (I

I
With V

TOTAL

IN

= I

= 15V, V

) with a fraction of bias supply current (I

VIN

+ (I

VIN

OUT

BIAS

= 5V, I

)(V

OUT/VIN

= 1.4mA, I

VIN

)

= 2.9mA, I

BIAS

BIAS

TOTAL

):

= 2.4mA.

Note 7: Switch on resistance is calculated by dividing V

to SW voltage

IN

by the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.

Note 8: The LT3430EFE/LT3430EFE-1 are guaranteed to meet performance
specifi cations from 0°C to 125°C junction temperature. Specifi cations over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3430IFE/LT3430IFE-1 are guaranteed over the full –40°C to 125°C
operating junction temperature range.

Note 9: See Peak Switch Current Limit vs Junction Temperature graph in
the Typical Performance Characteristics section.

Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.

Note 11: The maximum operational Boost-SW voltage is limited by
thermal and load current constraints. See ‘Boost Pin’ and ‘Thermal
Calculations’ in the Applications Information section.

34301fa

3

LT3430/LT3430-1

PHASE

(DEG)

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Peak Current Limit FB Pin Voltage and Current

6

TJ = 25°C

5

TYPICAL

4

3

SWITCH PEAK CURRENT (A)

2

GUARANTEED MINIMUM

20 40 60 80

DUTY CYCLE (%)

3430 G01

1.234

1.229

1.224

1.219

1.214

FEEDBACK VOLTAGE (V)

1.209

1.204

1000

–50

VOLTAGE

CURRENT

–25 0

JUNCTION TEMPERATURE (°C)

25 75

50 100 125

3430 G02

2.0

1.5

CURRENT (µA)

1.0

0.5

0

⎯S⎯H⎯D⎯

N Pin Bias Current

250

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

200

150

100

CURRENT (µA)

12

CURRENT DROPS TO A FEW µA

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

6

0

–50

–25 0

JUNCTION TEMPERATURE (°C)

25 75

Lockout and Shutdown Threshold Shutdown Supply Current Shutdown Supply Current

2.4

2.0

1.6

1.2

0.8

SHDN PIN VOLTAGE (V)

0.4

0

–50

0

–25 125

JUNCTION TEMPERATURE (°C)

LOCKOUT

START-UP

SHUTDOWN

50 100

25 75

3430 G04

40

V

= 0V

SHDN

= 25°C

T

A

35

30

25

20

15

10

INPUT SUPPLY CURRENT (µA)

5

0

10 20 30 40 50 60

0

INPUT VOLTAGE (V)

3430 G05

300

TA = 25°C

250

200

150

100

INPUT SUPPLY CURRENT (µA)

50

0

0

VIN = 60V

0.1 0.2 0.3 0.4
SHUTDOWN VOLTAGE (V)

50 100 125

3430 G03

= 15V

V

IN

0.5

3430 G06

Error Amplifi er Transconductance Error Amplifi er Transconductance Frequency Foldback

TRANSCONDUCTANCE (µmho)

2500

2000

1500

1000

500

0

–50

0

JUNCTION TEMPERATURE (°C)

50 100

25 75–25 125

3430 G07

3000

2500

2000

1500

V

GAIN (µMho)

1000

500

2 • 10

FB

ERROR AMPLIFIER EQUIVALENT CIRCUIT

R

LOAD

= 25°C

T

A

100 10k 100k 10M

PHASE

GAIN

R

–3

)(

= 50Ω

1k 1M

FREQUENCY (Hz)

OUT

200k

C
12pF

OUT

V

C

3430 G08

200

150

100

50

0

–50

600

500

400

300

200

OR FB CURRENT (µA)

SWITICHING FREQUENCY (kHz)

100

0

0

T

A

= 25°C

4

FB PIN
CURRENT

0.5

3430-1

VFB (V)

3430

SWITCHING
FREQUENCY

1.0

1.5

3430 G09

34301fa

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Input Voltage with

Switching Frequency

230

220

210

200

190

FREQUENCY (kHz)

180

170

–50

0

–25 125

JUNCTION TEMPERATURE (°C)

2.1

1.9

1.7

1.5

1.3

1.1

THRESHOLD VOLTAGE (V)

0.9

0.7
–50

(LT3430)

50 100

25 75

3430 G10

Pin Shutdown Threshold Switch Voltage Drop

V

C

50 100 125

–25 0

25 75

JUNCTION TEMPERATURE (°C)

5V Output BOOST Pin Current

7.5

7.0

6.5

6.0

INPUT VOLTAGE (V)

5.5

5.0
0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

3430 G13

MINIMUM INPUT
VOLTAGE TO START

MINIMUM INPUT
VOLTAGE TO RUN

LOAD CURRENT (A)

450

400

350

300

250

200

150

SWITCH VOLTAGE (mV)

100

50

0

0123

TA = 25°C

3430 G11

SWITCH CURRENT (A)

LT3430/LT3430-1

90

TA = 25°C

80

70

60

50

40

30

BOOST PIN CURRENT (mA)

20

10

0

0123

SWITCH CURRENT (A)

TJ = 125°C

TJ = 25°C

TJ = –40°C

3430 G14

3430 G12

Switch Peak Current Limit

6.0

5.5

5.0

4.5

4.0

3.5

SWITCH PEAK CURRENT LIMIT (A)

3.0

2.5
–50

0

–25 125

JUNCTION TEMPERATURE (°C)

25 75

50 100

3430 G16

Switch Minimum ON Time
vs Temperature

600

500

400

300

200

100

SWITCH MINIMUM ON TIME (ns)

0

–50

–25 0

JUNCTION TEMPERATURE (°C)

25 75

50 100 125

3430 G15

34301fa

5

LT3430/LT3430-1

PIN FUNCTIONS

GND (Pins 1, 8, 9, 16, 17): The GND pin connections act
as the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents fl ow through metal
paths between the GND pins and the load ground. Keep the
paths between the GND pins and the load ground short and
use a ground plane when possible. The FE package has an
exposed pad that is fused to the GND pins. The pad (Pin

17) should be soldered to the copper ground plane under
the device to reduce thermal resistance. (See Applications
Information—Layout Considerations.)

SW (Pins 2, 5): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin voltage negative during switch off time. Negative
voltage is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.

(Pins 3, 4): This is the collector of the on-chip power

V

IN

NPN switch. V
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
capacitor, through the catch diode back to SW. All trace
inductance in this path creates voltage spikes at switch
off, adding to the V

BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
BOOST voltage allows the switch to saturate and voltage
loss approximates that of a 0.1Ω FET structure.

NC (Pins 7, 13): No Connection.

powers the internal control circuitry when

IN

pin through the input bypass

IN

voltage across the internal NPN.

CE

This architecture increases effi ciency especially when the
input voltage is much higher than the output. Minimum
output voltage setting for this mode of operation is 3V.

(Pin 11): The VC pin is the output of the error amplifi er

V

C

and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. V
at about 0.9V for light loads and 2.1V at maximum load.
It can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.

FB (Pin 12): The feedback pin is used to set the output
voltage using an external voltage divider that generates

1.22V at the pin for the desired output voltage. Three
additional functions are performed by the FB pin. When
the pin voltage drops below 0.6V, switch current limit is
reduced and the external SYNC function is disabled. Below

0.8V, switching frequency is also reduced. See Feedback
Pin Functions in Applications Information for details.

SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between 10%
and 90% duty cycle. The synchronizing range is 125kHz
to 250kHz for the LT3430-1 and 228kHz to 700kHz for the
LT3430. See Synchronizing in Applications Information
for details.

⎯S⎯H⎯D⎯

N (Pin 15): The ⎯S⎯H⎯D⎯N pin is used to turn off the

regulator and to reduce input drain current to a few mi­croamperes. This pin has two thresholds: one at 2.38V to
disable switching and a second at 0.4V to force complete
micropower shutdown. The 2.38V threshold functions
as an accurate undervoltage lockout (UVLO); sometimes
used to prevent the regulator from delivering power until
the input voltage has reached a predetermined level.

sits

C

BIAS (Pin 10): The BIAS pin is used to improve effi ciency
when operating at higher input voltages and light load cur­rent. Connecting this pin to the regulated output voltage
forces most of the internal circuitry to draw its operating
current from the output voltage rather than the input supply.

6

⎯S⎯H⎯D⎯

If the
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.

N pin functions are not required, the pin can

34301fa

BLOCK DIAGRAM

LT3430/LT3430-1

The LT3430/LT3430-1 are constant frequency, current
mode buck converters. This means that there is an in­ternal clock and two feedback loops that control the duty
cycle of the power switch. In addition to the normal error
amplifi er, there is a current sense amplifi er that monitors
switch current on a cycle-by-cycle basis. A switch cycle
starts with an oscillator pulse which sets the R

fl ip-fl op

S

to turn the switch on. When switch current reaches a level
set by the inverting input of the comparator, the fl ip-fl op
is reset and the switch turns off. Output voltage control is
obtained by using the output of the error amplifi er to set
the switch current trip point. This technique means that the
error amplifi er commands current to be delivered to the
output rather than voltage. A voltage fed system will have
low phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes

V

IN

3, 4

BIAS

SYNC

10

14

SHUTDOWN

COMPARATOR

2.9V BIAS

REGULATOR

+

0.4V

–

INTERNAL
V

CC

SLOPE COMP

ANTISLOPE COMP

200kHz: LT3430

100kHz: LT3430-1

OSCILLATOR

Σ

it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.

Most of the circuitry of the LT3430/LT3430-1 operates
from an internal 2.9V bias line. The bias regulator normally
draws power from the regulator input pin, but if the BIAS
pin is connected to an external voltage equal to or higher
than 3V, bias power will be drawn from the external source
(typically the regulated output voltage). This will improve
effi ciency if the BIAS pin voltage is lower than regulator
input voltage.

High switch effi ciency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external ca­pacitor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.

R

LIMIT

–

+

CURRENT
COMPARATOR

BOOST

6

S

R

R

S

FLIP-FLOP

DRIVER

CIRCUITRY

R

SENSE

Q1
POWER
SWITCH

SHDN

5.5µA

2.38V

+

–

LOCKOUT

COMPARATOR

V

C(MAX)

CLAMP

FREQUENCY

FOLDBACK

×1

Q2

FOLDBACK

Q3

CURRENT

LIMIT

CLAMP

11

V

C

AMPLIFIER

= 2000µMho

g

m

ERROR

–

+

15

1.22V

2, 5

12

3430 F01

SW

FB

GND
1, 8, 9, 16, 17

Figure 1. LT3430/LT3430-1 Block Diagram

34301fa

7

LT3430/LT3430-1

APPLICATIONS INFORMATION

FEEDBACK PIN FUNCTIONS

The feedback (FB) pin on the LT3430/LT3430-1 is used to
set output voltage and provide several overload protection
features. The fi rst part of this section deals with selecting
resistors to set output voltage and the second part talks
about foldback frequency and current limiting created by
the FB pin. Please read both parts before committing to
a fi nal design.

The suggested value for the LT3430 output divider resistor
(see Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. For the LT3430-1, choose
the resistors so that the Thevinin resistance of the divider
at the feedback pin is 7.5kΩ. The output voltage error
caused by ignoring the input bias current on the FB pin
is less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.

.

122

R2

.

−

(NEAREST 1%)

R1

(kΩ)

% ERROR AT OUTPUT
DUE TO DISCREET 1%

RESISTOR STEPS

RV

2122

()

R

1

=

OUT

Table 1. *LT3430, **LT3430-1

OUTPUT

VOLTAGE

(V)

3* 4.99 7.32 +0.32

3.3* 4.99 8.45 –0.43

5* 4.99 15.4 –0.30

12* 4.12 46.4 –0.27

3** 12.7 18.7 +0.54

3.3** 12.1 20.5 –0.40

5** 10 30.9 –0.20

12** 8.25 73.2 +0.37

(kΩ)

More Than Just Voltage Feedback

The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
and in the external diode and inductor during short-cir­cuit conditions. A shorted output requires the switching
regulator to operate at very low duty cycles, and the

average current through the diode and inductor is equal
to the short-circuit current limit of the switch (typically
4A for the LT3430/LT3430-1, folding back to less than
2A). Minimum switch on time limitations would prevent
the switcher from attaining a suffi ciently low duty cycle if
switching frequency were maintained at 200kHz (100kHz
LT3430-1), so frequency is reduced by about 5:1 (3:1
LT3430-1) when the feedback pin voltage drops below

0.8V (see Frequency Foldback graph). This does not affect
operation with normal load conditions; one simply sees
a gear shift in switching frequency during start-up as the
output voltage rises.

In addition to lower switching frequency, the LT3430/
LT3430-1 also operate at lower switch current limit when
the feedback pin voltage drops below 0.6V. Q2 in Figure 2
performs this function by clamping the V

pin to a voltage

C

less than its normal 2.1V upper clamp level. This foldback
current limit greatly reduces power dissipation in the IC,
diode and inductor during short-circuit conditions. External
synchronization is also disabled to prevent interference
with foldback operation. Again, it is nearly transparent to
the user under normal load conditions. The only loads that
may be affected are current source loads which maintain
full load current with output voltage less than 50% of
fi nal value. In these rare situations the feedback pin can
be clamped above 0.6V with an external diode to defeat
foldback current limit. Caution: clamping the feedback
pin means that frequency shifting will also be defeated,
so a combination of high input voltage and dead shorted
output may cause the LT3430/LT3430-1 to lose control
of current limit.

The internal circuitry which forces reduced switching
frequency also causes current to fl ow out of the feedback
pin when output voltage is low. The equivalent circuitry
is shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and LT3430 reduces frequency at the rate
of approximately 1.4kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance (R

) must be low

THEV

enough to pull 115µA out of the FB pin with 0.44V on
the pin (R

≤ 3.8k)(LT3430-1 R

THEV

≈ 7.5k). The net

THEV

result is that reductions in frequency and current limit
are affected by output voltage divider impedance. Cau-

34301fa

8

APPLICATIONS INFORMATION

LT3430/LT3430-1

LT3430

TO FREQUENCY

ERROR

AMPLIFIER

SHIFTING

1.4V

++

1.2V

R3
1k

Q1

R4
2k

––

BUFFER

Q2

TO SYNC CIRCUIT

V

GND

C

Figure 2. Frequency and Current Limit Foldback

tion should be used if resistors are increased beyond the
suggested values and short-circuit conditions occur with
high input voltage. High frequency pickup will increase

and the protection accorded by frequency and current
foldback will decrease.

Choosing the Inductor

For most applications, the output inductor will fall into
the range of 5µH to 47µH (10µH to 100µH for LT3430-1).
Lower values are chosen to reduce physical size of the
inductor. Higher values allow more output current because
they reduce peak current seen by the LT3430/LT3430-1
switch, which has a 3A limit. Higher values also reduce
output ripple voltage.

When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc­tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested
as a way of handling these somewhat complicated and
confl icting requirements.

V

SW

20mV/DIV

20mV/DIV

VIN = 40V

= 5V

V

OUT

L = 22µH

L1

R1

FB

R2

+

2µs/DIV

C1

3430 F02

OUTPUT
5V

3430 F03

V

USING

OUT

100µF CERAMIC
OUTPUT
CAPACITOR

USING

V

OUT

100µF 0.08Ω
TANTALUM
OUTPUT
CAPACITOR

Figure 3. LT3430 Output Ripple Voltage Waveforms.
Ceramic vs Tantalum Output Capacitors

ceramic output capacitor; the signifi cant decrease in out­put ripple voltage is due to the very low ESR of ceramic
capacitors.

Output ripple voltage is determined by ripple current (I

LP-P

)
through the inductor and the high frequency impedance of
the output capacitor. At high frequencies, the impedance
of the tantalum capacitor is dominated by its effective
series resistance (ESR).

Output Ripple Voltage

Figure 3 shows a comparison of output ripple voltage for
the LT3430/LT3430-1 using either a tantalum or ceramic
output capacitor. It can be seen from Figure 3 that output
ripple voltage can be signifi cantly reduced by using the

Tantalum Output Capacitor

The typical method for reducing output ripple voltage
when using a tantalum output capacitor is to increase the
inductor value (to reduce the ripple current in the inductor).
The following equations will help in choosing the required

34301fa

9

LT3430/LT3430-1

APPLICATIONS INFORMATION

inductor value to achieve a desirable output ripple volt­age level. If output ripple voltage is of less importance,
the subsequent suggestions in Peak Inductor and Fault
Current and EMI will additionally help in the selection of
the inductor value.

Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (I

) times ESR)

LP-P

and a square wave (created by parasitic inductance (ESL)

Ceramic Output Capacitor

An alternative way to further reduce output ripple voltage
is to reduce the ESR of the output capacitor by using a
ceramic capacitor. Although this reduction of ESR removes
a useful zero in the overall loop response, this zero can
be replaced by inserting a resistor (R

pin and the compensation capacitor CC. (See Ceramic

V

C

Capacitors in Applications Information.)

and ripple current slew rate). Capacitive reactance is as­sumed to be small compared to ESR or ESL.

V I ESR ESL

RIPPLE LP P

=

()()

-

+

dI

()

dt

where:

ESR = equivalent series resistance of the output capaci­tor

ESL = equivalent series inductance of the output capaci­tor

dI/dt = slew rate of inductor ripple current = V

Peak-to-peak ripple current (I

) through the inductor

LP-P

IN

/L

and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It
is approximated by:

VVV

()( )

I

-

LP P

OUT IN OUT

=

()()()

Example: with VIN = 40V, V

–

VfL

IN

= 5V, L = 22µH, ESR =

OUT

0.080Ω and ESL = 10nH, output ripple voltage can be
approximated as follows:

540 5

IA

=

P-P

dI

dt

VA

=+=

40 22 10 200 10

()

==

22 10

RIPPLE

0 079 0 018 97

..

()−()

−

63

••

()()

40

−

6

•
0 99 0 08 10 10 10 1 8

.. • .

=

()()

6

10 1 8

•.

mV

+

()()

P-P

099

.

=

−

96

()

To reduce output ripple voltage further requires an increase
in the inductor value with the trade-off being a physically

Peak Inductor Current and Fault Current

To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the
maximum load current. An appropriate inductor should
then be chosen. In addition, a decision should be made
whether or not the inductor must withstand continuous
fault conditions.

If maximum load current is 1A, for instance, a 1A induc­tor may not survive a continuous 4A overload condition.
Dead shorts will actually be more gentle on the inductor
because the LT3430/LT3430-1 have frequency and current
limit foldback.

Table 2

VENDOR/
PART NO.

Sumida

CDRH104R-150 15 3.6 0.050 4

CDRH104R-220 22 2.9 0.073 4

CDRH104R-330 33 2.3 0.093 4

CDRH124-220 22 2.9 0.066 4.5

CDRH124-330 33 2.7 0.097 4.5

CDRH127-330 33 3.0 0.065 8

CDRH127-470 47 2.5 0.100 8

CEI122-220 22 2.3 0.085 8

Coiltronics

UP3B-330 33 3 0.069 6.8

UP3B-470 47 2.4 0.108 6.8

UP4B-680 68 4.3 0.120 7.9

Coilcraft

DO3316P-153 15 3 0.046 5.2

DO5022p-683 68 3.5 0.130 7.1

VALUE

(µH)

larger inductor with the possibility of increased component
height and cost.

I

DC

(Amps)

) in series with the

C

DCR

(Ohms)

HEIGHT

(mm)

34301fa

10

APPLICATIONS INFORMATION

LT3430/LT3430-1

Peak switch and inductor current can be signifi cantly higher
than output current, especially with smaller inductors
and lighter loads, so don’t omit this step. Powdered iron
cores are forgiving because they saturate softly, whereas
ferrite cores saturate abruptly. Other core materials fall
somewhere in between. The following formula assumes
continuous mode of operation, but errs only slightly on
the high side for discontinuous mode, so it can be used
for all conditions.

VVV

I

-

II

=+ =+

PEAK OUT

EMI

Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic fi eld radiation,
or whether it needs a closed core like a toroid to prevent
EMI problems. This is a tough decision because the rods
or barrels are temptingly cheap and small and there are
no helpful guidelines to calculate when the magnetic fi eld
radiation will be a problem.

Additional Considerations

After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department
if you feel uncertain about the fi nal choice. They have ex­perience with a wide range of inductor types and can tell
you about the latest developments in low profi le, surface
mounting, etc.

Maximum Output Load Current

Maximum load current for a buck converter is limited by
the maximum switch current rating (I
for the LT3430/LT3430-1 is 3A. Unlike most current mode
converters, the LT3430/LT3430-1 maximum switch current
limit does not fall off at high duty cycles. Most current
mode converters suffer a drop off of peak switch current
for duty cycles above 50%. This is due to the effects of
slope compensation required to prevent subharmonic
oscillations in current mode converters. (For detailed
analysis, see Application Note 19.)

LP P

I

OUT

22

()( )

OUT IN OUT

()( )()()

). The current rating

P

–

VfL

IN

The LT3430/LT3430-1 are able to maintain peak switch
current limit over the full duty cycle range by using patented
circuitry* to cancel the effects of slope compensation
on peak switch current without affecting the frequency
compensation it provides.

Maximum load current would be equal to maximum switch
current for an infi nitely large inductor, but with fi nite
inductor size, maximum load current is reduced by one­half peak-to-peak inductor current (I
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of IP.

I

OUT(MAX)

Continuous Mode

I–

P

For V

OUT

L = 15µH:

I

OUT MAX

Note that there is less load current available at the higher
input voltage because inductor ripple current increases.
At V

IN

conditions:

I

OUT MAX()

To calculate actual peak switch current with a given set
of conditions, use:

II

SW PEAK

*US Patent # 6,498,466

=

VVVVV

+

I

LP-P

2

= 5V, VIN = 12V, V

()

= 24V, duty cycle is 23% and for the same set of

()

()

=I

OUT F IN OUT F

−

P

5 0 52 12 5 0 52

()

3

=−

2 15 10 200 10 12

()()

..

30525

=− =

5 0 52 24 5 0 52

=−

=− =

=+

=+

()

3

2 15 10 200 10 24

()()

..

3 0 71 2 29

I

OUT

I

OUT

()

LfV

2

()()

.–.

+

••

+

.–.

••

L-P

P

2

() –

VVVVV

OUT F IN OUT F

()

= 0.52V, f = 200kHz and

F(D1)

()

−

63

A

()

−

63

A

+−

2

LfV

()()( )

). The following

LP-P

−

–

IIN

−

()

−

()

()

IN

34301fa

11

LT3430/LT3430-1

APPLICATIONS INFORMATION

Reduced Inductor Value and Discontinuous Mode

If the smallest inductor value is of most importance to a
converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor solu­tion. The maximum output load current in discontinuous
mode, however, must be calculated and is defi ned later
in this section.

Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current

). In this mode, inductor current falls to zero before

(I

LP-P

the next switch turn on (see Figure 8). Buck converters
will be in discontinuous mode for output load current
given by:

+()(––)

I

OUT

Discontinuous Mode

VVVVV

OUT F IN OUT F

<

()( )()()

VfL

2

IN

The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (I

LP-P

) low;
this is done to minimize output ripple voltage and maximize
output load current. In the case of large inductor values,
as seen in the equation above, discontinuous mode will
be associated with “light loads.”

When choosing small inductor values, however, discontinu­ous mode will occur at much higher output load currents.
The limit to the smallest inductor value that can be chosen
is set by the LT3430/LT3430-1 peak switch current (I

) and

P

the maximum output load current required, given by:

I

OUT(MAX)

Discontinuous Mode

2

I

P

=

22()( )

I

LP-P

2

IfLV

••

()

=

VVVVV

()(––)

PIN

+

OUT F IN OUT F

Example: For VIN = 15V, V

I

LP-P

=<

2

= 5V, VF = 0.52V, f = 200kHz

OUT

and L = 4.7µH.

I

OUT(MAX)

Discontinuous

=

Mode

I

OUT(MAX)

= 1.21A

236

3 200 10 4 7 10 15

•( • )( . • )( )

+

25052155052

(.)(––.)

−

Discontinuous Mode

What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be tolerated,
small inductor values can be used. If a higher output load
current is required, the inductor value must be increased.
If I

OUT(MAX)

criteria, use the I

no longer meets the discontinuous mode

OUT(MAX)

equation for continuous mode;
the LT3430/LT3430-1 are designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.

Short-Circuit Considerations

The LT3430/LT3430-1 are current mode controllers. They
use the V

node voltage as an input to a current compara-

C

tor which turns off the output switch on a cycle-by-cycle
basis as this peak current is reached. The internal clamp on

node, nominally 2V, then acts as an output switch

the V

C

peak current limit. This action becomes the switch current
limit specifi cation. The maximum available output power
is then determined by the switch current limit.

A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifi er responds to the
low output voltage by raising the control voltage, V

, to its

C

peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by V

. However, there is fi nite response

C

time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
t

ON(MIN)

(V

. When combined with the large ratio of VIN to

+ I • R), the diode forward voltage plus inductor I • R

F

voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:

12

ft

•

ON

VIR

•≤+

F

V

IN

34301fa

APPLICATIONS INFORMATION

LT3430/LT3430-1

where:
f = switching frequency

= switch minimum on time

t

ON

= diode forward voltage

V

F

= Input voltage

V

IN

I • R = inductor I • R voltage drop

If this condition is not observed, the current will not be
limited at I

, but will cycle-by-cycle ratchet up to some

PK

higher value. Using the nominal LT3430/LT3430-1 clock
frequencies of 200KHz/100kHz, a V
I • R) of say 0.7V, the maximum t

of 40V and a (VF +

IN

to maintain control

ON

would be approximately 90ns for the LT3430 and 180ns
for the LT3430-1, unacceptably short times.

The solution to this dilemma is to slow down the oscil­lator when the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition. Oscillator

quency is unaffected until FB voltage drops to about

fre
2/3 of its normal value. Below this point the oscillator
frequency decreases roughly linearly down to a limit of
about 40kHz. (30kHz for LT3430-1) This lower oscillator
frequency during short-circuit conditions can then maintain
control with the effective minimum on time.

/(V

It is recommended that for [V

IN

+ VF)] ratios >

OUT

10, a soft-start circuit should be used for the LT3430 to
control the output capacitor charge rate during start-up
or during recovery from an output short circuit, thereby
adding additional control over peak inductor current. See
Buck Converter with Adjustable Soft-Start later in this
data sheet.

Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current

E Case Size ESR (Max., Ω ) Ripple Current (A)

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

D Case Size

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

C Case Size

AVX TPS 0.2 (typ) 0.5 (typ)

from 22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you fi nd a tiny 22µF solid
tantalum capacitor, it will have high ESR, and output ripple
voltage will be terrible. Table 3 shows some typical solid
tantalum surface mount capacitors.

Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents. This
is historically true, and type TPS capacitors are specially
tested for surge capability, but surge ruggedness is not
a critical issue with the output capacitor. Solid tantalum
capacitors fail during very high turn-on surges, which
do not occur at the output of regulators. High discharge
surges, such as when the regulator output is dead shorted,
do not harm the capacitors.

Unlike the input capacitor, RMS ripple current in the output
capacitor is normally low enough that ripple current rating
is not an issue. The current waveform is triangular with
a typical value of 250mA

. The formula to calculate

RMS

this is:

Output capacitor ripple current (RMS):

OUTPUT CAPACITOR

The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT3430 applications is 0.05Ω to 0.2Ω.
A typical output capacitor is an AVX type TPS, 100µF at
10V, with a guaranteed ESR less than 0.1Ω (The LT3430-1
will typically use two of these capacitors in parallel). This
is a “D” size surface mount solid tantalum capacitor. TPS
capacitors are specially constructed and tested for low
ESR, so they give the lowest ESR for a given volume. The
value in microfarads is not particularly critical, and values

I

RIPPLE RMS

029.

=

()

VVV

()

OUT IN OUT

LfV

()()( )

−

()

IN

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Their low ESR reduces
output ripple voltage but also removes a useful zero in the
loop frequency response, common to tantalum capaci­tors. To compensate for this, a resistor R
in series with the V

compensation capacitor CC. Care

C

can be placed

C

must be taken however, since this resistor sets the high

34301fa

13

LT3430/LT3430-1

APPLICATIONS INFORMATION

frequency gain of the error amplifi er, including the gain at
the switching frequency. If the gain of the error amplifi er
is high enough at the switching frequency, output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
fi lter capacitor C
suggested to control possible ripple at the V

in parallel with the RC/CC network is

F

pin. An “All

C

Ceramic” solution is possible for the LT3430/LT3430-1
by choosing the correct compensation components for
the given application.

Example: For V

= 8V to 40V, V

IN

= 5V at 2A, the LT3430

OUT

can be stabilized, provide good transient response and
maintain very low output ripple voltage using the follow­ing component values: (refer to the fi rst page of this data
sheet for component references) C

= 22nF, CF = 220pF and C

C

C

OUT

= 4.7µF, RC = 3.3k,

IN

= 100µF. See Application
Note 19 for further detail on techniques for proper loop
compensation.

INPUT CAPACITOR

Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the volt­age ripple this causes at the input of LT3430/LT3430-1
and force the switching current into a tight local loop,
thereby minimizing EMI. The RMS ripple current can be
calculated from:

IIVVVV

RIPPLE RMS

=

()

OUT OUT IN OUT IN

–/

()

2

Ceramic capacitors are ideal for input bypassing. At
200kHz (100kHz) switching frequency, the energy storage
requirement of the input capacitor suggests that values
in the range of 4.7µF to 20µF (10µF to 47µF) are suitable
for most applications. If operation is required close to the
minimum input required by the output of the LT3430, a
larger value may be required. This is to prevent excessive
ripple causing dips below the minimum operating voltage
resulting in erratic operation.

Depending on how the LT3430/LT3430-1 circuit is powered
up you may need to check for input voltage transients.

The input voltage transients may be caused by input voltage
steps or by connecting the LT3430/LT3430-1 converter to
an already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large surge
of current in the input leads that will store energy in the
parasitic inductance of the leads. This energy will cause the
input voltage to swing above the DC level of input power
source and it may exceed the maximum voltage rating of
input capacitor and LT3430/LT3430-1.

The easiest way to suppress input voltage transients is
to add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to criti­cally dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5Ω to 2Ω and capacitance
will fall in the range of 5µF to 50µF.

If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be taken
to ensure the ripple and surge ratings are not exceeded.
The AVX TPS and Kemet T495 series are surge rated. AVX
recommends derating capacitor operating voltage by 2:1
for high surge applications.

CATCH DIODE

Highest effi ciency operation requires the use of a Schottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a signifi cant reverse recovery time.

The use of so-called “ultrafast” recovery diodes is generally
not recommended. When operating in continuous mode,
the reverse recovery time exhibited by “ultrafast” diodes
will result in a slingshot type effect. The power internal
switch will ramp up V

current into the diode in an at-

IN

tempt to get it to recover. Then, when the diode has fi nally
turned off, some tens of nanoseconds later, the V

SW

node
voltage ramps up at an extremely high dV/dt, perhaps 5 to
even 10V/ns! With real world lead inductances, the V
node can easily overshoot the V

rail. This can result in

IN

SW

14

34301fa

APPLICATIONS INFORMATION

LT3430/LT3430-1

poor RFI behavior and if the overshoot is severe enough,
damage the IC itself.

The suggested catch diode (D1) is an International Recti­fi er 30BQ060 Schottky. It is rated at 3A average forward
current and 60V reverse voltage. Typical forward voltage
is 0.52V at 3A. The diode conducts current only during
switch off time. Peak reverse voltage is equal to regulator
input voltage. Average forward current in normal operation
can be calculated from:

IVV

OUT IN OUT

I

D AVG

This formula will not yield values higher than 3A with
maximum load current of 3A.

BOOST PIN

For most LT 3430 applications, the boost components are
a 0.68µF capacitor and a MMSD914TI diode. The anode
is typically connected to the regulated output voltage to
generate a voltage approximately V
the output stage. However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 3V of headroom throughout
this period to keep the switch fully saturated. If the output
voltage is less than 3.3V, it is recommended that an alternate
boost supply is used. For output voltages greater than 6V,
it is recommended to place a zener diode (D4; page 20)
in series with the Boost diode to set Boost-to-SW voltage
between 4V to 6V. This minimizes power loss within the
IC, improving maximum ambient temperature operation.
In addition, D4 minimizes Boost current overshoot during
power switch turn on to reduce noise within the regula­tor loop. For output voltages greater than the standard
demoboard 5V output, a location for D4 is provided.

A 0.68µF boost capacitor is recommended for most LT3430
applications. Almost any type of fi lm or ceramic capaci­tor is suitable, but the ESR should be <1Ω to ensure it
can be fully recharged during the off time of the switch.
The LT3430 capacitor value is derived from conditions of
4800ns on time, 75mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under

=

()

–

()

V

IN

above VIN to drive

OUT

less demanding conditions, but this will not improve cir­cuit operation or effi ciency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation. For the
LT3430-1 a 1.5µF boost capacitor is recommended.

SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT3430/LT3430-1. Typically, UVLO is used in situ­ations where the input supply is current limited, or has
a relatively high source resistance. A switching regulator
draws constant power from the source, so source cur­rent increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating at
source voltages where these problems might occur.

Threshold voltage for lockout is about 2.38V. A 5.5µA
bias current fl ows out of the pin at this threshold. The
internally generated current is used to force a default high
state on the shutdown pin if the pin is left open. When
low shutdown current is not an issue, the error due to this
current can be minimized by making R
shutdown current is an issue, R
but the error due to initial bias current and changes with
temperature should be considered.

Rk

=

10

LO

R

HI

VIN = Minimum input voltage

Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci­tance to the switching nodes are minimized. If high resistor
values are used, the shutdown pin should be bypassed with
a 1000pF capacitor to prevent coupling problems from the
switch node. If hysteresis is desired in the undervoltage
lockout point, a resistor R
node. Resistor values can be calculated from:

to 100k 25k suggested

RV V

()

LO IN

=

238 55

..µ

VR A

()

238

.

−

−

()

LO

FB

can be raised to 100k,

LO

can be added to the output

10k or less. If

LO

34301fa

15

LT3430/LT3430-1

APPLICATIONS INFORMATION

R

FB

LT3430/LTC3430-1

INPUT

C2

RV VV V

R

RRV V

LO IN OUT

=

HI

=

()

FB HI OUT

25k suggested for R

−+

238 1

[]

./

−

238 55

..

/

()

∆

LO

IN

R

HI

SHDN

R

LO

∆∆

()

RA

()

LO

+

µ

2.38V

µA

5.5

0.4V

GND

Figure 4. Undervoltage Lockout

VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if
input voltage drops below 12V and should not restart
unless input rises back to 13.5V. ∆V is therefore 1.5V and

= 12V. Let RLO = 25k.

V

IN

k

25 12 238155 1 15

R

=

HI

25 10 41

=

Rk k

=

116 5 1 5 387

FB

−+

../ .

[]

238 25 55

.– .

k

.

()

224

.

/.

()

()

kA

()

k

=

116

=

+

µ

SYNCHRONIZING

The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The LT3430 synchronizing range

L1

V

+

STANDBY

–

+

TOTAL
SHUTDOWN

–

SW

OUTPUT

+

C1

3430 F04

is equal to initial operating frequency up to 700kHz. This
means that minimum practical sync frequency is equal to
the worst-case high self-oscillating frequency (228kHz), not
the typical operating frequency of 200kHz. Caution should
be used when synchronizing above 265kHz because at
higher sync frequencies the amplitude of the internal slope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insuffi cient slope compensa­tion. Application Note 19 has more details on the theory
of slope compensation. The LT3430-1 synchronizing range
is from 125kHz to 250kHz (slope compensation loss oc­curs above 133kHz).

At power-up, when V

is being clamped by the FB pin (see

C

Figure 2, Q2), the sync function is disabled. This allows
the frequency foldback to operate in the shorted output
condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches

0.6V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.

16

34301fa

APPLICATIONS INFORMATION

V

LT3430/LT3430-1

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
effi ciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-

LT3430/

LT3430-1

HIGH

V

IN

GND1

Figure 5. High Speed Switching Path

FREQUENCY

CIRCULATING

PATH

ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a fl yback spike across the LT3430/
LT3430-1 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3430/LT3430-1 that may exceed its
absolute maximum rating. A ground plane should always
be used under the switcher circuitry to prevent interplane
coupling and overall noise.

L1

D1C3 C1

5

LOAD

3430 F05

2

SW

V

3

IN

LT3430/
LT3430-1

V

4

IN

SW

5

6 BOOST

PINS 3 AND 4

V

IN

ARE SHORTED TOGETHER.

SW PINS 2 AND 5 ARE ALSO

SHORTED TOGETHER (USING
AVAILABLE SPACE UNDERNEATH
THE DEVICE BETWEEN PINS AND

GND PLANE)

MINIMIZE

LT3430/LT3430-1

C3-D1 LOOP

GND

V

IN

L1

D1

2

3

4

C3

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

5

6

7

8

C2

GND GND1

SW

V

IN

LT3430/

V

IN

LT3430-1

SW

BOOST

GND

CONNECT TO

GROUND PLANE

GND

SOLDER THE EXPOSED PAD

C1

D2

16

SHDN

15

14

SYNC

13

FB

12

V

11

BIAS

GND

C

10

9

C

R1

FB

R

C

C

C

V

OUT

KELVIN SENSE

R2

C

F

KEEP FB AND VC COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS

(PIN 17) TO THE ENTIRE COPPER
GROUND PLANE UNDERNEATH
THE DEVICE. NOTE: THE BOOST
AND BIAS COPPER TRACES ARE
ON A SEPARATE LAYER FROM
THE GROUND PLANE

V

OUT

3430 F06

Figure 6. Suggested Layout

34301fa

17

LT3430/LT3430-1

APPLICATIONS INFORMATION

The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3430/
LT3430-1 pinout has been designed to aid in this. The
ground for these components should be separated from
the switch current path. Failure to do so will result in poor
stability or subharmonic like oscillation.

Board layout also has a signifi cant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, should be soldered
to a continuous copper ground plane under the LT3430/
LT3430-1 die. The FE package has an exposed pad (Pin

17) which is the best thermal path for heat out of the
package. Soldering the exposed pad to the copper ground
plane under the device will reduce die temperature and
increase the power capability of the LT3430/LT3430-1. Add­ing multiple solder fi lled feedthroughs under and around
the four corner pins to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will reduce any additional heating effects.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky
diodes have very high “Q” junction capacitance that can
ring for many cycles when excited at high frequency. If

total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V
or higher with a poor layout, potentially exceeding the

lute max switch voltage. The path around switch,

abso
catch diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT3430/LT3430-1 have special circuitry inside
which mitigates this problem, but negative voltages over

0.8V lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.

A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso­nate with the inductor to form damped ringing at 1MHz
to 10MHz. This ringing is not harmful to the regulator
and it has not been shown to contribute signifi cantly to
EMI. Any attempt to damp it with a resistive snubber will
degrade effi ciency.

18

LT3430

SW RISE SW FALL

2V/DIV

50ns/DIV

Figure 7. Switch Node Resonance Figure 8. Discontinuous Mode Ringing

3430 F07

10mV/DIV

0.2A/DIV

V

= 40V

IN

= 5V

V

OUT

L = 22µH

1µs/DIV

3430 F08

SWITCH NODE
VOLTAGE

INDUCTOR
CURRENT AT

= 0.1A

I

OUT

34301fa

APPLICATIONS INFORMATION

LT3430/LT3430-1

THERMAL CALCULATIONS

Power dissipation in the LT3430/LT3430-1 chip comes
from four sources: switch DC loss, switch AC loss, boost
circuit current, and input quiescent current. The follow­ing formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating effi ciency at light
load currents.

Switch loss:

RI V

P

SW

SW OUT OUT

=

2

()( )

V

IN

+

tIVf

EFF OUT IN

12(/ )

()()()

(Note: Switching losses are less for the LT3430-1 oper­ating at only 100kHz)

Boost current loss:

2

P

BOOST

VI

OUT OUT

=

36/

()

V

IN

Quiescent current loss:

PV V

=

0 0015 0 003..

Q IN OUT

()

+

()

Thermal resistance for the LT3430/LT3430-1 package is in­fl uenced by the presence of internal or backside planes.

TSSOP (Exposed Pad) Package: With a full plane under
the TSSOP package, thermal resistance will be about
45°C/W.

To calculate die temperature, use the proper thermal
resistance number for the desired package and add in
worst-case ambient temperature:

= TA + (θJA • P

T

J

TOT

)

When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power:

VV V I

( )( – )( )

P

DIODE

F IN OUT LOAD

=

V

IN

VF = Forward voltage of diode (assume 0.52V at 2A)

(. )( – )()

PW

DIODE

P

INDUCTOR

R

IND

052 40 5 2

==

.

091

40

= (I

LOAD

)2(R

IND

)

= Inductor DC resistance (assume 0.1Ω)

RSW = Switch resistance (≈0.15) hot

= Effective switch current/voltage overlap time

t

EFF

= (t
t
t
t

+ tf + tIr + tIf)

r

= (VIN/1.2)ns

r

= (VIN/1.1)ns

f

= tIf = (I

Ir

OUT

/0.2)ns

f = Switch frequency

Example: with V

015 2 5

.

P

PW

PW

( )()()

=

SW

...

=+=

008 072 08

5236

()

=

BOOST

=+=

(. ) (. ) .

40 0 0015 5 0 003 0 08

Q

= 40V, V

IN

2

+

90 10 1 2 2 4 0 200 10

40

2

()

40

()

/

=

004

= 5V and I

OUT

93

−

•/ •

W

.

()( )

()

= 2A:

OUT

()

Total power dissipation in the IC is given by:

P

TOT

= PSW + P

BOOST

+ P

Q

P

INDUCTOR

Only a portion of the temperature rise in the external
inductor and diode is coupled to the junction of the
LT3430. Based on empirical measurements, the thermal
effect on the LT3430 junction temperature due to power
dissipation in the external inductor and catch diode can
be calculated as:

∆T

J

Using the example calculations for LT3430 dissipation, the
LT3430 die temperature will be estimated as:

= TA + (θJA • P

T

J

With the TSSOP package (θ
temperature of 50°C:

= 50 + (45 • 0.92) + (5 • 1.31) = 98°C

T

J

Die temperature can peak for certain combinations of VIN,

and load current. While higher VIN gives greater

V

OUT

switch AC losses, quiescent and catch diode losses, a

= 0.8W + 0.04W + 0.08W = 0.92W

(2)2(0.1) = 0.4W

(LT3430) ≈ (P

DIODE

) + [5 • (P

TOT

+ P

INDUCTOR

= 45°C/W), at an ambient

JA

DIODE

)(5°C/W)

+ P

INDUCTOR

)]

34301fa

19

LT3430/LT3430-1

APPLICATIONS INFORMATION

lower VIN may generate greater losses due to switch DC
losses. In general, the maximum and minimum V

levels

IN

should be checked with maximum typical load current for
calculation of the LT3430/LT3430-1 die temperature. If a
more accurate die temperature is required, a measure­ment of the SYNC pin resistance (to GND) can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.5V at the pin and monitoring the
pin current over temperature in an oven. This should be
done with minimal device power (low V

= 0V)) in order to calibrate SYNC pin resistance with

(V

C

and no switching

IN

ambient (oven) temperature.

Note: Some of the internal power dissipation in the IC,
due to BOOST pin voltage, can be transferred outside
of the IC to reduce junction temperature, by increasing
the voltage drop in the path of the boost diode D2 (see
Figure 9). This reduction of junction temperature inside
the IC will allow higher ambient temperature operation for
a given set of conditions. BOOST pin circuitry dissipates
power given by:

VI V

•/•36

()

P

BOOST Pin =

DISS

OUT SW C

V

IN

2

Typically VC2 (the boost voltage across the capacitor C2)
equals V

. This is because diodes D1 and D2 can be

OUT

considered almost equal, where:

V

C2

= V

OUT

– V

FD2

– (–V

FD1

) = V

OUT

section, the value of C2 was designed for a 0.7V droop in

= V

V

C2

. Hence, an output voltage as low as 4V would

DROOP

still allow the minimum 3.3V for the boost function using
the C2 capacitor calculated. If a target output voltage of
12V is required, however, an excess of 8V is placed across
the boost capacitor which is not required for the boost
function but still dissipates additional power.

What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.

Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by:

12 2 36 12

•/ •

PW

BOOST

()

=

20

=

04

.

If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :

12 2 36 5

•/ •

PW

BOOST

()

=

20

=

0 167

.

For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be, T(ambient) sav-

D2 D4

Hence the equation used for boost circuitry power dissi­pation given in the previous Thermal Calculations section
is stated as:

P

DISS BOOST

•/

VI

OUT SW

36

()

V

IN

•=

V

OUT()

Here it can be seen that boost power dissipation increases
as the square of V
V

C2

below V

to save power dissipation by increasing the

OUT

. It is possible, however, to reduce

OUT

voltage drop in the path of D2. Care should be taken that

does not fall below the minimum 3.3V boost voltage

V

C2

required for full saturation of the internal power switch.
For output voltages of 5V, V
switch turn on, V

will fall as the boost capacitor C2 is

C2

is approximately 5V. During

C2

dicharged by the BOOST pin. In the previous BOOST Pin

20

D2

BOOST

V

IN

V

IN

C3

SHDN

SYNC

GND

Figure 9. BOOST Pin, Diode Selection

LT3430/

LT3430-1

R

C

C

C

SW

BIAS

V

C

FB

C

C2

D1

F

L1

R1

R2

3430 F09

V

OUT

+

C1

34301fa

APPLICATIONS INFORMATION

LT3430/LT3430-1

ings = 0.233W • 45°C/W = 11°C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of
the zener should be considered to ensure minimum V
exceeds 3.3V + V

DROOP

.

C2

Input Voltage vs Operating Frequency Considerations

The absolute maximum input supply voltage for the LT3430/
LT3430-1 is specifi ed at 60V. This is based solely on internal
semiconductor junction breakdown effects. Due to internal
power dissipation, the actual maximum V

achievable in

IN

a particular application may be less than this.

A detailed theoretical basis for estimating internal power
loss is given in the section, Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switching
loss is also proportional to the square of input voltage.
For example, while the combination of V
= 5V at 2A and f
simultaneously raising V

= 200kHz may be easily achievable,

OSC

to 60V and f

IN

IN

OSC

= 40V, V

to 700kHz is

OUT

not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the result­ing increase in internal dissipation is of insuffi cient time
duration to raise die temperature signifi cantly.

A second consideration is controllability. A potential limita­tion occurs with a high step-down ratio of V

IN

to V

OUT

, as
this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:

VV

+

ON

OUT F

=

Vf

()

IN OSC

min t

where:

= input voltage

V

IN

V
V
f

= output voltage

OUT

= Schottky diode forward drop

F

= switching frequency

OSC

A potential controllability problem arises if the LT3430/
LT3430-1 are called upon to produce an on time shorter
than it is able to produce. Feedback loop action will lower
then reduce the V

control voltage to the point where

C

some sort of cycle-skipping or odd/even cycle behavior
is exhibited.

In summary:

1. Be aware that the simultaneous requirements of high
V

IN

, high I

and high f

OUT

may not be achievable in

OSC

practice due to internal dissipation. The Thermal Con­siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.

2. The simultaneous requirements of high V
high f

can result in an unacceptably short minimum

OSC

IN

, low V

OUT

and

switch on time. Cycle skipping and/or odd/even cycle
behavior will result although correct output voltage is
usually maintained. The LT3430-1 100kHz switching
frequency will allow higher V

IN/VOUT

ratios without

pulse skipping.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency
response, the following should be remembered—the
worse the board layout, the more diffi cult the circuit will
be to stabilize. This is true of almost all high frequency
analog circuits, read the Layout Considerations section
fi rst. Common layout errors that appear as stability prob­lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V

compensation

C

to a ground track carrying signifi cant switch current. In
addition, the theoretical analysis considers only fi rst
order non-ideal component behavior. For these reasons,
it is important that a fi nal stability check is made with
production layout and components.

The LT3430/LT3430-1 use current mode control. This al­leviates many of the phase shift problems associated with
the inductor. The basic regulator loop is shown in Figure

10. The LT3430/LT3430-1 can be considered as two g

m

blocks, the error amplifi er and the power stage.

Figure 11 shows the overall loop response. At the VC
pin, the frequency compensation components used are:

= 3.3k, CC = 0.022µF and CF = 220pF. The output

R

C

capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ. LT3430-1 uses two of these
capacitors in parallel.

The ESR of the tantalum output capacitor provides a use­ful zero in the loop frequency response for maintaining

34301fa

21

LT3430/LT3430-1

APPLICATIONS INFORMATION

stability. This ESR, however, contributes signifi cantly to
the ripple voltage at the output (see Output Ripple Voltage
in the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac­ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases where,
even with the tantalum output capacitor, an additional
zero is required in the loop to increase phase margin for
improved transient response.

A zero can be added into the loop by placing a resistor (R
at the V
C

C

pin in series with the compensation capacitor,

C

, or by placing a capacitor (CFB) between the output

)

C

and the FB pin.

When using R
First, the combination of output capacitor ESR and R

, the maximum value has two limitations.

C

C

may stop the loop rolling off altogether. Second, if the
loop gain is not rolled off suffi ciently at the switching
frequency, output ripple will perturb the V

pin enough to

C

cause unstable duty cycle switching similar to subharmonic
oscillations. If needed, an additional capacitor (C
added across the R
to further suppress V

network from the VC pin to ground

C/CC

ripple voltage.

C

) can be

F

With a tantalum output capacitor, the LT3430/LT3430-1
already includes a resistor (R
at the V

LT3430/LTC3430-1

GND

pin (see Figures 10 and 11) to compensate the

C

CURRENT MODE

POWER STAGE

= 2mho

g

m

ERROR

AMPLIFIER

–

=

g

m

2000µmho

R

O

200k

V

C

R

C

C

C

+

1.22V

C

F

) and fi lter capacitor (CF)

C

V

SW

C

R1

FB

FB

R

LOAD

R2

OUTPUT

TANTALUM

ESR

+

C1

loop over the entire V
skipping for high V

IN

range (to allow for stable pulse

IN

-to-V

ratios ≥ 10). A ceramic output

OUT

capacitor can still be used with a simple adjustment to the
resistor R

for stable operation (see Ceramic Capacitors

C

section for stabilizing LT3430). If additional phase margin
is required, a capacitor (C

) can be inserted between the

FB

output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can create
unacceptably large negative transients on the FB pin.

For V

IN

-to-V

ratios < 10, higher loop bandwidths are

OUT

possible by readjusting the frequency compensation
components at the V

pin.

C

When checking loop stability, the circuit should be operated
over the application’s full voltage, current and tempera­ture range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes
19 and 76.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for example,
a battery powered device with a wall adapter input, the
output of the LT3430/LT3430-1 can be held up by the
backup supply with the LT3430/LT3430-1 input discon­nected. In this condition, the SW pin will source current
into the V

pin. If the ⎯S⎯H⎯D⎯N pin is held at ground, only the

IN

shut down current of 30µA will be pulled via the SW pin

⎯S⎯H⎯D⎯

from the second supply. With the

80

CERAMIC

ESL

3430 F10

60

40

20

GAIN (dB)

PHASE

0

C1

–20

–40

10

V
V
I

LOAD

C

GAIN

FREQUENCY (Hz)

= 42V

IN

= 5V

OUT

= 1A

= 100µF, 10V, 0.1Ω

OUT

1k 10k 1M100 100k

N pin fl oating, the

= 22nF

C

= 220pF

F

3430 F11

RC = 3.3k
C
C

180

150

120

PHASE (DEG)

90

60

30

0

22

Figure 10. Model for Loop Response Figure 11. Overall Loop Response

34301fa

APPLICATIONS INFORMATION

LT3430/LT3430-1

LT3430/LT3430-1 will consume their quiescent operating
current of 1.5mA. The V

pin will also source current to

IN

any other components connected to the input line. If this
load is greater than 10mA or the input could be shorted to
ground, a series Schottky diode must be added, as shown
in Figure 12. With these safeguards, the output can be held
at voltages up to the V

absolute maximum rating.

IN

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
confi guration with the addition of R3, R4, C

and Q1. As

SS

the output starts to rise, Q1 turns on, regulating switch
current via the V

pin to maintain a constant dv/dt at the

C

D3

REMOVABLE

INPUT

30BQ060

54k

25k

C3

4.7µF

V

IN

SHDN

SYNC

GND

0.022µF

BOOST

LT3430

R

C

3.3k
C

C

SW

BIAS

V

FB

C

output. Output rise time is controlled by the current through

defi ned by R4 and Q1’s VBE. Once the output is in

C

SS

regulation, Q1 turns off and the circuit operates normally.
R3 is transient protection for the base of Q1.

Rise Time

()( )( )

=

SS OUT

V

BE

4

RC V

Using the values shown in Figure 10,

Rise Time ms=

47 10 15 10 5

()( )

39

••

07

–

()

=

5

.

The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.

D2

MMSD914TI

C2

0.68µF
33µH

C

F

220pF

D1
30BQ060

R1

15.4k

R2

4.99k

5V, 2A

+

C1
100µF
10V

ALTERNATE

SUPPLY

3430 F12

Figure 12. Dual Source Supply with 25µA Reverse Leakage

D2

MMSD914TI

INPUT

40V

C3

4.7µF
50V
CER

BOOST BIAS

V

IN

LT3430

SHDN

SYNC

GND

R

C

3.3k
C

C

0.022µF

V

SW

C2

0.68µF

FB

C

C

F

220pF

D1
30BQ060
OR B250A

Q1

L1

33µH

+

C1

100µF

10V

C

SS

R3

15nF

2k

R4
47k

L1: CDRH104R-220M

Figure 13. Buck Converter with Adjustable Soft-Start

R1

15.4k

R2

4.99k

3430 F13

OUTPUT
5V
2A

34301fa

23

LT3430/LT3430-1

APPLICATIONS INFORMATION

DUAL OUTPUT SEPIC CONVERTER

The circuit in Figure 14 generates both positive and negative
5V outputs with a single piece of magnetics. The two induc­tors shown are actually just two windings on a standard
Coiltronics inductor. The topology for the 5V output is a
standard buck converter. The –5V topology would be a
simple fl yback winding coupled to the buck converter if
C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a fl yback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current fl ows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to fl ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur­rents, see Design Note 100.

POSITIVE-TO-NEGATIVE CONVERTER

The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback
signal because the LT3430/LT3430-1 accepts only posi­tive feedback signals. The ground pin must be tied to the
regulated negative output. A resistor divider to the FB pin
then provides the proper feedback voltage for the chip.

The following equation can be used to calculate maximum
load current for the positive-to-negative converter:

⎡

I

P

⎢

I

MAX

⎣

=

VV

()( )

–

IN OUT

VVfL

()()()

2

(–.)()

+

OUT IN

VV VV

++

OUT IN OUT F

⎤

VV

()(–.)

OUT IN

⎥
⎦

015

015

IP = Maximum rated switch current

= Minimum input voltage

V

IN

= Output voltage

V

OUT

= Catch diode forward voltage

V

F

0.15 = Switch voltage drop at 3A

Example: with V

= 0.52V, IP = 3A: I

V

F

IN(MIN)

MAX

= 5.5V, V

= 0.6A.

= 12V, L = 10µH,

OUT

V

IN

7.5V TO 60V

C3

4.7µF

100V

CERAMIC

GND

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS #CTX25-4A

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 30BQ060

V

IN

SHDN

SYNC

GND

0.022µF

BOOST

LT3430

R

C

3.3k
C

C

Figure 14. Dual Output SEPIC Converter

SW

V

0.68µF

FB

C

100µF

TANT

C2

C

F

220pF

C4

10V

D2

MMSD914TI

L1A*

25µH

R1

15.4k

R2

4.99k

D1

L1B*

D3

100µF

10V TANT

V

OUT

5V

+

C1
100µF
10V TANT

++

C5

V

OUT

†

3430 F14

–5V

34301fa

24

APPLICATIONS INFORMATION

†

L1*
10µH

D4
7V

R1

36.5k

R2

4.12k

+

30BQ015

C1
100µF
16V TANT

OUTPUT**
–12V, 0.5A

D3

3430 F15

D2

MMSD914TI

C2

INPUT

5.5V TO
44V

C3

4.7µF

100V

CER

* INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

Figure 15. Positive-to-Negative Converter

V

IN

GND

BOOST

LT3430

C

F

V

SW

FB

V

C

R

0.68µF

D1
30BQ060

C

C

C

INDUCTOR VALUE

The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be
used, but in some cases (lower output load currents) it
may give a value that creates unnecessarily high output
ripple voltage.

The diffi culty in calculating the minimum inductor size
needed is that you must fi rst decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 3A. The fi rst step is to
use the following formula to calculate the load current above
which the switcher must use continuous mode. If your
load current is less than this, use the discontinuous mode
formula to calculate minimum inductor needed. If load
current is higher, use the continuous mode formula.

Output current where continuous mode is needed:

22

VI

()()

I

>

CONT

VV VV V

()( )

4

IN OUT IN OUT F

IN P

+++

Minimum inductor discontinuous mode:

()()

VI

2

=

OUT OUT

2

()( )

fI

P

L

MIN

LT3430/LT3430-1

Minimum inductor continuous mode:

()( )

VV

L

=

MIN

()( ) –

21

++

fV V I I

IN OUT P OUT

For a 40V to –12V converter using the LT3430/LT3430­1 with peak switch current of 3A and a catch diode of

0.52V:

()()

IA

=

CONT

()( .)

440124012052

40 3

+++

For a load current of 0.5A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:

()(.)

LH

MIN

212 05

==µ

(•)()

200 10 3

32

In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
10µH for this application.

Ripple Current in the Input and Output Capacitors

Positive-to-negative converters have high ripple current in
the input capacitor. For long capacitor lifetime, the RMS
value of this current must be less than the high frequency
ripple current rating of the capacitor. The following formula
will give an approximate value for RMS ripple current. This

formula assumes continuous mode and large inductor
value. Small inductors will give somewhat higher ripple

current, especially in discontinuous mode. The exact for­mulas are very complex and appear in Application Note
44, pages 29 and 30. For our purposes here I have simply
added a fudge factor (ff). The value for ff is about 1.2 for
higher load currents and L ≥15µH. It increases to about

2.0 for smaller inductors at lower load currents.

Capacitor I ff I

= ()( )

RMS OUT

ff = 1.2 to 2.0

IN OUT

⎡
⎢

⎣

22

.

67

V

OUT

V

IN

⎛

()

+

VV

OUT F

⎜
⎝

=

1 148

V

IN

.

⎤

⎞
⎟

⎥

⎠

⎦

The output capacitor ripple current for the positive-to­negative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak

34301fa

25

LT3430/LT3430-1

APPLICATIONS INFORMATION

value equal to the peak-to-peak triangular waveform of the
inductor. The low output ripple design in Figure 15 places
the input capacitor between V

and the regulated negative

IN

output. This placement of the input capacitor signifi cantly
reduces the size required for the output capacitor (versus
placing the input capacitor between V

and ground).

IN

The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:

•

DC V

I

=

P-P

==

DC Duty Cycle

I RMS

COUT

IN

•

fL

()

I

=

+

VV

OUT F

++

VVV

OUT IN F

P-P

12

The output ripple voltage for this confi guration is as low
as the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the

ESR of the chosen capacitor (see Output Ripple Voltage
in Applications Information).

Diode Current

Average diode current is equal to load current. Peak diode
current will be considerably higher.

Peak diode current:

Continuous Mode

()()()

VV

+

OUT

IN OUT

V

IN

I

Discontinuous Mode

=

VV

+

IN OUT

()()( )

2

LfV V

=

+

IN OUT

()( )

2

IV

OUT OUT

()()

Lf

Keep in mind that during start-up and output overloads,
average diode current may be much higher than with nor­mal loads. Care should be used if diodes rated less than
1A are used, especially if continuous overload conditions
must be tolerated.

TYPICAL APPLICATION

V

IN

5.5V*
TO 60V

4.7µF
100V

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY

3, 4

15

ONOFF

14

1, 8, 9, 16

3.3V, 2A Buck Converter

6

V

IN

LT3430-1

SHDN

SYNC

GND

0.022µF

BOOST

3.3k

SW

BIAS

V

C

FB

2, 5

10

12

11

220pF

3430 F16

1.5µF

30BQ060

MMSD914TI

68µH

20.5k

12.1k

+

100µF 10V
SOLID
TANTALUM
2 IN PARALLEL

V

3.3V
2A

OUT

26

34301fa

PACKAGE DESCRIPTION

3.58

(.141)

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

16 1514 13 12 11

4.90 – 5.10*
(.193 – .201)

3.58

(.141)

LT3430/LT3430-1

10 9

6.60 ±0.10

4.50 ±0.10

RECOMMENDED SOLDER PAD LAYOUT

0.09 – 0.20

(.0035 – .0079)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

0.45 ±0.05

0.65 BSC

4.30 – 4.50*
(.169 – .177)

0.50 – 0.75

(.020 – .030)

MILLIMETERS

(INCHES)

2.94

(.116)

1.05 ±0.10

1345678

2

0.25
REF

0° – 8°

0.65

(.0256)

BSC

0.195 – 0.30

(.0077 – .0118)

TYP

4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE

2.94

(.116)

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

FE16 (BB) TSSOP 0204

6.40

(.252)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

34301fa

27

LT3430/LT3430-1

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Burst Mode is a registered trademark of Linear Technology Corporation.

VIN: 7.3V to 45V/64V, V
TO220-5/7

VIN: 7.3V to 45V/64V, V
TO220-5/7

VIN: 7.4V to 60V, V

VIN: 3V to 25V, V

VIN: 5.5V to 60V, V

VIN: 3V to 25V, V

VIN: 7.4V to 40V, V

VIN: 3V to 25V, V

VIN: 5.5V to 60V, V

: 3.3V to 60V, V

V

IN

: 1.5V to 80V, V

IN

VIN: 2.5V to 5.5V, V

VIN: 2.5V to 5.5V, V

VIN: 2.3V to 5.5V, V

VIN: 5.5V to 60V, V

VIN: 4V to 60V, V

V

: 4V to 36V, V

IN

: 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7,

OUT(MIN)

: 2.21V, IQ: 8.5mA, ISD: 10µA DD-5/7,

OUT(MIN)

: 1.24V, IQ: 3.2mA, ISD: 2.5µA, S8

OUT(MIN)

: 1.20V, IQ: 1mA, ISD: 15µA, S8, TSSOP16E

OUT(MIN)

: 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E

OUT(MIN)

: 1.20V, IQ: 1mA, ISD: 6µA, MS8/E

OUT(MIN)

: 1.24V, IQ: 3.2mA, ISD: 30µA, N8, S8

OUT(MIN)

: 1.2V, IQ: 3.8mA, ISD: <1µA, TSSOP16E

OUT(MIN)

: 1.20V, IQ: 2.5mA, ISD: 25µA, TSSOP16/E

OUT(MIN)

: 1.20V, IQ: 100µA, ISD: <1µA, TSSOP16/E

OUT(MIN)

: 1.28V, IQ: 30µA, ISD: <1µA, MSE8

OUT(MIN)

: 0.6V, IQ: 40µA, ISD: <1µA, MS10E

OUT(MIN)

: 0.8V, IQ: 60µA, ISD: <1µA, TSSOP16E

OUT(MIN)

: 0.8V, IQ: 64µA, ISD: <1µA, TSSOP20E

OUT(MIN)

: 1.20V, IQ: 2.5mA, ISD: 30µA, TSSOP16E

OUT(MIN)

: 3.3V to 20V, IQ: 100µA, ISD: <1µA, TSSOP16E

OUT(MIN)

: 0.8V, IQ: 670µA, ISD: 20µA, QFN-32, SSOP-28

OUT(MIN)

28

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

34301fa

LT 0107 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2006