LINEAR TECHNOLOGY LT1963A Technical data
Application Note 104
October 2006
Load Transient Response Testing for Voltage Regulators
Practical Considerations for Testing and Evaluating Results
Jim Williams
INTRODUCTION
Semiconductor memory, card readers, microprocessors,
disc drives, piezoelectric devices and digitally based systems furnish transient loads that a voltage regulator must
service. Ideally, regulator output is invariant during a load
transient. In practice, some variation is encountered and
becomes problematic if allowable operating voltage tolerances are exceeded. This mandates testing the regulator
and its associated support components to verify desired
performance under transient loading conditions. Various
methods are employable to generate transient loads, allowing observation of regulator response.
Basic Load Transient Generator
Figure 1 diagrams a conceptual load transient generator.
The regulator under test drives DC and switched resistive
loads, which may be variable. The switched current and
+E
REGULATOR
INPUT SUPPLY
REGULATOR
UNDER TEST
DC LOAD
REGULATOR
CURRENT
MONITOR
R
SWITCHED
LOAD
LOAD
SWITCH
I
SWITCHED
VOLTAGE
MONITOR
E
REGULATOR
=
R
SWITCHED LOAD
AN104 F01
output voltage are monitored, permitting comparison of
the nominally stable output voltage versus load current
under static and dynamic conditions. The switched current
is either on or off; there is no controllable linear region.
Figure 2 is a practical implementation of the load transient
generator. The voltage regulator under test is augmented
by capacitors which provide an energy reservoir, similar to
a mechanical fl ywheel, to aid transient response. The size,
composition and location of these capacitors, particularly
, has a pronounced effect on transient response and
C
OUT
overall regulator stability.
1
Circuit operation is straightforward. The input pulse triggers the LTC1693 FET driver to
switch Q1, generating a transient load current out of the
Note 1. See Appendix A, “Capacitor Parasitic Effects on Load Transient
Response” and Appendix B, “Output Capacitors and Stability” for extended
discussion.
+E
REGULATOR
INPUT SUPPLY
PULSE
INPUT
REGULATOR
UNDER TEST
C
IN
+10
VC2
DC LOAD
O1
O2
G1
+
10µF
VC1
I1
LTC1693-1
I2
G2
REGULATOR
C
OUT
R
LOAD
Q1
IRLZ24
TO AC-COUPLED
OSCILLOSCOPE
TEKTRONIX P-6042 CURRENT
PROBE OR EQUIVALENT
MINIMIZE
INDUCTANCE
E
I
SWITCHED
REGULATOR
=
R
SWITCHED LOAD
AN104 F02
CH1
CH2
Figure 1. Conceptual Regulator Load Tester Includes Switched
and DC Loads and Voltage/Current Monitors. Resistor Values Set
DC and Switched Load Currents. Switched Current is Either On or
Off; There is No Controllable Linear Region
Figure 2. A Practical Regulator Load Tester. FET Driver and Q1
Switch R
. Oscilloscope Monitors Current Probe Output and
LOAD
Regulator Response
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
an104f
AN104-1
Application Note 104
regulator. An oscilloscope monitors the instantaneous load
voltage and, via a “clip-on” wideband probe, current. The
circuit’s load transient generating capabilities are evaluated
in Figure 3 by substituting an extraordinarily low impedance power source for the regulator. The combination of
a high capacity power supply, low impedance connections and generous bypassing maintains low impedance
across frequency. Figure 4 shows Figure 3 responding to
the LTC1693-1 FET driver (Trace A) by cleanly switching
1A in 15ns (Trace B). Such speed is useful for simulating
many loads but has restricted versatility. Although fast,
the circuit cannot emulate loads between the minimum
and maximum currents.
+E
REGULATOR
INPUT SUPPLY
CONTROL
INPUT
REGULATOR
UNDER TEST
+
–
CONTROL
AMPLIFIER
REGULATOR
CURRENT
MONITOR
Q1A1
CURRENT
SENSE RESISTOR
I =
R
CURRENT SENSE
E
INPUT
VOLTAGE
MONITOR
AN104 F05
Figure 5. Conceptual Closed Loop Load Tester. A1 Controls Q1’s
Source Voltage, Setting Regulator Output Current. Q1’s Drain
Current Waveshape is Identical to A1 Input, Allowing Linear
Control of Load Current. Voltage and Current Monitors are as in
Figure 1
HEWLETT-PACKARD
6012A POWER SUPPLY
MINIMIZE
INDUCTANCE
300ns
5V
LOAD TESTER
(FIGURE 2)
PULSE
–
+
3V
+ + + +
DC LOAD
(OPTIONAL)
VOLTAGE MONITOR TO
AC-COUPLED OSCILLOSCOPE
2200µF*
EACH
TEKTRONIX P-6042 CURRENT
PROBE OR EQUIVALENT
*SANYO OSCON
AN104 F03
CH1
CH2
Figure 3. Substituting Well Bypassed, Low Impedance Power
Supply for Regulator Allows Determining Load Tester’s
Response Time
A = 5V/DIV
B = 0.5A/DIV
HORIZ = 100ns/DIV
AN104 F04
Figure 4. Figure 2’s Circuit Responds to FET Driver Output
(Trace A), Switching a 1A Load (Trace B) in 15ns
Closed Loop Load Transient Generators
Figure 5’s conceptual closed loop load transient generator
linearly controls Q1’s gate voltage to set instantaneous
transient current at any desired point, allowing simulation
of nearly any load profi le. Feedback from Q1’s source to the
A1 control amplifi er closes a loop around Q1, stabilizing its
operating point. Q1’s current assumes a value dependant
on the control input voltage and the current sense resistor over a very wide bandwidth. Note that once A1 biases
to Q1’s conductance threshold, small variations in A1’s
output result in large current changes in Q1’s channel.
As such, large output excursions are not required from
A1; its small signal bandwidth is the fundamental speed
limitation. Within this restriction, Q1’s current waveform
is identically shaped to A1’s control input voltage, allowing linear control of load current. This versatile capability
permits a wide variety of simulated loads.
FET Based Circuit
Figure 6, a practical incarnation of a FET based closed loop
load transient generator, includes DC bias and waveform
inputs. A1 must drive Q1’s high capacitance gate at high
frequency, necessitating high peak A1 output currents and
attention to feedback loop compensation. A1, a 60MHz
current feedback amplifi er, has an output current capacity
exceeding 1A. Maintaining stability and waveform fi delity at high frequency while driving Q1’s gate capacitance
necessitates settable gate drive peaking components, a
damper network, feedback trimming and loop peaking
adjustments. A DC trim, also required, is made fi rst. With
no input applied, trim the “1mV adjust” for 1mV DC at
Q1’s source. The AC trims are made utilizing Figure 7’s
arrangement. Similar to Figure 3, this “brick wall” regulated
source provides minimal ripple and sag when step loaded
by the load transient generator. Apply the inputs shown
and trim the gate drive, feedback and loop peaking adjustments for the cleanest, square cornered response on the
oscilloscope’s current probe equipped channel.
an104f
AN104-2
DC BIAS
0 – 10V = 0 – 1A
WAVEFORM INPUT
0 – 1V = 0 – 1A
100k
51Ω
–
+
A2
LT1006
866Ω*
REGULATOR
INPUT
SUPPLY
8.16k*
100Ω*
+
A1
LT1210
–
IN OUT
C
IN
+15
C
0.01µF
–15
REGULATOR
UNDER TEST
GND
GATE DRIVE PEAKING
100Ω
Application Note 104
+E
2.5Ω
10µF
CERAMIC
REGULATOR
C
OUT
VOLTAGE MONITOR TO
AC-COUPLED OSCILLOSCOPE
TEKTRONIX P-6042 CURRENT
Q1
IRLZ24
PROBE OR EQUIVALENT
MINIMIZE
INDUCTANCE
CH1
CH2
+15
10k
–15
+1mV
ADJUST
120k
100Ω
1k LOOP PEAKING
68pF
560Ω
1k
FEEDBACK
AN104 F06
0.1Ω**
= FAIR-RITE
#2743001112
= 1% METAL FILM RESISTOR*
= VISHAY WSL2512.5%**
Figure 6. Detailed Closed Loop Load Tester. DC Level and Pulse Inputs Feed A1 to Q1 Current Sinking Regulator Load. Q1’s Gain
Allows Small A1 Output Swing, Permitting Wide Bandwidth. Damper Network, Feedback and Peaking Trims Optimize Edge Response
HEWLETT-PACKARD
0.5V, (0.5A)
MINIMIZE
INDUCTANCE
250ns TO 500ns
100kHz
CLOSED LOOP
LOAD TESTER
(FIGURES 6, 8)
1V, (100mA)
6012A POWER SUPPLY
+ + + +
PULSE
DC BIAS
–
+
VOLTAGE MONITOR TO
AC-COUPLED OSCILLOSCOPE
3V
TEKTRONIX P-6042 CURRENT
*SANYO OSCON
2200µF*
EACH
PROBE OR EQUIVILENT
CH1
CH2
AN104 F07
Figure 7. Closed Loop Load Tester Response Time is Determined as in Figure 3. “Brick Wall” Input Provides Low Impedance Source
Bipolar Transistor Based Circuit
Figure 8 considerably simplifi es the previous circuit’s loop
dynamics and eliminates all AC trims. The major trade-off
is a 2x speed reduction. The circuit is similar to Figure 6,
except that Q1 is a bipolar transistor. The bipolar’s greatly
reduced input capacitance allows A1 to drive a more benign
load. This permits a lower output current amplifi er and
eliminates the dynamic trims required to accommodate
Figure 6’s FET gate capacitance. The sole trim is the “1mV
adjust” which is accomplished as described before2. Aside
from the 2x speed reduction the bipolar transistor also introduces a 1% output current error due to its base current.
Note 2. This trim may be eliminated at some sacrifi ce in circuit complexity.
See Appendix D, “A Trimless Closed Loop Transient Load Tester”.
Q2 is added to prevent excessive Q1 base current when
the regulator supply is not present. The diode prevents
reverse base bias under any circumstances.
Closed Loop Circuit Performance
Figures 9 and 10 show the two wideband circuits’ operation.
The FET based circuit (Figure 9) only requires a 50mV A1
swing (Trace A) to enforce Trace B’s fl at-topped current
pulse with 50ns edges through Q1. Figure 10 details the
bipolar transistor based circuit’s performance. Trace A,
taken at Q1’s base, rises less than 100mV causing Trace
B’s clean 1A current conduction through Q1. This circuit’s
100ns edges, about 2x slower than the more complex
FET based version, are still fast enough for most practical
transient load testing.
an104f
AN104-3
Application Note 104
+E
REGULATOR
C
OUT
AN104 F08
Q1
D44H2
0.1Ω**
VOLTAGE MONITOR TO
AC-COUPLED OSCILLOSCOPE
TEKTRONIX P-6042 CURRENT
PROBE OR EQUIVALENT
MINIMIZE
INDUCTANCE
= 1% METAL FILM RESISTOR*
= VISHAY WSL2512.5%**
DC BIAS
0 – 10V = 0 – 1A
100k
–
LT1006
+
A2
866Ω*
REGULATOR
INPUT
SUPPLY
8.16k*
C
IN
1M
+15
REGULATOR
IN OUT
UNDER TEST
GND
Q2
VN2222L
+
SD
WAVEFORM INPUT
0 – 1V = 0 – 1A
51Ω
100Ω*
MINIMIZE CAPACITANCE
+15
10k
+1mV
ADJUST
–15
120k
A1
LT1206
–
–15
C
MUR11O
NC
560Ω
Figure 8. Figure 6 Implemented with Bipolar Transistor. Q1’s Reduced Input Capacitance Simplifi es Loop Dynamics, Eliminating
Compensation Components and Trims. Trade Off is 2x Speed Reduction and Base Current Induced 1% Error
CH1
CH2
A = 0.05V/DIV
AC-COUPLED
ON 2.5VDC
B = 0.5A/DIV
AC-COUPLED
ON 0.1ADC
HORIZ = 50ns/DIV
AN104 F09
Figure 9. Figure 6’s Closed Loop Load Tester Step Response
(Q1 Current is Trace B) is Quick and Clean, Showing 50ns Edges
and Flat Top. A1’s Output (Trace A) Swings Only 50mV, Allowing
Wideband Operation. Trace B’s Presentation is Slightly Delayed
Due to Voltage and Current Probe Time Skew
Load Transient Testing
The previously discussed circuits permit rapid and thorough
voltage regulator load transient testing. Figure 11 uses
Figure 6’s circuit to evaluate an LT1963A linear regulator.
Figure 12 shows regulator response (Trace B) to Trace A’s
asymmetrically edged input pulse. The ramped leading
edge, within the LT1963A’s bandwidth, results in Trace
B’s smooth 10mV
excursion. The fast trailing edge,
P-P
well outside LT1963A passband, causes Trace B’s abrupt
disruption. C
output level and a 75mV
cannot supply enough current to maintain
OUT
spike results before the regula-
P-P
tor resumes control. In Figure 13, a 500mA peak-to-peak
500kHz noise load, emulating a multitude of incoherent
A = 0.05V/DIV
AC-COUPLED
ON 0.6VDC
B = 0.5A/DIV
AC-COUPLED
ON 0.1ADC
HORIZ = 100ns/DIV
AN104 F10
Figure 10. Figure 8’s Bipolar Output Load Tester Response is
2x Slower than FET Version, but Circuit is Less Complex and
Eliminates Compensation Trims. Trace A is A1’s Output, Trace B
is Q1’s Collector Current
loads, feeds the regulator in Trace A. This is within regulator bandwidth and only 6mV
of disturbance appears
P-P
in Trace B, the regulator output. Figure 14 maintains the
same conditions, except that noise bandwidth is increased
to 5MHz. Regulator bandwidth is exceeded, resulting in
over 50mV
error, an 8x increase.
P-P
Figure 15 shows what happens when a 0.2A DC biased,
swept DC-5MHz, 0.35A load is presented to the regulator.
The regulator’s rising output impedance versus frequency
results in ascending error as frequency scales. This information allows determination of regulator output impedance
versus frequency.
an104f
AN104-4
DC BIAS
0 – 10V = 0 – 1A
WAVEFORM INPUT
0 – 1V = 0 – 1A
–
A2
LT1006
+
100k
866Ω*
51Ω
MINIMIZE CAPACITANCE
+5V
8.16k*
100Ω*
10µF
+
A1
LT1210
–
+15
–15
LT1963A
IN
3.3V
SD
GND
GATE DRIVE PEAKING
C
0.01µF
OUT
SENSE
100Ω
Application Note 104
3.3V
VOLTAGE MONITOR TO
10µF
Q1
IRLZ24
2.5Ω
10µF
CERAMIC
AC-COUPLED OSCILLOSCOPE
TEKTRONIX P-6042 CURRENT
PROBE OR EQUIVALENT
MINIMIZE
INDUCTANCE
CH1
CH2
+15
10k
–15
+1mV
ADJUST
120k
100Ω
1k LOOP PEAKING
68pF
560Ω 1k
FEEDBACK
AN104 F11
0.1Ω**
= FAIR-RITE
#2743001112
= 1% METAL FILM RESISTOR*
= VISHAY WSL2512.5%**
Figure 11. Closed Loop Load Tester Shown with LT1963A Regulator. Load Testing for a Variety of Current Load Waveshapes is Possible
A = 0.5A/DIV
AC-COUPLED
ON 0.3ADC
LEVEL
B = 0.02V/DIV
AC-COUPLED
ON 3.3VDC
HORIZ = 10µs/DIV
AN104 F12
Figure 12. Figure 11 Responds (Trace B) to Assymetrically Edged
Pulse Input (Trace A). Ramped Leading Edge, Within LT1963A
Bandwidth, Results in Trace B’s Smooth 10mV
Excursion. Fast
P-P
A = 0.5A/DIV
ON 0.1ADC
LEVEL
B = 0.02V/DIV
AC-COUPLED
ON 3.3VDC
AN104 F13
Figure 13. 500mA
HORIZ = 2ms/DIV
, 500kHz Noise Load (Trace A), Within
P-P
Regulator Bandpass, Produces Only 6mV Artifacts at Trace B’s
Regulator Output
Trailing Edge, Outside LT1963A Bandwidth, Causes Trace B’s
Abrupt 75mV
Disruption. Traces Latter Portion Intensifi ed for
P-P
Photographic Clarity
A = 0.5A/DIV
ON 0.1ADC
LEVEL
B = 0.02V/DIV
AC-COUPLED
ON 3.3VDC
HORIZ = 2ms/DIV
AN104 F14
Figure 14. Same Conditions as Figure 13, Except Noise
Bandwidth Increased to 5MHz. Regulator Bandwidth is
Exceeded, Resulting in 50mV
Output Error
P-P
A = 0.02V/DIV
AC-COUPLED
ON 3.3VDC
HORIZ = 500KHz/DIV
AN104 F15
Figure 15. Swept DC – 5MHz, 0.35A Load (On 0.2ADC) Results in
Above Regulator Response. Regulator Output Impedance Rises
with Frequency, Causing Corresponding Ascending Output Error
an104f
AN104-5
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