, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT®1809/LT1810 are single/dual low distortion railto-rail input and output op amps with a 350V/µs slew rate.
These amplifiers have a –3dB bandwidth of 320MHz at
unity-gain, a gain-bandwidth product of 180MHz (AV ≥ 10)
and an 85mA output current to fit the needs of low voltage,
high performance signal conditioning systems.
The LT1809/LT1810 have an input range that includes
both supply rails and an output that swings within 20mV
of either supply rail to maximize the signal dynamic range
in low supply applications.
The LT1809/LT1810 have very low distortion (–90dBc) up
to 5MHz that allows them to be used in high performance
data acquisition systems.
The LT1809/LT1810 maintain their performance for supplies from 2.5V to 12.6V and are specified at 3V, 5V and
±5V supplies. The inputs can be driven beyond the supplies without damage or phase reversal of the output.
The LT1809 is available in the 8-pin SO package with the
standard op amp pinout and the 6-pin SOT-23 package.
The LT1810 features the standard dual op amp pinout and
is available in 8-pin SO and MSOP packages. These
devices can be used as a plug-in replacement for many op
amps to improve input/output range and performance.
TYPICAL APPLICATIO
High Speed ADC Driver
5V
V
IN
1V
P-P
+
LT1809
–
–5V
R1
1k
R3
49.9Ω
C1
R2
1k
470pF
+A
U
IN
–A
LTC
PGA GAIN = 1
REF = 2.048V
IN
–5V
5V
®
1420
1809 TA01
•
•
•
12 BITS
10Msps
Distortion vs Frequency
–40
AV = +1
= 2V
V
IN
–50
VS = ±5V
–60
–70
–80
DISTORTION (dB)
–90
–100
–110
RL = 100Ω, 3RD
0.3
P-P
RL = 100Ω, 2ND
RL = 1k, 3RD
RL = 1k, 2ND
11030
FREQUENCY (MHz)
1809 TA02
1
LT1809/LT1810
1
2
3
4
OUT A
–IN A
+IN A
V
–
8
7
6
5
V
+
OUT B
–IN B
+IN B
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TOP VIEW
V
+
OUT B
–IN B
+IN B
OUT A
–IN A
+IN A
V
–
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
4
8
7
6
5
A
B
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–) ........................... 12.6V
Input Voltage (Note 2) ..............................................±V
Input Current (Note 2) ........................................ ±10mA
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
ORDER PART
NUMBER
SHDN
–IN
+IN
1
2
–
+
3
–
V
4
8
NC
+
V
7
OUT
6
NC
5
LT1809CS8
LT1809IS8
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 150°C, θJA = 100°C/W (Note 9)
JMAX
1809
1809I
ORDER PART
NUMBER
LT1810CS8
LT1810IS8
S8 PART MARKING
1810
1810I
T
= 150°C, θJA = 130°C/W (Note 9)
JMAX
LT1810CMS8
LT1810IMS8
MS8 PART MARKING
LTRF
LTTQ
T
= 150°C, θJA = 100°C/W (Note 9)
JMAX
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
T
= 25°C. V
A
SYMBOL PARAMETERCONDITIONSMINTYPMAXUNITS
V
OS
∆V
OS
I
B
∆I
B
2
= 5V, 0V; VS = 3V, 0V; V
S
= open; VCM = V
SHDN
= half supply, unless otherwise noted.
OUT
Input Offset VoltageVCM = V+ LT1809 SO-80.62.5mV
VCM = V– LT1809 SO-80.62.5mV
+
V
= V
CM
–
VCM = V
Input Offset ShiftVCM = V– to V+ LT1809 SO-80.32.0mV
V
= V– to V
CM
+
0.63.0mV
0.63.0mV
0.32.5mV
Input Offset Voltage Match (Channel-to-Channel) (Note 10)0.76mV
Input Bias CurrentVCM = V
Input Bias Current ShiftVCM = V– + 0.2V to V
Input Bias Current Match (Channel-to-Channel) (Note 10)VCM = V
+
–
V
= V
CM
V
CM
+ 0.2V–27.5–13µA
+
+
= V– + 0.2V0.28µA
1.88µA
14.835.5µA
0.14µA
LT1809/LT1810
ELECTRICAL CHARACTERISTICS
T
= 25°C. V
A
SYMBOL PARAMETERCONDITIONSMINTYPMAXUNITS
I
OS
∆I
OS
e
n
i
n
C
IN
A
VOL
CMRRCommon Mode Rejection RatioVS = 5V, V
PSRRPower Supply Rejection RatioVS = 2.5V to 10V, V
V
OL
V
OH
I
SC
I
S
I
SHDN
V
L
V
H
t
ON
t
OFF
GBWGain-Bandwidth ProductFrequency = 2MHz160MHz
SRSlew RateVS = 5V, AV = –1, RL = 1k, VO = 4V
FPBWFull Power BandwidthVS = 5V, V
THDTotal Harmonic DistortionVS = 5V, AV = 1, RL = 1k, VO = 2V
t
S
∆GDifferential Gain (NTSC)VS = 5V, AV = 2, RL = 150Ω0.015%
∆θDifferential Phase (NTSC)VS = 5V, AV = 2, RL = 150Ω0.05Deg
= 5V, 0V; VS = 3V, 0V; V
S
Input Offset CurrentVCM = V
Input Offset Current ShiftVCM = V– + 0.2V to V
= open; VCM = V
SHDN
= half supply, unless otherwise noted.
OUT
+
V
= V– + 0.2V0.24µA
CM
+
0.051.2µA
0.255.2µA
Input Noise Voltage Densityf = 10kHz16nV/√Hz
Input Noise Current Densityf = 10kHz5pA/√Hz
Input Capacitance2pF
Large-Signal Voltage GainVS = 5V, VO = 0.5V to 4.5V, RL = 1k to VS/22580V/mV
V
= 5V, VO = 1V to 4V, RL = 100Ω to VS/2410V/mV
S
= 3V, VO = 0.5V to 2.5V, RL = 1k to VS/21542V/mV
V
S
= V– to V
CM
= 3V, V
V
S
CMRR Match (Channel-to-Channel) (Note 10)VS = 5V, V
= 3V, V
V
S
= V– to V
CM
= V– to V
CM
= V– to V
CM
Input Common Mode RangeV
PSRR Match (Channel-to-Channel) (Note 10)VS = 2.5V to 10V, V
+
+
+
+
= 0V7187dB
CM
= 0V6587dB
CM
6682dB
6178dB
6082dB
5578dB
–
+
V
Minimum Supply Voltage (Note 6)2.32.5V
Output Voltage Swing LOW (Note 7)No Load1250mV
= 5mA50120mV
I
SINK
I
= 25mA180375mV
SINK
Output Voltage Swing HIGH (Note 7)No Load2080mV
= 5mA80180mV
I
SOURCE
= 25mA330650mV
I
SOURCE
Short-Circuit CurrentVS = 5V±45±85mA
V
= 3V±35±70mA
S
Supply Current per Amplifier12.517mA
Supply Current, ShutdownVS = 5V, V
V
= 3V, V
S
SHDN Pin CurrentVS = 5V, V
= 3V, V
V
S
Output Leakage Current, ShutdownV
= 0.3V0.175µA
SHDN
= 0.3V0.551.25mA
SHDN
= 0.3V0.310.90mA
SHDN
= 0.3V420750µA
SHDN
= 0.3V220500µA
SHDN
SHDN Pin Input Voltage Low0.3V
SHDN Pin Input Voltage HighVS – 0.5V
Turn-On TimeV
Turn-Off TimeV
Settling Time0.1%, VS = 5V, V
= 0.3V to 4.5V, RL = 10080ns
SHDN
= 4.5V to 0.3V, RL = 10050ns
SHDN
300V/µs
23.5MHz
OUT
P-P
= 4V
P-P
, fC = 5MHz–86dB
P-P
= 2V, AV = –1, RL = 500Ω27ns
STEP
V
3
LT1809/LT1810
ELECTRICAL CHARACTERISTICS
temperature range. VS = 5V, 0V; VS = 3V, 0V; V
SHDN
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C
= open; VCM = V
= half supply, unless otherwise noted.
OUT
SYMBOL PARAMETERCONDITIONSMINTYPMAXUNITS
V
OS
VOS TCInput Offset Voltage Drift (Note 8)VCM = V
∆V
Input Offset VoltageVCM = V+ LT1809 SO-8●13.0mV
Input Offset Voltage ShiftVCM = V
OS
Input Offset Voltage Match (Channel-to-Channel)VCM = V–, VCM = V
VCM = V
VCM = V
VCM = V
VCM = V
VCM = V
–
LT1809 SO-8●13.0mV
+
–
+
–
–
+
to V
LT1809 SO-8●0.52.5mV
–
+
to V
+
●13.5mV
●13.5mV
●925µV/°C
●925µV/°C
●0.53.0mV
●1.26.5mV
(Note 10)
I
B
∆I
B
I
OS
∆I
OS
A
VOL
CMRRCommon Mode Rejection RatioVS = 5V, VCM = V
PSRRPower Supply Rejection RatioVS = 2.5V to 10V, V
Input Bias CurrentVCM = V+ – 0.2V●210 µA
Input Bias Current ShiftVCM = V
Input Bias Current Match (Channel-to-Channel)VCM = V+ – 0.2V●0.15µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected by back-to-back diodes. If the differential
input voltage exceeds 1.4V, the input current should be limited to less than
10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LT1809C/LT1809I and LT1810C/LT1810I are guaranteed
functional over the operating temperature range of –40°C and 85°C.
Note 5: The LT1809C/LT1810C are guaranteed to meet specified
performance from 0°C to 70°C. The LT1809C/LT1810C are designed,
characterized and expected to meet specified performance from –40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LT1809I/LT1810I are guaranteed to meet specified performance from
–40°C to 85°C.
Note 6: Minimum supply voltage is guaranteed by power supply rejection
ratio test.
Note 7: Output voltage swings are measured between the output and
power supply rails.
Note 8: This parameter is not 100% tested.
Note 9: Thermal resistance varies depending upon the amount of PC board
metal attached to the V
amount of 2oz of copper metal trace connecting to the V
–
pin of the device. θJA is specified for a certain
–
pin as described
in the thermal resistance tables in the Applications Information section.
Note 10: Matching parameters are the difference between the two
amplifiers of the LT1810.
9
LT1809/LT1810
LOAD CURRENT (mA)
0.01
0.001
OUTPUT HIGH SATURATION VOLTAGE (V)
0.1
10
1100.1100
1809 G09
0.01
1
VS = 5V, 0V
TA = 125°C
TA = –55°C
TA = 25°C
COMMON MODE VOLTAGE (V)
–1
INPUT BIAS CURRENT (µA)
5
2
1809 G06
–10
–20
013
–25
–30
10
0
–5
–15
456
VS = 5V, 0V
TA = –55°C
TA = –55°C
TA = 25°C
TA = 25°C
TA = 125°C
TA = 125°C
UW
TYPICAL PERFOR A CE CHARACTERISTICS
VOS Distribution, VCM = 0V
(PNP Stage)
50
VS = 5V, 0V
40
30
20
PERCENT OF UNITS (%)
10
0
–3
–101
–2
INPUT OFFSET VOLTAGE (mV)
Supply Current vs Supply Voltage
25
20
15
10
SUPPLY CURRENT (mA)
5
TA = 125°C
TA = 25°C
TA = –55°C
23
1809 G01
VOS Distribution, VCM = 5V
(NPN Stage)
50
VS = 5V, 0V
40
30
20
PERCENT OF UNITS (%)
10
0
–3
–101
–2
INPUT OFFSET VOLTAGE (mV)
Offset Voltage
vs Input Common Mode
2.0
1.5
1.0
0.5
0
–0.5
OFFSET VOLTAGE (mV)
–1.0
TA = 125°C
TA = 25°C
TA = –55°C
23
1809 G02
VS = 5V, 0V
TYPICAL PART
∆V
Shift for VCM = 0V to 5V
OS
25
VS = 5V, 0V
20
15
10
PERCENT OF UNITS (%)
5
0
–1
–0.75 –0.5 –0.25
INPUT OFFSET VOLTAGE (mV)
Input Bias Current
vs Common Mode Voltage
0 0.25
0.5 0.75 1
1809 G03
0
2
3
19
0
TOTAL SUPPLY VOLTAGE (V)
Input Bias Current vs Temperature
5
VS = 5V, 0V
3
1
–1
–3
–5
–7
–9
INPUT BIAS CURRENT (µA)
–11
–13
–15
10
–35–5
–50
–20
TEMPERATURE (°C)
6
4
VCM = 5V
VCM = 0V
10
7
5
2585
40
8
10
1809 G04
55
70
1809 G07
–1.5
10
1
0.1
0.01
OUTPUT LOW SATURATION VOLTAGE (V)
0.001
0.01
1235
0
INPUT COMMON MODE VOLTAGE (V)
4
Output Saturation Voltage
vs Load Current (Output Low)
VS = 5V, 0V
TA = 125°C
TA = –55°C
TA = 25°C
1100.1100
LOAD CURRENT (mA)
1809 G05
Output Saturation Voltage
vs Load Current (Output High)
1809 G08
UW
SHDN PIN VOLTAGE (V)
0
0
SUPPLY CURRENT (mA)
2
6
8
10
2
4
5
18
1809 G12
4
13
12
14
16
VS = 5V, 0V
TA = –55°C
T
A
= 25°C
T
A
= 125°C
TYPICAL PERFOR A CE CHARACTERISTICS
LT1809/LT1810
Supply Current
vs SHDN Pin Voltage
Minimum Supply Voltage
1.0
VCM = V– + 0.5V
0.8
0.6
0.4
0.2
TA = –55°C
0
–0.2
–0.4
–0.6
CHANGE IN OFFSET VOLTAGE (mV)
–0.8
–1.0
1.5
TA = 125°C
TA = 25°C
3.5
3.0
2.5
2.0
TOTAL SUPPLY VOLTAGE (V)
4.0
4.5
1809 G10
5.0
Output Short-Circuit Current
vs Power Supply Voltage
120
100
80
60
40
20
–20
–40
–60
–80
OUTPUT SHORT-CIRCUIT CURRENT (mA)
–100
TA = –55°C
TA = 125°C
0
TA = –55°C
TA = 25°C
1.5
2.5
2.0
POWER SUPPLY VOLTAGE (±V)
“SINKING”
“SOURCING”
3.5
3.0
TA = 25°C
TA = 125°C
4.0
4.5
5.0
1809 G11
SHDN Pin Current
vs SHDN Pin VoltageOpen-Loop GainOpen-Loop Gain
SHDN PIN CURRENT (µA)
–50
–100
–150
–200
–250
–300
–350
–400
–450
50
0
0
VS = 5V, 0V
T
= –55°C
A
1
TA = 125°C
T
= 25°C
A
3
2
SHDN PIN VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
INPUT VOLTAGE (mV)
–1.5
–2.0
–2.5
0
4
5
1809 G13
0.5
1.52.0
1.0
OUTPUT VOLTAGE (V)
VS = 3V, 0V
RL = 1k
RL = 100Ω
2.5
3.0
1809 G14
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
INPUT VOLTAGE (mV)
–1.5
–2.0
–2.5
0
RL = 100Ω
1
2
OUTPUT VOLTAGE (V)
VS = 5V, 0V
R
= 1k
L
34
1809 G15
5
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
INPUT VOLTAGE (mV)
–1.5
–2.0
–2.5
–5
Open-Loop Gain
–3–4
–1–2
OUTPUT VOLTAGE (V)
R
RL = 100Ω
124
0
L
= 1k
VS = ±5V
3
1809 G16
Offset Voltage vs Output CurrentWarm-Up Drift vs Time (LT1809S8)
15
VS = ±5V
10
5
0
–5
OFFSET VOLTAGE (mV)
–10
5
–15
–60–202060
OUTPUT CURRENT (mA)
= 125°C
T
A
TA = –55°C
TA = 25°C
100–80–100–4004080
1809 G17
180
TA = 25°C
160
140
120
100
80
60
40
CHANGE IN OFFSET VOLTAGE (µV)
20
0
0
40
20
TIME AFTER POWER UP (SEC)
= ±5V
V
S
VS = 5V, 0V
VS = 3V, 0V
80 100 120 140 160
60
1809 G18
11
LT1809/LT1810
TEMPERATURE (°C)
–55
SLEW RATE (V/µs)
400
25
1809 G25
250
150
–25050
100
50
450
350
300
200
75 100 125
AV = 1
R
F
= RG = 1k
R
L
= 1k
RISING AND FALLING
SLEW RATE
VS = ±5V
VS = 5V, 0V
FREQUENCY (Hz)
–6
GAIN (dB)
12
15
–9
–12
9
0
6
3
–3
100k10M100M 500M
1809 G27
–15
1M
VS = 3V
AV = +2
VS = ±5V
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise Voltage vs Frequency
100
VS = 5V, 0V
90
80
70
60
50
NPN ACTIVE
V
= 4.5V
CM
V
= 2.5V
CM
110100
FREQUENCY (kHz)
NOISE VOLTAGE (nV/√Hz)
40
30
PNP ACTIVE
20
10
0
0.1
1809 G19
Input Noise Current vs Frequency
20
VS = 5V, 0V
16
12
CURRENT NOISE (pA/√Hz)
8
4
0
0.1
NPN ACTIVE
= 4.5V
V
CM
110100
FREQUENCY (kHz)
PNP ACTIVE
= 2.5V
V
CM
1809 G20
0.1Hz to 10Hz
Output Voltage Noise
10
8
6
4
2
0
–2
–4
OUTPUT VOLTAGE (µV/DIV)
–6
–8
–10
TIME (2 SEC/DIV)
1809 G21
Gain Bandwidth and Phase Margin
vs Supply Voltage
TA = 25°C
= 1k
R
L
PHASE MARGIN
190
185
180
175
GAIN BANDWIDTH (MHz)
170
165
160
GAIN BANDWIDTH
2
0
TOTAL SUPPLY VOLTAGE (V)
4
Gain and Phase vs Frequency
60
50
40
30
20
GAIN (dB)
10
0
–10
CL = 5pF
= 1k
R
L
–20
100k10M100M1G
12
VS = 3V, 0V
VS = 3V, 0V
1M
FREQUENCY (Hz)
VS = ±5V
GAIN
6
PHASE
VS = ±5V
Gain Bandwidth and Phase Margin
vs Temperature
100
1809 G24
55
50
45
PHASE MARGIN (DEG)
40
35
30
125
55
25
VS = ±5V
VS = ±5V
VS = 3V, 0V
50
75
50
45
PHASE MARGIN (DEG)
40
35
GAIN BANDWIDTH (MHz)
8
10
1809 G23
200
190
180
170
160
150
–55
PHASE MARGIN
VS = 3V, 0V
GAIN BANDWIDTH
0
–25
TEMPERATURE (°C)
Slew Rate vs Temperature
Closed-Loop Gain vs FrequencyClosed-Loop Gain vs Frequency
The LT1809/LT1810 have an input and output signal
range that includes both negative and positive power
supply. Figure 1 depicts a simplified schematic of the
amplifier. The input stage is comprised of two differential
amplifiers, a PNP stage Q1/Q2 and a NPN stage Q3/Q4
that are active over different ranges of common mode
input voltage. The PNP differential pair is active for
common mode voltages between the negative supply to
approximately 1.5V below the positive supply. As the
input voltage moves closer toward the positive supply,
the transistor Q5 will steer the tail current I1 to the current
mirror Q6/Q7, activating the NPN differential pair and
causing the PNP pair to become inactive for the rest of the
input common mode range up to the positive supply.
A pair of complementary common emitter stages
Q14/Q15 form the output stage, enabling the output to
swing from rail-to-rail. The capacitors C1 and C2 form the
local feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1809/LT1810 amplifiers combine high speed with
large output current in a small package, so there is a need
to ensure that the die’s junction temperature does not
exceed 150°C. The LT1809 is housed in an SO-8 package
or a 6-lead SOT-23 package and the LT1810 is in an SO-8
or 8-lead MSOP package. All packages have the V– supply
pin fused to the lead frame to enhance the thermal conductance when connecting to a ground plane or a large metal
trace. Metal trace and plated through-holes can be used to
spread the heat generated by the device to the backside of
the PC board. For example, on a 3/32" FR-4 board with 2oz
copper, a total of 660 square millimeters connected to
Pin␣ 4 of LT1810 in an SO-8 package (330 square millimeters on each side of the PC board) will bring the thermal
resistance, θJA, to about 85°C/W. Without extra metal
trace connected to the V– pin to provide a heat sink, the
thermal resistance will be around 105°C/W. More information on thermal resistance for all packages with various
metal areas connecting to the V– pin is provided in Tables
1, 2 and 3 for thermal consideration.
Junction temperature TJ is calculated from the ambient
temperature TA and power dissipation PD as follows:
TJ = TA + (PD • θJA)
The power dissipation in the IC is the function of the supply
voltage, output voltage and the load resistance. For a given
supply voltage, the worst-case power dissipation P
D(MAX)
occurs at the maximum supply current with the output
voltage at half of either supply voltage (or the maximum
swing is less than 1/2 the supply voltage). P
D(MAX)
is given
by:
P
Example: An LT1810 in SO-8 mounted on a 2500mm
D(MAX)
= (VS • I
S(MAX)
) + (VS/2)2/R
L
2
area of PC board without any extra heat spreading plane
connected to its V– pin has a thermal resistance of
105°C/W, θJA. Operating on ±5V supplies with both
amplifiers simultaneously driving 50Ω loads, the worstcase power dissipation is given by:
The maximum ambient temperature that the part is allowed to operate is:
TA = TJ – (P
D(MAX)
• 105°C/W)
= 150°C – (0.750W • 105°C/W) = 71°C
To operate the device at higher ambient temperature,
connect more metal area to the V– pin to reduce the
thermal resistance of the package as indicated in Table 2.
Input Offset Voltage
The offset voltage will change depending upon which input
stage is active and the maximum offset voltage is guaranteed to be less than 3mV. The change of VOS over the entire
input common mode range (CMRR) is less than 2.5mV on
a single 5V and 3V supply.
Input Bias Current
The input bias current polarity depends upon a given input
common voltage at whichever input stage is operating.
When the PNP input stage is active, the input bias currents
flow out of the input pins and flow into the input pins when
the NPN input stage is activated. Because the input offset
current is less than the input bias current, matching the
source resistances at the input pin will reduce total offset
error.
Output
The LT1809/LT1810 can deliver a large output current,
so the short-circuit current limit is set around 90mA to
prevent damage to the device. Attention must be paid to
keep the junction temperature of the IC below the absolute maximum rating of 150°C (refer to the Power Dissipation section) when the output is continuously short
circuited. The output of the amplifier has reverse-biased
diodes connected to each supply. If the output is forced
16
WUUU
APPLICATIO S I FOR ATIO
LT1809/LT1810
beyond either supply, unlimited current will flow through
these diodes. If the current is transient and limited to
several hundred milliamps, no damage to the device will
occur.
Overdrive Protection
When the input voltage exceeds the power supplies, two
pairs of crossing diodes, D1 to D4, will prevent the output
from reversing polarity. If the input voltage exceeds either
power supply by 700mV, diodes D1/D2 or D3/D4 will turn
on, keeping the output at the proper polarity. For the
phase reversal protection to perform properly, the input
current must be limited to less than 5mA. If the amplifier
is severely overdriven, an external resistor should be used
to limit the overdrive current.
The LT1809/LT1810’s input stages are also protected
against differential input voltages of 1.4V or higher by
back-to-back diodes, D5/D8, that prevent the emitter-base
breakdown of the input transistors. The current in these
diodes should be limited to less than 10mA when they are
active. The worst-case differential input voltage usually
occurs when the input is driven while the output is shorted
to ground in a unity-gain configuration. In addition, the
amplifier is protected against ESD strikes up to 3kV on all
pins by a pair of protection diodes on each pin that are
connected to the power supplies as shown in Figure 1.
Capacitive Load
The LT1809/LT1810 is optimized for high bandwidth and
low distortion applications. It can drive a capacitive load
about 20pF in a unity-gain configuration and more with
higher gain. When driving a larger capacitive load, a
resistor of 10Ω to 50Ω should be connected between the
output and the capacitive load to avoid ringing or oscillation. The feedback should still be taken from the output so
that the resistor will isolate the capacitive load to ensure
stability. Graphs on capacitive loads indicate the transient
response of the amplifier when driving capacitive load with
a specified series resistor.
Feedback Components
When feedback resistors are used to set up gain, care must
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input
does not degrade stability. For instance, the LT1809 in a
noninverting gain of 2, set up with two 1K resistors and a
capacitance of 3pF (device plus PC board), will probably
ring in transient response. The pole that is formed at
106MHz will reduce phase margin by 34 degrees when the
crossover frequency of the amplifier is around 70MHz. A
capacitor of 3pF or higher connected across the feedback
resistor will eliminate any ringing or oscillation.
SHDN Pin
The LT1809 has a SHDN pin to reduce the supply current
to less than 1.25mA. When the SHDN pin is pulled low, it
will generate a signal to power down the device. If the pin
is left unconnected, an internal pull-up resistor of 10k will
keep the part fully operating as shown in Figure 1. The
output will be high impedance during shutdown, and the
turn-on and turn-off time is less than 100ns. Because the
inputs are protected by a pair of back-to-back diodes, the
input signal will feed through to the output during shutdown mode if the amplitude of signal between the inputs
is larger than 1.4V.
17
LT1809/LT1810
TYPICAL APPLICATIO S
U
Driving A/D Converters
The LT1809/LT1810 have a 27ns settling time to 0.1% of
a 2V step signal and 20Ω output impedance at 100MHz
making it ideal for driving high speed A/D converters. With
the rail-to-rail input and output and low supply voltage
operation, the LT1809 is also desirable for single supply
applications. As shown in Figure 2, the LT1809 drives a
10Msps, 12-bit ADC, the LTC1420. The lowpass filter, R3
and C1, reduces the noise and distortion products that
might come from the input signal. High quality capacitors
5V
V
IN
1V
P-P
+
LT1809
–
–5V
R1
1k
R3
49.9Ω
R2
1k
and resistors, an NPO chip capacitor and metal-film surface mount resistors, should be used since these components can add to distortion. The voltage glitch of the
converter, due to its sampling nature, is buffered by the
LT1809 and the ability of the amplifier to settle it quickly
will affect the spurious-free dynamic range of the system.
Figure 2 to Figure 7 depict the LT1809 driving the LTC1420
at different configurations and voltage supplies. The FFT
responses show better than 90dB of SFDR for a ±5V
supply, and 80dB on a 5V single supply for the 1.394MHz
signal.
5V
C1
470pF
+A
IN
–A
LTC1420
PGA GAIN = 1
REF = 2.048V
IN
–5V
1809 F02
12 BITS
•
10Msps
•
•
Figure 2. Noninverting A/D Driver
0
–20
–40
–60
AMPLITUDE (dB)
–80
–100
–120
0
1234
FREQUENCY (MHz)
VS = ±5V
= +2
A
V
= 10Msps
f
SAMPLE
= 1.394MHz
f
IN
SFDR = 90dB
Figure 3. 4096 Point FFT Response
5
1809 F03
18
TYPICAL APPLICATIO S
LT1809/LT1810
U
V
IN
2V
P-P
ON 2.5V DC
0
–20
1k
1k
–
LT1809
+
5V
–5V
49.9Ω
470pF
+A
–A
PGA GAIN = 1
IN
REF = 2.048V
IN
5V
LTC1420
–5V
1809 F04
•
•
•
12 BITS
10Msps
–40
–60
AMPLITUDE (dB)
–80
–100
–120
0
1234
FREQUENCY (MHz)
VS = ±5V
= –1
A
V
= 10Msps
f
SAMPLE
= 1.394MHz
f
IN
SFDR = 90dB
5
1809 F05
Figure 4. Inverting A/D DriverFigure 5. 4096 Point FFT Response
0
–20
5V
3
2
1k
0.15µF
+
LT1809
–
5V
7
4
49.9Ω
6
1
470pF
1k
1
2
+A
IN
–A
LTC1420
PGA GAIN = 2
REF = 4.096V
IN
V
CM
3
1µF
1809 F06
•
•
•
12 BITS
10Msps
V
IN
1V
P-P
–40
–60
AMPLITUDE (dB)
–80
–100
–120
0
1234
FREQUENCY (MHz)
VS = 5V
= +2
A
V
= 10Msps
f
SAMPLE
= 1.394MHz
f
IN
SFDR = 80dB
5
1809 F07
Figure 6. Single Supply A/D Driver
Figure 7. 4096 Point FFT Response
19
LT1809/LT1810
TYPICAL APPLICATIO S
Single Supply Video Line Driver
U
The LT1809 is a wideband rail-to-rail op amp with a large
output current that allows it to drive video signals in low
supply applications. Figure 8 depicts a single supply video
line driver with AC coupling to minimize the quiescent
power dissipation. Resistors R1 and R2 are used to levelshift the input and output to provide the largest signal
swing. A gain of 2 is set up with R3 and R4 to restore the
signal at V
, which is attenuated by 6dB due to the
OUT
matching of the 75Ω line with the back-terminated
5V
C1
33µF
V
IN
R
T
75Ω
R1
5k
+
R2
5k
3
2
+
R3
1k
C2
150µF
+
LT1809
–
7
6
4
R4
1k
C4
3pF
resistor, R5. The back termination will eliminate any reflection of the signal that comes from the load. The input
termination resistor, RT, is optional—it is used only if
matching of the incoming line is necessary. The values of
C1, C2 and C3 are selected to minimize the droop of the
luminance signal. In some less stringent requirements,
the value of capacitors could be reduced. The –3dB bandwidth of the driver is about 95MHz on 5V supply and the
amount of peaking will vary upon the value of capacitor C4.
C3
1000µF
+
R5
75Ω
75Ω
COAX CABLE
R
LOAD
75Ω
1809 F08
V
OUT
Figure 8. 5V Single Supply Video Line Driver
5
VS = 5V
4
3
2
1
0
–1
–2
VOLTAGE GAIN (dB)
–3
–4
–5
0.210100
1
FREQUENCY (MHz)
1809 F09
Figure 9. Video Line Driver Frequency Response
20
PACKAGE DESCRIPTIO
LT1809/LT1810
U
Dimensions in inches (millimeters) unless otherwise noted.
5. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
6. MOLD FLASH SHALL NOT EXCEED .254mm
7. PACKAGE EIAJ REFERENCE IS:
SC-74A (EIAJ) FOR ORIGINAL
JEDEC MO-193 FOR THIN
SOT-23
(ThinSOT)
1.00 MAX
(.039 MAX)
.01 – .10
(.0004 – .004)
.80 – .90
(.031 – .035)
.30 – .50 REF
(.012 – .019 REF)
MILLIMETERS
(INCHES)
2.60 – 3.00
(.102 – .118)
.09 – .20
(.004 – .008)
(NOTE 2)
1.50 – 1.75
(.059 – .069)
(NOTE 3)
A
PIN ONE ID
.95
(.037)
REF
A2
1.90
(.074)
REF
.25 – .50
(.010 – .020)
(6PLCS, NOTE 2)
A1
S6 SOT-23 0401
21
LT1809/LT1810
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.193 ± 0.006
(4.90 ± 0.15)
12
0.043
(1.10)
MAX
0.007
(0.18)
0.021
± 0.006
(0.53 ± 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
° – 6° TYP
0
SEATING
PLANE
0.009 – 0.015
(0.22 – 0.38)
0.0256
(0.65)
BSC
4
3
0.118 ± 0.004**
(3.00 ± 0.102)
0.034
(0.86)
REF
0.005
± 0.002
(0.13 ± 0.05)
MSOP (MS8) 1100
22
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
LT1809/LT1810
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT1809/LT1810
U
TYPICAL APPLICATIO
Single 3V Supply, 4MHz, 4th Order Butterworth Filter
Benefiting from a low voltage supply operation, low
distortion and rail-to-rail output of LT1809, a low distortion filter that is suitable for antialiasing can be built as
232Ω
47pF
232Ω
V
IN
Figure 10. Single 3V Supply, 4MHz, 4th Order Butterworth Filter
665Ω
220pF
–
1/2 LT1810
+
V
S
2
10
0
–10
–20
–30
–40
GAIN (dB)
–50
–60
–70
VS = 3V, 0V
–80
–90
= 2.5V
V
P-P
IN
10k100k1M10M100M
FREQUENCY (Hz)
shown Figure 10. On a 3V supply, the filter has a passband of 4MHz with 2.5V
signal and a stopband that is
P-P
greater than 70dB to frequency of 100MHz.
274Ω
22pF
274Ω
562Ω
470pF
1809 F11
–
1/2 LT1810
+
V
OUT
1809 F10
Figure 11. Filter Frequency Response
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