LINEAR TECHNOLOGY LT1794 Technical data

FEATURES

■

Exceeds All Requirements For Full Rate,
Downstream ADSL Line Drivers

■

±500mA Minimum I

■

±11.1V Output Swing, VS = ±12V, RL = 100Ω

■

±10.9V Output Swing, VS = ±12V, IL = 250mA

■

Low Distortion: –82dBc at 1MHz, 2V

■

Power Saving Adjustable Supply Current

■

Power Enhanced Small Footprint Packages:

OUT

P-P

20-Lead TSSOP and 20-Lead SW

■

200MHz Gain Bandwidth

■

500V/µs Slew Rate

■

Specified at ±15V, ±12V and ±5V

U

APPLICATIO S

■

High Density ADSL Central Office Line Drivers

■

High Efficiency ADSL, HDSL2, G.lite,
SHDSL Line Drivers

■

Buffers

■

Test Equipment Amplifiers

■

Cable Drivers

Into 50Ω

LT1794

Dual 500mA, 200MHz

xDSL Line Driver Amplifier

U

DESCRIPTIO

The LT®1794 is a 500mA minimum output current, dual op
amp with outstanding distortion performance. The ampli­fiers are gain-of-ten stable, but can be easily compensated
for lower gains. The extended output swing allows for
lower supply rails to reduce system power. Supply current
is set with an external resistor to optimize power dissipa­tion. The LT1794 features balanced, high impedance in­puts with low input bias current and input offset voltage.
Active termination is easily implemented for further sys­tem power reduction. Short-circuit protection and thermal
shutdown insure the device’s ruggedness.

The outputs drive a 100Ω load to ±11.1V with ±12V
supplies, and ±10.9V with a 250mA load. The LT1794,
with its increased swing on lower supplies, can be used to
upgrade LT1795 line driver applications.

The LT1794 is available in the very small, thermally
enhanced, 20-lead TSSOP for maximum port density in
line driver applications. The 20-lead SW is also available.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

+IN

1000pF

–IN

U

High Efficiency ±12V Supply ADSL Central Office Line Driver

12V

R

BIAS

1k

1k

–12V

24.9k

SHDN

SHDNREF

12.7Ω

12.7Ω

1:2*

•

•

*COILCRAFT X8390-A OR EQUIVALENT

= 10mA PER AMPLIFIER

I

SUPPLY

WITH R

BIAS

= 24.9k

1794 TA01

110Ω

110Ω

+

LT1794

–

–

LT1794

+

1/2

1/2

100Ω

1

LT1794

WW

W

ABSOLUTE MAXIMUM RATINGS

U

(Note 1)

Supply Voltage (V+ to V–) .................................... ±18V

Input Current ..................................................... ±10mA

Output Short-Circuit Duration (Note 2)........... Indefinite

Operating Temperature Range ............... – 40°C to 85°C

U

W

PACKAGE/ORDER INFORMATION

TOP VIEW

–

1

V

2

NC

3

–IN

4

+IN

5

SHDN

SHDNREF

T

JMAX

6
7

+IN

8

–IN

9

NC

–

10

V

FE PACKAGE

20-LEAD PLASTIC TSSOP

= 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4)
UNDERSIDE METAL CONNECTED TO V

20
19
18
17
16
15
14
13
12
11

V
NC
OUT
V
NC
NC
V
OUT
NC
V

–

+

+

–

–

ORDER PART

NUMBER

LT1794CFE
LT1794IFE

Specified Temperature Range (Note 3).. – 40°C to 85°C

Junction Temperature.......................................... 150°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

U

TOP VIEW

1

NC

+

2

V

3

OUT

–

4

V

–

5

V

–

6

V

–

7

V

8

–IN

9

+IN

10

SHDN

SW PACKAGE

20-LEAD PLASTIC SO

T

= 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4)

JMAX

20
19
18
17
16
15
14
13
12
11

NC

+

V
OUT

–

V

–

V

–

V

–

V
–IN
+IN
SHDNREF

ORDER PART

NUMBER

LT1794CSW
LT1794ISW

Consult factory for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±15V, V

SHDNREF

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

OS

Input Offset Voltage 15.0 mV

Input Offset Voltage Matching 0.3 5.0 mV

Input Offset Voltage Drift ● 10 µV/°C

I

OS

I

B

Input Offset Current 100 500 nA

Input Bias Current ±0.1 ±4 µA

Input Bias Current Matching 100 500 nA

e

n

i

n

R

IN

Input Noise Voltage Density f = 10kHz 8 nV/√Hz
Input Noise Current Density f = 10kHz 0.8 pA/√Hz
Input Resistance V

= 0V, R

= (V+ – 2V) to (V–+ 2V) ● 550 MΩ

CM

= 24.9k between V+ and SHDN unless otherwise noted. (Note 3)

BIAS

● 7.5 mV

● 7.5 mV

● 800 nA

● ±6 µA

● 800 nA

Differential 6.5 MΩ

2

LT1794

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±15V, V

SHDNREF

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

C

IN

Input Capacitance 3pF
Input Voltage Range (Positive) (Note 5) ● V+ – 2 V+ – 1 V

Input Voltage Range (Negative) (Note 5)

CMRR Common Mode Rejection Ratio V

PSRR Power Supply Rejection Ratio VS = ±4V to ±15V 74 88 dB

A

V

I
I

VOL

OUT

OUT
S

Large-Signal Voltage Gain VS = ±15V, V

Output Swing VS = ±15V, RL = 100Ω 13.8 14.0 ±V

Maximum Output Current VS = ±15V, RL = 1Ω 500 720 mA
Supply Current per Amplifier VS = ±15V, R

Supply Current in Shutdown V
Output Leakage in Shutdown V
Channel Separation VS = ±12V, V

SR Slew Rate VS = ±15V, AV = –10, (Note 7) 300 600 V/µs

HD2 Differential 2nd Harmonic Distortion VS = ±12V, AV = 10, 2V
HD3 Differential 3rd Harmonic Distortion VS = ±12V, AV = 10, 2V
GBW Gain Bandwidth f = 1MHz 200 MHz

= 0V, R

= (V+ – 2V) to (V– + 2V) 74 83 dB

CM

VS = ±12V, V

VS = ±5V, V

= 24.9k between V+ and SHDN unless otherwise noted. (Note 3)

BIAS

● V

● 66 dB

● 66 dB

= ±13V, RL = 100Ω 70 82 dB

OUT

= ±10V, RL = 40Ω 63 76 dB

OUT

= ±3V, RL = 25Ω 60 70 dB

OUT

● 64 dB

● 57 dB

● 54 dB

● 13.6 ±V

–

+ 1 V– + 2 V

VS = ±15V, IL = 250mA 13.6 13.9 ±V

● 13.4 ±V

VS = ±12V, RL = 100Ω 10.9 11.1 ±V

● 10.7 ±V

VS = ±12V, IL = 250mA 10.6 10.9 ±V

● 10.4 ±V

VS = ±5V, RL = 25Ω 3.7 4.0 ±V

● 3.5 ±V

VS = ±5V, IL = 250mA 3.6 3.9 ±V

● 3.4 ±V

= 24.9k (Note 6) 10 13 18 mA

BIAS

VS = ±12V, R

V

= ±12V, R

S

V

= ±12V, R

S

= ±12V, R

V

S

VS = ±5V, R

= 0.4V 0.1 1 mA

SHDN

= 0.4V 0.3 1 mA

SHDN

= 24.9k (Note 6) 8.0 10 13.5 mA

BIAS

= 32.4k (Note 6) 8 mA

BIAS

= 43.2k (Note 6) 6 mA

BIAS

= 66.5k (Note 6) 4 mA

BIAS

= 24.9k (Note 6) 2.2 3.4 5.0 mA

BIAS

= ±10V, RL = 40Ω 80 110 dB

OUT

● 820mA

● 6.7 15.0 mA

● 1.8 5.8 mA

● 77 dB

VS = ±5V, AV = –10, (Note 7) 100 200 V/µs

, RL = 50Ω, 1MHz –85 dBc

P-P

, RL = 50Ω, 1MHz – 82 dBc

P-P

3

LT1794

TEMPERATURE (°C)

–50

OUTPUT SATURATION VOLTAGE (V)

–0.5

10

1794 G06

1.0

–30 –10 30

0.5

V

–

V

+

–1.0

–1.5

1.5

50 70 90

VS = ±12V

RL = 100Ω

RL = 100Ω

I

LOAD

= 250mA

I

LOAD

= 250mA

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: Applies to short circuits to ground only. A short circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.

Note 3: The LT1794C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and 85°C. The

Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.

Note 5: Guaranteed by the CMRR tests.
Note 6: R

BIAS

Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±15V supplies and ±1V on a ±3V output signal while
operating on ±5V supplies.

LT1794I is guaranteed to meet the extended temperature limits.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current
vs Ambient Temperature

15

VS = ±12V

14
13
12

10

PER AMPLIFIER (mA)

SUPPLY

I

= 24.9k TO SHDN

R

BIAS

= 0V

V

SHDNREF

11

9
8
7
6
5

–30 –10 10 30 50 70 90

–50

TEMPERATURE (

°C)

1794 G01

Input Common Mode Range
vs Supply Voltage

+

V

TA = 25°C

> 1mV

∆V

–0.5

OS

–1.0
–1.5
–2.0

2.0

1.5

COMMON MODE RANGE (V)

1.0

0.5

–

V

4

2

SUPPLY VOLTAGE (±V)

6

810

is connected between V+ and the SHDN pin.

Input Bias Current
vs Ambient Temperature

200

VS = ±12V

180

PER AMPLIFIER = 10mA

I

S

160
140
120

(nA)

100

BIAS

±I

80
60
40
20

0

–30

12

14

1794 G02

–50

10 30

–10

TEMPERATURE (°C)

50

70 90

1794 G03

Input Noise Spectral Density

100

TA = 25°C

= ±12V

V

S

PER AMPLIFIER = 10mA

I

S

10

1

INPUT VOLTAGE NOISE (V/VHz)

0.1
1 100 1k 10k

4

10

FREQUENCY (Hz)

e

n

i

n

1794 G04

800
780

INPUT CURRENT NOISE (pA/VHz)

760
740
720
700

(mA)

SC

I

680
660
640

620

600

100k

100

10

1

0.1

Output Short-Circuit Current
vs Ambient Temperature

VS = ±12V

PER AMPLIFIER = 10mA

I

S

SOURCING

–50

–30 10

–10

TEMPERATURE (°C)

30

50

SINKING

70

1794 G05

Output Saturation Voltage
vs Ambient Temperature

90

UW

FREQUENCY (Hz)

1k 10k

0

GAIN (dB)

5

10

15

20

100k 1M 10M 100M

1794 G12

–5
–10
–15
–20

25

30

VS = ±12V
A

V

= 10

2mA PER AMPLIFIER

10mA PER AMPLIFIER
15mA PER AMPLIFIER

TYPICAL PERFOR A CE CHARACTERISTICS

LT1794

Open-Loop Gain and Phase
vs Frequency

120
100

80
60
40
20

GAIN (dB)

0

–20

TA = 25°C

= ±12V

V

S

–40

= –10

A

V

= 100Ω

R

L

–60

PER AMPLIFIER = 10mA

I

S

–80

100k 10M 100M

GAIN

1M

FREQUENCY (Hz)

PHASE

1794 G07

120
80
40
0
–40
–80
–120
–160
–200
–240
–280

PHASE (DEG)

–3dB Bandwidth
vs Supply Current Slew Rate vs Supply Current

45

TA = 25°C

= ±12V

V

40

S

= 10

A

V

= 100Ω

R

35

L

30

25

20

15

–3dB BANDWIDTH (MHz)

10

5

0

4

2

SUPPLY CURRENT PER AMPLIFIER (mA)

CMRR vs Frequency PSRR vs Frequency

100

90
80
70
60

50
40
30
20
10

COMMON MODE REJECTION RATIO (dB)

0

0.1

TA = 25°C

= ±12V

V

S

= 10mA PER AMPLIFIER

I

S

1 10 100

FREQUENCY (MHz)

1794 G10

100

90
80
70
60
50
40

30

20
10

POWER SUPPLY REJECTION (dB)

0

–10

0.01 1 10 100

(+) SUPPLY

0.1

6 8 10 12 14

VS = ±12V

= 10

A

V

= 10mA PER AMPLIFIER

I

S

(–) SUPPLY

FREQUENCY (MHz)

1794 G08

1794 G11

1000

TA = 25°C

900

= ±12V

V

S

= –10

A

V

800

R

= 1k

L

700

600
500

400

SLEW RATE (V/µs)

300
200
100

0

345

2

SUPPLY CURRENT PER AMPLIFIER (mA)

67

Frequency Response
vs Supply Current

RISING

FALLING

8910

11 12

13 14

1794 G09

15

1000

100

10

1

OUTPUT IMPEDANCE (Ω)

0.1

0.01

Output Impedance vs Frequency I

TA = 25°C

±12V

V

S

AMPLIFIER = 2mA

AMPLIFIER = 10mA

0.01 0.1

IS PER

IS PER

IS PER
AMPLIFIER = 15mA

1 10 100

FREQUENCY (MHz)

1734 G13

(mA)

SHDN

I

2.5

2.0

1.5

1.0

0.5

0

0

vs V

SHDN

TA = 25°C

= ±12V

V

S

V

SHDNREF

0.5

1.0

= 0V

1.5

SHDN

2.0
V

2.5

SHDN

(V)

3.0

3.5

4.0

4.5

1794 G14

5.0

Supply Current vs V

35

TA = 25°C

= ±12V

V

S

30

25

20

15

10

5

SUPPLY CURRENT PER AMPLIFIER (mA)

0

0

V

SHDNREF

0.5

1.0

= 0V

1.5

2.0
V

2.5

SHDN

SHDN

3.0

(V)

3.5

4.0

4.5

1794 G14

5

5.0

LT1794

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Harmonic Distortion
vs Output Amplitude

–40

f = 1MHz

= 25°C

T

A

–50

= ±12V

V

S

A

= 10

V

= 50Ω

R

L

–60

PER AMPLIFIER = 10mA

I

S

–70

–80

DISTORTION (dBc)

–90

–100

02

6

4 8 10 12 14 16 18

V

OUT(P-P)

HD3

HD2

Differential Harmonic Distortion
vs Supply Current

–40

–45

–50

–55

–60

–65

–70

DISTORTION (dBc)

–75

–80

–85

23456 11

I

SUPPLY

f = 1MHz, HD3

f = 100kHz, HD2

f = 100kHz, HD3

f = 1MHz, HD2

PER AMPLIFIER (mA)

VO = 10V
VS = ±12V

= 10

A

V

= 50Ω

R

L

78910

1794 G16

P-P

1794 G18

Differential Harmonic Distortion
vs Frequency

–40

VO = 10V

–45
–50
–55
–60
–65
–70

DISTORTION (dBc)

–75
–80
–85
–90

P-P

TA = 25°C
V

= ±12V

S

= 10

A

V

= 50Ω

R

L

PER AMPLIFIER = 10mA

I

S

200100

400300

500

FREQUENCY (kHz)

600 700 900

Undistorted Output Swing
vs Frequency

20

)

15

P-P

10

SFDR > 40dB

= 25°C

T

A

5

OUTPUT VOLTAGE (V

= ±12V

V

S

= 10

A

V

= 50Ω

R

L

PER AMPLIFIER = 10mA

I

S

0

100k

300k 1M 3M 10M

FREQUENCY (Hz)

HD3

800

HD2

1000

1794 G17

1794 G19

6

TEST CIRCUIT

LT1794

12V

R

SHDN

2

19

9

+

8

–

10k

–12V

OUT (+)

E

IN

49.9Ω

SPLITTER

MINICIRCUITS

ZSC5-2-2

OUT (–)

10k

110Ω

110Ω

13

12

–

+

–12V

10 (SHDN)

A

6

5

4

1k

0.01µF

1k

B

171811 (SHDNREF)

16

15

14

V

OUT(P-P)

3

7

12.7Ω

1:2*

R

≈ 50Ω

L

12.7Ω

1794 TC

*COILCRAFT X8390-A OR EQUIVALENT
V

AMPLITUDE SET AT EACH AMPLIFIER OUTPUT

OUTP-P

DISTORTION MEASURED ACROSS LINE LOAD

SUPPLY BYPASSING

+

0.1µF 4.7µF

+

0.1µF

4.7µF

100 LINE LOAD

12V

+

4.7µF

0.1µF

–12V

WUUU

APPLICATIO S I FOR ATIO

The LT1794 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1794 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1794 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1794 is available in small footprint surface
mount packages to minimize PCB area in multiport central
office DSL cards.

To minimize signal distortion, the LT1794 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed­loop gain of less than 10 is desired, external frequency
compensating components can be used.

Setting the Quiescent Operating Current

Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro­vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
starting point to evaluate the LT1794 is to set the quiescent
current to 10mA per amplifier.

The internal biasing circuitry is shown in Figure 1. Ground­ing the SHDNREF pin and directly driving the SHDN pin with
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the

7

LT1794

WUUU

APPLICATIO S I FOR ATIO

SHDN

5I

2k

I

TO

START-UP

CIRCUITRY

SHDNREF

2

I

I

=

BIAS

SHDN

5

PER AMPLIFIER (mA) = 64 • I

I

SUPPLY

= I

SHDNREF

2I

2I

1k

I

BIAS

TO AMPLIFIERS
BIAS CIRCUITRY

1794 F01

BIAS

Figure 1. Internal Current Biasing Circuitry

30

VS = ±12V

25

20

15

PER AMPLIFIER (mA)

10

SUPPLY

I

5

outputs are in a high impedance state. Part to part varia­tions however, will cause inconsistent control of the qui­escent current if direct voltage drive of the SHDN pin is used.

Using a single external resistor, R

, connected in one of

BIAS

two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect on
supply current per amplifier with R

connected be-

BIAS

tween the SHDN pin and the 12V V+ supply of the LT1794
and the approximate design equations. Figure 3 illustrates
the same control with R

connected between the

BIAS

SHDNREF pin and ground while the SHDN pin is tied to V+.
Either approach is equally effective.

V+ = 12V

R

BIAS

SHDN

I

S

R

SHDNREF

PER AMPLIFIER

=

BIAS

PER AMPLIFIER (mA)

I

S

+

V

(mA)

– 1.2V

+

V

– 1.2V

≈

R

BIAS

• 25.6

+ 2k

• 25.6 – 2k

0

7 40 70 100 130 160 190

45

40

35

30

25

20

PER AMPLIFIER (mA)

15

SUPPLY

10

I

5

0

4 7 10 50 90 130 170 210 25030 70 100 150 190 230 270 290

VS = ±12V

10

Figure 2. R

Figure 3. R

R

(kΩ)

BIAS

to V+ Current Control

BIAS

V+ = 12V

SHDN

PER AMPLIFIER

I

S

R

=

BIAS

PER AMPLIFIER (mA)

I

S

SHDNREF

R

BIAS

R

(kΩ)

BIAS

to Ground Current Control

BIAS

V

(mA)

+

– 1.2V

V

≈

R

+

– 1.2V

BIAS

1794 F02

+ 5k

• 64 – 5k

1794 F03

• 64

8

WUUU

APPLICATIO S I FOR ATIO

LT1794

Logic Controlled Operating Current

The DSP controller in a typical xDSL application can have
I/O pins assigned to provide logic control of the LT1794
line driver operating current. As shown in Figure 4 one or
two logic control inputs can control two or four different
operating modes. The logic inputs add or subtract current
to the SHDN input to set the operating current. The one
logic input example selects the supply current to be either
full power, 10mA per amplifier or just 2mA per amplifier,
which significantly reduces the driver power consumption
while maintaining less than 2Ω output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
line driving back termination resistors. With this termina­tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back­termination resistors and respond accordingly.

The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operating levels between full power and termination modes.
These modes can be useful for overall system power
management when full power transmissions are not
necessary.

Shutdown and Recovery

The ultimate power saving action on a completely idle port
is to fully shut down the line driver by pulling the SHDN pin
to within 0.4V of the SHDNREF potential. As shown in
Figure 5 complete shutdown occurs in less than 10µs and,
more importantly, complete recovery from the shut down
state to full operation occurs in less than 2µs. The biasing
circuitry in the LT1794 reacts very quickly to bring the
amplifiers back to normal operation.

V

SHDN

SHDNREF = 0V

AMPLIFIER

OUTPUT

1794 F05

Figure 5. Shutdown and Recovery Timing

Two Control Inputs

RESISTOR VALUES (kΩ)

TO V

3.3V

43.2

13.0

22.1

10

7
5
2

(12V) R

CC

5V

60.4

21.5

36.5

10

7
5
2

R

SHDN

V

3V

LOGIC

R

40.2

SHDN

R

11.5

C1

19.1

R

CO

V

V

C1

H
H
L
L

SUPPLY CURRENT PER AMPLIFIER (mA)

C0

H

10

L

7

H

5

L

2

3V

4.99

8.66

14.3

10

SHDN

7
5
2

TO V

3.3V

6.81

10.7

17.8

10

7
5
2

LOGIC

5V

19.6

20.5

34.0

10

7
5
2

V

LOGIC

V

C1

0V

V

C0

One Control Input

RESISTOR VALUES (kΩ)
R

TO V

3.3V

43.2

8.25

(12V) R

CC

5V

60.4

13.7

SHDN

V

3V

LOGIC

40.2

R

SHDN

7.32

R

C

V

SUPPLY CURRENT PER AMPLIFIER (mA)

C

HL10210210210210210

3V

4.99

5.49

SHDN

TO V

3.3V

6.81

6.65

LOGIC

5V

19.6

12.7

2

1794 F04

V

LOGIC

V

0V

C

Figure 4. Providing Logic Input Control of Operating Current

R

C1

R

C0

R

C

12V OR V

12V OR V

LOGIC

R

SHDN

SHDN

2k

SHDNREF

LOGIC

R

SHDN

SHDN

2k

SHDNREF

9

LT1794

WUUU

APPLICATIO S I FOR ATIO

Power Dissipation and Heat Management

xDSL applications require the line driver to dissipate a
significant amount of power and heat compared to other
components in the system. The large peak to RMS varia­tions of DMT and CAP ADSL signals require high supply
voltages to prevent clipping, and the use of a step-up
transformer to couple the signal to the telephone line can
require high peak current levels. These requirements
result in the driver package having to dissipate on the
order of 1W. Several multiport cards inserted into a rack
in an enclosed central office box can add up to many,
many watts of power dissipation in an elevated ambient
temperature environment. The LT1794 has built-in ther­mal shutdown cir

cuitry that will protect the amplifiers if
operated at excessive temperatures, however data trans­missions will be seriously impaired. It is important in the
design of the PCB and card enclosure to take measures to
spread the heat developed in the driver away to the
ambient environment to prevent thermal shutdown (which
occurs when the junction temperature of the LT1794
exceeds 165°C).

Estimating Line Driver Power Dissipation

Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mW

of power on to the 100Ω

RMS

telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1794 is
set to 10mA per amplifier.

The power dissipated in the LT1794 is a combination of the
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
the upper power transistor of one amplifier, while sourc­ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:

1000pF

+IN

–IN

110Ω

110Ω

20mA DC

+

–

–

+

A

1k

1k

B

–12V

12V

24.9k – SETS I

2V

RMS

SHDN

I

= 57mA

LOAD

SHDNREF

–2V

RMS

PER AMPLIFIER = 10mA

Q

17.4Ω

1:1.7

•

•

RMS

17.4Ω

1794 F06

PD = P

QUIESCENT

+ P

Q(UPPER)

PD = (V+ – V–) • IQ + (V+ – V

I

+ (V– – V

LOAD

OUTBRMS

100Ω 3.16V

+ P

Q(LOWER)

OUTARMS

) • I

LOAD

RMS

) •

10

Figure 6. Estimating Line Driver Power Dissipation

WUUU

APPLICATIO S I FOR ATIO

LT1794

With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies­cent driver power dissipation is:

PDQ = 24V • 20mA = 480mW

This can be reduced in many applications by operating
with a lower quiescent current value.

When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.

At full power to the line the driver power dissipation is:

P

D(FULL)

P

D(FULL)

= 24V • 8mA + (12V – 2V

+ [|–12V – (–2V

)|] • 57mA

RMS

RMS

) • 57mA

RMS

RMS

= 192mW + 570mW + 570mW = 1.332W

The junction temperature of the driver must be kept less
than the thermal shutdown temperature when processing
a signal. The junction temperature is determined from the
following expression:

TJ = T

AMBIENT

(°C) + P

D(FULL)

(W) • θJA (°C/W)

θJA is the thermal resistance from the junction of the

LT1794 to the ambient air, which can be minimized by

heat-spreading PCB metal and airflow through the enclo­sure as required. For the example given, assuming a
maximum ambient temperature of 85°C and keeping the
junction temperature of the LT1794 to 140°C maximum,
the maximum thermal resistance from junction to ambient
required is:

CC

–

°°

θ

JA MAX

()

140 85

W

.

1 332

CW

./=

=°

41 3

Heat Sinking Using PCB Metal

Designing a thermal management system is often a trial
and error process as it is never certain how effective it is
until it is manufactured and evaluated. As a general rule,
the more copper area of a PCB used for spreading heat
away from the driver package, the more the operating
junction temperature of the driver will be reduced. The
limit to this approach however is the need for very com­pact circuit layout to allow more ports to be implemented
on any given size PCB.

Fortunately xDSL circuit boards use multiple layers of
metal for interconnection of components. Areas of metal
beneath the LT1794 connected together through several
small 13 mil vias can be effective in conducting heat away
from the driver package. The use of inner layer metal can
free up top and bottom layer PCB area for external compo­nent placement.

25

20

15

(mA)

Q

10

TOTAL I

5

0
–240 –200 –160 –120 –80 –40 0 40 80 120 160 200 240

I

(mA)

LOAD

Figure 7. IQ vs I

LOAD

1794 F07

11

LT1794

WUUU

APPLICATIO S I FOR ATIO

Figure 8 shows four examples of PCB metal being used for
heat spreading. These are provided as a reference for what
might be expected when using different combinations of
metal area on different layers of a PCB. These examples are
with a 4-layer board using 1oz copper on each. The most
effective layers for spreading heat are those closest to the
LT1794 junction. The LT1794IFE is used because the
small TSSOP package is most effective for very compact
line driver designs. This package also has an exposed
metal heat sinking pad on the bottom side which, when
soldered to the PCB top layer metal, directly conducts heat
away from the IC junction. Soldering the thermal pad to the

TOPOLOGY

EXAMPLE A

= 40°C/W

θ

JA

13MIL VIAS USED: 30

TOP LAYER 2nd LAYER 3rd LAYER BOTTOM LAYER VIA PATTERN

board produces a thermal resistance from junction to
case, θJC, of approximately 3°C/W.

Example A utilizes the most total metal area and provides
the lowest thermal resistance. Example B however uses
less metal on the top and bottom layers and still achieves
reasonable thermal performance. For the most compact
board design, inner layer metal can be used for heat
dissipation. This is shown in examples C and D where
minimum metal is used on the top and none on the bottom
layers, only the 2nd and 3rd layers have a heat-conducting
plane. Example C, with the larger metal areas performs
better.

EXAMPLE B

θ

= 47°C/W

JA

13MIL VIAS USED: 35

EXAMPLE C

θ

= 51°C/W

JA

13MIL VIAS USED: 32

EXAMPLE D

= 60°C/W

θ

JA

13MIL VIAS USED: 22

SCALE:

1794 F08

1 INCH

Figure 8. Examples of PCB Metal Used for Heat Dissipation. LT1794IFE Driver Mounted on Top Layer.
Heat Sink Pad Soldered to Top Layer Metal. External Components Mounted on Bottom Layer

12

WUUU

APPLICATIO S I FOR ATIO

LT1794

Similar results can be obtained with the LT1794CSW in the
wide SO-20 package. With this package heat is conducted
primarily through the V– pins, Pins 4 to 7 and 14 to 17;
these pins should be soldered directly to the PCB metal
plane.

Important Note: The metal planes used for heat sinking
the LT1794 are electrically connected to the negative
supply potential of the driver, typically –12V. These
planes must be isolated from any other power planes
used in the board design.

When PCB cards containing multiple ports are inserted
into a rack in an enclosed cabinet, it is often necessary to
provide airflow through the cabinet and over the cards.
This is also very effective in reducing the junction-to­ambient thermal resistance of each line driver. To a limit,
this thermal resistance can be reduced approximately
5°C/W for every 100lfpm of laminar airflow.

Layout and Passive Components

With a gain bandwidth product of 200MHz the LT1794
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors (i.e.,

0.1µF). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1µF to 10µF).

The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.

Figure␣ 9 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
parallel combination of RC and RG is less than or equal to
RF/9. For lowest distortion and DC output offset, a series
capacitor, CC, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by R

C

and CC should be less than 5MHz to minimize peaking.
Figure 10 shows compensation in the noninverting con-

figuration. The RC, CC network acts similarly to the invert­ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.

Another compensation scheme for noninverting circuits is
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + RF/RG at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + RF/RG at mid-band and for stability, a gain of 10 or
greater at high frequencies.

R

1

= 1 +

CCC

F

R

G

< 5MHz

1794 F10

O
I

V

(OPTIONAL)

V

O

V

V

(RC || RG) ≤ RF/9

2πR

I

R

C

C

C

R

G

+

–

R

F

Compensation

The LT1794 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.

R

F

–R

V

F

O

O

=

R

V

G

I

(RC || RG) ≤ RF/9

1

< 5MHz

2πR

CCC

1794 F09

R

V

I

(OPTIONAL)

G

R

C

C

C

–

+

Figure 9. Compensation for Inverting Gains

V

Figure 10. Compensation for Noninverting Gains

V

+

V

i

–

R

F

R

G

C

C

O

= 1 (LOW FREQUENCIES)

V

I

= 1 +

V

O

RG ≤ RF/9

1

< 5MHz

2πR

GCC

R

F

(HIGH FREQUENCIES)

R

G

Figure 11. Alternate Noninverting Compensation

1794 F11

13

LT1794

WUUU

APPLICATIO S I FOR ATIO

V

I

R

C

C

C

R

G

C

BIG

+

V

–

R

F

O

V

O

= 1 AT LOW FREQUENCIES

V

I

R

F

= 1 + AT MEDIUM FREQUENCIES

R

G

R

F

= 1 + AT HIGH FREQUENCIES

(RC || RG)

1794 F12

Figure 12. Combination Compensation

In differential driver applications, as shown on the first
page of this data sheet, it is recommended that the gain
setting resistor be comprised of two equal value resistors
connected to a good AC ground at high frequencies. This
ensures that the feedback factor of each amplifier remains
less than 0.1 at any frequency. The midpoint of the
resistors can be directly connected by ground, with the
resulting DC gain to the VOS of the amplifiers, or just
bypassed to ground with a 1000pF or larger capacitor.

Line Driving Back-Termination

The standard method of cable or line back-termination is
shown in Figure 13. The cable/line is terminated in its
characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.).
A back-termination resistor also equal to the chararacteristic
impedance should be used for maximum pulse fidelity of
outgoing signals, and to terminate the line for incoming
signals in a full-duplex application. There are three main
drawbacks to this approach. First, the power dissipated in
the load and back-termination resistors is equal so half of
the power delivered by the amplifier is wasted in the
termination resistor. Second, the signal is halved so the
gain of the amplifer must be doubled to have the same
overall gain to the load. The increase in gain increases
noise and decreases bandwidth (which can also increase
distortion). Third, the output swing of the amplifier is
doubled which can limit the power it can deliver to the load
for a given power supply voltage.

An alternate method of back-termination is shown in
Figure 14. Positive feedback increases the effective back­termination resistance so RBT can be reduced by a factor

CABLE OR LINE WITH

+

V

I

CHARACTERISTIC IMPEDANCE R

R

BT

–

R

F

R

G

RBT = R
V

O

=

V

I

L

1

(1 + RF/RG)

2

L

V

O

R

L

1794 F13

Figure 13. Standard Cable/Line Back Termination

R

P2

R

P1

V

I

+

R

V

V

P

A

–

R

F

R

G

FOR RBT =

()

V

V

R

L

n

R

R

P1

F

1 +

RP1 + R

R

()

P2

G

RP2/(RP2 + RP1)

1 + 1/n

O

=

I

–

R

F

1 +

R

()

G

BT

= 1 –

R

P1

RP2 + R

V

O

R

L

1794 F14

1
n

P1

Figure 14. Back Termination Using Postive Feedback

of n. To analyze this circuit, first ground the input. As RBT␣=
RL/n, and assuming RP2>>RL we require that:

VA = VO (1 – 1/n) to increase the effective value of
RBT by n.

VP = VO (1 – 1/n)/(1 + RF/RG)
VO = VP (1 + RP2/RP1)

Eliminating VP, we get the following:

(1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n)

For example, reducing RBT by a factor of n = 4, and with an
amplifer gain of (1 + RF/RG) = 10 requires that RP2/R

P1

=␣ 12.3.

14

WUUU

APPLICATIO S I FOR ATIO

LT1794

Note that the overall gain is increased:

/

V

O

=

V

I

+

11 1

// / /

()

[]

RRR

PPP

221

+

nRRRRR

()

FG P P P

+

()

−+

()

[]

12 1

A simpler method of using positive feedback to reduce the
back-termination is shown in Figure 15. In this case, the
drivers are driven differentially and provide complemen­tary outputs. Grounding the inputs, we see there is invert­ing gain of –RF/RP from –VO to V

A

VA = VO (RF/RP)

and assuming RP >> RL, we require

VA = VO (1 – 1/n)

solving

RF/RP = 1 – 1/n

So to reduce the back-termination by a factor of 3 choose
RF/RP = 2/3. Note that the overall gain is increased to:

VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)]

Using positive feedback is often referred to as active
termination.

Figure 17 shows a full-rate ADSL line driver incorporating
positive feedback to reduce the power lost in the back
termination resistors by 40% yet still maintains the proper
impedance match to the100Ω characteristic line imped­ance. This circuit also reduces the transformer turns ratio
over the standard line driving approach resulting in lower
peak current requirements. With lower current and less
power loss in the back termination resistors, this driver
dissipates only 1W of power, a 30% reduction.

While the power savings of positive feedback are attractive
there is one important system consideration to be ad­dressed, received signal sensitivity. The signal received
from the line is sensed across the back termination resis­tors. With positive feedback, signals are present on both
ends of the RBT resistors, reducing the sensed amplitude.
Extra gain may be required in the receive channel to
compensate, or a completely separate receive path may be
implemented through a separate line coupling transformer.

A demo board, DC306A, is available for the LT1794. This
demo board is a complete line driver with an LT1361
receiver included. It allows the evaluation of both standard
and active termination approaches. It also has circuitry
built in to evaluate the effects of operating with reduced
supply current.

V

+

I

–

R

G

R

P

R

R

–V

I

Figure 15. Back Termination Using Differential Postive Feedback

P

G

–

+

V

R

A

BT

R

F

R

F

R

BT

–V

A

1794 F15

V

O

R

FOR R

n =

R

L

V

R

O

L

V

I

–V

O

L

=

BT

n

1

R

F

1 –

R

P

R

R

F

F

+

1 +

R

R

G

=

P

R

F

1 –2

R

()

P

Considerations for Fault Protection

The basic line driver design, shown on the front page of
this data sheet, presents a direct DC path between the
outputs of the two amplifiers. An imbalance in the DC
biasing potentials at the noninverting inputs through
either a fault condition or during turn-on of the system can
create a DC voltage differential between the two amplifier
outputs. This condition can force a considerable amount
of current to flow as it is limited only by the small valued
back-termination resistors and the DC resistance of the
transformer primary. This high current can possibly cause
the power supply voltage source to drop significantly
impacting overall system performance. If left unchecked,
the high DC current can heat the LT1794 to thermal
shutdown.

15

LT1794

WUUU

APPLICATIO S I FOR ATIO

Using DC blocking capacitors, as shown in Figure 16, to
AC couple the signal to the transformer eliminates the
possibility for DC current to flow under any conditions.
These capacitors should be sized large enough to not
impair the frequency response characteristics required for
the data transmission.

Another important fault related concern has to do with
very fast high voltage transients appearing on the tele­phone line (lightning strikes for example). TransZorbs®,
varistors and other transient protection devices are often
used to absorb the transient energy, but in doing so also

12V

1000pF

+IN

110Ω

110Ω

+

LT1794

–

1/2

SHDN

1k

1k

create fast voltage transitions themselves that can be
coupled through the transformer to the outputs of the line
driver. Several hundred volt transient signals can appear
at the primary windings of the transformer with current
into the driver outputs limited only by the back termination
resistors. While the LT1794 has clamps to the supply rails
at the output pins, they may not be large enough to handle
the significant transient energy. External clamping diodes,
such as BAV99s, at each end of the transformer primary
help to shunt this destructive transient energy away from
the amplifier outputs.

TransZorb is a registered trademark of General Instruments, GSI

24.9k

12.7Ω

0.1µF

12V –12V

1:2

•

•

BAV99

LINE
LOAD

12.7Ω

0.1µF

12V –12V

1794 F16

BAV99

–IN

–

LT1794

+

1/2

SHDNREF

–12V

Figure 16. Protecting the Driver Against Load Faults and Line Transients

16

WW

SI PLIFIED SCHE ATIC

+

V

–IN

–

V

(one amplifier shown)

Q9

Q3

Q1

Q2

Q4

Q11

LT1794

Q10

Q13

Q17

Q7

R1

Q8

Q12

Q5

Q6

C1

Q14

+IN OUT

Q15

C2

Q18

Q16

1794 SS

17

LT1794

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation CA

4.95

(.195)

6.60 ±0.10

4.50 ±0.10

RECOMMENDED SOLDER PAD LAYOUT

0.09 – 0.20

(.0036 – .0079)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

0.65 BSC

4.30 – 4.50*
(.169 – .177)

0.45 – 0.75

(.018 – .030)

MILLIMETERS

(INCHES)

0.45

6.40 – 6.60*
(.252 – .260)

4.95

(.195)

20 1918 17 16 15

2.74

(.108)

±0.05

1.05 ±0.10

1345678910

2

° – 8°

0

0.65

(.0256)

BSC

0.195 – 0.30

(.0077 – .0118)

4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE

111214 13

2.74

(.108)

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

FE20 (CA) TSSOP 0203

6.40
BSC

18

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

SW Package

20-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

0.496 – 0.512*

(12.598 – 13.005)

19 18

20

16

17

14 13

15

LT1794

1112

NOTE 1

0.291 – 0.299**
(7.391 – 7.595)

0.010 – 0.029

(0.254 – 0.737)

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

*

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

**

NOTE 1

× 45°

0

0.016 – 0.050

(0.406 – 1.270)

0.093 – 0.104

(2.362 – 2.642)

° – 8° TYP

0.050

(1.270)

1

BSC

0.014 – 0.019

(0.356 – 0.482)

2345

TYP

6

78

0.394 – 0.419

(10.007 – 10.643)

910

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

S20 (WIDE) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1794

TYPICAL APPLICATIO

+IN

1000pF

182Ω

182Ω

U

+

LT1794

–

1/2

1k

1k

12V

24.9k

SHDN

1.65k

1.65k

13.7Ω

1:1.2*

•

•

100Ω
LINE

*COILCRAFT X8502-A OR EQUIVALENT
1W DRIVER POWER DISSIPATION

1.15W POWER CONSUMPTION

1794 F17

–IN

–

LT1794

+

1/2

13.7Ω

SHDNREF

–12V

Figure 17. ADSL Line Driver Using Active Termination

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1361 Dual 50MHz, 800V/µs Op Amp ±15V Operation, 1mV VOS, 1µA I
LTC®1563-2 Low Cost Active RC Lowpass Filter fC Up to 360kHz, Differential Operation, ±5V Supplies
LT1795 Dual 500mA, 50MHz Current Feedback Amplifier Shutdown/Current Set Function, ADSL CO Driver
LT1813 Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Low Noise, Low Power Differential Receiver, 4mA/Amplifier
LT1886 Dual 200mA, 700MHz Op Amp 12V Operation, 7mA/Amplifier, ADSL Modem Line Driver

B

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1794fs, sn1794 LT/TP 0501 4K • PRINTED IN THE USA

 LINEAR TECHN OLOGY CORPORATION 2001