LINEAR TECHNOLOGY LT1763 Technical data
Application Note 101
Minimizing Switching Regulator Residue
in Linear Regulator Outputs
Banishing Those Accursed Spikes
Jim Williams
July 2005
INTRODUCTION
Linear regulators are commonly employed to post-regulate
switching regulator outputs. Benefi ts include improved
stability, accuracy, transient response and lowered output
impedance. Ideally, these performance gains would be
accompanied by markedly reduced switching regulator
generated ripple and spikes. In practice, all linear regulators
encounter some diffi culty with ripple and spikes, particularly as frequency rises. This effect is magnifi ed at small
regulator V
to V
IN
differential voltages; unfortunate,
OUT
because such small differentials are desirable to maintain
effi ciency. Figure 1 shows a conceptual linear regulator
and associated components driven from a switching
regulator output.
The input fi lter capacitor is intended to smooth the ripple and
spikes before they reach the regulator. The output capacitor maintains low output impedance at higher frequencies,
improves load transient response and supplies frequency
compensation for some regulators. Ancillary purposes
include noise reduction and minimization of residual inputderived artifacts appearing at the regulators output. It is
this last category–residual input-derived artifacts–that is of
concern. These high frequency components, even though
small amplitude, can cause problems in noise-sensitive
video, communication and other types of circuitry. Large
numbers of capacitors and aspirin have been expended in
attempts to eliminate these undesired signals and their resultant effects. Although they are stubborn and sometimes
seemingly immune to any treatment, understanding their
origin and nature is the key to containing them.
Switching Regulator AC Output Content
Figure 2 details switching regulator dynamic (AC) output
content. It consists of relatively low frequency ripple at the
switching regulator’s clock frequency, typically 100kHz to
3MHz, and very high frequency content “spikes” associated with power switch transition times. The switching
regulator’s pulsed energy delivery creates the ripple. Filter
capacitors smooth the output, but not completely. The
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
INPUT DC + RIPPLE
AND SPIKES FROM
SWITCHING REGULATOR
FILTER
CAPACITOR
Figure 1. Conceptual Linear Regulator and Its Filter Capacitors
Theoretically Reject Switching Regulator Ripple and Spikes
LINEAR
IN OUT
REGULATOR
GND
PURE DC
OUTPUT
FILTER
CAPACITOR
AN101 F01
RIPPLE: TYPICALLY 100kHz to 3MHz
Figure 2. Switching Regulator Output Contains Relitively Low
Frequency Ripple and High Frequency “Spikes” Derived From
Regulators Pulsed Energy Delivery and Fast Transition Times
SWITCHING SPIKES: HARMONIC CONTENT
APPROACHING 100MHz
AN101 F02
an101f
AN101-1
Application Note 101
spikes, which often have harmonic content approaching
100MHz, result from high energy, rapidly switching power
elements within the switching regulator. The fi lter capacitor
is intended to reduce these spikes but in practice cannot
entirely eliminate them. Slowing the regulator’s repetition rate and transition times can greatly reduce ripple
and spike amplitude, but magnetics size increases and
1
effi ciency falls
. The same rapid clocking and fast switching that allows small magnetics size and high effi ciency
results in high frequency ripple and spikes presented to
the linear regulator.
Ripple and Spike Rejection
The regulator is better at rejecting the ripple than the very
wideband spikes. Figure 3 shows rejection performance
for an LT1763 low dropout linear regulator. There is 40db
attenuation at 100KHz, rolling off to about 25db at 1MHz.
The much more wideband spikes pass directly through the
regulator. The output fi lter capacitor, intended to absorb the
spikes, also has high frequency performance limitations.
The regulator and fi lter capacitors imperfect response,
due to high frequency parasitics, reveals Figure 1 to be
overly simplistic. Figure 4 restates Figure 1 and includes
the parasitic terms as well as some new components.
The fi gure considers the regulation path with emphasis on
high frequency parasitics. It is important to identify these
parasitic terms because they allow ripple and spikes to
propagate into the nominally regulated output. Additionally,
understanding the parasitic elements permits a measurement strategy, facilitating reduction of high frequency output content. The regulator includes high frequency parasitic
paths, primarily capacitive, across its pass transistor and
into its reference and regulation amplifi er. These terms
combine with fi nite regulator gain-bandwidth to limit high
frequency rejection. The input and output fi lter capacitors
include parasitic inductance and resistance, degrading their
effectiveness as frequency rises. Stray layout capacitance
provides additional unwanted feedthrough paths. Ground
potential differences, promoted by ground path resistance
and inductance, add additional error and also complicate
measurement. Some new components, not normally associated with linear regulators, also appear. These additions
include ferrite beads or inductors in the regulator input
and output lines. These components have their own high
frequency parasitic paths but can considerably improve
overall regulator high frequency rejection and will be addressed in following text.
Note 1: Circuitry employing this approach has achieved signifi cant harmonic content reduction at
some sacrifi ce in magnetics size and effi ciency. See Reference 1.
80
70
60
50
40
30
IL = 500mA
RIPPLE REJECTION (dB)
20
= V
V
IN
OUT(NOMINAL)
1V + 50mV
10
= 10µF
C
OUT
= 0.01µF
C
BYP
0
100 100k
10 1k 10k 1M
Figure 3. Ripple Rejection Characteristics for an LT1763 Low
Dropout Linear Regulator Show 40dB Attenuation at 100kHz,
Rolling Off Towards 1MHz. Switching Spike Harmonic Content
Approaches 100MHz; Passes Directly From Input to Output
+
RIPPLE
RMS
FREQUENCY (Hz)
AN101 F03
an101f
AN101-2
OUTPUT
LOAD
FILTER
*
CAPACITOR
AN101 F04
PARASITIC
L AND R
MONITORING
OSCILLOSCOPE
Application Note 101
PARASITIC C
PARASITIC
LAYOUT PARASITIC C
FERRITE BEAD
OR INDUCTOR
PARASITIC
FILTER
CAPACITOR
REF
PARASITIC
AND PSRR VS FREQUENCY)
REGULATOR (FINITE GAIN-BANDWIDTH
***
* = GROUND POTENTIAL DIFFERENCES PROMOTE OUTPUT HIGH FREQUENCY CONTENT AND CORRUPT MEASUREMENT.
PARASITIC C
AND SPIKES FROM
INPUT DC + RIPPLE
FERRITE BEAD
OR INDUCTOR
SWITCHING REGULATOR
L AND R
PARASITIC
Figure 4. Conceptual Linear Regulator Showing High Frequency Rejection Parasitics. Finite GBW and PSRR vs Frequency
Limit Regulator's High Frequency Rejection. Passive Components Attenuate Ripple and Spikes, But Parasitics Degrade
Effectiveness. Layout Capacitance and Ground Potential Differences Add Errors, Complicate Measurement
an101f
AN101-3
Application Note 101
SPIKE PATH
5V
74AHCO4
SPIKE GATING/BUFFER
30Ω
LOAD
AN101 F05
++
FBFB
REGULATOR
UNDER TEST
100Ω
Q1
SPIKE
AMPLITUDE
2N3866
100Ω
1k
5V
750Ω
5V
22µF
+
1Ω
L1
15V
A1
+
OUT
LT1763-3
IN
LT1210
OUT
C
0.01µF
SD GND BYP
IN
C
750Ω
750Ω
–15V
–
RIPPLE FREQUENCY AND
AMPLITUDE CONTROL
1.2V
OR EQUIVILENT
HP-3310A FUNCTION GENERATOR
5V
–
SPIKE GENERATOR
SYNC. DIFFERENTIATOR/
20pF
–1.2V
SYNC.
OUTPUT
LOW
OUTPUT
AMPLITUDE
SPIKE WIDTH
C1, 1/2
LT1712
1k
50Ω
DC/RIPPLE PATH
LT1712
+
–
–5V
–5V
100k*
0.01µF
+
0.1µF
5V
100k*
1k
C2, 1/2
–
A2
LT1006
+
2k*2k*
+
10µF
50Ω
RAMPS
P-P
TO 0.1V
P-P
TYP 0.01V
BIAS INPUT
REGULATOR DC
TYP 3.3V to 3.5V
= SEE TEXT
= SEE TEXT
IN
* = 1% METAL FILM RESISTOR
L1 = 4 TURNS #26, 1/4" DIAMETER
OUT
FB = FERRITE BEAD. FAIR-RITE 2743002122. INDUCTORS OPTIONAL. SEE TEXT
= IN4148
C
C
Figure 5. Circuit Simulates Switching Regulator Output. DC, Ripple Amplitude, Frequency and Spike Duration/Height are
Independantly Settable. Split Path Scheme Sums Wideband Spikes with DC and Ripple, Presenting Linear Regulator with Simulated
Switching Regulator Output. Function Generator Sources Waveforms to Both Paths
AN101-4
2.5V
LT1460
5V
an101f
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