Stable with Aluminum, Tantalum or
Ceramic Capacitors
■
Reverse Battery Protected
■
No Reverse Current
■
No Protection Diodes Needed
■
Overcurrent and Overtemperature Protected
■
Available in Tiny 5-Lead SOT-23 Package
U
APPLICATIO S
■
Cellular Phones
■
Pagers
■
Battery-Powered Systems
■
Frequency Synthesizers
■
Wireless Modems
LT1761 Series
100mA, Low Noise,
LDO Micropower
Regulators in SOT-23
U
DESCRIPTIO
The LT®1761 series are micropower, low noise, low
dropout regulators. With an external 0.01μF bypass
capacitor, output noise drops to 20μV
100kHz bandwidth. Designed for use in battery-powered
systems, the low 20μA quiescent current makes them an
ideal choice. In shutdown, quiescent current drops to less
than 0.1μA. The devices are capable of operating over an
input voltage from 1.8V to 20V, and can supply 100mA of
output current with a dropout voltage of 300mV. Quiescent current is well controlled, not rising in dropout as it
does with many other regulators.
The LT1761 regulators are stable with output capacitors
as low as 1μF. Small ceramic capacitors can be used
without the series resistance required by other regulators.
Internal protection circuitry includes reverse battery protection, current limiting, thermal limiting and reverse
current protection. The device is available in fixed output
voltages of 1.2V, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V, 3.3V and
5V, and as an adjustable device with a 1.22V reference
voltage. The LT1761 regulators are available in the 5-lead
SOT-23 package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
over a 10Hz to
RMS
TYPICAL APPLICATIO
5V Low Noise Regulator
V
5.4V TO
20V
IN
1μF
IN
SHDN
OUT
LT1761-5
BYP
GND
U
0.01μF
+
5V AT100mA
20μV
10μF
RMS
NOISE
1761 TA01
V
OUT
100μV/DIV
10Hz to 100kHz Output Noise
1761 G48
20μV
RMS
1761sfc
1
LT1761 Series
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
IN Pin Voltage ........................................................ ±20V
OUT Pin Voltage .................................................... ±20V
Input to Output Differential Voltage ....................... ±20V
ADJ Pin Voltage ...................................................... ±7V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1761 regulators are tested and specified under pulse load
conditions such that T
= 25°C. Performance at –40°C and 125°C is assured by design,
T
A
≈ TA. The LT1761E is 100% production tested at
J
characterization and correlation with statistical process controls. The
LT1761MP is 100% tested and guaranteed over the –55°C to 125°C
temperature range.
Note 3: The LT1761 (adjustable versions) are tested and specified for
these conditions with the ADJ pin connected to the OUT pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT1761
(adjustable version) is tested and specified for these conditions with an
external resistor divider (two 250k resistors) for an output voltage of
2.44V. The external resistor divider will add a 5μA DC load on the output.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: VIN – V
Note 7: GND pin current is tested with V
DROPOUT
= V
IN
.
OUT(NOMINAL)
or VIN = 2.3V
(whichever is greater) and a current source load. This means the device is
tested while operating in its dropout region or at the minimum input
voltage specification. This is the worst-case GND pin current. The GND pin
current will decrease slightly at higher input voltages.
Note 8: ADJ pin bias current flows into the ADJ pin.
Note 9: SHDN pin current flows into the SHDN pin.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT1761, LT1761-1.2, LT1761-1.5, LT1761-1.8 and
LT1761-2 dropout voltage will be limited by the minimum input voltage
specification under some output voltage/load conditions. See the curve of
Minimum Input Voltage in the Typical Performance Characteristics.
Note 12: To satisfy requirements for minimum input voltage, current limit
is tested at V
IN (Pin 1): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if the
device is more than six inches away from the main input
filter capacitor. In general, the output impedance of a
battery rises with frequency, so it is advisable to include a
bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1μF to 10μF is sufficient. The
LT1761 regulators are designed to withstand reverse
voltages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if a
battery is plugged in backwards, the device will act as if
there is a diode in series with its input. There will be no
reverse current flow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
GND (Pin 2): Ground.
SHDN (Pin 3, Fixed/-SD Devices): Shutdown. The SHDN
pin is used to put the LT1761 regulators into a low power
shutdown state. The output will be off when the SHDN pin
is pulled low. The SHDN pin can be driven either by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current of
the open-collector gate, normally several microamperes,
and the SHDN pin current, typically 1μA. If unused, the
SHDN pin must be connected to V
. The device will not
IN
function if the SHDN pin is not connected. For the
LT1761-BYP, the SHDN pin is internally connected to V
BYP (Pins 3/4, Fixed/-BYP Devices): Bypass. The BYP
pin is used to bypass the reference of the LT1761 regulators to achieve low noise performance from the regulator.
The BYP pin is clamped internally to ±0.6V (one VBE) from
ground. A small capacitor from the output to this pin will
bypass the reference to lower the output voltage noise. A
maximum value of 0.01μF can be used for reducing output
voltage noise to a typical 20μV
bandwidth. If not used, this pin must be left unconnected.
ADJ (Pin 4, Adjustable Devices Only): Adjust Pin. For the
adjustable LT1761, this is the input to the error amplifier.
This pin is internally clamped to ±7V. It has a bias current
of 30nA which flows into the pin (see curve of ADJ Pin Bias
Current vs Temperature in the Typical Performance Characteristics section). The ADJ pin voltage is 1.22V referenced
to ground and the output voltage range is 1.22V to 20V.
OUT (Pin 5): Output. The output supplies power to the
load. A minimum output capacitor of 1μF is required to
prevent oscillations. Larger output capacitors will be
required for applications with large transient loads to limit
peak voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
over a 10Hz to 100kHz
RMS
IN
.
1761sfc
13
LT1761 Series
WUUU
APPLICATIO S I FOR ATIO
The LT1761 series are 100mA low dropout regulators with
micropower quiescent current and shutdown. The devices
are capable of supplying 100mA at a dropout voltage of
300mV. Output voltage noise can be lowered to 20μV
RMS
over a 10Hz to 100kHz bandwidth with the addition of a
0.01μF reference bypass capacitor. Additionally, the refer-
ence bypass capacitor will improve transient response of
the regulator, lowering the settling time for transient load
conditions. The low operating quiescent current (20μA)
drops to less than 1μA in shutdown. In addition to the low
quiescent current, the LT1761 regulators incorporate several protection features which make them ideal for use in
battery-powered systems. The devices are protected
against both reverse input and reverse output voltages. In
battery backup applications where the output can be held
up by a backup battery when the input is pulled to ground,
the LT1761-X acts like it has a diode in series with its
output and prevents reverse current flow. Additionally, in
dual supply applications where the regulator load is
returned to a negative supply, the output can be pulled
below ground by as much as 20V and still allow the device
to start and operate.
Adjustable Operation
The adjustable version of the LT1761 has an output
voltage range of 1.22V to 20V. The output voltage is set by
the ratio of two external resistors as shown in Figure 1. The
device servos the output to maintain the ADJ pin voltage
at 1.22V referenced to ground. The current in R1 is then
equal to 1.22V/R1 and the current in R2 is the current in R1
plus the ADJ pin bias current. The ADJ pin bias current,
30nA at 25°C, flows through R2 into the ADJ pin. The
output voltage can be calculated using the formula in
Figure 1. The value of R1 should be no greater than 250k
to minimize errors in the output voltage caused by the ADJ
pin bias current. Note that in shutdown the output is turned
off and the divider current will be zero. Curves of ADJ
Pin Voltage vs Temperature and ADJ Pin Bias Current
vs Temperature appear in the Typical Performance
Characteristics.
The adjustable device is tested and specified with the ADJ
pin tied to the OUT pin for an output voltage of 1.22V.
Specifications for output voltages greater than 1.22V will
be proportional to the ratio of the desired output voltage to
1.22V: V
/1.22V. For example, load regulation for an
OUT
output current change of 1mA to 100mA is –1mV typical
at V
= 1.22V. At V
OUT
= 12V, load regulation is:
OUT
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT1761 regulators may be used with the addition of a
bypass capacitor from V
to the BYP pin to lower output
OUT
voltage noise. A good quality low leakage capacitor is recommended. This capacitor will bypass the reference of the
regulator, providing a low frequency noise pole. The noise
pole provided by this bypass capacitor will lower the output voltage noise to as low as 20μV
with the addition
RMS
of a 0.01μF bypass capacitor. Using a bypass capacitor has
the added benefit of improving transient response. With no
bypass capacitor and a 10μF output capacitor, a 10mA to
100mA load step will settle to within 1% of its final value
in less than 100μs. With the addition of a 0.01μF bypass
capacitor, the output will stay within 1% for a 10mA to
100mA load step (see LT1761-5 Transient Response in
Typical Performance Characteristics section). However,
regulator start-up time is inversely proportional to the size
of the bypass capacitor, slowing to 15ms with a 0.01μF
bypass capacitor and 10μF output capacitor.
14
IN
V
IN
OUT
LT1761
ADJ
GND
Figure 1. Adjustable Operation
R2
R1
1761 F01
V
OUT
+
VV
VV
InA
ADJ
OUTPUT RANGE = 1.22V TO 20V
⎛
⎞
R
2
=+
122 1
.
OUTADJ
ADJ
⎜
⎝
=
122
.
=°
30
AT 25 C
IR
+
()()
⎟
R
1
⎠
2
1761sfc
WUUU
APPLICATIO S I FOR ATIO
LT1761 Series
Output Capacitance and Transient Response
The LT1761 regulators are designed to be stable with a
wide range of output capacitors. The ESR of the output
capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 1μF with an
ESR of 3Ω or less is recommended to prevent oscillations. The LT1761-X is a micropower device and output
transient response will be a function of output capacitance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used
to decouple individual components powered by the
LT1761-X, will increase the effective output capacitor
value. With larger capacitors used to bypass the reference (for low noise operation), larger values of output
capacitors are needed. For 100pF of bypass capacitance,
2.2μF of output capacitor is recommended. With a 330pF
4.0
3.5
3.0
2.5
2.0
ESR (Ω)
C
1.5
BYP
C
1.0
0.5
0
1
STABLE REGION
= 0
= 100pF
BYP
C
= 330pF
BYP
C
> 3300pF
BYP
310
245
OUTPUT CAPACITANCE (μF)
Figure 2. Stability
6
9
78
1761 F02
bypass capacitor or larger, a 3.3μF output capacitor is
recommended. The shaded region of Figure 2 defines the
region over which the LT1761 regulators are stable. The
minimum ESR needed is defined by the amount of bypass
capacitance used, while the maximum ESR is 3Ω.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V
dielectrics are good for providing high capacitances in a
small package, but they tend to have strong voltage and
temperature coefficients as shown in Figures 3 and 4.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be significant enough
to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verified.
20
0
–20
–40
–60
CHANGE IN VALUE (%)
–80
–100
0
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
X5R
Y5V
26
4
8
DC BIAS VOLTAGE (V)
14
12
10
16
1761 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
20
0
–20
–40
–60
CHANGE IN VALUE (%)
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
–50
–250
2575
TEMPERATURE (°C)
X5R
Y5V
50100 125
1761 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
1761sfc
15
LT1761 Series
U
WUU
APPLICATIONS INFORMATION
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capacitor produced Figure 5’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components:
1. Output current multiplied by the input/output voltage
differential: (I
2. GND pin current multiplied by the input voltage:
(I
)(VIN).
GND
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the
sum of the two components listed above.
)(VIN – V
OUT
OUT
), and
The LT1761 series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions, the maximum
junction temperature rating of 125°C must not be
exceeded. It is important to give careful consideration to
all sources of thermal resistance from junction to ambient.
Additional heat sources mounted nearby must also be
considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by power devices.
The following table lists thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. Measured Thermal Resistance
COPPER AREATHERMAL RESISTANCE
TOPSIDE*BACKSIDEBOARD AREA(JUNCTION-TO-AMBIENT)
2500mm22500mm
1000mm22500mm
2
225mm
100mm
50mm
*Device is mounted on topside.
2500mm
2
2500mm
2
2500mm
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2
2
2
2
2
125°C/W
125°C/W
130°C/W
135°C/W
150°C/W
16
LT1761-5
C
= 10μF
OUT
= 0.01μF
C
BYP
= 100mA
I
LOAD
V
OUT
500μV/DIV
100ms/DIV 1761 F05
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
1761sfc
WUUU
APPLICATIO S I FOR ATIO
LT1761 Series
Calculating Junction Temperature
Example: Given an output voltage of 3.3V, an input voltage
range of 4V to 6V, an output current range of 0mA to 50mA
and a maximum ambient temperature of 50°C, what will
the maximum junction temperature be?
The power dissipated by the device will be equal to:
I
OUT(MAX)(VIN(MAX)
where,
I
OUT(MAX)
V
IN(MAX)
I
GND
So,
P = 50mA(6V – 3.3V) + 1mA(6V) = 0.14W
The thermal resistance will be in the range of 125°C/W to
150°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
0.14W(150°C/W) = 21.2°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
JMAX
= 50mA
= 6V
at (I
OUT
= 50°C + 21.2°C = 71.2°C
– V
= 50mA, VIN = 6V) = 1mA
OUT
) + I
GND(VIN(MAX)
)
Protection Features
The LT1761 regulators incorporate several protection
features which make them ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
20V. Current flow into the device will be limited to less than
1mA (typically less than 100μA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
which can be plugged in backward.
The output of the LT1761-X can be pulled below ground
without damaging the device. If the input is left open
circuit or grounded, the output can be pulled below ground
by 20V. For fixed voltage versions, the output will act
like a large resistor, typically 500kΩ or higher, limiting
current flow to typically less than 100μA. For adjustable
versions, the output will act like an open circuit; no
current will flow out of the pin. If the input is powered by
a voltage source, the output will source the short-circuit
current of the device and will protect itself by thermal
limiting. In this case, grounding the SHDN pin will turn
off the device and stop the output from sourcing the
short-circuit current.
The ADJ pin of the adjustable device can be pulled above
or below ground by as much as 7V without damaging the
device. If the input is left open circuit or grounded, the ADJ
pin will act like an open circuit when pulled below ground
and like a large resistor (typically 100k) in series with a
diode when pulled above ground.
In situations where the ADJ pin is connected to a resistor
divider that would pull the ADJ pin above its 7V clamp
voltage if the output is pulled high, the ADJ pin input
current must be limited to less than 5mA. For example, a
resistor divider is used to provide a regulated 1.5V output
1761sfc
17
LT1761 Series
WUUU
APPLICATIO S I FOR ATIO
from the 1.22V reference when the output is forced to 20V.
The top resistor of the resistor divider must be chosen to
limit the current into the ADJ pin to less than 5mA when the
ADJ pin is at 7V. The 13V difference between output and
ADJ pin divided by the 5mA maximum current into the ADJ
pin yields a minimum top resistor value of 2.6k.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage or is left open
100
TJ = 25°C
= 0V
V
90
IN
CURRENT FLOWS
80
INTO OUTPUT PIN
V
OUT
70
(LT1761-BYP, -SD)
60
50
40
30
LT1761-3
20
REVERSE OUTPUT CURRENT (μA)
10
0
0123
= V
LT1761-2.5
LT1761-2.8
LT1761-1.2
ADJ
LT1761-1.5
LT1761-1.8
LT1761-2
4
OUTPUT VOLTAGE (V)
circuit. Current flow back into the output will follow the
curve shown in Figure 6.
When the IN pin of the LT1761-X is forced below the OUT
pin or the OUT pin is pulled above the IN pin, input current
will typically drop to less than 2μA. This can happen if the
input of the device is connected to a discharged (low
voltage) battery and the output is held up by either a
backup battery or a second regulator circuit. The state of
the SHDN pin will have no effect on the reverse output
current when the output is pulled above the input.
LT1761-BYP
LT1761-SD
LT1761-5
5
LT1761-3.3
678910
1761 F06
Figure 6. Reverse Output Current
1761sfc
18
PACKAGE DESCRIPTIO
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302 REV B
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LT1761 Series
U
S5 Package
5-Lead Plastic TSOT-23
(LTC DWG # 05-08-1635)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.