FEATURES
I
LOAD
(A)
0
V
OUT
(V)
5.00
1725 F10b
4.75
0.5
1.0
1.5
2.0
5.25
VIN = 36V
VIN = 72V
VIN = 48V
LT1725
General Purpose
Isolated Flyback Controller
U
DESCRIPTIO
■
Drives External Power MOSFET with External
Resistor
I
SENSE
■
Application Input Voltage Limited Only by
External Power Components
■
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
■
Accurate Regulation Without User Trims
■
Regulation Maintained Well into Discontinuous Mode
■
Switching Frequency from 50kHz to 250kHz with
External Capacitor
■
Optional Load Compensation
■
Optional Undervoltage Lockout
■
Available in 16-Pin SO and SSOP Packages
U
APPLICATIO S
■
Telecom Isolated Converters
■
Offline Isolated Power Supplies
■
Instrumentation Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The LT®1725 is a monolithic switching regulator controller specifically designed for the isolated flyback topology.
It drives the gate of an external MOSFET and is generally
powered from a third transformer winding. These features
allow for an application input voltage limited only by
external power path components. The third transformer
winding also provides output voltage feedback information, such that an optoisolator is not required. Its gate
drive capability coupled with a suitable external MOSFET
can deliver load power up to tens of watts.
The LT1725 has a number of features not found on most
other switching regulator ICs. By utilizing current mode
switching techniques, it provides excellent AC and DC line
regulation. Its unique control circuitry can maintain regulation well into discontinuous mode in most applications.
Optional load compensation circuitry allows for improved
load regulation. An optional undervoltage lockout pin
halts operation when the application input voltage is too
low. An optional external capacitor implements a softstart function. A 3V output is available at up to several mA
for powering primary side application circuitry.
TYPICAL APPLICATIO
35.7k
1%
3.01k
1%
1nF
47pF
51k
51k
51k
2.7k
0.1µF
3V
OUT
FB
SFST
VC
OSCAP
t
ON
ENDLY
MENAB
R
OCMP
R
CMPC
SGND PGND
LT1725
UVLO
I
SENSE
U
48V to Isolated 5V Converter
V
36V TO 72V
V
GATE
BAS16
22Ω
CC
+
15µF
100pF
47k
820k
33k
IN
1µF
1.5µF
68Ω
150pF
CTX02-14989
6
1
2
4
IRF620
0.18Ω
1725 TA01a
9
11
10
12
18Ω
12CWQ06
150µF
470pF
+
51Ω
1W
V
OUT
I
OUT
= 5V
= 0 to 2A
Output Load Regulation
1725fa
1
LT1725
PACKAGE/ORDER I FOR ATIO
UU
W
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
VCC Supply Voltage ................................................. 22V
UVLO Pin Voltage .................................................... V
I
Pin Voltage .................................................... 2V
SENSE
FB Pin Current ..................................................... ± 2mA
Operating Junction
Temperature Range
LT1725C .............................................. 0°C to 100°C
LT1725I ........................................... –40°C TO 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
CC
TOP VIEW
1
PGND
2
I
SENSE
3
SFST
4
R
OCMP
5
R
CMPC
6
OSCAP
7
V
C
8
FB
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 125°C, θJA = 110°C/W (GN)
JMAX
= 125°C, θJA = 100°C/W (SO)
T
JMAX
16
GATE
15
V
CC
14
t
ON
13
ENDLY
12
MINENAB
11
SGND
10
UVLO
9
3V
OUT
S PACKAGE
16-LEAD PLASTIC SO
ORDER PART NUMBER
LT1725CGN
LT1725IGN
GN PART MARKING
1725
1725I
LT1725CS
LT1725IS
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
I
CC
Feedback Amplifier
V
FB
I
FB
g
m
I
, I
SRC
V
CL
VCC Turn-On Voltage
V
Turn-Off Voltage
CC
Hysteresis (Note 3) (V
V
CC
Supply Current VC = Open
Start-Up Current
Feedback Voltage 1.230 1.245 1.260 V
Feedback Pin Input Current 500 nA
Feedback Amplifier Transconductance ∆lC = ±10µA
Feedback Amplifier Source or Sink Current
SNK
Feedback Amplifier Clamp Voltage 2.5 V
Reference Voltage/Current Line Regulation 12V ≤ VIN ≤ 18V
Voltage Gain VC = 1V to 2V 2000 V/V
Soft-Start Charging Current V
Soft-Start Discharge Current V
The ● denotes specifications which apply over the full operating
= 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
A
●
14.0 15.1 16.0 V
●
8 9.7 11 V
– V
TURN-ON
= 0V 25 40 50 µA
SFST
= 1.5V, V
SFST
)
TURN-OFF
= 0V 0.8 1.5 mA
UVLO
●
4.0 5.4 6.5 V
●
61015mA
●
●
1.220 1.270 V
●
400 1000 1800 µmho
●
30 50 80 µA
●
120 280 µA
0.01 0.05 %/V
2
1725fa
LT1725
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes specifications which apply over the full operating
= 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Output
V
GATE
I
GATE
t
r
t
f
Output High Level I
Output Low Level I
Output Sink Current in Shutdown, V
UVLO
= 0V V
GATE
I
GATE
GATE
I
GATE
GATE
= 100mA
= 500mA
= 100mA
= 500mA
= 2V
●
11.5 12.1 V
●
11.0 11.8 V
●
●
●
1.2 2.5 mA
0.3 0.45 V
0.6 1.0 V
Rise Time CL = 1000pF 30 ns
Fall Time CL = 1000pF 30 ns
Current Amplifier
V
C
V
ISENSE
Control Pin Threshold Duty Cycle = Min 0.90 1.12 1.25 V
●
0.80 1.35 V
Switch Current Limit Duty Cycle ≤ 30% 220 250 270 mV
●
Duty Cycle ≤ 30%
200 280 mV
Duty Cycle = 80% 220 mV
∆V
ISENSE
/∆V
C
0.30 mV
Timing
f Switching Frequency C
C
OSCAP
t
ON
t
ED
t
EN
R
t
Oscillator Capacitor Value (Note 2) 33 200 pF
Minimum Switch On Time R
Flyback Enable Delay Time R
Minimum Flyback Enable Time R
Timing Resistor Value (Note 2) 24 200 kΩ
Maximum Switch Duty Cycle
= 100pF 90 100 115 kHz
OSCAP
= 50k 200 ns
tON
= 50k 200 ns
ENDLY
= 50k 200 ns
MENAB
●
80 125 kHz
●
85 90 %
Load Compensation
Sense Offset Voltage 25mV
Current Gain Factor 0.80 0.95 1.05 mV
UVLO Function
V
UVLO
I
UVLO
UVLO Pin Threshold
UVLO Pin Bias Current V
●
1.21 1.25 1.29 V
= 1.2V –0.25 + 0.1 +0.25 µA
UVLO
V
= 1.3V –4.50 – 3.5 –2.50 µA
UVLO
3V Output Function
V
REF
Reference Output Voltage I
LOAD
= 1mA
●
2.8 3.0 3.2 V
Output Impedance 10 Ω
Current Limit
●
815 mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: Component value range guaranteed by design.
Note 3: The V
turn-on/turn-off voltages and hysteresis voltage are
CC
proportional in magnitude to each other-guaranteed by design.
1725fa
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LT1725
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Hysteresis Voltage vs
VCC Turn-On Voltage vs
Temperature
16.00
V
CC
Temperature Start-Up Current vs Temperature
6.50
250
15.75
15.50
15.25
15.00
TURN-ON VOLTAGE (V)
14.75
CC
V
14.50
14.25
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
Supply Current vs Temperature
13
12
11
10
SUPPLY CURRENT (mA)
9
1725 G01
6.25
6.00
5.75
5.50
5.25
HYSTERESIS VOLTAGE (V)
CC
V
5.00
4.75
–50
–25 0
25 75
TEMPERATURE (°C)
UVLO Pin Input Current vs
Temperature
1
V
0
–1
–2
–3
–4
UVLO PIN INPUT CURRENT (µA)
–5
UVLO
V
UVLO
50 100 125
= 1.2V
= 1.3V
1725 G02
200
150
100
START-UP CURRENT (µA)
50
0
–50
–25
25
0
TEMPERATURE (°C)
Oscillator Frequency vs
Temperature
115
110
105
100
95
OSCILLATOR FREQUENCY (kHz)
90
50
75
100
125
1725 G03
(V)
V
4
1.0
0.8
0.6
GATE
0.4
0.2
8
–50
0
–25
TEMPERATURE (°C)
50
25
75
100
125
1725 G04
–6
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
1725 G05
85
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
1725 G06
VC Clamp Voltage, Switching
–0.5
–1.0
(V)
GATE
–1.5
-V
CC
V
–2.0
–2.5
–3.0
VCC-V
0
1
V
vs I
GATE
0
1
SINK
TA = 125°C
TA = 25°C
TA = –55°C
10 100 1000
I
(mA)
SINK
1725 G07
GATE
TA = –55°C
vs I
SOURCE
TA = 125°C
TA = 25°C
10 100 1000
I
(mA)
SOURCE
1725 G08
Threshold vs Temperature
3.0
2.5
2.0
1.5
1.0
SWITCHING THRESHOLD
0.5
CLAMP VOLTAGE, SWITCHING THRESHOLD (V)
C
0
V
–50
–25 0
TEMPERATURE (°C)
CLAMP VOLTAGE
50 100 125
25 75
1725 G09
1725fa
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LT1725
Minimum Switch-On Time vs
Temperature
275
R
= 50k
TON
250
225
200
175
150
MINIMUM SWITCH-ON TIME (ns)
125
–50
–25 0
25 75
TEMPERATURE (°C)
Feedback Amplifier Output Current
vs FB Pin Voltage
80
60
40
TA = 25°C
20
0
–20
–40
–60
FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)
–80
1.05
Minimum Enable Time vs
Temperature
275
R
MINENAB
250
225
200
175
MINIMUM ENABLE TIME (ns)
150
50 100 125
1725 G10
TA = –55°C
1.15 1.25
1.10 1.20 1.30 1.40
FB PIN VOLTAGE (V)
125
–50
TA = 125°C
1.35
1725 G13
= 50k
–25 0
50 100 125
25 75
TEMPERATURE (°C)
Enable Delay Time vs
Temperature
275
250
225
200
175
ENABLE DELAY TIME (ns)
150
125
–50
–25 0
1725 G11
Feedback Amplifier
Transconductance vs Temperature
1600
1400
1200
1000
800
600
400
200
FEEDBACK AMPLIFIER TRANSCONDUCTANCE (µmho)
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
50 100 125
25 75
TEMPERATURE (°C)
1725 G14
1725 G12
Soft-Start Charging Current vs
Temperature
60
50
40
30
20
10
SOFT-START CHARGING CURRENT (µA)
0
–50
–25 0
TEMPERATURE (°C)
50 100 125
25 75
V(SFST) = 0V
1725 G15
Soft-Start Sink Current vs
Temperature
2.5
2.0
1.5
1.0
0.5
SOFT-START SINK CURRENT (mA)
0
–50
–25
25
0
TEMPERATURE (°C)
V(SFST) = 1.5V
50
75
100
125
1725 G16
1725fa
5
LT1725
U
UU
PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanoseconds. It should be connected directly to a good quality
ground plane.
I
(Pin 2): Pin to measure switch current with exter-
SENSE
nal sense resistor. The sense resistor should be of a
noninductive construction as high speed performance is
essential. Proper grounding technique is also required to
avoid distortion of the high speed current waveform. A
preset internal limit of nominally 250mV at this pin effects
a switch current limit.
SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function. See Applications Information for details.
(Pin 4): Input pin for optional external load compen-
R
OCMP
sation resistor. Use of this pin allows nominal compensation for nonzero output impedance in the power transformer
secondary circuit, including secondary winding impedance,
output Schottky diode impedance and output capacitor
ESR. In less demanding applications, this resistor is not
needed. See Applications Information for more details.
R
(Pin 5): Pin for external filter capacitor for optional
CMPC
load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applications Information for further details.
OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Information for details.
VC (pin 7): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a capacitor between this node and ground.
FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal
bandgap (V
) reference, times the effective output-to-
BG
third winding transformer turns ratio is the primary determinant of the output voltage. The Thevenin equivalent
resistance of the feedback divider should be roughly 3k.
See Applications Information for more details.
3V
(Pin 9): Output pin for nominal 3V reference. This
OUT
facilitates various user applications. This node is internally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.
UVLO (Pin 10): This pin allows the use of an optional
external resistor divider to set an undervoltage lockout
based upon V
sufficient to allow the part to start up, but the UVLO pin is
held below its threshold, output switching action will be
disabled, but the part will draw its normal quiescent
current from V
oscillation action on the V
“trickle-charge” bootstrapped configuration.)
The bias current on this pin is a function of the state of the
UVLO comparator; as the threshold is exceeded, the bias
current increases. This creates a hysteresis band equal to
the change in bias current times the Thevenin impedance
of the user’s resistive divider. The user may thereby adjust
the impedance of the UVLO divider to achieve a desired
degree of hysteresis. A 100pF capacitor to ground is
recommended on this pin. See Applications Information
for details.
SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FB pin, OSCAP capacitor and the VC compensation capacitor free of large ground currents.
MINENAB (Pin 12): Pin for external programming resistor
to set minimum enable time. See Applications Information
for details.
(not VCC) level. (Note: If the VCC voltage is
IN
. This typically causes a benign relaxation
CC
pin in the conventional
CC
6
1725fa
LT1725
U
UU
PI FU CTIO S
ENDLY (Pin 13): Pin for external programming resistor to
set enable delay time. See Applications Information for
details.
tON (Pin 14): Pin for external programming resistor to set
switch minimum on time. See Applications Information
for details.
W
BLOCK DIAGRA
V
CC
3V
UVLO
BIAS
OUT
3V REG
(INTERNAL)
VCC (Pin 15): Supply voltage for the LT1725. Bypass this
pin to ground with 1µF or more.
GATE (Pin 16): This is the gate drive to the external power
MOSFET switch and has large dynamic currents flowing
through it. Keep the trace to the MOSFET as short as
possible to minimize electromagnetic radiation and voltage spikes. A series resistance of 5Ω or more may help to
dampen ringing in less than ideal layouts.
OSCAP
FB
OSC
FDBK
MINENABt
ON
LOGIC
V
C
ENDLY
MOSFET
DRIVER
PGND
COMP
SOFT-START
SFST R
COMPENSATION
R
OCMP
LOAD
I
AMP
CMPC
1725 BD
GATE
I
SENSE
SGND
1725fa
7
LT1725
UWW
TI I G DIAGRA
V
SW
VOLTAGE
V
IN
GND
SWITCH
STATE
OFF ON
MINIMUM t
ON
FLYBACK AMP
STATE
ENABLE DELAY
MINIMUM ENABLE TIME
V
FLBK
OFF ON
ENABLEDDISABLED DISABLED
0.80×
V
FLBK
COLLAPSE
DETECT
1725 TD
W
FLYBACK ERROR A PLIFIER
V
IN
M1
R1
FB
Q1 Q2
R2
I
T1
•
D1
+
+
C1
•
ISOLATED
V
OUT
–
•
I
M
V
BG
I
FXD
V
C
ENAB
C2
I
M
1725 EA
8
1725fa
OPERATIO
LT1725
U
The LT1725 is a current mode switcher controller IC
designed specifically for the isolated flyback topology. The
Block Diagram shows an overall view of the system. Many
of the blocks are similar to those found in traditional
designs, including: Internal Bias Regulator, Oscillator,
Logic, Current Amplifier and Comparator, Driver and Output Switch. The novel sections include a special Flyback
Error Amplifier and a Load Compensation mechanism.
Also, due to the special dynamic requirements of flyback
control, the Logic system contains additional functionality
not found in conventional designs.
The LT1725 operates much the same as traditional current
mode switchers, the major difference being a different
type of error amplifier that derives its feedback information from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is Application
Note AN19.
ERROR AMPLIFIER—PSEUDO DC THEORY
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when MOSFET output
switch M1 turns off, its drain voltage rises above the V
rail. The amplitude of this flyback pulse as seen on the third
winding is given as:
V
FLBK
V V I ESR
++
()
OUT F SEC
=
N
•
ST
IN
The relatively high gain in the overall loop will then cause
the voltage at the FB pin to be nearly equal to the bandgap
reference V
may then be expressed as:
V
FLBK BG
Combination with the previous V
expression for V
programming resistors, transformer turns ratio and diode
forward voltage drop:
VV
OUT BG ST F SEC
Additionally, it includes the effect of nonzero secondary
output impedance, which is discussed below in further
detail, see Load Compensation Theory. The practical aspects of applying this equation for V
Applications Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dotted line connections to the
block labeled “ENAB”. Timing signals are then required to
enable and disable the flyback amplifier.
ERROR AMPLIFIER—DYNAMIC THEORY
. The relationship between V
BG
RR
+
12
()
=
R
=
V
2
FLBK
in terms of the internal reference,
OUT
12
RR
+
()
2
R
–– •
NVIESR
()
expression yields an
are found in the
OUT
FLBK
and V
BG
VF = D1 forward voltage
I
= transformer secondary current
SEC
ESR = total impedance of secondary circuit
NST = transformer effective secondary-to-third
winding turns ratio
The flyback voltage is then scaled by external resistor
divider R1/R2 and presented at the FB pin. This is then
compared to the internal bandgap reference by the differential transistor pair Q1/Q2. The collector current from Q1
is mirrored around and subtracted from fixed current
source I
this net current to provide the control voltage to set the
current mode trip point.
at the VC pin. An external capacitor integrates
FXD
There are several timing signals which are required for
proper LT1725 operation. Please refer to the Timing
Diagram.
Minimum Output Switch On Time
The LT1725 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse and output voltage information is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution chosen is to require the output switch to be on for an absolute
minimum time per each oscillator cycle. This in turn establishes a minimum load requirement to maintain regulation. See Applications Information for further details.
1725fa
9
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