LINEAR TECHNOLOGY LT1719 Technical data

FEATURES

■

UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive

■

Low Power: 4.2mA at 3V

■

SOT-23 Package

■

Separate Input and Output Power Supplies
(SO-8␣ Only)

■

Output Optimized for 3V and 5V Supplies

■

TTL/CMOS Compatible Rail-to-Rail Output

■

Low Power Shutdown Mode: 0.1µA

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APPLICATIO S

■

High Speed Differential Line Receiver

■

Crystal Oscillator Circuits

■

Level Translators

■

Threshold Detectors/Discriminators

■

Zero-Crossing Detectors

■

High Speed Sampling Circuits

■

Delay Lines

LT1719

4.5ns Single/Dual Supply
3V/5V Comparator with

Rail-to-Rail Output

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DESCRIPTIO

The LT®1719 is an UltraFastTM comparator optimized for low
voltage operation. The input voltage range extends from
100mV below VEE to 1.2V below VCC. Internal hysteresis
makes the LT1719 easy to use even with slow moving input
signals. The rail-to-rail outputs directly interface to TTL and
CMOS. Alternatively the symmetric output drive can be
harnessed for analog applications or for easy translation to
other single supply logic levels. A shutdown control allows
for reduced power consumption and extended battery life in
portable applications.

The LT1719 is available in the SO-8 and 6-lead SOT-23
package. The SO-8 package has separate supplies which
allow flexible operation, accomodating separate analog input
ranges and output logic levels.

For a dual/quad comparator with similar performance, see
the LT1720/LT1721.

, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.

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TYPICAL APPLICATION

2.7V to 6V Crystal Oscillator with TTL/CMOS Output

2.7V TO 6V

2k

620Ω

1MHz TO 10MHz

CRYSTAL (AT-CUT)

220Ω

+

C1

LT1719

–

0.1µF 1.8k

GROUND

CASE

2k

1719 TA01

OUTPUT

Propagation Delay vs Overdrive

8

7

RISING EDGE

6

5

4

DELAY (ns)

3

2

1

0

0

)

(t

PDLH

FALLING EDGE

10 20 40

OVERDRIVE (mV)

25°C

= 100mV

V

STEP
+

= 5V

V

= 10pF

C

LOAD

(t

)

PDHL

30

50

1719 TA02

1

LT1719

TOP VIEW

+V

S

OUT
SHDN
GND

V

CC

+IN
–IN

V

EE

S8 PACKAGE

8-LEAD PLASTIC SO

1

2

3

4

8

7

6

5

+

–

–IN 1
V

–

2

+IN 3

6 SHDN
5 OUT
4 V

+

TOP VIEW

S6 PACKAGE

6-LEAD PLASTIC SOT-23

WW

W

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ABSOLUTE MAXIMUM RATINGS

(Note 1)

Supply Voltage

+VS to GND (LT1719S8) ...................................... 7V

VCC to VEE (LT1719S8)....................................... 12V

+VS to VEE (LT1719S8) ...................................... 12V

VEE to GND (LT1719S8) ...................... –12V to 0.3V

V+ to V– (LT1719S6) ............................................. 7V

Input Current (+IN, –IN or SHDN)..................... ±10mA

Output Current (Continuous) ............................ ±20mA

Operating Temperature Range

C Grade .................................................. 0°C to 70°C

I Grade .............................................. – 40°C to 85°C

Junction Temperature.......................................... 150°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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W

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PACKAGE/ORDER INFORMATION

ORDER PART

NUMBER

LT1719CS8
LT1719IS8

S8 PART MARKING

T

= 150°C, θJA = 110°C/W

JMAX

S6 PART MARKING

T

= 150°C, θJA = 230°C/W

JMAX

Consult factory for parts specified with wider operating temperature ranges.

1719
1719I

ORDER PART

NUMBER

LT1719CS6
LT1719IS6

LTHW
LTJF

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at T
VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

+V
V+ – V
V

CMR

V

TRIP

V

TRIP

V

OS

V

HYST

∆VOS/∆T Input Offset Voltage Drift ● 10 µV/°C
I

B

I

OS

CMRR Common Mode Rejection Ratio (Note 4) (LT1719S8) ● 55 70 dB

PSRR Power Supply Rejection Ratio (Note 6) (LT1719S8) 65 80 dB

A

V

V

OH

2

The ● denotes specifications that apply over the full operating temperature

= 25°C. V

A

– V

S

–

+
–

Input Supply Voltage (LT1719S8 only) ● 2.7 10.5 V

EE

Output Supply Voltage (LT1719S8 only) ● 2.7 6 V
Supply Voltage (LT1719CS6 only) ● 2.7 6 V
Input Voltage Range (Note 2) (LT1719S8) ● VEE – 0.1 VCC – 1.2 V

Input Trip Points (Note 3) ● –1.5 5.5 mV

Input Offset Voltage (Note 3) 0.4 2.5 mV

Input Hysteresis Voltage (Note 3) ● 2.0 3.5 7 mV

Input Bias Current ● –6 –2.5 0 µA
Input Offset Current ● 0.2 0.6 µA

Voltage Gain (Note 8) ∞
Output High Voltage I

= 1V, V

CM

(Note 5) (LT1719S6)

(Note 7) (LT1719S6) 65 80 dB

= 4mA, VIN = V

SOURCE

SHDN

= 0.5V, V

TRIP

OVERDRIVE

+

+ 10mV (LT1719S8) ● +VS – 0.4 V

= 20mV, C

(LT1719S6)

(LT1719S6)

= 10pF and for the LT1719S8

OUT

–

● V

– 0.1 V+ – 1.2 V

● –5.5 1.5 mV

● 3.5 mV

● 55 65 dB

+

● V

– 0.4 V

LT1719

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at T

= 25°C. V

A

CM

The ● denotes specifications that apply over the full operating temperature

= 1V, V

SHDN

= 0.5V, V

OVERDRIVE

= 20mV, C

= 10pF and for the LT1719S8

OUT

VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V– = 0V, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

OL

t

PD20

t

PD5

t

SKEW

t

r

t

f

t

JITTER

Output Low Voltage I
Propagation Delay V

Propagation Delay V

= 10mA, VIN = V

SINK

OVERDRIVE

V

OVERDRIVE

OVERDRIVE

= 20mV (Note 9) VEE = 0V(LT1719S8) 4.5 6.5 ns

= 20mV, VEE = –5V (LT1719S8 only) 4.2 ns
= 5mV (Notes 9, 10) VEE = 0V(LT1719S8) 7 10 ns

Propagation Delay Skew (Note 11) 0.5 1.5 ns
Output Rise Time 10% to 90% 2.5 ns
Output Fall Time 90% to 10% 2.2 ns
Output Timing Jitter VIN = 1.2V

(6dBm), ZIN = 50Ω t

P-P

f = 20MHz t

f

MAX

t

OFF

t

ON

I

CC

Maximum Toggle Frequency V

OVERDRIVE

V

OVERDRIVE

Turn-Off Delay Time to Z

= 50mV, +VS or V+ = 3V 70 MHz
= 50mV, +VS or V+ = 5V 62.5 MHz

≥10kΩ 75 ns

OUT

Wake-Up Delay Time to VOH or VOL, I
Positive Input Stage Supply Current +VS = VCC = 5V, VEE = –5V ● 1.0 2.2 mA

(LT1719S8 0nly) +VS = VCC = 3V, VEE = 0V ● 0.9 1.8 mA

I

EE

Negative Input Stage Supply Current + VS = VCC = 5V, VEE = –5V ● –4.8 –2.6 mA

(LT1719S8 0nly) +VS = VCC = 3V, VEE = 0V ● –3.8 –2.2 mA

I

S

Positive Output Stage Supply Current +VS = VCC = 5V, VEE = –5V ● 4.2 8 mA

(LT1719S8 0nly) VS = VCC = 3V, VEE = 0V ● 3.3 6 mA

+

I

Supply Current (LT1719S6) V+ = 5V ● 4.6 9 mA

V+ = 3V ● 4.2 7 mA

I

SHDN5

I

SHDN3

I

CCS

I

SS

I

EES
+

I

S

I

CCSO

I

SSO

I

EEO
+

I

O

Shutdown Pin Current +VS or V+ = 5V ● –300 –110 –30 µA
Shutdown Pin Current +VS or V+ = 3V ● –200 –80 –20 µA
Disabled Supply Currents (LT1719S8) +VS = 6V, VCC = 5V, VEE = –5V ● 0.2 30 µA

(LT1719S8) V

= +VS – 0.5V ● 750 µA

SHDN

(LT1719S8) ● –30 –0.2 µA
(LT1719S6) V+ = 6V, V

= +VS – 0.5V ● 780 µA

SHDN

(LT1719S8) +VS = 6V, VCC = 5V, VEE = –5V ● 0.1 20 µA
(LT1719S8) Shutdown Pin Open ● 0.1 20 µA
(LT1719S8) ● –20 0.1 µA

(LT1719S6) V+ = 6V, Shutdown Pin Open ● 0.2 40 µA

Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.

Note 2: If one input is within these common mode limits, the other
input can go outside the common mode limits and the output will be
valid.

Note 3: The LT1719 comparator includes internal hysteresis. The trip
points are the input voltage needed to change the output state in each
direction. The offset voltage is defined as the average of V

–

, while the hysteresis voltage is the difference of these two.

V

TRIP

TRIP

+

and

Note 4: The LT1719S8 common mode rejection ratio is measured with

= 5V, VEE = –5V and is defined as the change in offset voltage

V

CC

measured from V

= –5.1V to VCM = 3.8V, divided by 8.9V.

CM

–

– 10mV ● 0.4 V

TRIP

–

= 0V(LT1719S6) ● 8.0 ns

V

–

= 0V(LT1719S6) ● 13 ns

V

+

PD

–

PD

= 1mA 350 ns

LOAD

15 ps
11 ps

Note 5: The LT1719S6 common mode rejection ratio is measured
with V+ = 5V and is defined as the change in offset voltage measured
from V

= –0.1V to VCM = 3.8V, divided by 3.9V.

CM

Note 6: The LT1719S8 power supply rejection ratio is measured with
V

= 1V and is defined as the worst of: the change in offset voltage

CM

from V
voltage from V

= –5.5V to VEE = 0V divided by 5.5V, or the change in offset

EE

= +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V)

CC

divided by 3.3V.
Note 7: The 1719S6 power supply rejection ratio is measured with

V

= 1V and is defined as the change in offset voltage measured from

CM
+

= 2.7V to V+ = 6V, divided by 3.3V.

V

RMS
RMS

3

LT1719

TEMPERATURE (°C)

–50

0

3.8

4.2

25 75

1719 G03

–0.2

–5.0

–25 0

50 100 125

–5.2

–5.4

4.0

COMMON MODE INPUT VOLTAGE (V)

+VS = VCC OR V+ = 5V

VEE = –5V (LT1719S8)

V

–

= GND (LT1719S6)

SUPPLY VOLTAGE, VCC = +VS OR V+ (V)

0

SUPPLY CURRENTS (mA)

2

6

5

4

3

2

1

0

–1

–2

–3

1719 G06

173456

TA = 25°C
V

EE

= GND

I+ (LT1719S6)

IS (LT1719S8)

ICC (LT1719S8)

IEE (LT1719S8)

ELECTRICAL CHARACTERISTICS

Note 8: Because of internal hysteresis, there is no small-signal region
in which to measure gain. Proper operation of internal circuity is
ensured by measuring VOH and VOL with only 10mV of overdrive.

Note 9: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to V

TRIP

±

.

Note 10: t

PD

with low values of overdrive. The LT1719 is 100% tested with a
100mV step and 20mV overdrive. Correlation tests have shown that

limits can be guaranteed with this test, if additional DC tests are

t

PD

performed to guarantee that all internal bias conditions are correct.
Note 11: Propagation Delay Skew is defined as:

= |t

t

SKEW

W

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TYPICAL PERFORMANCE CHARACTERISTICS

Input Offset and Trip Voltages
vs Supply Voltage

3

V

2

1

0

–1

AND TRIP POINT VOLTAGE (mV)

25°C

–2

OS

V

= 1V

V

CM

OR V– = GND

V

EE

–3

2.5

3.0 3.5

SUPPLY VOLTAGE, VCC = +VS OR V+ (V)

TRIP

V

OS

V

TRIP

4.5 5.5 6.0

4.0 5.0

+

–

1719 G01

Input Offset and Trip Voltages
vs Temperature

3

V

2

1

0

–1

AND TRIP POINT VOLTAGE (mV)

+VS = VCC or V+ = 5V

–2

OS

V

–3

= 1V

V

CM

OR V– = GND

V

EE

–20 20 60 100

TRIP

V

OS

V

TRIP

TEMPERATURE (°C)

+

–

cannot be measured in automatic handling equipment

– t

PDHL

|

PDLH

Input Common Mode Limits
vs Temperature

140–40–60 0 40 80 120

1719 G02

Input Current
vs Differential Input Voltage

2

25°C

1

0

–1

–2

–3

INPUT BIAS (µA)

–4

–5

–6

–7

4

–4 –3 –2 –1 0 5

–5

DIFFERENTIAL INPUT VOLTAGE (V)

1234

1719 G04

Quiescent Supply Current
vs Temperature

10

VCC = +VS OR V+ = 5V
V

= GND

EE

8

6

4

2

0

SUPPLY CURRENT (mA)

–2

–4

–6

–25 25 75 125

–50

050

TEMPERATURE (°C)

Quiescent Supply Current
vs Supply Voltage

I+ (LT1719S6)

+IS (LT1719S8)

ICC (LT1719S8)

IEE (LT1719S8)

100

1339 G05

W

FREQUENCY (MHz)

0

6

8

30

NO LOAD

1719 G12

4

3

10 20 40

2

5

7

9

+V

S

SUPPLY CURRENT (mA)

25°C
+V

S

= 5V

C

LOAD

= 20pF

C

LOAD

= 10pF

SUPPLY VOLTAGE, +VS = VCC OR V+ (V)

2.5

4.0

3.5

PROPAGATION DELAY (ns)

5.5

5.0
t

TPLH

t

TPLH

t

TPHL

t

TPHL

4.5

4.0 5.0

1719 G09

3.0 3.5

4.5 5.5 6.0

25°C
V

STEP

= 100mV
OVERDRIVE = 20mV
C

LOAD

= 10pF

VEE/V–= GND

V

EE

= –5V

(V

CC

, +VS = 5.5V

MAX

)

(LT1719S8 ONLY)

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TYPICAL PERFORMANCE CHARACTERISTICS

LT1719

Propagation Delay
vs Load Capacitance

9

25°C

= 100mV

V

8

STEP

OVERDRIVE = 20mV

7

+V

= VCC OR V+ = 5V

S

OR V– = 0V

V

EE

6

5

4

3

PROPAGATION DELAY (ns)

2

1

0

10 20 40

0

OUTPUT LOAD CAPACITANCE (pF)

Output Low Voltage
vs Load Current

0.5
+VS OR V+ = 5V

= –10mV

V

IN

0.4

0.3

–55°C

OUTPUT VOLTAGE (V)

0.2

0.1

0

V

4

OUTPUT SINK CURRENT (mA)

CC

8

125°C

= 2.7V

RISING EDGE

(t

PDLH

FALLING EDGE

(t

30

125°C

25°C

12

PDHL

16

)

)

1719 G07

1719 G10

Propagation Delay
vs Temperature

8.0
t

PDLH

VCM = 1V

7.5

7.0

6.5

6.0

5.5

5.0

PROPAGATION DELAY (ns)

4.5

50

4.0

= 100mV

V

STEP

OVERDRIVE = 20mV

–25 0 50

–50

OVERDRIVE = 5mV

TEMPERATURE (°C)

C

LOAD

OR V– = GND

V

EE

= VCC = V

+V

S

3V

5V

3V
5V

25

= 10pF

+

75 100 125

1719 G08

Propagation Delay
vs Supply Voltage

Output High Voltage
vs Load Current

0.0

(V)

S

125°C

–0.2

–0.4

–0.6

–0.8

OUTPUT VOLTAGE RELATIVE TO +V

–1.0

20

0

25°C

4

8

OUTPUT SOURCE CURRENT (mA)

–55°C

+VS OR V+= 5V
V

= 10mV

IN

25°C

V

= 2.7V

CC

12

16

20

1719 G11

Supply Current vs Frequency

SUPPLY

SHDN PIN

Shutdown Currents
vs Shutdown Voltage

4

3

LT1719S8

2

CURRENTS (mA)

1

0

TA = 25°C

= GND

V

EE

+V

= VCC = 5V

S

–50

CURRENT (µA)

–100

V

V

–4

S

S

I

S

I

CC

–3 VS –2 VS –1 V
SHDN PIN VOLTAGE (V)

1719 G13a

Shutdown Currents
vs Shutdown Voltage

5

4

+

SUPPLY I

SHDN PIN

S

LT1719S6

3

2

CURRENT (mA)

1

0

TA = 25°C

–50

+

= 5V

V

CURRENT (µA)

–100

+

–4

V

+

V

–3 V+ –2 V+ –1 V+
SHDN PIN VOLTAGE (V)

1719 G13b

5

LT1719

W

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TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Currents
vs Temperature

10

1

SHUTDOWN CURRENTS (µA)

0.1

–50 25 50 75 100 125–25 0

SHUTDOWN = +V

SHUTDOWN PIN OPEN

– 0.5V

S

TEMPERATURE (°C)

+I

S

SHUTDOWN

PIN

CURRENT

+I

S

VCC = +VS = 5V

= –5V

V

EE

1719 G14

150

UUU

PIN FUNCTIONS

LT1719S8

VCC (Pin 1): Positive Supply Voltage for Input Stage.
+ IN (Pin 2): Noninverting Input of Comparator.

Wake-Up Delay
vs Temperature

700

600

500

400

300

WAKE-UP DELAY (ns)

200

100

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

1719 G15

LT1719S6

– IN (Pin 1): Inverting Input of Comparator.

–

V

(Pin 2): Negative Supply, usually Grounded.

– IN (Pin 3): Inverting Input of Comparator.

VEE (Pin 4): Negative Supply Voltage for Input Stage and

Chip Substrate.

GND (Pin 5): Ground.
SHDN (Pin 6): Shutdown. Pull to ground to enable

comparator.

OUT (Pin 7): Output of Comparator.

+VS (Pin 8): Positive Supply Voltage for Output Stage.

+ IN (Pin3): Noninverting Input of Comparator.

V+ (Pin 4): Positive Supply Voltage.
OUT (Pin 5): Output of Comparator.
SHDN (Pin 6): Shutdown. Pull to ground to enable

comparator.

6

TEST CIRCUITS

0V

–3V

PULSE

IN

50Ω

0.1µF

1N5711

LT1719

Response Time Test Circuit

+V

– V

s

CM

0V

–5V

130Ω

400Ω

–100mV

25Ω

2N3866

750Ω

*V1 = –1000 • (OVERDRIVE + V
NOTE: RISING EDGE TEST SHOWN.

FOR FALLING EDGE, REVERSE LT1719 INPUTS

V1*

25Ω

50k

50Ω

– V

V

CC

2

+

LT1719S8

3

–

VEE – V

(V+ – VCM)

CM

1

8

DUT

5

4

CM

–V

CM

+

)

TRIP

0.01µF

7

6(6)

0.01µF

10 × SCOPE PROBE

≈ 10pF)

(C

IN

1719 TC02

BANDWIDTH-LIMITED TRIANGLE WAVE

~

1kHz, VCM ±7.5V

V

CC

0.1µF

50k

+

50Ω

50Ω

V

CM

1/2 LT1638

+
–

100k

NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.

DUT

LT1719

–

100k

100k

200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS
WHEN DUT IS NOT POWERED

200k

100k

+
–

1/2 LT1638

2.4k

0.15µF

±V

LTC203

LTC203

TRIP

Test Circuit

15 3 214

16

9

10 6 711

2 14 153

1

8

7 11 106

10nF

10nF

TRIP

HYST

TRIP

+

OS

–

1000 × V

1µF

1

8

16

9

1719 TC01

1µF

–

–

1/2 LT1112

+

1/2 LT1112

+

10k

1000 × V

1000 × V

10k

1000 × V

7

LT1719

–

+

V

EE

V

CC

2.7V TO 6V

+V

S

GND

Single Supply

–

+

V

EE

V

CC

5V

–5V

3V

+V

S

GND

±5V

IN

, 3V

OUT

–

+

V

EE

V

CC

10V

5V

+V

S

GND

10VIN, 5V

OUT

–

+

V

EE

V

CC

–5.2V

3V

+V

S

GND

1719 F01

Front End Entirely Negative

LT1719S8 LT1719S8

LT1719S8

LT1719S8

APPLICATIONS INFORMATION

Power Supply Configurations (SO-8 Package)

The LT1719S8 has separate supply pins for the input and
output stages that allow flexible operation, accommodat­ing separate voltage ranges for the analog input and the
output logic. Of course, a single 3V/5V supply may be used
by tying +VS and VCC together as well as GND and VEE.

The minimum voltage requirement can be simply stated as
both the output and the input stages need at least 2.7V and
the VEE pin must be equal to or less than ground.

The following rules must be adhered to in any
configuration:

2.7V ≤ (V

2.7V ≤ (+VS – GND) ≤ 6V
(+VS – VEE) ≤ 10.5V
VEE ≤ Ground

Although the ground pin need not be tied to system
ground, most applications will use it that way. Figure 1
shows three common configurations. The final one is
uncommon, but it will work and may be useful as a level
translator; the input stage is run from –5.2V and ground
while the output stage is run from 3V and ground. In this
case the common mode input voltage range does not
include ground, so it may be helpful to tie VCC to 3V
anyway. Conversely, VCC may also be tied below ground,
as long as the above rules are not violated.

Input Voltage Considerations

The LT1719 is specified for a common mode range of
–100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
range is 100mV below VEE/V– to 1.2V below VCC/V+. The
criterion for this common mode limit is that the output still
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other input
signal can go outside the common mode limits, up to the
absolute maximum limits, and the output will retain the
correct polarity.

When either input signal falls below the negative common
mode limit, the internal PN diode formed with the sub­strate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode

8

– VEE) ≤ 10.5V

CC

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Figure 1. Variety of SO-8 Power Supply Configurations

between the input and the negative rail can speed up
recovery from negative overdrive by preventing the sub­strate diode from turning on.

When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least –400mV common mode.
However, the offset and hysteresis in this mode will
increase dramatically, to as much as 15mV each. The input
bias currents will also increase.

When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state can take as long as 1µs.

The propagation delay does not increase significantly
when driven with large differential voltages, but with low
levels of overdrive, an apparent increase may be seen with
large source resistances due to an RC delay caused by the
2pF typical input capacitance.

Input Protection

The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage

LT1719

1719 F02

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APPLICATIONS INFORMATION

equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir­cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.

The LT1719 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.

Input Bias Current

Input bias current is measured with both inputs held at 1V.
As with any PNP differential input stage, the LT1719 bias
current flows out of the device. It will go to zero on the
higher of the two inputs and double on the lower of the two
inputs. With more than two diode drops of differential
input voltage, the LT1719’s input protection circuitry
activates, and current out of the lower input will increase
an additional 30% and there will be a small bias current
into the higher of the two input pins, of 4µA or less. See the
Typical Performance curve “Input Current vs Differential
Input Voltage.”

High Speed Design Considerations

Application of high speed comparators is often plagued by
oscillations. The LT1719 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1719 outputs, a 4mV step can be
created at a 100Ω input source with only 0.02pF of output
to input coupling. The LT1719’s pinout has been arranged
to minimize problems by placing the sensitive inputs away
from the outputs, shielded by the power rails. The input
and output traces of the circuit board should also be
separated, and the requisite level of isolation is readily
achieved if a topside ground plane runs between the
output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.

Figure 2 shows a typical topside layout of the LT1719S8 on
such a multilayer board. Shown is the topside metal etch
including traces, pin escape vias, and the land pads for an
SO-8 LT1719 and its adjacent X7R 10nF bypass capacitors
in the 1206 case. The same principles should be used with
the SOT 23-6.

Figure 2. Typical Topside Metal for Multilayer PCB Layouts

The ground trace from Pin 5 runs under the device up to
the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1719 and
the bypass capacitors, which minimizes interference from
high frequency energy running around the ground plane or
power distribution traces.

The supply bypass should include an adjacent
10nF ceramic capacitor and a 2.2µF tantalum capacitor no
farther than 5cm away; use more capacitance on +VS if
driving more than 4mA loads. To prevent oscillations, it is
helpful to balance the impedance at the inverting and
noninverting inputs; source impedances should be kept
low, preferably 1kΩ or less.

The outputs of the LT1719 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines to
maintain signal integrity. The LT1719 can drive DC termi­nations of 200Ω or more, but lower characteristic imped­ance traces can be used with series termination or AC
termination topologies.

Shutdown Control

The LT1719 features a shutdown control pin for reduced
quiescent current when the comparator is not needed.
During shutdown, the inputs and the outputs become high
impedances. The LT1719 is enabled when the shutdown
input is pulled low with a threshold roughly two diode
drops below +VS or V+. Therefore, if driven by a standard
TTL gate, a pull-up resistor should be used. Because

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shutdown is active high, this resistor adds little power
drain during shutdown. A logic high disables the compara­tor. The LT1719S8 logic interface is based on the output
power rails, +VS and GND.

For applications that do not use the shutdown feature, it
may be helpful to tie the shutdown control to ground
through a 100Ω resistor rather than directly. This allows
the SHDN pin to be pulled high during debug or in-circuit
test (bed of nails) so that the output node can be wiggled
without damaging the low impedance output driver of the
LT1719.

The shutdown state is not guaranteed to be useful as a
multiplexer. Digital signals can have extremely fast edge
rates that may be enough to momentarily activate the
LT1719 output stage via internal capacitive coupling. No
damage to the LT1719 will result, but this could prove
deleterious to the intended recipient of the signal.

The LT1719 includes a FET pull-up on the shutdown
control pin (see Simplified Schematic) as well as other
internal structures to make the shutdown state current
drain <<1µA. Shutdown is guaranteed with an open circuit
on the shutdown control pin. When the shutdown control
pin is driven to +VS/V+ – 0.5V, the 70kΩ linear region
impedance of the pull-up FET will cause a current flow of
7µA (typ) into the +VS/V+ pin and out the shutdown pin.
Currents in all other power supply terminals will be <1µA.

Power Supply Sequencing

The LT1719S8 is designed to tolerate any power supply
sequencing at system turn-on and power down. In any of
the previously shown power supply configurations, the
various supplies can activate in any order without exces­sive current drain by the LT1719.

As always, the Absolute Maximum Ratings must not be
exceeded, either on the power supply terminals or the
input terminals. Power supply sequencing problems can
occur when input signals are powered from supplies that
are independent of the LT1719’s supplies. For the com­parator inputs, the signals should be powered from the
same VCC and VEE supplies as the LT1719. For the shut­down input, the signal should be powered from the same
+VS as the LT1719.

Hysteresis

The LT1719 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.

The input-output transfer characteristic is illustrated in
Figure 3 showing the definitions of VOS and V

HYST

based
upon the two measurable trip points. The hysteresis band
makes the LT1719 well behaved, even with slowly moving
inputs.

OUT

V

V

HYST

+

–

– V

TRIP

TRIP

V

–

HYST

)

/2

V

TRIP

(= V

TRIP

V

OL

0

–

V

TRIP

V

Figure 3. Hysteresis I/O Characteristics

+

V

+ V

TRIP

=

OS

2

+

V

OH

∆VIN = V

IN

1719 F03

+

–

– V

IN

The exact amount of hysteresis will vary from part to part
as indicated in the specifications table. The hysteresis
level will also vary slightly with changes in supply voltage
and common mode voltage. A key advantage of the
LT1719 is the significant reduction in these effects, which
is important whenever an LT1719 is used to detect a
threshold crossing in one direction only. In such a case,
the relevant trip point will be all that matters, and a stable
offset voltage with an unpredictable level of hysteresis, as
seen in competing comparators, is useless. The LT1719 is
many times better than prior comparators in these re­gards. In fact, the CMRR and PSRR tests are performed by
checking for changes in either trip point to the limits
indicated in the specifications table. Because the offset
voltage is the average of the trip points, the CMRR and
PSRR of the offset voltage is therefore guaranteed to be at
least as good as those limits. This more stringent test also
puts a limit on the common mode and power supply
dependence of the hysteresis voltage.

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Additional hysteresis may be added externally. The rail-to­rail outputs of the LT1719 make this more predictable than
with TTL output comparators due to the LT1719’s small
variability of VOH (output high voltage).

To add additional hysteresis, set up positive feedback by
adding additional external resistor R3 as shown in
Figure 4. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1719 pulls the
outputs to +VS and ground to within 200mV of the rails
with light loads, and to within 400mV with heavy loads. For
the load of most circuits, a good model for the voltage on
the right side of R3 is 300mV or +VS – 300mV, for a total
voltage swing of (+VS – 300mV) – (300mV) = +V
– 600mV.

V

REF

R2

R1

R3

+

LT1719S8

–

S

The second step is to recalculate R2 to set the same
average threshold as before. The average threshold before
was set at VTH = (V

)(R1)/(R1 + R2). The new R2 is

REF

calculated based on the average output voltage (+VS/2)
and the simplified circuit model in Figure 5. To assure that
the comparator’s noninverting input is, on average, the
same VTH as before:

R2′ = (V

Figure 5. Model for Additional Hysteresis Calculations

– VTH)/(VTH/R1 + [VTH – (+VS)/2]/R3)

REF

V

REF

R2′

V

TH

R1

R3

+

LT1719S8

–

V

AVERAGE

=

1719 F05

+V

2

S

INPUT

Figure 4. Additional External Hysteresis

1719 F04

With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:

R3 = (R1R2)(+VS – 0.6V)/(additional hysteresis)

Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.

For additional hysteresis of 10mV or less, it is not uncom­mon for R2′ to be the same as R2 within 1% resistor
tolerances.

This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3
is low enough to effect the bias string, and adjustment of
R1 may also be required. Note that the currents through the
R1/R2 bias string should be many times the input currents
of the LT1719. For 5% accuracy, the current must be at least
20 times the input current, more for higher accuracy. This
illustration used an LT1719S8; with an LT1719S6 the same
procedure is used with V+ substituted for +VS.

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Interfacing the LT1719 to ECL

The LT1719 comparators can be used in high speed
applications where Emitter-Coupled Logic (ECL) is de­ployed. To interface the output of the LT1719 to ECL logic
inputs, standard TTL/CMOS to ECL level translators such

5V

+V

S

or V

5V

DO NOT USE FOR LT1719

10KH/E

+

R2

R3

LEVEL TRANSLATION. SEE TEXT

10KH/E
100K/E

180Ω

LSTTL

(a) STANDARD TTL TO PECL TRANSLATOR

LT1719

270Ω

820Ω

R1

as the 10H124, 10H424 and 100124 can be used. These
components come at a cost of a few nanoseconds addi­tional delay as well as supply currents of 50mA or more,
and are only available in quads. A faster, simpler and lower
power translator can be constructed with resistors as
shown in Figure 6.

+

+V

OR V

R1

R2

S

5V OR 5.2V

4.5V

510Ω
620Ω

180Ω
180Ω

R3

750Ω
510Ω

(b) LT1719 OUTPUT TO PECL TRANSLATOR

V

3V

LT1719

(c) 3V LT1719 OUTPUT TO PECL TRANSLATOR

+

+VS or V

LT1719

(d) LT1719 OUTPUT TO STANDARD ECL TRANSLATOR

ECL

R2

R1

R3R4

R4

R1

R3

R2

V

ECL

10KH/E
100K/E

Figure 6

V

ECL

5V OR 5.2V

4.5V

ECL FAMILY

10KH/E

100K/E – 4.5V

R1

300Ω
330Ω

V

ECL

–5.2V

180Ω
180Ω

+V

R2

S

OR V

5V
3V
5V
3V

R3

OMIT

1500Ω

+

560Ω
270Ω
680Ω
330Ω

R1

R4

560Ω

1000Ω

270Ω
510Ω
270Ω
390Ω

R2

R3

R4

330Ω

1200Ω

300Ω

330Ω

1500Ω

300Ω

430Ω

270Ω

1719 F06

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Figure 6a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used for
the LT1719, or with CMOS logic, because it depends on the
820Ω resistor to limit the output swing (VOH) of the all-NPN
TTL gate with its so-called totem-pole output. The LT1719
is fabricated in a complementary bipolar process and the
output stage has a PNP driver that pulls the output nearly
all the way to the supply rail, even when sourcing 10mA.

Figure 6b shows a three resistor level translator for inter­facing the LT1719 to ECL running off the same supply rail.
No pull-down on the output of the LT1719 is needed, but
pull-down R3 limits the VIH seen by the PECL gate. This is
needed because ECL inputs have both a minimum and
maximum VIH specification for proper operation. Resistor
values are given for both ECL interface types; in both cases
it is assumed that the LT1719 operates from the same
supply rail.

Figure 6c shows the case of translating to PECL from an
LT1719 powered by a 3V supply rail. Again, resistor values
are given for both ECL interface types. This time four re­sistors are needed, although with 10KH/E, R3 is not needed.
In that case, the circuit resembles the standard TTL trans­lator of Figure 6a, but the function of the new resistor, R4,
is much different. R4 loads the LT1719 output when high
so that the current flowing through R1 doesn’t forward
bias the LT1719’s internal ESD clamp diode. Although this
diode can handle 20mA without damage, normal opera­tion and performance of the output stage can be impaired
above 100µA of forward current. R4 prevents this with the
minimum additional power dissipation.

Finally, Figure 6d shows the case of driving standard,
negative-rail, ECL with the LT1719. Resistor values are
given for both ECL interface types and for both a 5V and 3V
LT1719 supply rail. Again, a fourth resistor, R4 is needed
to prevent the low state current from flowing out of the
LT1719, turning on the internal ESD/substrate diodes.
Resistor R4 again prevents this with the minimum addi­tional power dissipation.

Of course, in the SO-8 package, if the VEE of the LT1719 is
the same as the ECL negative supply, the GND pin can be
tied to it as well and +VS grounded. Then the output stage
has the same power rails as the ECL and the circuits of
Figure 6b can be used.

For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond, with
most layouts. Avoid the temptation to use speedup capaci­tors. Not only can they foul up the operation of the ECL gate
because of overshoots, they can damage the ECL inputs,
particularly during power-up of separate supply
configurations.

Similar circuits can be used with the emerging LVECL and
LVPECL standards.

The level translator designs shown assume one gate load.
Multiple gates can have significant IIH loading, and the
transmission line routing and termination issues also
make this case difficult.

ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1719 and the circuits shown
give levels that are stable with temperature. This will lower
the noise margin over temperature. In some configura­tions it is possible to add compensation with diode or
transistor junctions in series with the resistors of these
networks.

For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola,
now ON semiconductor.

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Circuit Description

The block diagram of the LT1719 is shown in Figure 7. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary com­mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.

The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single 2.7V
supply, the LT1719 still has a respectable 1.6V of input
common mode range. The differential input voltage range
is rail-to-rail, without the large input currents found in
competing devices. The input stage also features phase
reversal protection to prevent false outputs when the
inputs are driven below the –100mV common mode
voltage limit.

The internal hysteresis is implemented by positive, nonlin­ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con­nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technology’s rail-to-rail amplifiers and other products.
But the output of a comparator is digital, and this output
stage can drive TTL or CMOS directly. It can also drive ECL,
as described earlier, or analog loads as demonstrated in
the applications to follow.

The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current
from +VS/V+ to ground that occurs at transitions, to
minimize the frequency-dependent increase in power con­sumption. The frequency dependence of the supply cur­rent is shown in the Typical Performance Characteristics.

+IN

–IN

VCC OR V

+

A

V1

–

VEE OR V

+

–

SHUTDOWN

+

NONLINEAR STAGE

+

–

+

+

Σ

+

A

V2

–

BIAS CONTOL

+

–

Figure 7. LT1719 Block Diagram

Σ

+VS OR V

OUT

GND OR V

1719 F07

–

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Speed Limits

The LT1719 comparator is intended for high speed appli­cations, where it is important to understand a few limita­tions. These limitations can roughly be divided into three
categories: input speed limits, output speed limits, and
internal speed limits.

There are no significant input speed limits except the
shunt capacitance of the input nodes. If the 2pF typical
input nodes are driven, the LT1719 will respond.

The output speed is constrained by two mechanisms, the
first of which is the slew currents available from the output
transistors. To maintain low power quiescent operation,
the LT1719 output transistors are sized to deliver 25mA to
45mA typical slew currents. This is sufficient to drive small
capacitive loads and logic gate inputs at extremely high
speeds. But the slew rate will slow dramatically with heavy
capacitive loads. Because the propagation delay (tPD)
definition ends at the time the output voltage is halfway
between the supplies, the fixed slew current makes the
LT1719 faster at 3V than 5V with large capacitive loads and
sufficient input overdrive.

Another manifestation of this output speed limit is skew,
the difference between t
the LT1719 vary with the process variations of the PNP
and NPN transistors, for rising edges and falling edges
respectively. The typical 0.5ns skew can have either
polarity, rising edge or falling edge faster. Again, the skew
will increase dramatically with heavy capacitive loads.

A separate output speed limit is the clamp turnaround. The
LT1719 output is optimized for fast initial response, with
some loss of turnaround speed, limiting the toggle fre­quency. The output transistors are idled in a low power
state once VOH or VOL is reached, by detecting the Schottky
clamp action. It is only when the output has slewed from
the old voltage to the new voltage, and the clamp circuitry
has settled, that the idle state is reached and the LT1719
is fully ready to toggle again. This is typically 8ns for each
direction, resulting in a maximum toggle frequency of

62.5MHz. With higher frequencies, dropout and runt pulses
can result. Increases in capacitive load will increase the

PD

+

and t

–

. The slew currents of

PD

time needed for slewing due to the limited slew currents
and the maximum toggle frequency will decrease further.
For high toggle frequency applications, consider the
LT1394, whose linear output stage can toggle at 100MHz
typical.

The internal speed limits manifest themselves as disper­sion. All comparators have some degree of dispersion,
defined as a change in propagation delay versus input
overdrive. The propagation delay of the LT1719 will vary
with overdrive, from a typical of 4.5ns at 20mV overdrive
to 7ns at 5mV overdrive (typical). The LT1719’s primary
source of dispersion is the hysteresis stage. As a change
of polarity arrives at the gain stage, the positive feedback
of the hysteresis stage subtracts from the overdrive avail­able. Only when enough time has elapsed for a signal to
propagate forward through the gain stage, backwards
through the hysteresis path and forward through the gain
stage again, will the output stage receive the same level of
overdrive that it would have received in the absence of
hysteresis.

The LT1719S8 is several hundred picoseconds faster
when VEE = –5V, relative to single supply operation. This
is due to the internal speed limit; the gain stage operates
between VEE and +VS, and it is faster with higher reverse
voltage bias due to reduced silicon junction capacitances.

In many applications, as shown in the following examples,
there is plenty of input overdrive. Even in applications
providing low levels of overdrive, the LT1719 is fast
enough that the absolute dispersion of 2.5ns (= 7 – 4.5) is
often small enough to ignore.

The gain and hysteresis stage of the LT1719 is simple,
short and high speed to help prevent parasitic oscillations
while adding minimum dispersion. This internal “self-latch”
can be usefully exploited in many applications
occurs early in the signal chain, in a low power, fully
differential stage. It is therefore highly immune to distur­bances from other parts of the circuit, such as the output,
or on the supply lines. Once a high speed signal trips the
hysteresis, the output will respond, after a fixed propaga­tion delay, without regard to these external influences
that can cause trouble in nonhysteretic comparators.

because it

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±V

Test Circuit

TRIP

The input trip points test circuit uses a 1kHz triangle wave
to repeatedly trip the comparator being tested. The LT1719
output is used to trigger switched capacitor sampling of
the triangle wave, with a sampler for each direction. Be­cause the triangle wave is attenuated 1000:1 and fed to the
LT1719’s differential input, the sampled voltages are there­fore 1000 times the input trip voltages. The hysteresis and
offset are computed from the trip points as shown.

Crystal Oscillator

A simple crystal oscillator using an LT1719 is shown on
the first page of this data sheet. The 2k-620Ω resistor pair
set a bias point at the comparator’s noninverting input.
The 2k-1.8k-0.1µF path sets the inverting input node at an
appropriate DC average level based on the output. The
crystal’s path provides resonant positive feedback and
stable oscillation occurs. Although the LT1719 will give
the correct logic output when one input is outside the
common mode range, additional delays may occur when
it is so operated, opening the possibility of spurious
operating modes. Therefore, the DC bias voltages at the
inputs are set near the center of the LT1719’s common

mode range and the 220Ω resistor attenuates the feed­back to the noninverting input. The circuit will operate with
any AT-cut crystal from 1MHz to 10MHz over a 2.7V to 6V
supply range. As the power is applied, the circuit remains
off until the LT1719 bias circuits activate, at a typical V

CC

of 2V to 2.2V (25°C), at which point the desired frequency
output is generated.

The output duty cycle of this circuit is roughly 50%, but it
is affected by resistor tolerances and to a lesser extent, by
comparator offsets and timings. If a 50% duty cycle is
required, the circuit of Figure 8 forces a 50% duty cycle.
Crystals are narrow-band elements, so the feedback to the
noninverting input is a filtered analog version of the square
wave output. Changing the noninverting reference level
can therefore vary the duty cycle. C1 operates as in the
previous example while A1 compares a band-limited ver­sion of the output and biases C1’s negative input. C1’s only
degree of freedom to respond is variation of pulse width;
hence the output is forced to 50% duty cycle. Again, the
circuit operates from 2.7V to 6V. There is a slight duty
cycle dependence on comparator loading, so minimal
capacitive and resistive loading should be used in critical
applications.

V

CC

2.7V TO 6V

2k

620Ω

Figure 8. Crystal Oscillator with a Forced 50% Duty Cycle

1MHz TO 10MHz

CRYSTAL (AT-CUT)

220Ω

+

C1

LT1719

–

0.1µF

GROUND

CASE

1.8k

100k

2k

0.1µF

1k

A1

LT1636

+

0.1µF

–

200k

200k

OUTPUT

V

CC

1720 F07

16

WW

SI PLIFIED SCHE ATIC

LT1719

)

+

(V
+V

S

OUTPUT

)

–

GND (V

1719 SS

TO BIAS

SOURCES

15k

SHDN

150Ω

)

+

(V

CC

V

–IN

150Ω

)

+IN

–

(V

EE

V

17

LT1719

PACKAGE DESCRIPTION

8-Lead Plastic Small Outline (Narrow .150 Inch)

U

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package

(Reference LTC DWG # 05-08-1610)

0.189 – 0.197*
(4.801 – 5.004)

7

8

5

6

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0°– 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

TYP

0.150 – 0.157**
(3.810 – 3.988)

1

3

2

4

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

SO8 1298

18

PACKAGE DESCRIPTION

U

Dimensions in inches (millimeters) unless otherwise noted.

S6 Package

6-Lead Plastic SOT-23

(Reference LTC DWG # 05-08-1634)
(Reference LTC DWG # 05-08-1636)

2.80 – 3.10

(.110 – .118)

(NOTE 3)

LT1719

SOT-23

(Original)

.90 – 1.45

A

(.035 – .057)

.00 – 0.15

A1

(.00 – .006)

.90 – 1.30

A2

(.035 – .051)

.35 – .55

L

(.014 – .021)

.20

(.008)

DATUM ‘A’

L

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

4. DIMENSIONS ARE INCLUSIVE OF PLATING

5. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

6. MOLD FLASH SHALL NOT EXCEED .254mm

7. PACKAGE EIAJ REFERENCE IS:
SC-74A (EIAJ) FOR ORIGINAL
JEDEC MO-193 FOR THIN

SOT-23

(ThinSOT)

1.00 MAX

(.039 MAX)

.01 – .10

(.0004 – .004)

.80 – .90

(.031 – .035)

.30 – .50 REF

(.012 – .019 REF)

MILLIMETERS

(INCHES)

2.60 – 3.00

(.102 – .118)

.09 – .20

(.004 – .008)

(NOTE 2)

1.50 – 1.75

(.059 – .069)

(NOTE 3)

A

PIN ONE ID

.95

(.037)

REF

A2

1.90

(.074)

REF

.25 – .50

(.010 – .020)

(6PLCS, NOTE 2)

A1

S6 SOT-23 0401

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1719

TYPICAL APPLICATION

U

High Performance Sine Wave
to Square Wave Converter

Propagation delay of comparators is typically specified for
a 100mV step with some fraction of that for overdrive. But
in many signal processing applications, such as in com­munications, the goal is to convert a sine wave, such as a
carrier, to a square wave for use as a timing clock. The
desired behavior is for the output timing to be dependent
on the input timing only. No phase shift should occur as a
function of the input amplitude, which would result in AM
to FM conversion.

The circuit of Figure 9a is a simple LT1719S8-based sine
wave to square wave converter. The ±5V supplies on the
input allow very large swing inputs, while the 3V logic
supply keeps the output swing small to minimize cross
talk. Figure 9b shows the time delay vs input amplitude
with a 10MHz sine wave. The LT1719 delay changes just

0.65ns over the 26dB amplitude range; 2.33° at 10MHz.
The delay is particularly flat yielding excellent AM rejection

from 0dBm to 15dBm. If a 2:1 transformer is used to drive
the input differentially, this exceptionally flat zone spans
–5dBm to 10dBm, a common range for RF signal levels.

Similar delay performance is achieved with input frequen­cies as high as 50MHz. There is, however, some additional
encroachment into the central flat zone by both the small
amplitude and large amplitude variations.

With small input signals, the hysteresis and dispersion
make the LT1719 act like a comparator with a 12mV
hysteresis span. In other words, a 12mV

sine wave at

P-P

10MHz will barely toggle the LT1719, with 90° of phase lag
or 25ns additional delay.

Above 5V

at 10MHz, the LT1719 delay starts to de-

P-P

crease due to internal capacitive feed-forward in the input
stage. Unlike some comparators, the LT1719 will not
falsely anticipate a change in input polarity, but the feed­forward is enough to make a transition propagate through
the LT1719 faster once the input polarity does change.

5

4

25°C

= 5V

V

5V

+

LT1719S8

–

–5V

3V

SQUARE WAVE

OUTPUT

1719 F08a

SINE WAVE

INPUT

50Ω

Figure 9a. LT1719-Based Sine Wave to Square Wave Converter

Figure 9b. Time Delay vs Sine Wave Input Amplitude

CC

= –5V

V

3

EE

= 3V

+V

S

10MHz

2

TIME DELAY (ns)

1

632mV

0

–5

0

P-P

2V

P-P

51015

INPUT AMPLITUDE (dBm)

6.32V

20 25

P-P

1719 F08b

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator
LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016
LT1394 7ns, UltraFast, Single Supply Comparator 6mA Single Supply Comparator
LT1671 60ns, Low Power, Single Supply Comparator 450µA Single Supply Comparator
LT1713/LT1714 Single/Dual 7ns, Rail-to-Rail Comparator Rail-to-Rail Inputs and Outputs
LT1720/LT1721 Dual/Quad 4.5ns, Single Supply 3V/5V Comparator Dual/Quad Comparator Similar to the LT1719

20

Linear Technolog y Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

1719f LT/TP 1100 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000