Linear Technology LT1683EG, LT1683IG Datasheet

LT1683

Ultralow Noise

FEATURES

■

Greatly Reduced Conducted and Radiated EMI

■

Low Switching Harmonic Content

■

Independent Control of Output Switch Voltage and
Current Slew Rates

■

Greatly Reduced Need for External Filters

■

Dual N-Channel MOSFET Drivers

■

20kHz to 250kHz Oscillator Frequency

■

Easily Synchronized to External Clock

■

Regulates Positive and Negative Voltages

■

Easier Layout Than with Conventional Switchers

U

APPLICATIO S

■

Power Supplies for Noise Sensitive Communication
Equipment

■

EMI Compliant Offline Power Supplies

■

Precision Instrumentation Systems

■

Isolated Supplies for Industrial Automation

■

Medical Instruments

■

Data Acquisition Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Push-Pull DC/DC Controller

U

DESCRIPTIO

The LT®1683 is a switching regulator controller designed
to lower conducted and radiated electromagnetic interfer­ence (EMI). Ultralow noise and EMI are achieved by
controlling the voltage and current slew rates of external
N-channel MOSFET switches. Current and voltage slew
rates can be independently set to optimize harmonic
content of the switching waveforms vs efficiency. The
LT1683 can reduce high frequency harmonic power by as
much as 40dB with only minor losses in efficiency.

The LT1683 utilizes a dual output (push-pull) current
mode architecture optimized for low noise topologies. The
IC includes gate drivers and all necessary oscillator,
control and protection circuitry. Unique error amp cir­cuitry can regulate both positive and negative voltages.
The oscillator may be synchronized to an external clock for
more accurate placement of switching harmonics.

Protection features include gate drive lockout for low VIN,
opposite gate lockout, soft-start, output current limit,
short-circuit current limiting, gate drive overvoltage clamp
and input supply undervoltage lockout.

TYPICAL APPLICATIO

Ultralow Noise 48V to 5V DC/DC Converter

51k

1N4148

11V

23.2k

976Ω

1.2nF

25k

25k

510Ω

0.5W

FZT853

2N3904

68µF
20V

14 2

SHDN

5

V5

6

SYNC

7

C

16.9k

3.3k

3.3k

1.5k

T

8

R

T

16

R

VSL

15

R

CSL

12

V

C

22nF0.22µF

SS

10nF

10µF

20V

V

IN

LT1683

GND

17

1113

GCL

CAP A

GATE A

CAP B

GATE B

PGND

NFB

8.2V

3

5pF

1

5pF

18

19

Si9422

4

CS

20

9

FB

10

48V

39µF
63V

MBR0530

U

10pF
200V

Si9422

30pF

MIDCOM 31244

MBRS340

MBRS340

10pF
200V

30pF

0.1Ω

22µH

150µF

OS-CON

OPTIONAL

B

22µH

2×100µF

POSCAP

7.50k

2.49k

A

1683 TA01

5V/2A

200µV/DIV

20mV/DIV

5V Output Noise

(Bandwidth = 100MHz)

A

B

5µs/DIV

1683 TA01a

200µV

1683f

P-P

1

LT1683

1
2
3
4
5
6
7
8
9

10

TOP VIEW

G PACKAGE

20-LEAD PLASTIC SSOP

20
19
18
17
16
15
14
13
12
11

GATE A

CAP A

GCL

CS
V5

SYNC

C

T

R

T

FB

NFB

PGND
GATE B
CAP B
V

IN

R

VSL

R

CSL

SHDN
SS
V

C

GND

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltage (VIN)................................................ 20V

Gate Drive Current .....................................Internal Limit

V5 Current .................................................Internal Limit

SHDN Pin Voltage.................................................... 20V

Feedback Pin Voltage (Trans. 10ms) ...................... ±10V

Feedback Pin Current............................................ 10mA

Negative Feedback Pin Voltage (Trans. 10ms)........ ±10V

CS Pin.......................................................................... 5V

GCL Pin ..................................................................... 16V

SS Pin.......................................................................... 3V

Operating Junction Temperature Range

(Note 3) ............................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

UUW

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LT1683EG
LT1683IG

T

= 150°C, θJA = 110°C/W

JMAX

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = V

The ● denotes the specifications which apply over the full operating

, R

, R

REF

VSL

= 16.9k, RT = 16.9k and

CSL

other pins open unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amplifiers

V

REF

I

FB

FB

REG

V

NFR

I

NFR

NFB
g

m

I

ESK

I

ESRC

V

CLH

V

CLL

A

V

FB

OV

I

SS

2

Reference Voltage Measured at Feedback Pin ● 1.235 1.250 1.265 V
Feedback Input Current VFB = V
Reference Voltage Line Regulation 2.7V ≤ VIN ≤ 20V ● 0.012 0.03 %/V
Negative Feedback Reference Voltage Measured at Negative Feedback Pin ● –2.56 –2.500 –2.45 V

Negative Feedback Input Current V
Negative Feedback Reference Voltage Line Regulation 2.7V ≤ VIN ≤ 20V ● 0.009 0.03 %/V

REG

Error Amplifier Transconductance ∆IC = ±50µA 1100 1500 2200 µmho

Error Amp Sink Current VFB = V
Error Amp Source Current VFB = V
Error Amp Clamp Voltage High Clamp, VFB = 1V 1.27 V
Error Amp Clamp Voltage Low Clamp, VFB = 1.5V 0.12 V
Error Amplifier Voltage Gain 180 250 V/V
FB Overvoltage Shutdown Outputs Drivers Disabled 1.47 V
Soft-Start Charge Current VSS = 1V 9.0 12 µA

REF

with Feedback Pin Open

= V

NFB

NFR

+ 150mV, VC = 0.9V ● 120 200 350 µA

REF

– 150mV, VC = 0.9V ● 120 200 350 µA

REF

● 250 1000 nA

–37 –25 µA

● 700 2500 µmho

1683f

LT1683

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VC = 0.9V, VFB = V

The ● denotes the specifications which apply over the full operating

, R

, R

REF

VSL

= 16.9k, RT = 16.9k and

CSL

other pins open unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Sync

f

MAX

f

SYNC

V

SYNC

R

SYNC

Gate Drives (Specifications Apply to Either A or B Unless Otherwise Noted)

DC

MAX

VG

ON

VG

OFF

IG

SO

IG

SK

V

INUVLO

Current Sense

t

IBL

V

SENSE

V

SENSEF

Slew Control (for the Following Slew Tests See Test Circuit in Figure 1b)

V

SLEWR

V

SLEWF

VI

SLEWR

VI

SLEWF

Supply and Protection

V

INMIN

I

VIN

V

SHDN

∆V

SHDN

I

SHDN

V5 5V Reference Voltage 6.5V ≤ VIN ≤ 20V, IV5 = 5mA 4.85 5 5.20 V

IV5

SC

Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.

Note 2: Supply current specification includes loads on each gate as in
Figure 1a. Actual supply currents vary with operating frequency, operating
voltages, V5 load, slew rates and type of external FET.

Note 3: The LT1683E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 125°C operating range

Max Switch Frequency 250 kHz
Synchronization Frequency Range Oscillator Frequency = 250kHz 290 kHz
SYNC Pin Input Threshold ● 0.7 1.4 2.0
SYNC Pin Input Resistance 40 kΩ

Maximum Switch Duty Cycle R

VSL

= R

= 4.85k, ● 45 46 %

CSL

Osc Frequency = 25kHz

Gate On Voltage VIN = 12, GCL = 12 10 10.4 10.7 V

V

= 12, GCL = 8 7.6 7.9 8.1 V

IN

Gate Off Voltage VIN = 12V 0.2 0.35 V
Max Gate Source Current VIN = 12V 0.3 A
Max Gate Sink Current VIN = 12V 0.3 A
Gate Drive Undervoltage Lockout (Note 5) V

= 6.5V, Gates Enabled 7.3 7.5 V

GCL

Switch Current Limit Blanking Time 100 ns
Sense Voltage Shutdown Voltage VC Pulled Low ● 86 103 120 mV
Sense Voltage Fault Threshold ● 230 300 mV

Output Voltage Slew Rising Edge R
Output Voltage Slew Falling Edge R
Output Current Slew Rising Edge (CS Pin Voltage) R
Output Current Slew Falling Edge (CS Pin Voltage) R

Minimum Input Voltage (Note 4) V
Supply Current (Note 2) R

= R

VSL

VSL

VSL

VSL

GCL

VSL

R

VSL

= 17k 26 V/µs

CSL

= R

= 17k 19 V/µs

CSL

= R

= 17k 2.1 V/µs

CSL

= R

= 17k 2.1 V/µs

CSL

= V

IN

= R

= 17k, VIN = 12 ● 25 45 mA

CSL

= R

= 17k, VIN = 20 ● 35 55 mA

CSL

● 2.55 3.6 V

Shutdown Turn-On Threshold ● 1.31 1.39 1.48 V
Shutdown Turn-On Voltage Hysteresis ● 50 110 180 mV
Shutdown Input Current Hysteresis ● 10 24 35 µA

6.5V ≤ V

≤ 20V, IV5 = –5mA 4.80 5 5.15 V

IN

5V Reference Short-Circuit Current VIN = 6.5V Source 10 mA

= 6.5V Sink –10 mA

V

IN

are assured by design, characterization and correlation with statistical
process controls. The LT1683I is guaranteed and tested over the –40° to
125° operating temperature range.

Note 4: Output gate drivers will be enabled at this voltage. The GCL
voltage will also determine drivers’ activity.

Note 5: Gate drivers are ensured to be on when V

is greater than the

IN

maximum value.

1683f

3

LT1683

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Feedback Voltage and Input
Current vs Temperature

1.260

1.258

1.256

1.254

1.252

1.250

1.248

1.246

FEEDBACK VOLTAGE (V)

1.244

1.242

1.240
–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Feedback Overvoltage Shutdown
vs Temperature

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

FEEDBACK VOLTAGE (V)

1.30

1.25

1.20
–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

1683 G03

750
700
650

FB INPUT CURRENT (nA)

600
550
500
450
400
350
300
250

1683 G01

Error Amp Transconductance vs
Temperature

2000
1900
1800
1700
1600
1500
1400
1300
1200

TRANSCONDUCTANCE (µmho)

1100
1000

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Negative Feedback Voltage and
Input Current vs Temperature

2.480

2.485

2.490

2.495

2.500

2.505

2.510

NEGATIVE FEEDBACK VOLTAGE (V)

2.515

2.520
–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Error Amp Output Current vs
Feedback Pin Voltage from Nominal

500
400
300
200
100

0

–100

CURRENT (µA)

–200
–300
–400
–500

–400 –300 –200 –100 0 100 200 300 400

FEEDBACK PIN VOLTAGE FROM NOMINAL (mV)

1683 G04

1683 G02

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

–40°C

125°C

NFB INPUT CURRENT (µA)

25°C

1683 G05

VC Pin Threshold and Clamp
Voltage vs Temperature

1.4

1.2

1.0

0.8

0.6

PIN VOLTAGE (V)

C

V

0.4

0.2

0

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

4

1683 G06

CS Pin Trip and CS Fault Voltage
vs Temperature

240

220

200

180

160

140

CS PIN VOLTAGE (mV)

120

100

80

–50 –25 0 25 50 75 100 125 150

FAULT

TRIP

TEMPERATURE (°C)

1683 G07

SHDN Pin On and Off Thresholds
vs Temperature

1.50

1.45

1.40

1.35

SHDN PIN VOLTAGE (V)

1.30

1.25
–50 –25 0 25 50 75 100 125 150

ON

OFF

TEMPERATURE (°C)

1683 G08

1683f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LT1683

SHDN Pin Hysteresis Current vs
Temperature VIN Current vs Temperature

27

25

23

21

19

SHDN PIN CURRENT (µA)

17

15

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

1683 G09

24

WITH NO EXTERNAL MOSFETs

22

20

18

16

CURRENT (mA)

IN

V

14

12

10

VIN = 12 R

VIN = 20 R

VIN = 12 R

–50 –25 0 25 50 75 100 125 150

, R

CSL

, R

CSL

, R

CSL

TEMPERATURE (°C)

Gate Drive A/B High Voltage vs

Slope Compensation

110

100

90

80

70

PERCENT OF MAX CS VOLTAGE

60

50

10 20 30 40 50

0

DUTY CYCLE (%)

VC PIN = 0.9V

= 25°C

T

A

1683 G12

Temperature

10.7

10.6

10.5

10.4

10.3

10.2

10.1

10.0

9.90

GATE DRIVE A/B PIN VOLTAGE (V)

9.80

9.70
–50 –25 0 25 50 75 100 125 150

GCL = 12V

GCL = 6V

TEMPERATURE (°C)

VSL

VSL

VSL

= 5.7k

= 17k

= 17k

VIN = 12V
NO LOAD

1683 G10

1683 G13

CS Pin to VC Pin Transfer
Function

1.6
TA = 25°C

1.4

1.2

1.0

0.8

0.6

PIN VOLTAGE (V)

C

V

0.4

0.2

0

20 40 60 80 100 120

0

Gate Drive A/B Low Voltage vs
Temperature

6.5

0.50

6.4

6.3

6.2

6.1

6.0

5.9

5.8

5.7

5.6

5.5

VIN = 12V

0.45
NO LOAD

0.40

0.35

0.30

0.25

0.20

0.15

0.10

GATE DRIVE A/B PIN VOLTAGE (V)

0.05

0

–50 –25 0 25 50 75 100 125 150

CS PIN VOLTAGE (mV)

1683 G11

TEMPERATURE (°C)

1683 G14

Gate Drive Undervoltage Lockout
Voltage vs Temperature

7.3
GCL = 6V

7.2

7.1

7.0

6.9

6.8

6.7

PIN VOLTAGE (V)

IN

6.6

V

6.5

6.4

6.3

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

1683 G15

Soft-Start Current vs Temperature

9.5
SS VOLTAGE = 0.9V

9.3

9.1

8.9

8.7

8.5

8.3

8.1

SS PIN CURRENT (µA)

7.9

7.7

7.5

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

1683 G16

V5 Voltage vs Load Current

5.08

5.06

5.04

5.02

5.00

V5 PIN VOLTAGE (V)

4.98

4.96
–10 –5 0 51015

–15

T = 125°C

T = 25°C

T = –40°C

LOAD CURRENT (mA)

1683 G17

1683f

5

LT1683

UUU

PI FU CTIO S

Part Supply

V5 (Pin 5): This pin provides a 5V output that can sink or

source 10mA for use by external components. V5 source
current comes from V
must be greater than 6.5V in order for this voltage to be in
regulation. If this pin is used, a small capacitor (<1µF) may
be placed on this pin to reduce noise. This pin can be left
open if not used.

GND (Pin 11): Signal Ground. The internal error amplifier,
negative feedback amplifier, oscillator, slew control cir­cuitry, V5 regulator, current sense and the bandgap refer­ence are referred to this ground. Keep the connection to
this pin, the feedback divider and VC compensation net­work free of large ground currents.

SHDN (Pin 14): The shutdown pin can disable the switcher.
Grounding this pin will disable all internal circuitry.

Increasing SHDN voltage will initially turn on the internal
bandgap regulator. This provides a precision threshold for
the turn on of the rest of the IC. As SHDN increases past

1.39V the internal LDO regulator turns on, enabling the
control and logic circuitry.

24µA of current is sourced out of the pin above the turn on
threshold. This can be used to provide hysteresis for the
shutdown function. The hysteresis voltage will be set by
the Thevenin resistance of the resistor divider driving this
pin times the current sourced out. Above approximately

2.1V the hysteresis current is removed. There is approxi­mately 0.1V of voltage hysteresis on this pin as well.

The pin can be tied high (to V

. Sink current goes to GND. V

IN

for instance).

IN

IN

V

(Pin 17): Input Supply. All supply current for the part

IN

comes from this pin including gate drives and V5 regula­tor. Charge current for gate drives can produce current
pulses of hundreds of milliamperes. Bypass this pin with
a low ESR capacitor.

When V
undervoltage lockout where the gate drivers are driven
low. This, along with gate drive undervoltage lockout,
prevents unpredictable behavior during power up.

PGND (Pin 20): Power Driver Ground. This ground comes
from the MOSFET gate drivers. This pin can have several
hundred milliamperes of current on it when the external
MOSFETs are being turned off.

is below 2.55V the part will go into supply

IN

Oscillator

SYNC (Pin 6): The SYNC pin can be used to synchronize

the part to an external clock. The oscillator frequency
should be set close to the external clock frequency.
Synchronizing the clock to an external reference is useful
for creating more stable positioning of the switcher volt­age and current harmonics. This pin can be left open or
tied to ground if not used.

CT (Pin 7): The oscillator capacitor pin is used in conjunc­tion with RT to set the oscillator frequency. For RT = 16.9k:

C

(nf) = 129/f

OSC

RT (Pin 8): The oscillator resistor pin is used to set the
charge and discharge currents of the oscillator capacitor.
The nominal value is 16.9k. It is possible to adjust this
resistance ±25% to set oscillator frequency more accu­rately.

OSC

(kHz)

6

1683f

UUU

PI FU CTIO S

LT1683

Gate Drive

GATE A, GATE B (Pins 1, 19): These pins connect to the

gates of the external N-channel MOSFETs. GATE␣ A and
GATE␣ B turn on with alternate clock cycles. These drivers
are capable of sinking and sourcing at least 300mA.

The GCL pin sets the upper voltage of the gate drive. The
gate pins will not be activated until V
voltage as defined by the GCL pin (gate undervoltage
lockout).

The gate drive outputs have current limit protection to safe
guard against accidental shorts.

If the gate drive voltage is greater than about 1V the
opposite gate drive is inhibited thus preventing cross
conduction.

GCL (Pin 3): This pin sets the maximum gate voltage to the
GATE␣ A and GATE␣ B pins to the MOSFET gate drives. This
pin should be either tied to a Zener, a voltage source or VIN.

If the pin is tied to a Zener or a voltage source, the
maximum gate drive voltage will be approximately
V

– 0.2V. If it is tied to VIN, the maximum gate voltage

GCL

is approximately VIN – 1.6.
Approximately 50µA of current can be sourced from this

pin if V
This pin also controls undervoltage lockout of the gate

drives. If the pin is tied to a Zener or voltage source, the
gate drive will not be enabled until VIN > V
pin is tied to VIN, then undervoltage lockout is disabled.

There is an internal 19V Zener tied from this pin to ground
to provide a fail-safe for maximum gate voltage.

GCL

< V

– 0.8V.

IN

reaches a minimum

IN

+ 0.8V. If this

GCL

The voltage slew rate is inversely proportional to this
capacitance and proportional to the current that the part
will sink and source on this pin. That current is inversely
proportional to R

R

(Pin 15): A resistor to ground sets the current slew

CSL

rate for the external drive MOSFETs during switching. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states of the
MOSFET current will determine how the di/dt related
harmonics are reduced. This time is proportional to R
and RS (the current sense resistor) and maximum current.
Longer times produce a greater reduction of higher fre­quency harmonics.

R

(Pin 16): A resistor to ground sets the voltage slew

VSL

rate for the drains of the external drive MOSFETs. The
minimum resistor value is 3.3k and the maximum value is
68k. The time to slew between on and off states on the
MOSFET drain voltage will determine how harmonics are
reduced from this source. This time is proportional to
R

, C

VSL

more rolloff of harmonics. C
tance from CAP A or B to the drain of the MOSFET.

and the input voltage. Longer times produce

VA/B

VSL

.

CSL

is the equivalent capaci-

VA/B

Switch Mode Control

SS (Pin 3): The SS pin allows for ramping of the switch

current threshold at startup. Normally a capacitor is placed
on this pin to ground. An internal 9µA current source will
charge this capacitor up. The voltage on the VC pin cannot
exceed the voltage on SS. Thus peak current will ramp up
as the SS pin ramps up. During a short circuit fault the SS
pin will be discharged to ground thus reinitializing soft­start.

Slew Control

CAP A, CAP B (Pins 2, 18): These pins are the feedback

nodes for the external voltage slewing capacitors. Nor­mally a small 1pf to 5pf capacitor is connected from this
pin to the drain of its respective MOSFET.

When SS is below the VC clamp voltage the VC pin will
closely track the SS pin.

This pin can be left open if not used.

1683f

7

LT1683

UUU

PI FU CTIO S

CS (Pin 4): This is the input to the current sense amplifier.
It is used for both current mode control and current
slewing of the external MOSFETs. Current sense is accom­plished via a sense resistor (RS) connected from the
sources of the external MOSFETs to ground. CS is con­nected to the top of RS. Current sense is referenced to the
GND pin.

The switch maximum operating current will be equal to

0.1V/RS. At CS = 0.1V, the gate drivers will be immediately
turned off (no slew control).

If CS = 0.22V in addition to the drivers being turned off, V

C

and SS will be discharged to ground (short-circuit protec­tion). This will hasten turn off on subsequent cycles.

FB (Pin 9): The feedback pin is used for positive voltage
sensing. It is the inverting input to the error amplifier. The
noninverting input of this amplifier connects internally to
a 1.25V reference.

If the voltage on this pin exceeds the reference by 220mV,
then the output drivers will immediately turn off the
external MOSFETs (no slew control). This provides for
output overvoltage protection

NFB (Pin 10): The negative feedback pin is used for
sensing a negative output voltage. The pin is connected to
the inverting input of the negative feedback amplifier
through a 100k source resistor. The negative feedback
amplifier provides a gain of –0.5 to the FB pin. The nominal
regulation point would be –2.5V on NFB. This pin should
be left open if not used.

If NFB is being used then overvoltage protection will occur
at 0.44V below the NFB regulation point.

At NFB < –1.8 current sense blanking will be disabled.
VC (Pin 12): The compensation pin is used for frequency

compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground. The
voltage on VC is proportional to the switch peak current.
The normal range of voltage on this pin is 0.25V to 1.27V.
However, during slope compensation the upper clamp
voltage is allowed to increase with the compensation.

During a short-circuit fault the VC pin will be discharged to
ground.

When this input is below 0.9V then the current sense
blanking will be disabled. This will assist start up.

TEST CIRCUITS

20mA

5pF

CAP A/CAP B

GATE A/GATE B

Figure 1a. Typical Test Circuitry Figure 1b. Test Circuit for Slew

2

IN5819

ZVN3306A

1683 F01a

+

10

–

CAP A/CAP B

GATE A/GATE B

CS

5pF

0.1

0.9A

IN5819

Si4450DY

1683 F01b

+

10

–

8

1683f

BLOCK DIAGRA

+

NEGATIVE
FEEDBACK

AMP

–

NFB

100k 50k

W

V

IN

C

IN

SHDN R

REGULATOR

V

IN

V

REG

V5

TO
DRIVERS

R

CSL

R

CSL

LT1683

R

VSL

VSL

G

CL

C

VA

CAP A

FB

+

ERROR

–

AMP

SLEW

CONTROL

GATE A

CAP B

MA

C

VB

+

C

VC

V

C

C

SS

SS

1.25V

COMP

–

+

+

SENSE

AMP

GATE B

PGND

CS

MB

R

SENSE

–

SQ

R

T

R

T

C

T

C

T

OSCILLATOR

SYNC GND

FF

R

TQBQ

FF

SUB

1683 BD

1683f

9

LT1683

OPERATIO

U

In noise sensitive applications switching regulators tend
to be ruled out as a power supply option due to their
propensity for generating unwanted noise. When switch­ing supplies are required due to efficiency or input/output
constraints, great pains must be taken to work around the
noise generated by a typical supply. These steps may
include pre and post regulator filtering, precise synchro­nization of the power supply oscillator to an external clock,
synchronizing the rest of the circuit to the power supply
oscillator or halting power supply switching during noise
sensitive operations. The LT1683 greatly simplifies the
task of eliminating supply noise by enabling the design of
an inherently low noise switching regulator power supply.

The LT1683 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switches. Current mode
control provides excellent AC and DC line regulation and
simplifies loop compensation.

Slew control capability provides much greater control
over the power supply components that can create con­ducted and radiated electromagnetic interference. Com­pliance with EMI standards will be an easier task and will
require fewer external filtering components.

The LT1683 uses two external N-channel MOSFETs as the
power switches. This allows the user to tailor the drive
conditions to a wide range of voltages and currents.

CURRENT MODE CONTROL

Referring to the block diagram. A switching cycle begins
with an oscillator discharge pulse, which resets the RS
flip-flop, turning on one of the external MOSFET drivers.
The switch current is sensed across the external sense
resistor and the resulting voltage is amplified and com­pared to the output of the error amplifier (VC pin). The
driver is turned off once the output of the current sense
amplifier exceeds the voltage on the VC pin. In this way
pulse by pulse current limit is achieved. The toggle flip­flop ensures that the two MOSFETs are enabled on alter­nate clock cycles. Internal slope compensation is provided
to ensure stability under high duty cycle conditions.

Output regulation is obtained using the error amp to set
the switch current trip point. The error amp is a
transconductance amplifier that integrates the difference
between the feedback output voltage and an internal 1.25V
reference. The output of the error amp adjusts the switch
current trip point to provide the required load current at the
desired regulated output voltage. This method of control­ling current rather than voltage provides faster input
transient response, cycle-by-cycle current limiting for
better output switch protection and greater ease in com­pensating the feedback loop. The VC pin is used for loop
compensation and current limit adjustment. During nor­mal operation the VC voltage will be between 0.25V and

1.27V. An external clamp on VC or SS may be used for
lowering the current limit.

The negative voltage feedback amplifier allows for direct
regulation of negative output voltages. The voltage on the
NFB pin gets amplified by a gain of – 0.5 and driven on to
the FB input, i.e., the NFB pin regulates to –2.5V while the
amplifier output internally drives the FB pin to 1.25V as in
normal operation. The negative feedback amplifier input
impedance is 100k (typ) referred to ground.

Soft-Start

Control of the switch current during start up can be
obtained by using the SS pin. An external capacitor from
SS to ground is charged by an internal 9µA current source.
The voltage on VC cannot exceed the voltage on SS. Thus
as the SS pin ramps up the VC voltage will be allowed to
ramp up. This will then provide for a smooth increase in
switch maximum current. SS will be discharged as a result
of the CS voltage exceeding the short circuit threshold of
approximately 0.22V.

Slew Control

Control of output voltage and current slew rates is achieved
via two feedback loops. One loop controls the MOSFET
drain dV/dt and the other loop controls the MOSFET dI/dt.

The voltage slew rate uses an external capacitor between
CAP A or CAP B and the respective MOSFET drain. These
integrating caps close the voltage feedback loop. The
external resistor R

sets the current for the integrator.

VSL

10

1683f

OPERATIO

LT1683

U

The voltage slew rate is thus inversely proportional to both
the value of capacitor and R

The current slew feedback loop consists of the voltage
across the external sense resistor, which is internally
amplified and differentiated. The derivative is limited to a
value set by R
proportional to both the value of sense resistor and R

The two control loops are combined internally so that a
smooth transition from current slew control to voltage
slew control is obtained. When turning on, the driver
current will slew before voltage. When turning off, voltage
will slew before current. In general it is desirable to have
R

and R

VSL

Internal Regulator

Most of the control circuitry operates from an internal 2.4V
low dropout regulator that is powered from VIN. The
internal low dropout design allows VIN to vary from 2.7V
to 20V with stable operation of the controller. When SHDN
< 1.3V the internal regulator is completely disabled.

5V Regulator

A 5V regulator is provided for powering external circuitry.
This regulator draws current from VIN and requires VIN to
be greater than 6.5V to be in regulation. It can sink or
source 10mA. The output is current limited to prevent
against destruction from accidental short circuits.

Safety and Protection Features

There are several safety and protection features on the
chip. The first is overcurrent limit. Normally the gate
drivers will go low when the output of the internal sense
amplifier exceeds the voltage on the VC pin. The VC pin is
clamped such that maximum output current is attained
when the CS pin voltage is 0.1V. At that level the outputs
will be immediately turned off (no slew). The effect of this
control is that the output voltage will foldback with
overcurrent.

In addition, if the CS voltage exceeds 0.22V, the VC and SS
pins will be discharged to ground also, resetting the soft­start function. Thus if a short is present this will allow for
faster MOSFET turnoff and less MOSFET stress.

. The current slew rate is thus inversely

CSL

of similar value.

CSL

VSL

.

CSL.

If the voltage on the FB pin exceeds regulation by approxi­mately 0.22V, the outputs will immediately go low. The
implication is that there is an overvoltage fault.

The voltage on GCL determines two features. The first is
the maximum gate drive voltage. This will protect the
MOSFET gate from overvoltage.

With GCL tied to a Zener or an external voltage source then
the maximum gate driver voltage is approximately
V

␣ – 0.2V. If GCL is tied to VIN, then the maximum gate

GCL

voltage is determined by VIN and is approximately
VIN – 1.6V. There is an internal 19V Zener on the GCL pin
that prevents the gate driver pin from exceeding approxi­mately 19V.

In addition, the GCL voltage determines undervoltage
lockout of the gate drives. This feature disables the gate
drivers if VIN is too low to provide adequate voltage to turn
on the MOSFETs. This is helpful during start up to insure
the MOSFETs have sufficient gate drive to saturate.

If GCL is tied to a voltage source or Zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds GCL
voltage by 0.8V. For V
insured to be off for VIN < 7.3V and they will be turned on
by V

If GCL is tied to VIN, the gate drivers are always enabled
(undervoltage lockout is disabled).

When driving a push pull transformer, it is important to
make sure that both drivers are not on at the same time.
Even though runaway cannot occur under such cross
conduction with this chip because current slew is regu­lated, increased current would be possible. This chip has
opposite gate lockout whereby when one MOSFET is on
the other MOSFET cannot be turned on until the gate of the
first drops below 1V. This insures that cross conduction
will not occur.

The gate drives have current limits for the drive currents.
If the sink or source current is greater than 300mA then the
current will be limited.

The V5 regulator also has internal current limiting that will
only guarantee ±10mA output current.

GCL

+ 0.8V.

above 6.5V, the gate drives are

GCL

1683f

11

LT1683

OPERATIO

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There is also an on chip thermal shutdown circuit that will
turn off the outputs in the event the chip temperature rises
to dangerous levels. Thermal shutdown has hysteresis
that will cause a low frequency (<1kHz) oscillation to occur
as the chip heats up and cools down.

The chip has an undervoltage lockout feature that will
force the gate drivers low in the event that VIN drops below

Table 1. Safety and Protection Features

FEATURE FUNCTION EFFECT on GATE DRIVERS SLEW CONTROL EFFECT on VC, SS

Maximum Current Fault Turn Off FETs at Maximum Immediately Goes Low Overridden None

Switch Current (V

Short-Circuit Fault Turn Off FETs and Reset V

for Short-Circuit (V

Overvoltage Fault Turn Off Drivers If FB > V

(Output Overvoltage)

GCL Clamp Set Max Gate Voltage to Prevent Limits Max Voltage None None

FET Gate Breakdown

Gate Drive Disable Gate Drives When V
Undervoltage Lockout Is Too Low. Set Via GCL Pin

Thermal Shutdown Turn Off Drivers If Chip Immediately Goes Low Overridden None

Temperature Is Too Hot

Opposite Gate Lockout Prevents Opposite Driver from Inhibits Turn On of None None

Turning on Until Driver Is Off Opposite Driver

(Cross Conduction in Transformer)
VIN Undervoltage Lockout Disable Part When VIN ≅ 2.55V Immediately Goes Low Overridden None
Gate Drive Source and Sink Current Limit Limit Gate Drive Current Limit Drive Current None None
V5 Source/Sink Current Limit Limit Current from V5 None None None
Shutdown Disable Part When SHDN <1.3V

= 0.1)

SENSE

= 0.2) to GND

SENSE

2.5V. This insures predictable behavior during start up and
shut down. SHDN can be used in conjuction with an
external resistor divider to completely disable the part if
the input voltage is too low. This can be used to insure
adequate voltage to reliably run the converter. See the
section in Applications Information.

Table 1 summarizes these features.

C

+ 0.22V Immediately Goes Low Overridden None

REG

IN

Immediately Goes Low Overridden Discharge VC, SS

Immediately Goes Low Overridden None

12

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APPLICATIO S I FOR ATIO

Reducing EMI from switching power supplies has tradi­tionally invoked fear in designers. Many switchers are
designed solely on efficiency and as such produce wave­forms filled with high frequency harmonics that then
propagate through the rest of the system.

The LT1683 provides control over two of the more impor­tant variables for controlling EMI with switching inductive
loads: switch voltage slew rate and switch current slew
rate. The use of this part will reduce noise and EMI over
conventional switch mode controllers. Because these
variables are under control, a supply built with this part will
exhibit far less tendency to create EMI and less chance of
encountering problems during production.

It is beyond the scope of this data sheet to get into EMI
fundamentals. Application Note 70 contains much infor­mation concerning noise in switching regulators and
should be consulted.

Oscillator Frequency

The oscillator determines the switching frequency and
therefore the fundamental positioning of all harmonics.
The use of good quality external components is important
to ensure oscillator frequency stability. The oscillator is of
a sawtooth design. A current defined by external resistor
RT is used to charge and discharge the capacitor CT . The
discharge rate is approximately ten times the charge rate.

By allowing the user to have control over both compo­nents, trimming of oscillator frequency can be more easily
achieved.

The external capacitance CT is chosen by:

Nominally RT should be 16.9k. Since it sets up current, its
temperature coefficient should be selected to compliment
the capacitor. Ideally, both should have low temperature
coefficients.

Oscillator frequency is important for noise reduction in
two ways. First the lower the oscillator frequency the lower
the waveform’s harmonics, making it easier to filter them.
Second the oscillator will control the placement of the
output voltage harmonics which can aid in specific prob­lems where you might be trying to avoid a certain fre­quency bandwidth.

Oscillator Sync

If a more precise frequency is desired (e.g., to accurately
place harmonics) the oscillator can be synchronized to an
external clock. Set the RC timing components for an
oscillator frequency 10% lower than the desired sync
frequency.

Drive the SYNC pin with a square wave (with greater than

1.4V amplitude). The rising edge of the sync square wave
will initiate clock discharge. The sync pulse should have a
minimum pulse width of 0.5µs.

Be careful in sync’ing to frequencies much different from
the part since the internal oscillator charge slope deter­mines slope compensation. It would be possible to get into
subharmonic oscillation if the sync doesn’t allow for the
charge cycle of the capacitor to initiate slope compensa­tion. In general, this will not be a problem until the sync
frequency is greater than 1.5 times the oscillator free-run
frequency.

CnF

()

=

T

where f is the desired oscillator frequency in kHz. For R
equal to 16.9k, this simplifies to:

CnF

()

=

T

e.g., CT = 1.29nF for f = 100kHz

2180

f kHz R k

()•()

129

f kHz

()

Ω

T

T

Slew Rate Setting

The primary reason to use this part is to gain advantage of
lower EMI and noise due to slew control. The rolloff in
higher frequency harmonics has its theoretical basis with
two primary components. First, the clock frequency sets
the fundamental positioning of harmonics and second, the
associated normal frequency rolloff of harmonics.

1683f

13

LT1683

C1

MOSFET DRAIN

C2

CAP A OR B

C3

1683 F02

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APPLICATIO S I FOR ATIO

This part creates a second higher frequency rolloff of
harmonics that inversely depends on the slew time, the
time that voltage or current spends between the off state
and on state. This time is adjustable through the choice of
the slew resistors, the external resistors to ground on the
R

and R

VSL

the external voltage feedback capacitors CAV, CBV (from
CAP A or CAP B to their respective MOSFET drains) and the
sense resistor. Lower slew rates (longer slew times, lower
frequency for harmonics rolloff) is created with higher
values of R
resistor

Setting the voltage and current slew rates should be done
empirically. The most practical way of determining these
components is to set CAV, CBV and the sense resistor
value. Then, start by making R
resistor pot in series with 3.3k. Starting from the lowest
resistor setting (fast slew) adjust the pots until the noise
level meets your guidelines. Note that slower slewing
waveforms will dissipate more power so that efficiency
will drop. You can monitor this as you make your slew
adjustment by measuring input and output voltage and
their respective currents. Monitor the MOSFET tempera­ture as slew rates are slowed. These components will heat
up as efficiency decreases.

pins and the external components used for

CSL

, R

VSL

, CAV, CBV and the current sense

CSL

, R

VSL

each a 50k

CSL

normally set with consideration of the maximum current
in the MOSFETs.

Setting the voltage slew also involves selection of the
capacitors CAV, CBV. The voltage slew time is proportional
to the output voltage swing (basically input voltage), the
external voltage feedback capacitor and the R

VSL

value.
Thus at higher input voltages smaller capacitors will be
used with lower R

values. For a starting point use

VSL

Table␣ 2.

Table 2

INPUT VOLTAGE CAPACITOR VALUE

< 25V 5pF
50V 2.5pF
100V 1pF

Smaller value capacitors can be made in two ways. The
first is simply combining two capacitors in series. The
equivalent capacitance is then (C1 • C2)/(C1 + C2).

The second method makes use of a capacitor divider. Care
should be taken that the voltage ratings of the capacitors
satisfy the full voltage swing (2x input voltage for push­pull configurations) thus essentially the same rating as the
MOSFETs.

Measuring noise should be done carefully. It is easy to
introduce noise by poor measurement techniques. Con­sult AN70 for recommended measurement techniques.
Keeping probe ground leads very short is essential.

Usually it will be desirable to keep the voltage and current
slew resistors approximately the same. There are circum­stances where a better optimization can be found by
adjusting each separately, but as these values are sepa­rated further, a loss of independence of control may occur.

It is possible to use a single slew setting resistor. In this
case the R

VSL

and R

pins are tied together. A resistor

CSL

with a value of 1.8k to 34k (one half the individual resis­tors) can then be tied from these pins to ground.

In general only the R

value will be available for adjust-

CSL

ment of current slew. The current slew time does also
depend on the current sense resistor but this resistor is

14

Figure 2

The equivalent slew capacitance for Figure 2 is (C1 • C2)/
(C1 + C2 + C3).

Positive Output Voltage Setting

Sensing of a positive output voltage is usually done using
a resistor divider from the output to the FB pin. The
positive input to the error amp is connected internally to a

1.25V bandgap reference. The FB pin will regulate to this
voltage.

Referring to Figure 3, R1 is determined by:

RR

12



V



125



OUT

.



1=−





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LT1683

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APPLICATIO S I FOR ATIO

The FB bias current represents a small error and can
usually be ignored for values of R1||R2 up to 10k.

One word of caution, sometimes a feedback zero is added
to the control loop by placing a capacitor across R1. If the
feedback capacitively pulls the FB pin above the internal
regulator voltage (2.4V), output regulation may be dis­rupted. A series resistance with the feedback pin can
eliminate this potential problem. There is an internal clamp
on FB that clamps at 0.7V above the regulation voltage that
should also help prevent this problem.

R1

FB PIN

R2

Figure 3

Negative Output Voltage Setting

Negative output voltage can be sensed using the NFB pin.
In this case regulation will occur when the NFB pin is at
–2.5V. The nominal input bias current for the NFB is –25µA
(I

), which needs to be accounted for in setting up the

NFB

divider.
Referring to Figure 4, R1 is chosen such that:

V

OUT

1683 F03

LT1683 will act to prevent either output from going
beyond its set output voltage. The highest output (lightest
load) will dominate control of the regulator. This technique
would prevent either output from going unregulated high
at no load. However, this technique will also compromise
output load regulation.

Shutdown

If SHDN is pulled low, the regulator will turn off. As the
SHDN pin voltage is increased from ground the internal
bandgap regulator will be powered on. This will set a 1.39V
threshold for turn on of the internal regulator that runs
most of the control circuitry of the regulator. Note after the
control circuitry powers on, gate driver activity will depend
on the voltage of VIN with respect to the voltage on GCL.

As the SHDN pin enables the internal regulator a 24µA
current will be sourced from the pin that can provide
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage sag
from an initial high current draw.

In addition to the current hysteresis, there is also approxi­mately 100mV of voltage hysteresis on the SHDN pin.

When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.

.

25








=

RR

12



V

OUT

−




.•

+µ

RA

25 2 25



A suggested value for R2 is 2.5k. The NFB pin is normally
left open if the FB pin is being used.

R1

NFB PIN

I

NFB

R2

Figure 4

–V

1683 F04

OUT

Dual Polarity Output Voltage Sensing

Certain applications may benefit from sensing both posi­tive and negative output voltages. When doing this each
output voltage resistor divider is individually set as previ­ously described. When both FB and NFB pins are used, the

If a resistor divider is used to set the turn on threshold then
the resistors are determined by the following equations.



V

ON SHDN

VRA

HYST

RA RB

=





=

+

RB



•








•

V





V

∆

SHDN

RA RB

+

I

SHDN

RA

V

IN

SHDN

RB








Reworking these equations yields:

(• • )

VV VV

RA

HYST SHDN ON SHDN

=

(• )

(• • )

VV VV

HYST SHDN ON SHDN

=

RB

IVV

SHDN ON SHDN

[]

−

IV

SHDN SHDN

−

−

•( )

∆

∆

1683f

15

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APPLICATIO S I FOR ATIO

So if we wanted to turn on at 20V with 2V of hysteresis:

•. •.

2 1 39 20 0 1

RA

RB

VVVV

=

•. •.

2 1 39 20 0 1

VVVV

=

µ

24 20 1 39

Resistor values could be altered further by adding Zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
voltage.

Frequency Compensation

Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(VC␣ pin).

Referring to Figure 6, the main pole is formed by capacitor
CVC and the output impedance of the error amplifier
(approximately 400kΩ). The series resistor RVC creates a
“zero” which improves loop stability and transient re­sponse. A second capacitor C
size of the main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the V
pin. VC pin ripple is caused by output voltage ripple
attenuated by the output divider and multiplied by the error
amplifier. Without the second capacitor, VC pin ripple is:

−

µ

•.

24 1 39

AV

−

•( . )

AV V

C

0.01µF

−

R

VC

2k

VC

Figure 6

VC2

C

4.7nF

, typically one-tenth the

=

=

VC2

.

23 4

.

175

VC PIN

1683 F06

k

k

C

To prevent irregular switching, VC pin ripple should be
kept below 50mV

. Worst-case VC pin ripple occurs at

P-P

maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor for C

pin reduces

VC2

switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.

Setting Current Limit

The sense resistor sets the value for maximum operating
current. When the CS pin voltage is 0.1V the gate drivers
will immediately go low (no slew control). Therefore the
sense resistor value should be set to RS = 0.1V/I
where I
I

SW(PEAK)

SW(PEAK)

will depend on the topology and component

is the peak current in the MOSFETs.

SW(PEAK)

,

values and tolerances. Certainly it should be set below the
saturation current value for the transformer.

If CS pin voltage is 0.22V in addition to the drivers going
low, VC and SS will be discharged to ground. This is to
provide additional protection in the event of a short circuit.
By discharging VC and SS the MOSFET will not be stressed
as hard on subsequent cycles since the current trip will be
set lower.

Turn off of the MOSFETs will normally be inhibited for
about 100ns at the start of every turn on cycle. This is to
prevent noise from interfering with normal operation of
the controller. This current sense blanking does not pre­vent the outputs from be turned off in the event of a fault.
Slewing of the gate voltage effectively provides additional
blanking.

Traces to the SENSE resistor should be kept short and
wide to minimize resistance and inductance.

V

CPINRIPPLE

where V

125.• • •

=

= Output ripple (V

RIPPLE

RIPPLE VC

V

OUT

)

P-P

VgmR

gm = Error amplifier transconductance
RVC = Series resistor on VC pin
V

= DC output voltage

OUT

16

Soft-Start

The soft-start pin is used to provide control of switching
current during startup. The max voltage on the VC pin is
approximately the voltage on the SS pin. A current source
will linearly charge a capacitor on the SS pin. The VC pin
voltage will thus ramp also. The approximate time for the
voltage on these pins to ramp is (1.31V/9µA) • CSS or
approximately 146ms per µF.

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APPLICATIO S I FOR ATIO

The soft-start current will be initiated as soon as the part
turns on. Soft-start will be reinititated after a short-circuit
fault.

Thermal Considerations

Most of the IC power dissipation is derived from the V
pin. The VIN current depends on a number of factors
including: oscillator frequency; loads on V5; slew settings;
gate charge current. Additional power is dissipated if V5
sinks current and during the MOSFET gate discharge.

The power dissipation in the IC will be the sum of:

1) The RMS VIN current times V

IN

2) V5 RMS sink current times 5V

3) The gate drive’s RMS discharge current times voltage
Because of the strong VIN component it is advantageous

to operate the LT1683 at as low a VIN as possible.
It is always recommended that package temperature be

measured in each application. The part has an internal
thermal shutdown to minimize the chance of IC destruc­tion but this should not replace careful thermal design.

The thermal shutdown feature does not protect the exter­nal MOSFETs. A separate analysis must be done for those
devices to insure that they are operating within safe limits.

Once IC power dissipation, P

, is determined die junc-

DIS

tion temperature is then computed as:

TJ = T

where T
thermal resistance. For the 20-pin SSOP, θ

+ P

AMB

is ambient temperature and θ

AMB

DIS

• θ

JA

is the package

JA

is 100°C/W.

JA

Magnetics

Design of magnetics is dependent on topology. The fol­lowing details the design of the magnetics for a push-pull
converter. In this converter the transformer usually stores
little energy. The following equations should be consid­ered as the starting point to building a prototype.

The following definitions will be used:
VIN = Input supply voltage
RON = Switch-on resistance

IN

ISW = Maximum switch current
V

= Desired output voltage

OUT

I

= Output current

OUT

f = Oscillator frequency
VF = Forward drop of the rectifier
Duty cycle is the major defining equation for this topology.

Note that the output L and C basically filter the chopped
voltage so duty cycle controls output voltage. N is the
turns ratio of the transformer. The turns ratio must be
large enough to ensure that the transformer can put out a
voltage equal to the output voltage plus the diode under
minimum input conditions. Note the transformer operates
at half the oscillator frequency (f).

VV

+

OUT F

−+

()

[]

()

DC

N

=

DC V I R R

2•

()

is the maximum duty cycle of each driver with

MAX

MAX IN MIN SW ON SENSE

respect to the entire cycle, which consists of two periods
(A on and B on). So the effective duty cycle is 2 • DC

MAX

.
The controller, in general, determines maximum duty
cycle. A 44% maximum duty cycle is a guaranteed value
for this part.

Remember to add sufficient margin in the turns ratio to
account for IR drops in the transformer windings, worst­case diode forward drops and switch on voltage. Also at
very slow slew rates the effective DC may be reduced.

There are a number of ways to choose the inductance
value for L. We suggest as a starting point that L be
selected such that the converter is continuous at
I

OUT(MAX)

/4. If your minimum I

is higher than this or

OUT

your components can handle higher peak currents then
use a higher number.

D1

1:N

V

IN

L

PRI

D2

R

SENSE

Figure 7. Push-Pull Topology

L

V

OUT

CR

OUT

1683 F07

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Continuous operation occurs when the current in the
inductor never goes to zero. Discontinuous operation
occurs when the inductor current drops to zero before the
start of the next cycle and can occur with small inductors
and light loads. There is nothing inherently bad about
discontinuous operation, however, converter control and
operation are somewhat different. The inductor is smaller
for discontinuous operation but the peak currents in the
switch, the transformer, the diodes, inductor and capaci­tor will be higher which may produce greater losses.

For continuous operation the inductor ripple current must
be less than twice the output current. The worst case for
this is at maximum input (lowest duty cycle, DC
the following we will evaluate at nominal input since the
I

/4 is somewhat arbitrary.

OUT

Note when both inputs are off, the inductor current splits
between both secondary outputs and the diode common
goes to 0V.

Looking at the inductor current during off time, output
ripple current is:

∆=

II

OUT OUT MIN

II

OUT MIN OUT MAX

=

L

•

2

() ( )

VVDC

OUT MIN F

()

=

+

()

∆

()

/

4

••

12

−

()

•

If

OUT

MIN

) but in

With the value of L set, the ripple in the inductor is:

+

VV DC

OUT F

()

∆=

I

L

However, the peak inductor current is evaluated at maxi­mum load and maximum input voltage (minimum DC).

II

LMAX LMAX

The magnetizing ripple current can be shown to be:

∆=

and the peak current in the switch is:

I

SW(PEAK)

This current should be less than the current limit.
Worst-case switch ripple is:

∆I

In the push-pull converter the maximum switch voltage
will be 2 • VIN. Because voltage is slew-controlled, the
leakage spikes are small. So, the MOSFET should have a
maximum rated switch voltage at least 20% higher than
2␣ • VIN.

=+

() ()

+

VV

I

MAG

SW(PEAK)

OUT F

••

NL f

PRI

= N • I

= N • ∆I

−

••

12

()

Lf

•

I

∆

LMAX

()

2

+ ∆I

L(MAX)

L(MAX)

MAG

+ ∆I

MAG

The inductance of the transformer primary should be such
that L, when reflected into the primary, dominates the
input current. In other words, we want the magnetizing
current of the transformer small with respect to the
current going through the transformer to L. In general,
then, the inductance of the primary should be at least five
times that of L reflected to the input. This ensures that
most of the power will be passed through the transformer
to the load. It also increases the power capability of the
converter and reduces the peak currents that the switch
will see.

L

5

L

PRI

If the magnetizing current is small, say below 100mA, then
a smaller L can be used with a higher percentage of the
switch current generated by the magnetizing current.

•

=

2

N

18

So, given the turns ratio, primary inductance and current,
the transformer can be designed. The design of the trans­former will require analyzing the power losses of the
transformer and making necessary adjustments.

Most transformer companies can assist you with design­ing an optimal solution. For instance Midcom, Inc. (1-800­643-2661). Linear Technology’s application group can
also help.

As an example say we are designing a 48V ±20% to 5V
100kHz converter with 2A output and 500mA ripple. Then
starting with a guess for the on voltage of the MOSFET plus
sense resistor of 0.5V and VF of 0.5V:

+

N =

88 48 80 0 5

505

%• • % .

()

.

−

1

=

61

.

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LT1683

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APPLICATIO S I FOR ATIO

For continuous operation at I
inductor ripple (the same as output ripple):

A

∆= =I

L

The duty cycle for nominal input is:

DC

Then

L

Off-the-shelf components can be used for this inductor.
Say we choose a 22µH inductor then ripple current at
maximum input (DC = 29.1%) is:

∆=

L

The maximum inductor current is:

2

2

=

NOM

==

+

505 12353

()

505 12291

()

A

1•

4

VV

OUT F

NV I R

2

••

2

.

61

.• • .%

1 100

A kHz

+

22 100

()

IN NOM SW ON

()

55

.

•.

47 5

−

()

•

.• • .%

−

()

•

µ=IF kHz

+

−

.%

35 3

OUT(MIN)

=µ

16

= I

H=

.

103

OUT(MAX)

A

/4,

Peak switch current is:

1

•.=+=

I A mA mA

SW PEAK()

Note that you can discern your magnetizing ripple by
looking at the reflected inductance ripple and subtracting
it from the switch current ripple.

∆I

= N • IL – ∆I

MAG

The max ripple current on the switch is:

∆=+=I

SW MAX()

Knowing the peak switch current we can go back and
iterate with a more accurate switch on voltage. We would
have to know the RON of the FET. In our case our assump­tions of a 0.5V switch on voltage is valid for
RON + R

Capacitors

Correct choice of input and output capacitors is very
important to low noise switcher performance. Push-pull
topologies and other low noise topologies will in general
have continuous currents, which reduce the requirements
for capacitance. However, noise depends more on the ESR
of the capacitors. In addition lower ESR can also improve
efficiency.

SENSE

< 1Ω.

2 51 81 494

.

61

SW

A

.

103

.

61

mA A

81 0 25

.

A

.

IA

L MAX()

Primary inductance should be greater than:

L

= 5 • 22µH • 6.12 = 4.1mH

PRI

The secondary inductance would then be:

4.1mH/6.12 = 110µH

The magnetizing ripple current is approximately:

∆= =I

MAG

103

1

•. •

4 1 100

.

61

.=+ =2

252

2

55

.

mH kHz

A

mA

81

Input capacitors must also withstand surges that occur
during the switching of some types of loads. Some solid
tantalum capacitors can fail under these surge conditions.

Design Note 95 offers more information but the following
is a brief summary of capacitor types and attributes.

Aluminum Electrolytic:

can be used in this application but in general you will need
higher capacitance to achieve low ESR. Additional
nonelectrolytic capacitors may be required to achieve
better performance.

Specialty Polymer Aluminum:

with their series CD capacitors. While they are only avail­able for voltages below 16V, they have very low ESR and
good surge capability.

Low cost and higher voltage. They

Panasonic has come out

1683f

19

LT1683

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APPLICATIO S I FOR ATIO

Solid Tantalum:

the maximum voltage rating is 50V. With large surge
currents the capacitor may need to be derated or you need
a special type such as AVX TPS line.

OS-CON:

able for 35V or less. Form factor may be a problem.

Ceramic:

voltage bypass. They may resonate with their ESL before
ESR becomes dominant. Recent multilayer ceramic (MLC)
capacitors provide larger capacitance with low ESR.

There are continuous improvements being made in ca­pacitors so consult with manufacturers as to your specific
needs.

Input Capacitors

The input capacitor should have low ESR at high frequen­cies since this will be an important factor concerning how
much conducted noise is created.

There are two separate requirements for input capacitors.
The first is for supply to the part’s VIN pin. The VIN pin will
provide current for the part itself and the gate charge
current.

The worst component from an AC point is the gate charge
current. The actual peak current depends on gate capaci­tance and slew rate, being higher for larger values of each.
The total current can be estimated by gate charge and
frequency of operation. Because of the slewing with this
part gate charge is spread out over a longer time period
than with a normal FET driver. This reduces capacitance
requirements.

Typically the current will have spikes of under 100mA
located at the gate voltage transitions. This is charge/
discharge to and from the threshold voltage. Most slewing
occurs with the gate voltage near threshold.

Since the part’s VIN will typically be under 15V many
options are available for choice of capacitor. Values of

Small size and low impedance. Typically

Lower impedance than aluminum but only avail-

Generally used for high frequency and high

input capacitor for just VIN requirement will typically be in
the 50µF range with an ESR of under 0.1Ω.

In addition to the part supply, decoupling of the supply to
the transformer needs to be considered. If this is the same
supply as the VIN pin then that capacitor will need to be
increased. However, often with this part the transformer
supply will be a higher voltage and as such a separate
capacitor.

The transformer decoupling capacitor will see the switch
current as ripple.

The above switch current computation can be used to
estimate the capacity for these capacitors.

ESR

ESR

•

•

DC

DC

MIN

f

MIN

f

C

=

IN

∆

where ∆V
ESR is the equivalent series resistance for the cap. In
general allowed sag will be a few tenths of volts.

Output Filter Capacitor

The output capacitor is chosen both for capacity and ESR.
The capacity must supply the load current in the switch off
state. While slew control reduces higher frequency com­ponents of the ripple current in the capacitor, the capacitor
ESR and the magnitude of the output ripple current
controls the fundamental component. ESR should also be
low to reduce capacitor dissipation.

The capacitance value can be computed by consideration
of desired load ripple, duty cycle and ESR.

C

OUT

CAP

=

1

V

∆

CAP

−

I

()

SW MAX

is the allowed sag on the input capacitor.

1

V

∆

OUT

−

I

∆

()

LMAX

20

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LT1683

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APPLICATIO S I FOR ATIO

MOSFET Selection

There is a wide variety of MOSFETs to choose from for this
part. The part will work with either normal threshold (3V to
4V) or logic level threshold devices (1V to 2V).

Select a voltage rating to insure under worst-case condi­tions that the MOSFET will not break down. Next choose an
R

sufficiently low to meet both the power dissipation

ON

capabilities of the MOSFET package as well as overall
efficiency needs of the converter.

The LT1683 can handle a large range of gate charges.
However at very large charge stability may be affected.

The power dissipation in the MOSFET depends on several
factors. The primary element is I2R heating when the
device is on. In addition, power is dissipated when the
device is slewing. An estimate for power dissipation is:







PV

=



IN



∆

2

I

+

•
I

SR






2

fIR DC

•••

+

ON



2

I

4

22



−+

VR I

IN ON





+



3

•

2

•




V

SR

4





2



∆

I

























Setting GCL Voltage

Setting the voltage on the GCL pin depends on what type
of MOSFET is used and the desired gate drive undervolt­age lockout voltage.

First determine the maximum gate drive that you require.
Typically you will want it to be at least 2V greater than the
maximum threshold. Higher voltages will lower the on
resistance and increase efficiency. Be certain to check the
maximum allowed gate voltage. Often this is 20V but for
some logic threshold MOSFETs it is only 8V to 10V.

V

needs to be set approximately 0.2V above the desired

GCL

max gate threshold. In addition VIN needs to be at least

1.6V above the gate voltage.
The GCL pin can be tied to VIN which will result in a

maximum gate voltage of V

– 1.6V.

IN

This pin also controls undervoltage lockout of the gate
drives. The undervoltage lockout will prevent the MOSFETs
from switching until there is sufficient drive present.

If GCL is tied to a voltage source or Zener less than 6.8V,
the gate drivers will not turn on until VIN exceeds the GCL
voltage by 0.8V. For V

above 6.5V, the gate drives are

GCL

insured to be off for VIN < 7.3V and they will be turned on
by V

GCL

+ 0.8V.

where I is the average current, ∆I is the ripple current in the
switch, ISR is the current slew rate, VSR is the voltage slew
rate, f is the oscillator frequency, DC is the duty cycle and
RON is the MOSFET on-resistance.

If GCL is tied to VIN, the gate drivers are always on
(undervoltage lockout is disabled).

Approximately 50µA of current can be sourced from this
pin if VIN > V

+ 0.8V. This could be used to bias a Zener.

GCL

The GCL pin has an internal 19V Zener to ground that will
provide a failsafe for maximum gate voltage.

As an example say we are using a Siliconix Si4480DY
which has R

rated at 6V. To get 6V, V

DS(ON)

needs to be

GCL

set to 6.2V and VIN needs to be at least 7.6V.

1683f

21

LT1683

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APPLICATIO S I FOR ATIO

Gate Driver Considerations

In general, the MOSFETs should be positioned as close to
the part as possible to minimize inductance.

When the part is active the gate drives will be pulled low to
less than 0.2V. When the part is off, the gate drives contain
a 40k resistor in series with a diode to ground that will offer
passive holdoff protection. If you are using some logic
level MOSFETs this might not be sufficient. A resistor may
be placed from gate to ground, however the value should
be reasonably high to minimize DC losses and possible AC
issues.

The gate drive source current comes from VIN. The sink
current exits through PGND. In general the decoupling cap
should be placed close to these two pins.

Switching Diodes

In general, switching diodes should be Schottky diodes.
Size and breakdown voltage depend on the specific con­verter. A lower forward drop will improve converter effi­ciency. No other special requirements are needed.

PCB Layout Considerations

As with any switcher careful consideration should be given
to PC board layout. Because this part reduces high fre­quency EMI the board layout is less critical, however high
currents and voltages still produce the need for careful
board layout to eliminate poor and erratic performance.

Basic Considerations

Keep the high current loops physically small in area. The
main loops are shown in Figure 8: the power switch loops
(A and B) and the rectifier loop (C and D). These loops can
be kept small by physically keeping the components close
to one another. In addition, connection traces should be
kept wide to lower resistance and inductances. Compo­nents should be placed to minimize connecting paths.
Careful attention to ground connections must also be
maintained. Without getting into elaborate detail be care­ful that currents from different high current loops do not

get coupled into the ground paths of other loops. Using
singular points of connection for the grounds is the best
way to do this. The two major points of connection are the
bottom of the input decoupling cap and the bottom of the
output decoupling cap. Typically the sense resistor device
PGND and device GND will tie to the bottom of the input
cap.

There are two other loops to pay attention to. The current
slew involves a high bandwidth control that goes through
the MOSFET switch, the sense resistor and into the CS pin
of the part and out the GATE pin to the MOSFET. Trace
inductance and resistance should be kept low on the GATE
drive trace. The CS trace should have low inductance. The
sense resistor should be physically close to PGND and the
MOSFETs’ sources.

Finally care should be taken with the CAP A, CAP B pins.
The part will tolerate stray capacitance to ground on these
pins (<5pF) however stray capacitance to the respective
drains should be minimized. This path would provide an
alternate capacitive path for the voltage slew.

More Help

AN70 contains information about low noise switchers and
measurement of noise and should be consulted. AN19 and
AN29 also have general knowledge concerning switching
regulators. Also, our Application Department is always
ready to lend a helping hand.

A

B

C

A

IN

GATE A GATE B

CS

Figure 8

3

1

2

D

C

4

1683 F08

C

OUT

22

1683f

TYPICAL APPLICATIO

LT1683

U

Ultralow Noise 48V to ±12V DC/DC Converter

10k

D2

D3

12V

23.2k

976Ω

1200pF

25k

25k

D1

C3

10µF

25V

16.9k

3.3k

3.3k

510Ω

0.5W

FZT853

2N3904

17

V

IN

14 2

SHDN

5

V5

6

SYNC

7

C

T

8

R

T

16

R

VSL

15

R

12

10nF

CSL

V

C

SS

1k

22nF0.22µF

LT1683

GND

1113

C4
22µF
50V

3

GCL

CAP A

GATE A

CAP B

GATE B

PGND

NFB

10

8.2V

CS

FB

1

18

19

4

20

9

5pF

5pF

Si9422

48V

47µF
100V

MBR01100

Si9422

5pF
200V

25pF

CTX0215542

T1

1

6
2

3,4

5

5pF
200V

25pF

0.068Ω

1683 TA03

L1

10µH

33µF

16V, ×2

16V, ×2

L2

10µH

C1

33µF

12V/1A

C2

–12V/1A

10.0k

2.74k

8.66k

C1, C2:SANYO 16TPC33
C3: MURATA GRM235Y5V106Z
C4: NIPPON THCR60EIE226Z
D1, D2, D3 IN4148

1k

D4, D5, D6, D7 MBRS1100
L1, L2: COOPER DS50224
T1: COOPER CTX02-15542

8,9

D4

D5

D6

D7

7

10

PACKAGE DESCRIPTIO

5.20 – 5.38**
(.205 – .212)

° – 8°

0

.13 – .22

(.005 – .009)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

.55 – .95

(.022 – .037)

MILLIMETERS

(INCHES)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

U

G Package

20-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

.65

(.0256)

BSC

.25 – .38

(.010 – .015)

1.73 – 1.99

(.068 – .078)

.05 – .21

(.002 – .008)

G20 SSOP 0501

7.07 – 7.33*
(.278 – .289)

1718 14 13 12 1115161920

7.65 – 7.90

(.301 – .311)

12345678910

1683f

23

LT1683

TYPICAL APPLICATIO

U

Ultralow Noise 24V to 5V DC/DC Converter

11V

6.9k

1.5nF

25k

2N3904

68µF
20V

14 2

SHDN

5

V5

6

SYNC

7

C

16.9k

3.3k

3.3k25k

1k

1nF15nF

8

16

15

12

10nF

T

R

T

R

VSL

R

CSL

V

C

SS

17

V

IN

LT1683

GND

1113

39µF

3

GCL

CAP A

GATE A

CAP B

GATE B

PGND

NFB

10

8.2V

CS

FB

1

18

19

4

20

9

IRF540

24V

3pF

10pF

IRF540

COILTRONICS

VP5-1200

7

6–10

3

11

2–12

1

3pF

10pF

10mΩ

MBR2045CT

9

4
8

5

MBR2045CT

4.7µH

330µF

2×330µF

POSCAP

7.50k

2.49k

OPTIONAL

1µH

5V/5A

1683 TA02

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1533 Ultralow Noise 1A Switching Regulator Push-Pull Design for Low Noise Isolated Supplies
LT1534 Ultralow Noise 2A Switching Regulator Ultralow Noise Regulator for Boost Topologies
LT1738 Ultralow Noise DC/DC Controller High Current Output Ultralow Noise Boost Regulator;

Drives External MOSFET
LT1777 Low Noise Step-Down Switching Regulator Programmable dI/dt; Internally Limited dV/dt
LT1425 Isolated Flyback Switching Regulator Excellent Regulation without Transformer “Third Winding”
LT1576 1.5A, 200kHz Step-Down Switching Regulator Constant Frequency, 1.21V Reference Voltage
LT176X Family Low Dropout, Low Noise Linear Regulator 150mA to 3A, SOT-23 to TO-220
LTC1922-1 Synchronous Phase Modulated Full-Bridge Controller Adaptive DirectSenseTM Zero Voltage Switching, 50W to

Kilowatts, Synchronous Rectification
DirectSense is a trademark of Linear Technology Corporation.

1683f

LT/TP 0402 2K • PRINTED IN USA

24

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2001