Linear LT1225CN8, LT1225CS8 Schematic [ru]
LT1225
Very High Speed
Operational Amplifier
EATU
F
■
Gain of 5 Stable
■
150MHz Gain Bandwidth
■
400V/µs Slew Rate
■
20V/mV DC Gain, RL = 500Ω
■
1mV Maximum Input Offset Voltage
■
±12V Minimum Output Swing into 500Ω
■
Wide Supply Range: ±2.5V to ±15V
■
7mA Supply Current
■
90ns Settling Time to 0.1%, 10V Step
■
Drives All Capacitive Loads
PPLICATI
A
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Wideband Amplifiers
■
Buffers
■
Active Filters
■
Video and RF Amplification
■
Cable Drivers
■
Data Acquisition Systems
RE
S
O
U
S
DUESCRIPTIO
The LT1225 is a very high speed operational amplifier with
excellent DC performance. The LT1225 features reduced
input offset voltage and higher DC gain than devices with
comparable bandwidth and slew rate. The circuit is a
single gain stage with outstanding settling characteristics.
The fast settling time makes the circuit an ideal choice for
data acquisition systems. The output is capable of driving
a 500Ω load to ±12V with ±15V supplies and a 150Ω load
to ±3V on ±5V supplies. The circuit is also capable of
driving large capacitive loads which makes it useful in
buffer or cable driver applications.
The LT1225 is a member of a family of fast, high performance amplifiers that employ Linear Technology
Corporation’s advanced bipolar complementary
processing.
U
O
A
PPLICATITYPICAL
20MHz,AV = 50 Instrumentation Amplifier
+
LT1225
–
1k
+
V
IN
–
250Ω
250Ω
200pF
1k
–
LT1225
+
1k
1k
10k
+
LT1225
–
10k
V
OUT
LT1225 TA01
Gain of 5 Pulse Response
LT1225 TA02
1
LT1225
WU
U
PACKAGE
/
O
RDER I FOR ATIO
W
O
A
LUTEXI T
S
Total Supply Voltage (V+ to V–) .............................. 36V
Differential Input Voltage .........................................±6V
Input Voltage ............................................................±V
Output Short Circuit Duration (Note 1) ............Indefinite
Operating Temperature Range
LT1225C................................................ 0°C to 70°C
Maximum Junction Temperature
Plastic Package .............................................. 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
e
n
i
n
R
IN
C
IN
CMRR Common-Mode Rejection Ratio VCM = ±12V 94 115 dB
PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 86 95 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate (Note 3) 250 400 V/µs
GBW Gain Bandwidth f = 1MHz 150 MHz
tr, t
f
t
s
R
O
I
S
Input Offset Voltage (Note 2) 0.5 1.0 mV
Input Offset Current 100 400 nA
Input Bias Current 48 µA
Input Noise Voltage f = 10kHz 7.5 nV/√Hz
Input Noise Current f = 10kHz 1.5 pA/√Hz
Input Resistance VCM = ±12V 24 40 MΩ
Input Capacitance 2pF
Input Voltage Range + 12 14 V
Input Voltage Range – –13 –12 V
Large Signal Voltage Gain V
Output Swing RL = 500Ω±12.0 ±13.3 V
Output Current V
Full Power Bandwidth 10V Peak, (Note 4) 6.4 MHz
Rise Time, Fall Time A
Overshoot A
Propagation Delay 50% VIN to 50% V
Settling Time 10V Step, 0.1%, AV = –5 90 ns
Differential Gain f = 3.58MHz, AV = 5, RL = 150Ω 1.0 %
Differential Phase f = 3.58MHz, AV = 5, RL = 150Ω 1.7 Deg
Output Resistance A
Supply Current 79 mA
A
WUW
ARB
U
G
S
I
TOP VIEW
1
NULL
S
8-LEAD PLASTIC DIP
ICS
VS = ±15V, TA = 25°C, VCM = 0V unless otherwise noted.
Differential 70 kΩ
= ±10V, RL = 500Ω 12.5 20 V/mV
OUT
= ±12V 24 40 mA
OUT
= 5, 10% to 90%, 0.1V 7 ns
VCL
= 5, 0.1V 20 %
VCL
OUT
= 5, f = 1MHz 4.5 Ω
VCL
2
–IN
3
+IN
–
4
V
N8 PACKAGE
T
= 15O°C, θJA = 130°C/W (N8)
J MAX
= 15O°C, θJA = 220°C/W (S8)
T
J MAX
8
NULL
+
V
7
OUT
6
NC
5
S8 PACKAGE
8-LEAD PLASTIC SOIC
LT1225 PO01
7ns
ORDER PART
NUMBER
LT1225CN8
LT1225CS8
S8 PART MARKING
1225
2
LT1225
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
CMRR Common-Mode Rejection Ratio VCM = ±2.5V 94 115 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate (Note 3) 250 V/µs
GBW Gain Bandwidth f = 1MHz 100 MHz
tr, t
f
t
s
I
S
Input Offset Voltage (Note 2) 1.0 2.0 mV
Input Offset Current 100 400 nA
Input Bias Current 48 µA
Input Voltage Range + 2.5 4 V
Input Voltage Range – –3 – 2.5 V
Large-Signal Voltage Gain V
Output Voltage RL = 500Ω±3.0 ±3.7 V
Output Current V
Full Power Bandwidth 3V Peak, (Note 4) 13.3 MHz
Rise Time, Fall Time A
Overshoot A
Propagation Delay 50% VIN to 50% V
Settling Time – 2.5V to 2.5V, 0.1%, AV = –4 70 ns
Supply Current 79 mA
ICS
VS = ±5V, TA = 25°C, VCM = 0V unless otherwise noted.
= ±2.5V, RL = 500Ω 10 15 V/mV
OUT
= ±2.5V, RL = 150Ω 13 V/mV
V
OUT
= 150Ω±3.0 ±3.3 V
R
L
= ±3V 20 40 mA
OUT
= 5, 10% to 90%, 0.1V 9 ns
VCL
= 5, 0.1V 10 %
VCL
OUT
9ns
LECTRICAL C CHARA TERIST
E
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
I
OS
I
B
CMRR Common-Mode Rejection Ratio VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V 93 115 dB
PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 85 95 dB
A
VOL
V
OUT
I
OUT
SR Slew Rate VS = ±15V, (Note 3) 250 400 V/µs
I
S
Note 1: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 2: Input offset voltage is tested with automated test equipment
in <1 second.
Input Offset Voltage VS = ±15V, (Note 2) 0.5 1.5 mV
= ±5V, (Note 2) 1.0 2.5 mV
V
S
Input V
Input Offset Current VS = ±15V and VS = ±5V 100 600 nA
Input Bias Current VS = ±15V and VS = ±5V 4 9 µA
Large Signal Voltage Gain VS = ±15V, V
Output Swing VS = ±15V, RL = 500Ω±12.0 ±13.3 V
Output Current VS = ±15V, V
Supply Current VS = ±15V and VS = ±5V 7 10.5 mA
Drift 10 µV/°C
OS
= ±5V, V
V
S
= ±5V, RL = 500Ω or 150Ω ±3.0 ±3.3 V
V
S
= ±5V, V
V
S
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
ICS
= ±10V, RL = 500Ω 10 12.5 V/mV
OUT
= ±2.5V, RL = 500Ω 8 10 V/mV
OUT
= ±12V 24 40 mA
OUT
= ±3V 20 40 mA
OUT
Note 3: Slew rate is measured between ±10V on an output swing of ±12V
on ±15V supplies, and ±2V on an output swing of ±3.5V on ±5V supplies.
Note 4: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2πVp.
3
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