LG Innotek VL3000 User Manual

Data sheet for the LTD-VL3000

Product: LTE_CDMA Wireless Modem

Model name: LTD-VL3000

Table of Contents

1. Overview

2. Major features

3. Interface

4. Electrical specifications

5. RF specifications

6. Mechanical specifications

7. General specifications

8. RFx information

9. Approbation FCC

1. Overview

The LTD-VL3000 is a personal mobile communication device that incorporates

the latest compact radio technology, including smaller and lighter components and support for CDMA BC0(850)/ BC1 1900MHz bands and LTE(700/850/1700/1900 MHz). This device acts as the vehicle’s telematics

system and connects to CDMA EVDO and LTE wireless networks and wireless

modules to allow voice and data communication. Furthermore, this device can operate on land and water as well as other similar areas. In LTE mode (CAT4), the device provides uplink speeds of up to 50 Mbps and downlink speeds of up to 150 Mbps for seamless transfer of data such as movies and video calls. The device also supports the transfer of large amounts of data.

The device communicates with the host system via a standard RS-232 or USB

port, and AT commands and control commands can be used to send data. Voice calls are also possible.

34 x 40 x 3.5 mm (L x W x T) (Tolerance

Technology

2. Major features

Dimensions

Weight

Mechanical

Interface

Temperature*

Main chipset

Memory

Standard

TBD g (max)

USB, general purpose I/O pins

Operation: -20 ℃ - +70 ℃ Storage: -40 ℃ - +85 ℃

MDM9628

4Gb(NAND) / 1Gb(SDRAM)

CDMA (EVDO)

LTE

– width, length : TBD)

- DL Speed : 3.1 Mbps

- UL Speed : 1.8 Mbps

- DL Speed : 150 Mbps

ETC

Band

Power

DC power

Functions

- UL Speed : 50 Mbps

CDMA BC0, BC1 LTE B2, B4, B5, B13

CDMA : Typ. 24dBm (Power Class 3) LTE : Typ. 23dBm (Power Class 3)

4 V

Voice, data, SMS

3. Interface

3.1 LGA Pad Layout (Top View)

Figure 1. LGA Pin map

3. Interface

PAD. NAME

DIRECTION

DESCRIPTION

Antenna Interface Pads

MAIN_ANT

RF Main Antenna

DIV_ANT

RF Diversity Antenna

User Interface Pads

ACC_PWR_ON

BOOT_OK

MSG

96H_END

MAIN_ANT_DTC_EN

Main ANT Detect Enable

DIV_ANT_DTC_EN

Diversity ANT Detect Enable

SPI_LEVEL_SHIFT_EN

SPI LEVEL SHIFT Enable

ETHERNET_DCDC_ENABLE

Ethernet power enable

GPIO1

General purpose I/O

GPIO2

General purpose I/O

GPIO3

Input/Output (Not support INTERR UPT)

General purpose I/O

GPIO4

General purpose I/O

ADC Interface Pads

ADC1

ADC Convertor input for main antenna detect

ADC2

ADC Convertor input for diversity antenna detect

PCM Interface Pads

PCM_EN

PCM 3.3 Level Shifter Enable

PCM_CLK

PCM Clock

PCM_SYNC

PCM Frame Sync

PCM_DIN

PCM Data In

PCM_DOUT

PCM Data Out

JTAG Pin Description

MDM_JTAG_TMS

JTAG mode select input

MDM_JTAG_PS_HOLD

JTAG PS HOLD detect

MDM_JTAG_TDI

JTAG data input

MDM_JTAG_TRST_N

JTAG reset for debug

MDM_JTAG_TDO

JTAG debugging

MDM_JTAG_TCK

JTAG clock input

MDM_JTAG_SRST_N

JTAG reset

USB Interface Pads

USB_HS_DM

USB high speed data (minus)

USB_HS_DP

USB high speed data (plus)

USB_VBUS

USB power

USB_ID

USB ID

SDIO Interface Pads

SDC_CLK

Secure digital controller clock

SDC_CMD

Secure digital controller command

SDC_DATA0

Secure digital controller data bit 0

SDC_DATA1

Secure digital controller data bit 1

SDC_DATA2

Secure digital controller data bit 2

3.2 Pin description

C21

AC21

H6

I5

H4

G3 F20 Z20

I7

AD4

F6

E5

L6

N6

E19

AA19

W3

X2

W1

Y3

Y1

AC7

AD8 AD6 AE7 AB6 AB8 AE9

N2

M1

K1

L2

S1

Q1

T2

R2

S3

Input/Output

Input

Output

Input Input

Output

Input

Output

Input/Output

input

Input

Output

Input

Input/Output

Input

Output

Input/Output Input/Output Input/Output

Input/Output

(Do not use

with External PU)

Table 1. Pin descriptions

3. Interface

SDC_DATA3

Secure digital controller data bit 3

SGMMI Interface Pads

EPHY_RST_N or UIM2_RESET

Ethernet PHY reset

EPHY_INT_N or UIM2_DETECT

Ethernet PHY interrupt

SGMII_DATA or UIM2_CLK

SGMII input Output data

GND

Ground

SGMII_RX_P

SGMII receive

SGMII_RX_M

SGMII receive

SGMII_TX_M

SGMII transmit

SGMII_TX_P

SGMII transmit

SGMII_CLK or UIM2_DATA

SGMII clock

SPI Interface Pads

SPI_MOSI

SPI Serial Output

SPI_CLK

SPI Serial Clock

SPI_CS_N

SPI Chip Select

SPI_MISO

SPI Serial input

SPI_INTERRUPT

MICOM → LGA SPI interrupt

UART Interface Pads

UART2_TX

UART2 Transmit data

UART2_RX

UART2 Receive data

UART1_TX

Debug UART5 Transmit Data

UART1_RX

Debug UART5 Receive Data

UART3_TX

UART6 Transmit data

UART3_RX

UART6 Receive data

USIM Interface Pads

UIM1_PRESENT

Detection of an external UIM card

UIM1_CLK

Clock Output to an external UIM card

UIM1_RESET

Reset Output to an external UIM card

UIM1_DATA

Data connection with an external UIM card

VREG_L6_UIM1

Supply Output for an external UIM card

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

HSIC Pin Description

HSIC_DATA

HSIC data

HSIC_STB

HSIC Strobe signal

NC

No Connect

NC

No Connect

DSRC Pin Description

COEX_UART_RX

LTE receiver sync for coexistence with UART

COEX_UART_TX

LTE transmitter sync for coexistence with UART

RFCLK2_QCA

Low noise RF clock Output

NC

No

Q3

AA11

AE11 AB10

AD10

X10

W11

Z10

Y11

AC11

S5 T6 R6 U5 Q5

M5 N4 K5

L4 O5 P4

I3 H2 E1

G1

F2 E3

D2 A1 C1 B2

AB2 AC1 AD2

AE1

Y7

Z6 X4

AA3

Input/Output

Output

Input

Input/Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input/Output

Output

Input/Output

Input

Output

- plus

-minus

- plus

-minus

Connect

Table 1. Pin descriptions

3. Interface

DSRC_SLP_CLK

DSRC sleep clock

WLAN_3V_EN_DSRC

Used for WLAN enable

DSRC_PPS

Pulse Per Second

MDM2AP_INT_N

MDM to AP interrupt, PCM_LDO_EN

AP2MDM_INT_N

AP to MDM interrupt

Control Pads

LGA_PHONE_ON

ON/OFF Control

MDM_RESOUT_N

Reset Output

LGA_RESIN_N

External Reset Input

Power Supply Pads

VPH_PWR for PAM

power supply (4.0V)

VPH_PWR for PAM

power

VPH_PWR for PAM

power

VPH_PWR for PAM

power

VPH_PWR for PMIC

power

VPH_PWR for PMIC

power

VPH_PWR for PMIC

power

VPH_PWR for PMIC

power

Voltage Reference Pad

VREG_L11_1P8

LDO out for 1.8V pull up

VREG_L11_1P8

LDO out for 1.8V pull up

Voltage Reference for SGMII (VREG_L5_UIM2) – Ethernet

IO

Ethernet I/O voltage

NC Pads

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

X6 Y5 Z4 X8 Z8

A3 B4

C3

A17 B16 A15 B14

A9 B8

A7

C7 C9

D8

AE3

G9

B12

I9

G7 C5 D4

A21 E21 G21

I21 K21 M21 O21 Q21 S21 U21

W21

Y21

AA21 AE21

B20 D20 H20

J20

Output

Input/Output

Output Input

Input

Output

Input

Input Input Input Input

Input Input

Input

Output Output

전압 level

Output

supply (4.0V) supply (4.0V) supply (4.0V) supply (4.0V) supply (4.0V)

supply (4.0V)

Table 1. Pin descriptions

3. Interface

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

GND

Ground

L20 N20 P20 R20 T20 V20 X20

AB20 AD20

A19 C19 G19

I19

K19 M19 O19 Q19 S19 U19

W19

Y19

AC19 AE19

B18 D18 F18

H18

J18

L18 N18 P18 R18 T18 V18 X18 Z18

AB18 AD18

C17 E17 G17

I17 K17 M17 O17 Q17 S17 U17

W17

Y17

Table 1. Pin descriptions

LG Innotek VL3000 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual