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LP156WH3
Liquid Crystal Display
Product Specification
1. General Description
The LP156WH3 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 15.6 inches diagonally measured active display area with HD
resolution (1366 horizontal by 768 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP156WH3 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP156WH3 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP156WH3 characteristics provide an excellent flat display for office automation products such
as Notebook PC.
EEPROM Block
for EDID & Tcon
Operating
1
1366
User connector
TFT-LCD Panel
40
Pin
LVDS
1port
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
DVCC
Power
Block
LED Driver
Block
TCLKs
VGH, VGL, GMA
Control & DataPower
768
DVCC, AVDD
GIP CLKs, DSC
VOUT_LED
FB1~2
(HD, GIP, TN)
Source Driver
(Bottom)
LED Backlight Ass’y
EDID signal & Power
General Features
Active Screen Size15.6 inches diagonal
Outline Dimension
Pixel Pitch0.252mm X 0.252 mm
Pixel Format1366 horiz. by 768 vert. Pixels RGB strip arrangement
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LP156WH3
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
ParameterSymbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
VCC-0.34.0Vdcat 25 r 5qC
TOP050qC1
HST-2060qC1
HOP1090%RH1
HST1090%RH1
Values
UnitsNotes
MinMax
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb
Temperature [
]
qC Max, and no condensation of water.
90% 80%
60
50
60%
Humidity[(%)RH]
Storage
40
30
20
10
0
-20
10
20304050
6070800
Dry Bulb Temperature []
Ver. 1.0Dec. 10, 2012
40%
Operation
20%
10%
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LP156WH3
Liquid Crystal Display
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
The LP156WH3 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
Values
ParameterSymbol
MinTypMax
LOGIC :
UnitNotes
Power Supply Input VoltageV
Power Supply Input CurrentMosaicI
Power ConsumptionP
Power Supply Inrush CurrentI
LVDS ImpedanceZ
CC3.03.33.6V1
CC-210245mA2
CC-0.70.8W2
CC_P--1500mA3
LVDS90100110Ω4
BACKLIGHT : ( with LED Driver)
LED Power Input VoltageV
LED Power Input CurrentI
LED Power ConsumptionP
LED Power Inrush CurrentI
LED7.012.021.0V5
LED-190210mA6
LED-2.32.5W6
LED_P--2000mA7
PWM Duty Ratio5-100%8
PWM Jitter
PWM ImpedanceZ
PWM FrequencyF
-
PWM204060kΩ
PWM200-1000Hz10
0-0.2%9
PWM High Level VoltageV
PWM Low Level VoltageV
LED_EN ImpedanceZ
LED_EN High VoltageV
LED_EN Low VoltageV
LED_EN_H3.0-3.6V
LED_EN_L0-0.3V
PWM_H
PWM_L
PWM204060kΩ
3.0-3.6V
0-0.3V
Life Time12,000--Hrs11
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is same
e measu
used
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Liquid Crystal Display
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
3. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
LP156WH3
Rising time
Vcc
0V
10%
90%
3.3V
0.5ms
4. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
5. The measuring position is the connector of LCM and the test conditions are under 25.
6. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
7. The below figures are themeasuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
Rising time
V
LED
90%
12.0V
0V
10%
0.5ms
8. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
9. If Jitter of PWM is bigger than maximum, it may induce flickering.
10. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
11. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
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in
input
in compa
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LP156WH3
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
PinSymbolDescriptionNotes
1NCNo Connection
2VCCLCD Logic and driver power (3.3V Typ.)
3VCCLCD Logic and driver power (3.3V Typ.)
4V EEDIDDDC Power (3.3V)
5NCNo Connection
6Clk EEDIDDDC Clock (LGD P-Vcom Pin)
7DATA EEDIDDDC Data (LGD P-Vcom Pin)
8ORX0-Negative LVDS differential data input
9ORX0+Positive LVDS differential data input
10GNDHigh Speed Ground
11ORX1-Negative LVDS differential data input
12ORX1+Positive LVDS differential data input
13GNDHigh Speed Ground
14ORX2-Negative LVDS differential data input
15ORX2+Positive LVDS differential data input
16GNDHigh Speed Ground
17ORXC-Negative LVDS differential clock input
18ORXC+Positive LVDS differential clock input
19GNDHigh Speed Ground
20
21
22GNDHigh Speed Ground
23
24
25GNDHigh Speed Ground
26
27
28GNDHigh Speed Ground
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
GNDLED Backlight Ground
GNDLED Backlight Ground
GNDLED Backlight Ground
NC
PWMSystem PWM Signal input for dimming
LED_EN
NC
VLEDLED Backlight Power (7V-21V)
VLEDLED Backlight Power (7V-21V)
VLEDLED Backlight Power (7V-21V)
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
LED Backlight On/Off
No Connection
[Interface Chip]
1. LCD :
TLI, TL2356EP(LCD Controller)
Including LVDSReceiver.
2. System : SiW LVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
UJU, IS050-L40B-C10-B or equivalent
[Connector pin arrangement]
140
[EDID & LGD P-Vcom Share pin]
1. Pin for EDID & P-Vcom : #6, #7
2. P-Vcom Address : 01010000
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V
IN
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Product Specification
3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
LP156WH3
Liquid Crystal Display
LVDS -
LVDS +
# |VID| = |(LVDS+) ˀ (LVDS-)|
# V
= {(LVDS+) + (LVDS-)}/2
0V
CM
DescriptionSymbolMinTypMaxUnitNotes
LVDS Differential Voltage|V
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
3-3-2. AC Specification
|VID|
V
CM
|100-600mV-
ID
CM
IN
|VID| /21.2VDD- |VID|/2V-
0.3-VDDV-
T
clk
V
IN_MAXVIN_MIN
VDD=1.8V
LVDS Clock
LVDS Data
t
SKEW
DescriptionSymbolMinMaxUnitNotes
LVDS Clock to Data Skew Margin
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
t
SKEW(Fclk
1) 85MHz > Fclk ˻ 65MHz : -400 ~ +400
2) 65MHz > Fclk ˻ 25MHz : -600 ~ +600
= 1/T
t
SKEW
t
SKEW
t
SKEW_EO
F
DEV
F
MOD
)
clk
- 400+ 400ps
- 600+ 600ps
- 1/7+ 1/7T
-
· 3
-200KHz-
85MHz > Fclk ≥
65MHz
65MHz > Fclk ≥
25MHz
clk
-
%-
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t
SKEW_EO
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LP156WH3
Liquid Crystal Display
Product Specification
LVDS Odd Clock
LVDS Even Clock
LVDS Even Data
Freq.
F
max
F
center
F
min
T
clk
T
clk
< Clock skew margin between channel >
1
F
MOD
F
center
* F
Time
DEV
3-3-3. Data Format
1) LVDS 1 Port
RCLK+
RA+/-
RB+/-
RC+/-
RD+/-
R3R2
G4G3
B5B4
G7G6
Previous(N-1)th CycleNext(N+1)th Cycle
R1R0
G2G1
B3B2
R7R6
< SpreadSpectrum >
G0R5R4R3R2R1R0
B1B0G5G4G3G2G1
DE VSYNC HSYNCB5B4B3B2
XB7B6G7G6R7R6
Current(Nth ) Cycle
G0
B1
DE
R5R4
B0G5
VSYNCHSYNC
X
B7B6
< LVDS Data Format >
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