( ) Preliminary Specification
( ) Final Specification
Title
Customer Sony
MODEL
FOR
APPROVAL
SUPPLIER LG Display Co., Ltd.
*MODEL LP156WF4
Suffix SPU1
*When you obtain standard approval,
please use the above model name without suffix
SIGNATURE APPROVED BY
/
/
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0 Jul., 17, 2013
APPROVED BY
APPROVED BY
S. R. Kim / S.Manager
REVIEWED BY
REVIEWED BY
C. I. Kim / Manager
PREPARED BY
PREPARED BY
S. Y. Kim / Engineer
H. M. Lee / Engineer
Products Engineering Dept.
LG Display Co., Ltd
SIGNATURE
SIGNATURE
0 / 31
Product Specification
Contents
LP156WF4
Liquid Crystal Display
No ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1
2
3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTREISTICS
INTERFACE CONNECTIONS
eDP SIGNAL TIMING SPECIFICATION
SIGNAL TIMING SPECIFICATIONS
SIGNAL TIMING WAVEFORMS
COLOR INPUT DATA REFERNECE
POWER SEQUENCE
Page
1
2
3
4
5
6-7
8
9
10
10
11
12
4
5
A APPENDIX. LGD PROPOSAL FOR SYSTEM COVER DESIGN
6 RELIABLITY
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 Environment
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
9 PRECAUTIONS
Ver. 1.0 Jul., 17, 2013
OPTICAL SFECIFICATIONS
MECHANICAL CHARACTERISTICS
A APPENDIX. Enhanced Extended Display Identification Data
0.1 Jun., 21, 2013 13~14 Update the Color Coordinates & Gray Scale V0.1
18 Update the rear view drawing
29~31 Update the EEDID
1.0 Jul., 17, 2013 - Final Specification V1.0
6 Change the VLED Min. Voltage (6V
13 Change the Contrast Ratio Spec.(800:1 typ.
7V)
700:1 typ.)
EDID
ver.
Ver. 1.0 Jul., 17, 2013
2 / 31
LP156WF4
Liquid Crystal Display
Product Specification
1. General Description
The LP156WF4 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally black mode. This TFT-LCD has 15.6 inches diagonally measured active display area with FHD
resolution (1920 horizontal by 1080 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP156WF4 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP156WF4 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP156WF4 characteristics provide an excellent flat display for office automation products such as
Notebook PC.
EEPROM Block
for Tcon & EDID
1
1920
TFT-LCD Panel
30
eDP
2 Lane
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
DVCC
Power
Block
LED Driver
Block
TCLKs
VGH, VGL, GMA
Control & Data Power
1080
DVCC, AVDD
GSP,GSC,GOE
VOUT_LED
FB1~6
(FHD,AH-IPS)
Source Driver Circuit
EDID signal & Power
General Features
Active Screen Size 15.6 inches diagonal
Outline Dimension
Pixel Pitch 0.17925 mm x 0.17925 mm
Pixel Format 1920 horiz. By 1080 vert. Pixels RGB strip arrangement
Color Depth 6-bit, 262,144 colors
Luminance, White 330 cd/m
Power Consumption Total 5.6W (Typ.) Logic : 1.0W (Typ. @ Mosaic), B/L : 4.6W (Typ. @VLED12V)
Weight 350g (Max.) / 340g (Typ.)
Display Operating Mode Normally Black
Surface Treatment Glare treatment of the front Polarizer
RoHS Compliance Yes
The LP156WF4 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
Unit Notes
Min Typ Max
LOGIC :
Values
Power Supply Input Voltage V
Power Supply Input Current Mosaic I
Power Consumption P
Power Supply Inrush Current I
CC_P
Differential Impedance Z
CC
CC
CC
m
3.0 3.3 3.6 V 1
- 310 360 mA 2
- 1.0 1.2 W 2
- - 1500 mA 3
90 100 110 4
BACKLIGHT : ( with LED Driver)
LED Power Input Voltage V
LED Power Input Current I
LED Power Consumption P
LED Power Inrush Current I
LED
LED
LED
LED_P
7.0 12.0 21.0 V 5
- 385 395 mA 6
- 4.6 4.7 W 6
- - 1500 mA 7
PWM Duty Ratio 5 - 100 %
PWM Jitter
-
0 - 0.2 % 9
8
PWM Impedance Z
PWM Frequency F
PWM High Level Voltage V
PWM Low Level Voltage V
LED_EN Impedance Z
LED_EN High Voltage V
LED_EN Low Voltage V
LED_EN_H
LED_EN_L
PWM
PWM
PWM_H
PWM_L
PWM
20 40 60
200 - 1000 Hz
3.0 - 5.3 V
0 - 0.3 V
20 40 60
3.0 - 5.3 V
0 - 0.3 V
10
Life Time 10,000 - - Hrs 11
Ver. 1.0 Jul., 17, 2013
5 / 31
Liquid Crystal Display
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25
2. This Spec. is the max load condition for the cable impedance designing.
3. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
, fv = 60Hz condition and Mosaic pattern.
LP156WF4
, fv = 60Hz,
Rising time
Vcc
0V
10%
90%
3.3V
0.5ms
4. This impedance value is needed for proper display and measured form eDP Tx to the mating connector.
5. The measuring position is the connector of LCM and the test conditions are under 25.
6. The current and power consumption with LED Driver are under the Vled = 12.0V , 25
, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
7. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
Rising time
V
LED
90%
12.0V
0V
10%
0.5ms
8. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
9. If Jitter of PWM is bigger than maximum, it may induce flickering.
10. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
11. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
Ver. 1.0 Jul., 17, 2013
6 / 31
LP156WF4
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 30 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin Symbol Description Notes
1
NC
2
GND High Speed (Main Link) Ground
3
Lane1_N Complement Signal-Lane 1
4
Lane1_p True Signal-Main Lane 1
5
GND High Speed (Main Link) Ground
6
Lane0_N Complement Signal-Lane 0
7
Lane0_p True Signal-Main Lane 0
8
GND High Speed (Main Link) Ground
9
AUX_P True Signal-Auxiliary Channel
10
AUX_N Complement Signal-Auxiliary Channel
11
GND High Speed (Main Link) Ground
12
VCC
13
VCC
14
NC
15
GND LCM Ground
16
GND LCM Ground
17
HPD HPD signal pin
18
GND LCM Ground (LED Backlight Ground)
19
GND LCM Ground (LED Backlight Ground)
20
GND LCM Ground (LED Backlight Ground)
21
GND LCM Ground (LED Backlight Ground)
22
LED_EN
23
PWM
24
NC No Connection
25
NC No Connection
26
VLED
27
VLED
28
VLED
29
VLED
30
NC No Connection
No Connection
LCD Logic and driver power (3.3V Typ.)
LCD Logic and driver power (3.3V Typ.)
No Connection
LED Backlight On/Off
System PWM Signal input for dimming
LED Backlight Power (7.0V-21V)
LED Backlight Power (7.0V-21V)
LED Backlight Power (7.0V-21V)
LED Backlight Power (7.0V-21V)
[Interface Chip]
1. LCD :
TLI, TL2370DP (LCD Controller
Including eDP Receiver.
2. System : TBD or equivalent
* Pin to Pin compatible with eDP
[Connector]
KN38-30S-0.5H, HRS, 30, 0.5
or its compatibles
[Connector pin arrangement]
30
[LCD Module Rear View]
[LGD P-Vcom Share pin]
1. Pin for P-Vcom : #24, #25
2. P-Vcom Address : 01010000
1
Ver. 1.0 Jul., 17, 2013
7 / 31
LP156WF4
Liquid Crystal Display
Product Specification
3-3. eDP Signal Timing Specifications
3-3-1. DC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
Description Symbol Min Max Unit Notes
Differential peak-to-peak Input voltage
VDIFF p-p
120 -
mV
For high bit rate
40 - For reduced bit rate
Rx DC common mode voltage V
CM
0 2.0 V -
3-3-2. AC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
Description Symbol Min Typ Max Unit Notes
Unit Interval for high bit rate
(2.7Gbps/lane)
Unit Interval for high bit rate
(1.62Gbps/lane)
Lane-to-Lane skew
UI_High_Rate - 370 - ps
UI_Low_Rate - 617 - ps
V Rx-SKEWINTER_PAIR
- - 5200 ps -
Range is nominal
350ppm.
DisplayPort Link Rx does not
require local crystal for link
clock generation
Lane intra-pair skew
Ver. 1.0 Jul., 17, 2013
V Rx-SKEWINTRA_PAIR
- - 100 ps For high bit rate
- - 300 ps For reduced bit rate
8 / 31
LP156WF4
Liquid Crystal Display
Product Specification
3-4. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be
satisfied with the following specifications and specifications of eDP Tx/Rx for its proper operation.
Table 6. TIMING TABLE
ITEM Symbol Min Typ Max Unit Note
DCLK Frequency f
Period
Hsync
Width t
Width-Active t
Period t
Vsync
Width t
Width-Active t
Horizontal back porch t
Data
Enable
Horizontal front porch t
Vertical back porch t
Vertical front porch t
CLK
t
HP
WH
WHA
VP
WV
WVA
HBP
HFP
VBP
VFP
- 138.7 -
- 2080 -
- 32 -
- 1920 -
- 1111 -
- 5 -
- 1080 -
- 80 -
- 48 -
- 23 -
- 3 -
MHz eDP 2 Lane
tCLK
tHP
tCLK
tHP
Appendix) all reliabilities are specified for timing specification based on refresh rate of 60Hz. However,
LP156WF4 has a good actual performance even at lower refresh rate (e.g. 40Hz or 50Hz) for power saving
mode, whereas LP156WF4 is secured only for function under lower refresh rate. 60Hz at Normal mode, 50Hz,
3-5. Signal Timing Waveforms
Data Enable, Hsync, Vsync
High: 0.7VCC
Low: 0.3VCC
Condition : VCC =3.3V
DCLK
Hsync
tWH
Data Enable
t
WV
Vsync
Data Enable
CLK
t
t
VBP
HBP
0.5 Vcc
t
HP
tVP
WHA
t
t
WVA
t
Ver. 1.0 Jul., 17, 2013
t
HFP
t
VFP
9 / 31
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