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Ver. 0.1Apr., 30, 2013
Products Engineering Dept.
LG Display Co., Ltd
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Product Specification
Contents
LP156WF4
Liquid Crystal Display
NoITEM
COVER
CONTENTS
RECORD OF REVISIONS
1
2
3
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTREISTICS
3-1
INTERFACE CONNECTIONS
3-2
eDP SIGNAL TIMING SPECIFICATION
3-3
SIGNAL TIMING SPECIFICATIONS
3-4
SIGNAL TIMING WAVEFORMS
3-5
COLOR INPUT DATA REFERNECE
3-6
POWER SEQUENCE
3-7
Page
1
2
3
4
5
6-7
8
9
10
10
11
12
4
5
6RELIABLITY
7INTERNATIONAL STANDARDS
8PACKING
9PRECAUTIONS
Ver. 0.1Apr., 30, 2013
OPTICAL SFECIFICATIONS
MECHANICAL CHARACTERISTICS
AAPPENDIX. LPL PROPOSAL FOR SYSTEM COVER DESIGN
7-1SAFETY
7-2Environment
8-1DESIGNATION OF LOT MARK
8-2PACKING FORM
AAPPENDIX. Enhanced Extended Display Identification Data
13-15
16-18
19-23
24
25
25
26
26
27-28
29-31
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Product Specification
RECORD OF REVISIONS
LP156WF4
Liquid Crystal Display
Revision No Revision DatePageDescription
0.0Feb., 23, 2013-Preliminary SpecificationV0.0
0.1Apr., 29, 201329 ~ 31Update EDIDV0.2
EDID
ver.
Ver. 0.1Apr., 30, 2013
3 / 31
LP156WF4
Liquid Crystal Display
Product Specification
1. General Description
The LP156WF4 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally black mode. This TFT-LCD has 15.6 inches diagonally measured active display area with FHD
resolution (1920 horizontal by 1080 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP156WF4 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP156WF4 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP156WF4 characteristics provide an excellent flat display for office automation products such as
Notebook PC.
EEPROM Block
User connector
for Tcon & EDID
1
1920
TFT-LCD Panel
30
Pin
eDP
2 Lane
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
DVCC
Power
Block
LED Driver
Block
TCLKs
Control & DataPower
1080
DVCC, AVDD
VGH, VGL, GMA
GSP,GSC,GOE
VOUT_LED
FB1~6
(FHD,AH-IPS)
Source Driver Circuit
LED Backlight Ass‟y
EDID signal & Power
General Features
Active Screen Size15.6 inches diagonal
Outline Dimension
Pixel Pitch0.17925 mm x 0.17925 mm
Pixel Format1920 horiz. By 1080 vert. Pixels RGB strip arrangement
Color Depth6-bit, 262,144 colors
Luminance, White300 cd/m2 (Typ. 5 point)
Power ConsumptionTotal 5.7W (Typ.) Logic : 1.1W (Typ. @ Mosaic), B/L : 4.6W (Typ. @VLED12V)
Weight350 g (Max.) / 340 g (Typ.)
Display Operating ModeNormally Black
Surface TreatmentAnti glare treatment of the front Polarizer
RoHS ComplianceYes
The LP156WF4 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
UnitNotes
MinTypMax
LOGIC :
Power Supply Input VoltageVCC3.03.33.6V1
Power Supply Input CurrentMosaicICC-330390mA2
Power ConsumptionPCC-1.11.3W2
Power Supply Inrush CurrentICC_P--1500mA3
Differential ImpedanceZm90100110Ω4
BACKLIGHT : ( with LED Driver)
LED Power Input VoltageVLED6.012.021.0V5
LED Power Input CurrentILED-380390mA6
LED Power ConsumptionPLED-4.54.6W6
LED Power Inrush CurrentILED_P--1500mA7
PWM Duty Ratio5-100%8
Values
PWM Jitter
-
0-0.2%9
PWM ImpedanceZPWM204060kΩ
PWM FrequencyFPWM200-1000Hz10
PWM High Level VoltageV
PWM Low Level VoltageV
PWM_H
PWM_L
3.0-5.3V
0-0.3V
LED_EN ImpedanceZPWM204060kΩ
LED_EN High VoltageVLED_EN_H3.0-5.3V
LED_EN Low VoltageVLED_EN_L0-0.3V
Life Time15,000--Hrs11
Ver. 0.1Apr., 30, 2013
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Liquid Crystal Display
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25℃, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25℃, fv = 60Hz condition and Mosaic pattern.
2. This Spec. is the max load condition for the cable impedance designing.
3. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
LP156WF4
Rising time
Vcc
0V
10%
90%
3.3V
0.5ms
4. This impedance value is needed for proper display and measured form eDP Tx to the mating connector.
5. The measuring position is the connector of LCM and the test conditions are under 25℃.
6. The current and power consumption with LED Driver are under the Vled = 12.0V , 25℃, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
7. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
Rising time
VLED
0V
10%
90%
12.0V
0.5ms
8. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
9. If Jitter of PWM is bigger than maximum, it may induce flickering.
10. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
11. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
Ver. 0.1Apr., 30, 2013
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LP156WF4
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 30 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
PinSymbolDescriptionNotes
1
NC
2
GNDHigh Speed (Main Link) Ground
3
Lane1_NComplement Signal-Lane 1
4
Lane1_pTrue Signal-Main Lane 1
5
GNDHigh Speed (Main Link) Ground
6
Lane0_NComplement Signal-Lane 0
7
Lane0_pTrue Signal-Main Lane 0
8
GNDHigh Speed (Main Link) Ground
9
AUX_PTrue Signal-Auxiliary Channel
10
AUX_NComplement Signal-Auxiliary Channel
11
GNDHigh Speed (Main Link) Ground
12
VCC
13
VCC
14
BISTLCD Panel Self Test
15
GNDLCM Ground
16
GNDLCM Ground
17
HPDHPD signal pin
18
GNDLCM Ground (LED Backlight Ground)
19
GNDLCM Ground (LED Backlight Ground)
20
GNDLCM Ground (LED Backlight Ground)
21
GNDLCM Ground (LED Backlight Ground)
22
LED_EN
23
PWM
24
NCNo Connection
25
NCNo Connection
26
VLED
27
VLED
28
VLED
29
VLED
30
NCNo Connection
No Connection
LCD Logic and driver power (3.3V Typ.)
LCD Logic and driver power (3.3V Typ.)
LED Backlight On/Off
System PWM Signal input for dimming
LED Backlight Power (6.0V-21V)
LED Backlight Power (6.0V-21V)
LED Backlight Power (6.0V-21V)
LED Backlight Power (6.0V-21V)
[Interface Chip]
1. LCD :
Analogix, ANX2804 (LCD Controller
Including eDP Receiver.
2. System : TBD or equivalent
* Pin to Pin compatible with eDP
[Connector]
KN38B-30S-0.5H, HIROSE, 30, 0.5
or its compatibles
[Connector pin arrangement]
30
[LCD Module Rear View]
1
Ver. 0.1Apr., 30, 2013
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LP156WF4
Liquid Crystal Display
Product Specification
3-3. eDP Signal Timing Specifications
3-3-1. DC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
DescriptionSymbolMinMaxUnitNotes
Differential peak-to-peak Input voltage
Rx DC common mode voltageVCM02.0V-
VDIFF p-p
120-
mV
40-For reduced bit rate
For high bit rate
3-3-2. AC Specification
The VESA Display Port related AC specification is compliant with the VESA Display Port Standard v1.1a.
DescriptionSymbolMin TypMax UnitNotes
Unit Interval for high bit rate
(2.7Gbps/lane)
Unit Interval for high bit rate
(1.62Gbps/lane)
Lane-to-Lane skew
UI_High_Rate-370-ps
UI_Low_Rate-617-ps
V Rx-SKEWINTER_PAIR
--5200ps -
Range is nominal ±350ppm.
DisplayPort Link Rx does not
require local crystal for link
clock generation
Lane intra-pair skew
Ver. 0.1Apr., 30, 2013
V Rx-SKEWINTRA_PAIR
--100psFor high bit rate
--300psFor reduced bit rate
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LP156WF4
Liquid Crystal Display
Product Specification
3-4. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be
satisfied with the following specifications and specifications of eDP Tx/Rx for its proper operation.
Table 6. TIMING TABLE
ITEMSymbolMinTypMaxUnitNote
DCLKFrequencyf
Period
Hsync
Widtht
Width-Activet
Periodt
Vsync
Widtht
Width-Activet
Horizontal back porcht
Data
Enable
Horizontal front porcht
Vertical back porcht
Vertical front porcht
CLK
t
WH
WHA
WV
WVA
HBP
HFP
VBP
VFP
HP
VP
-138.7-
-2080-
-32-
-1920-
-1111-
-5-
-1080-
-80-
-48-
-23-
-3-
MHzeDP 2 Lane
tCLK
tHP
tCLK
tHP
Appendix) all reliabilities are specified for timing specification based on refresh rate of 60Hz. However,
LP156WF4 has a good actual performance even at lower refresh rate (e.g. 40Hz or 50Hz) for power saving
mode, whereas LP156WF4 is secured only for function under lower refresh rate. 60Hz at Normal mode, 50Hz,
40Hz at Power save mode. Don‟t care Flicker level (power save mode).
3-5. Signal Timing Waveforms
Data Enable, Hsync, Vsync
High: 0.7VCC
Low: 0.3VCC
Condition : VCC =3.3V
DCLK
Hsync
t
tCLK
WH
t
HBP
0.5 Vcc
t
HP
tWHA
Data Enable
t
VP
t
WV
Vsync
t
VBP
tWVA
Data Enable
Ver. 0.1Apr., 30, 2013
t
HFP
t
VFP
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