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LP156WF3-SLB2
Specification
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LG Display LP156WF3-SLB2 Specification

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LP156WF3
Liquid Crystal Display
Product Specification
SPECIFICATION
FOR
APPROVAL
(
Preliminary Specification
))(
Final Specification
LG Display Co., Ltd.SUPPLIER
LP156WF3*MODEL
SLB2Suffix
SIGNATURE
MODEL
DELLBUYER
*When you obtain standard approval,
please use the above model name without suffix
SIGNATUREAPPROVED BY
/
/
APPROVED BY
S. R. Kim / S.Manager
REVIEWED BY
M. J. Lee / Manager
/
Please return 1 copy for your confirmation with your signature and comments.
Ver. 1.0 03. Mar. 2011
PREPARED BY
S. K. Ahn / Engineer
J. P. Lee / Engineer
Products Engineering Dept.
LG Display Co., Ltd
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LP156WF3
Liquid Crystal Display
Product Specification
Contents
COVER
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION1
ABSOLUTE MAXIMUM RATINGS2
ELECTRICAL SPECIFICATIONS3
ELECTRICAL CHARACTREISTICS3-1
INTERFACE CONNECTIONS3-2
LVDS SIGNAL TIMING SPECIFICATIONS3-3
SIGNAL TIMING SPECIFICATIONS3-4
SIGNAL TIMING WAVEFORMS3-5
COLOR INPUT DATA REFERNECE3-6
POWER SEQUENCE3-7
OPTICAL SFECIFICATIONS4
ITEMNo
Page
1
2
3
4
5
6
7
8
11
11
12
13
14
MECHANICAL CHARACTERISTICS5
RELIABLITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
PRECAUTIONS9
APPENDIX. Enhanced Extended Display Identification Data A
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18
27
28
28
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32
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LP156WF3
Liquid Crystal Display
Product Specification
RECORD OF REVISIONS
DescriptionPageRevision DateRevision No
First draft-26. Jan. 20110.0
Update Optical Characteristics1425. Feb. 20110.1
EDID
ver
0.0
0.1
-Update Designation of Lot Mark30
-Update E-EDID Table (Checksum : C2)33-35
1.0Final Specification-03. Mar. 20111.0
Ver. 1.0 03. Mar. 2011
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1. General Description
The LP156WF3 is a Color Active Matrix Liquid Crystal Display with an integral RGB LED backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally black mode. This TFT-LCD has 15.6 inches diagonally measured active display area with Full HD resolution(1920 horizontal by 1080 vertical pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each dot, thus, presenting a palette of more than 1.073G(True) colors.
The LP156WF3 has been designed to apply the interface method that enables low power, high speed, low EMI. The LP156WF3 is intended to support applications where thin thickness, low power are critical factors and graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the LP156WF3(SLB2) characteristics provide an excellent flat display for office automation products such as Notebook PC.
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LP156WF3
Liquid Crystal Display
Product Specification
General Features
15.6 inches diagonal Active Screen Size
359.8 (H, Typ.) Ý 212.6 (V, Typ.) Ý 7.2(D, max.) mmOutline Dimension
0.179mm Ý 0.179 mm Pixel Pitch
1920 horiz. by 1080 vert. Pixels RGB strip arrangementPixel Format
10-bit, 1.073G colorsColor Depth
210 cd/m
Έ(Typ.) [5.77W(Logic, Typ.) + 14.1W(B/L, Typ.)]Power Consumption
650gWeight (Max.)
Transmissive mode, Normally blackDisplay Operating Mode
Surface Treatment
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(Typ.), 5 pointLuminance, White
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୅
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
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LP156WF3
Liquid Crystal Display
Product Specification
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Notes
Symbol
Values
Units
MaxMin
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
OP
Storage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb Temperature [
10
0
]
30
20
qC Max, and no condensation of water.
90% 80%
60
50
40
60%
Humidity[(%)RH]
40%
20%
10%
Storage
Operation
at 25 r 5qCVdc4.0-0.3VCC
1qC500TOP
1qC60-20HST
1%RH9010H
1%RH9010HST
-20
10
20 30 40 50
60 70 800
Dry Bulb Temperature [୅]
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3. Electrical Specifications
3-1. Electrical Characteristics
The LP156WF3(SLB2)requires two power inputs. One is employed to power the LCD electronics and to drive the TFT array and liquid crystal. The second input which powers the LED, is typically generated by an LED Driver. The LED Driver is an internal unit to the LCD.
Table 2. ELECTRICAL CHARACTERISTICS
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LP156WF3
Liquid Crystal Display
Product Specification
Parameter Symbol
MODULE :
Power Supply Input Current
Differential Impedance
LED Backlight :
Power Supply Input Voltage
Operating Voltage
Operating Current per string
Power Consumption
CC
Zm
BL+
LED (R,G,B)
LED (R,G,B)
BL
Values
--I
MaxTypMin
3.63.33.0VCCPower Supply Input Voltage
2114.47.5V
28 50 35
V
V
NotesUnit
DC
1mA201017501490I
1Watt6.635.774.92PcPower Consumption
2Ohm11010090
DC
3V36.3--V
3mA
4Watt19.514.1P
5Hrs--15,000Life Time
Note)
1. The specified current and power consumption are under the Vcc = 3.3V , 25୅, fv = 60Hz condition
whereas Mosaic pattern (8x6) is displayed and fv is the frame frequency.
2. This impedance value is needed to proper display and measured form LVDS Tx to the mating connector.
3. RGB LED
Operating Voltage and Operating Current per string should be within Max. SPEC.
4. The LED power consumption ( Typ ) shown above does include power of internal LED driver circuit for typical current condition. ( Luminance = 210nit condition ) The power consumption ( Max ) condition is R,G,B LED 100% Dimming.
5. The life time is determined as the time at which brightness of LED is 50% compare to that of initial value at the typical LED current.
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3-2. Interface Connections
This LCD employs two interface connections, a 50 pin connector is used for the module electronics interface and the other connector is used for the integral backlight system.
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LP156WF3
Liquid Crystal Display
Product Specification
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1
DescriptionSymbolPin
GroundGND1
Power Supply, 3.3V Typ.AVDD2
Power Supply, 3.3V Typ.AVDD3
4
RXinO3- - LVDS differential data input, Chan 3-Odd27
Power Supply, 3.3V Typ.AVDD
ow
er Supply, 3.3V Typ.AVDD5
P Power Supply, 3.3V Typ.AVDD6 Power Supply, 3.3V Typ.AVDD7 Power Supply, 3.3V Typ.AVDD8 Digital Power supply (3.3V Typ)DVDD9 Digital Power supply (3.3V Typ)DVDD10
BISTBIST11
Two wire serial interface clockClk EEDID12 Two wire serial interface dataDATA EEDID13 GroundGND14
- LVDS differential data input, Chan 0-OddRXinO0-15 + LVDS differential data input, Chan 0-OddRXinO0+16 GroundGND17
- LVDS differential data input, Chan 1-OddRXinO118 + LVDS differential data input, Chan 1-OddRXinO1+19 GroundGND20
- LVDS differential data input, Chan 2-OddRXinO2-21 + LVDS differential data input, Chan 2-OddRXinO2+22 GroundGND23
- LVDS Differential Clock input (Odd)RXOC-24 + LVDS Differential Clock input (Odd)RXOC+25 GroundGND26
1, Interface chips
1.1 LCD : LGE (MAKO)
1.2 System : * Pin to Pin compatible with LVDS
2.Connector
2.1 LCD : JAE FI-VHP50S-A-HF11
2.2 Mating: JAE or equivalent
2.3 Connector pin arrangement
LCD rear view
1
+ LVDS differential data input, Chan 3-OddRXinO3+28 GroundGND29
- LVDS differential data input, Chan 4-OddRXinO4-30 + LVDS differential data input, Chan 4-OddRXinO4+31 GroundGND32
- LVDS differential data input, Chan 0-EvenRXinE0-33 + LVDS differential data input, Chan 0-EvenRXinE0+34 GroundGND35
- LVDS differential data input, Chan 1-EvenRXinE1-36 + LVDS differential data input, Chan 1-EvenRXinE1+37 GroundGND38
- LVDS differential data input, Chan 2-EvenRXinE2-39 + LVDS differential data input, Chan 2-EvenRXinE2+40 GroundGND41
- LVDS Differential Clock input (Even)RXEC-42 + LVDS Differential Clock input (Even)RXEC+43 GroundGND44
- LVDS differential data input, Chan 3-EvenRXinE3-45 + LVDS differential data input, Chan 3-EvenRXinE3+46 GroundGND47
- LVDS differential data input, Chan 4-EvenRXinE4-48 + LVDS differential data input, Chan 4-EvenRXinE4+49 GroundGND50
[LCD Module Rear View]
)
Notes
including LVDS Receiver, VESA LVDS 10bit Format
or equivalent
50
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP156WF3
Liquid Crystal Display
Product Specification
Description
LVDS Common mode Voltage
LVDS Input Voltage Range
3-3-2. AC Specification
LVDS Clock to Data Skew Margin
Symb
ol
ID
CM
IN
SKEW
SKEW
NotesUnitMaxMin
|LVDS Differential Voltage
-mV600100|V
-V1.80.6V
-V2.10.3V
NotesUnitMaxMinSymbolDescription
85MHz > Fclk ˻
65MHz
65MHz > Fclk ˻
25MHz
- 600
ps+ 400- 400t
ps+ 600t
LVDS Clock to Clock Skew Margin (Even to Odd)
SKEW_EO
Maximum deviation of input clock frequency during SSC
DEV
Maximum modulation frequency of input clock during SSC
Ver. 1.0 03. Mar. 2011
MOD
-1/7
+ 1/7t
T
clk
%· 3-F
KHz200-F
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Freq.
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LP156WF3
Liquid Crystal Display
Product Specification
< Clock skew margin between channel >
F
max
F
center
F
min
3-3-3. Data Format
1) LVDS Data Port
X
m
tvk
< Spread Spectrum >
m

QGm
Time
kl}
< LVDS Data Format >
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Table 4. BACKLIGHT CONNECTOR PIN CONFIGURATION (CN2)
GroundGND1
7.5V - 21V LED PowerVBL+2
7.5V - 21V LED PowerVBL+3
7.5V - 21V LED PowerVBL+ 4
7.5V - 21V LED PowerVBL+5
7.5V - 21V LED PowerVBL+6
GroundVBL-7
GroundVBL-8
GroundVBL-9
GroundVBL-10
GroundVBL-11
No ConnectionNC12
GroundGND13
DATA for RGB controlI2C_DATA14
CLK for RGB controlI2C_CLK15
GroundGND16
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Product Specification
Liquid Crystal Display
NotesDescriptionSymbolPin
1. Connector
1.1 LCD : Hirose DF19KR
or equivalent
1.2 Mating : Hirose equivalent.
1.3 Connector pin arrangement
1
[LCD Module Rear View]
LP156WF3
20
BL_Enable17
BLIM18
BL On/Off Control (On: 3.0~3.6v, Off: 0~0.5v)
PWM for Luminance Control (200~1KHz, 3.3V, 5~100%) or DC(0~3.3v)
ReservedReserved19
GroundGND20
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3-3. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be satisfied with the following specifications and specifications of LVDS Tx/Rx for its proper operation.
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LP156WF3
Liquid Crystal Display
Product Specification
Table 5. TIMING TABLE
NoteUnitMaxTypMinSymbolITEM
f
t
WHA
WVA
HBP
HFP
t
VBP
t
CLK
HP
WH
VP
WV
VFP
-
Hsync
Vsync
Data
Enable
FrequencyDCLK
Period
Width
Width-Active
Period
Width
Width-Active
Horizontal back porch
Horizontal front porch
Vertical back porch
Vertical front porch
3-4. Signal Timing Waveforms (Normal status)
Data Enable, Hsync, Vsync
High: 0.7VCC
Low: 0.3VCC
LVDS 2 PortMHz-69.25
107810401020
161616t
tCLK
960960960t
112211111096t
555t
tHP
108010801080t
504034t
tCLK
522410t
282310
tHP
931
Condition : VCC =3.3V
DCLK
Hsync
t
tCLK
WH
t
HBP
0.5 Vcc
t
HP
tWHA
Data Enable
t
VP
t
WV
Vsync
t
VBP
tWVA
Data Enable
Ver. 1.0 03. Mar. 2011
t
HFP
t
VFP
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