LG Display LP156WF1-TLC1 Specification

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LP156WF1
Liquid Crystal Display
Product Specification
FOR
APPROVAL
()Preliminary Specification
()Final Specification
Title 15.5” Full HD TFT LCD
Customer Sony
MODEL
/
/
SUPPLIER LG Display Co., Ltd.
*MODEL LP156WF1
Suffix TLC1
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
SIGNATUREAPPROVED BY
APPROVED BY
K. J. Kwon / S.Manager
REVIEWED BY
REVIEWED BY
S. R. Kim / Manager
SIGNATURE
SIGNATURE
/
Please return 1 copy for your confirmation with your signature and comments.
Ver. 1.0 Dec. 10, 2009
PREPARED BY
PREPARED BY
C. J. Park / Engineer
Products Engineering Dept.
LG Display Co., Ltd
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LP156WF1
Liquid Crystal Display
Product Specification
Contents
No
1
2
3
4
COVER
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTREISTICS
3-1
INTERFACE CONNECTIONS
3-2
LVDS SIGNAL TIMING SPECIFICATION
3-3
SIGNAL TIMING SPECIFICATIONS
3-3
SIGNAL TIMING WAVEFORMS
3-4
COLOR INPUT DATA REFERNECE
3-5
POWER SEQUENCE
3-6
OPTICAL SFECIFICATIONS
ITEM
Page
1
2
3
4
5
6-7
8
9-10
11-12
12
13
14
15-17
5
Ver. 1.0 Dec. 10, 2009
MECHANICAL CHARACTERISTICS
APPENDIX. LPL PROPOSAL FOR SYSTEM COVER DESIGNA
RELIABLITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
PRECAUTIONS9
18-21
22-24
25
26
26
27
27
28-29
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LP156WF1
Liquid Crystal Display
Product Specification
RECORD OF REVISIONS
Revision No Revision Date Page Description
0.1 Oct. 1. 2009 6
11-12 Add Tentative Timing Table for 50Hz and 40Hz Refresh Rate
Correct LED Power Inrush Current 1.5Æ1500
Active area size 15.6inch Æ 15.5inch-Nov 2. 20090.2
EDID
ver
0.0First Draft (Preliminary Specification)-Sep. 19. 20090.0
1.0Final Draft-Dec. 10, 20091.0
Ver. 1.0 Dec. 10, 2009
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1. General Description
The LP156WF1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally white mode. This TFT-LCD has 15.5 inches diagonally measured active display area with FHD resolution (1920 horizontal by 1080 vertical pixel array). Each pixel is divided into Red, Green and Blue sub­pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144 colors. The LP156WF1 has been designed to apply the interface method that enables low power, high speed, low EMI. The LP156WF1 is intended to support applications where thin thickness, low power are critical factors and graphic displays are important. In combination with the vertical arrangement of the sub­pixels, the LP156WF1 characteristics provide an excellent flat display for office automation products such as Notebook PC.
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LP156WF1
Liquid Crystal Display
Product Specification
User connector
LVDS
2port
40
Pin
VCC
VLED
LED_EN
PWM
Control & Data Power
General Features
EEPROM Block
EEPROM Block
for EDID
for EDID
EEPROM Block
EEPROM Block
for Tcon Operating
for Tcon Operating
Timing Control
Timing Control
(Tcon) Block
(Tcon) Block
DVCC
Power
Block
LED Driver
LED Driver
Block
TCLKs
Power
Block
Block
15.5 inches diagonal Active Screen Size
359.3(H, typ.) Ý 209.5(V, typ.) Ý 5.7(D,max) [mm]]Outline Dimension
0.17925 mm x 0.17925 mmPixel Pitch
1920 horiz. By 1080 vert. Pixels RGB strip arrangementPixel Format
6-bit, 262,144 colorsColor Depth
220 cd/m
Total 6.94 Watt(Typ.) @ LCM circuit 1.74 Watt (Typ.), B/L input 5.2 Watt (Typ.)Power Consumption
470g ( Max.) / 450g ( Typ.)Weight
Transmissive mode, normally whiteDisplay Operating Mode
Hard Coating(3H), Glare treatment of the front polarizerSurface Treatment
YesRoHS Compliance
Yes for allBFR / PVC / As Free
VGH, VGL, GMA
GIP CLKs, DSC
2
(Typ.5 point)Luminance, White
M
i
n
i
-
L
V
D
DVCC, AVDD
VOUT_LED
FB1~6
1
1920
TFT-LCD Panel
(HD, GIP, TN)
S
1080
Source Driver (Bottom Bent)
LED Backlight Ass’y
EDID signal & Power
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
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LP156WF1
Liquid Crystal Display
Product Specification
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
VCC -0.3 4.0 Vdc at 25 r 5qC
TOP 050qC1
HST -20 60 qC1
HOP 10 90 %RH 1
HST 10 90 %RH 1
Values
Units Notes
Min Max
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb Temperature [
10
0
20
]
30
qC Max, and no condensation of water.
90% 80%
60
50
40
60%
Humidity[(%)RH]
40%
20%
10%
Storage
Operation
-20
10
20 30 40 50
60 70 800
Dry Bulb Temperature [୅]
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3. Electrical Specifications
3-1. Electrical Characteristics
The LP156WF1 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
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LP156WF1
Liquid Crystal Display
Product Specification
Table 2. ELECTRICAL CHARACTERISTICS
LOGIC :
BACKLIGHT : ( with LED Driver)
PWM Jitter
Values
SymbolParameter
NotesUnit
MaxTypMin
CCPower Supply Input Voltage
CCMosaicPower Supply Input Current
CCPower Consumption
CC_PPower Supply Inrush Current
LVDSLVDS Impedance
LEDLED Power Input Voltage
LEDLED Power Input Current
LEDLED Power Consumption
LED_PLED Power Inrush Current
11010090Z
ȳ
1V3.63.33.0V
2mA610530-I
2W2.01.74-P
3mA1500--I
4
5V21.012.07.0V
6mA500433-I
6W6.05.2-P
7mA1500--I
8%100-5PWM Duty Ratio
-
PWMPWM Impedance
kȳ604020Z
9%0.2-0
PWMPWM Frequency
PWM High Level Voltage
PWM Low Level Voltage
Ver. 1.0 Dec. 10, 2009
PWM_H
PWM_L
PWMLED_EN Impedance
LED_EN_HLED_EN High Voltage
LED_EN_LLED_EN Low Voltage
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10Hz1000-200F
V5.3-3.0V
V0.3-0V
kȳ604020Z
V5.3-3.0V
V0.3-0V
11Hrs--12,000Life Time
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Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used. The Vcc condition is same as the minimum of T1 at Power on sequence.
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LP156WF1
Liquid Crystal Display
Product Specification
Rising time Vcc
0V
5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25୅.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition and the Vled control block LGD used. VLED control block is same with Vcc control block.
90%
10%
0.5ms
3.3V
Rising time
LED
V
0V
10%
12.0V
90%
0.5ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user conditionU
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3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Test loop to 34pinTest Loop1
LCD Logic and driver power (3.3V Typ.)VCC2
LCD Logic and driver power (3.3V Typ.)VCC3
DDC Power (3.3V)V EEDID4
LCD Panel Self Test EnableBist5
DDC ClockClk EEDID6
DDC DataDATA EEDID7
31
32
33
34
35
36
37
38
39
40
ORX0-8
ERX0+ Positive LVDS differential data input21
Test Loop
LED_EN
NC
Negative LVDS differential data input
Positive LVDS differential data inputORX0+9
High Speed GroundGND10
Negative LVDS differential data inputORX1-11
Positive LVDS differential data inputORX1+12
High Speed GroundGND13
Negative LVDS differential data inputORX2-14
Positive LVDS differential data inputORX2+15
High Speed GroundGND16
Negative LVDS differential clock inputORXC-17
Positive LVDS differential clock inputORXC+18
High Speed GroundGND19
Negative LVDS differential data inputERX0-20
i
gh Speed GroundGND19
H
Negative LVDS differential data inputERX1-23
Positive LVDS differential data inputERX1+24
High Speed GroundGND19
Negative LVDS differential data inputERX2-26
Positive LVDS differential data inputERX2+27
High Speed GroundGND19
Negative LVDS differential clock inputERXC-29
Positive LVDS differential clock inputERXC+30
LED Backlight GroundGND
LED Backlight GroundGND
LED Backlight GroundGND
Test loop to 1pin System PWM Signal input for dimmingPWM
LED Backlight On/Off No Connection
LED Backlight Power (7V-21V)VLED
LED Backlight Power (7V-21V)VLED
LED Backlight Power (7V-21V)VLED
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Product Specification
LP156WF1
Liquid Crystal Display
NotesDescriptionSymbolPin
[Interface Chip]
1. LCD : SiW, ST2_BS(LCD Controller) Including LVDS Receiver.
2. System : SiW LVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
20455-040E-0x, I-PEX or its compatibles
[Mating Connector]
20345-#40E-## series or equivalent
[Connector pin arrangement]
40
[LCD Module Rear View]
1
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP156WF1
Liquid Crystal Display
Product Specification
Description
LVDS Differential Voltage |V
LVDS Common mode Voltage V
LVDS Input Voltage Range V
3-3-2. AC Specification
Description Symbol Min Max Unit Notes
LVDS Clock to Data Skew Margin
Symb
ol
| 100 600 mV -
ID
CM
IN
t
SKEW
t
SKEW
Min Max Unit Notes
0.6 1.8 V -
0.3 2.1 V -
- 400 + 400 ps
- 600 + 600 ps
85MHz > Fclk ˻
65MHz > Fclk ˻
65MHz
25MHz
LVDS Clock to Clock Skew Margin (Even to Odd)
Maximum deviation of input clock frequency during SSC
Maximum modulation frequency of input clock during SSC
Ver. 1.0 Dec. 10, 2009
t
SKEW_EO
F
DEV
F
MOD
-1/7 + 1/7 T
clk
- · 3% -
- 200 KHz -
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