LG Display LP140WD2-TLD1 Specification

◆

()Preliminary Specification
()Final Specification

Title 14.0”W HD+ TFT LCD

LP140WD2

Liquid Crystal Display

Product Specification

SPECIFICATION

FOR

APPROVAL

Customer HP

MODEL

SIGNATUREAPPROVED BY

/

/

/

SUPPLIER LG Display Co., Ltd.

*MODEL LP140WD2

Suffix TLD1

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

APPROVED BY

H. S. Kim / S.Manager

REVIEWED BY

REVIEWED BY

J. S. Park / Manager

PREPARED BY

PREPARED BY

C. W. Lee / Engineer

D. J. Lee / Engineer

SIGNATURE

SIGNATURE

Please return 1 copy for your confirmation with
your signature and comments.

Ver. 0.0 Nov. 26. 2010

Products Engineering Dept.

LG Display Co., Ltd

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Product Specification

Contents

LP140WD2

Liquid Crystal Display

COVER
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION1
ABSOLUTE MAXIMUM RATINGS2

ELECTRICAL SPECIFICATIONS3
ELECTRICAL CHARACTREISTICS3-1

INTERFACE CONNECTIONS3-2
LVDS SIGNAL TIMING SPECIFICATIONS3-3

SIGNAL TIMING SPECIFICATIONS3-4
SIGNAL TIMING WAVEFORMS3-5

COLOR INPUT DATA REFERNECE3-6
POWER SEQUENCE3-7
OPTICAL SFECIFICATIONS4

ITEMNo

Page

1
2
3
4
5

6-7

8

9-10

11
11

12
13

14-16

MECHANICAL CHARACTERISTICS5
RELIABLITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
LABEL DESCRIPTION8-3
PRECAUTIONS9
APPENDIX A. Enhanced Extended Display Identification DataA

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Product Specification

RECORD OF REVISIONS

LP140WD2

Liquid Crystal Display

Revision No Revision Date Page Description

0.0 Nov. 26, 2010 All First Draft (Preliminary Specification) 0.0

EDID

ver

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LP140WD2

Liquid Crystal Display

Product Specification

1. General Description

The LP40WD2 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Tran s istor as the active element. It is a trans missi ve type d isplay operating in
the normally white mode. This TFT-LCD has 14.0 inches diagonally measured active display area with HD+
resolution (1600 horizontal by 900 ve rtical pi xel arra y). Each pixe l is divided into Red, G reen and Blue sub­pixels or dots which are arranged in vertical stripes. Gray scale or the brightness o f the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP140WD2 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP140WD2 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are impor tant. In combination wi th the vertical a rrangement of the sub­pixels, the LP140WD2 characteristics provide an excellent flat display for office automation products such
as Notebook PC.

EEPROM Block

EEPROM Block

for EDID

for EDID

EEPROM Block

EEPROM Block

for Tcon Operating

User connector

for Tcon Operating

1

1600

1

Chip On Gate

TFT-LCD Panel

40

Pin

Timing Control

LVDS

2port

VCC

VLED

LED_EN

PWM

Timing Control

(Tcon) Block

(Tcon) Block

DVCC

Power

Block

LED Driver

LED Driver

Block

TCLKs

Power

Block

Block

VGH, VGL, GMA

Control & Data Power

M

i

n

i

-

L

V

D

S

AVCC, AVDD

GOE, GSP, GSC

VOUT_LED

FB1~4

900

(HD+, TN)

Source Driver
(Bottom Bent)

LED Backlight Ass’y

EDID signal & Power

General Features

Active Screen Size 14.0 inches diagonal
Outline Dimension 320.4(H, typ) × 187.1(V, typ) × 3.6(D,max) [mm]
Pixel Pitch 0.1932mm × 0.1932 mm
Pixel Format 1600 horiz. By 900 vert. Pixels RGB strip arrangement
Color Depth 6-bit, 262,144 colors

2

Luminance, White 250 cd/m
Power Consumption Total 5.1 Watt (Typ.) @ Logic input 1.0 Watt (Typ.), B/L input 4.1 Watt (Typ.)

Weight 320g (Max.)
Display Operating Mode Transmissive mode, normally white
Surface Treatment Anti-glare treatment of the front polarizer(3H)

RoHS Comply Yes

(Typ.5 point)

900

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LP140WD2

Liquid Crystal Display

Product Specification

2. Absolute Maximum Ratings

The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity

VCC -0.3 4.0 Vdc at 25  5C

TOP 050C1
HST -20 60 C1

HOP 10 90 %RH 1

HST 10 90 %RH 1

Values

Units Notes

Min Max

Note : 1. Temperature and relative humidity range are shown in the figure below.

Wet bulb temperature should be 39

Wet Bulb
Temperature [℃]

30

20

10

0

C Max, and no condensation of water.

90% 80%

60

50

40

60%

Humidity[(%)RH]

40%

20%

10%

Storage

Operation

-20

10

20 30 40 50

60 70 800

Dry Bulb Temperature [℃]

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LP140WD2

Liquid Crystal Display

Product Specification

3. Electrical Specifications
3-1. Electrical Characteristics

The LP140WD2 requires two power inputs. The first logic is employed to power the LCD electronics and to

drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter Symbol

Unit Notes

Min Typ Max

LOGIC :

Values

Power Supply Input Voltage V
Power Supply Input Current Mosaic I
Power Consumption P
Power Supply Inrush Current I
LVDS Impedance Z

CC 3.0 3.3 3.6 V 1

CC -

CC -1.0-W2

CC_P - - 2000 mA 4

LVDS 90 100 110

305

-mA2

Ω

BACKLIGHT : ( with LED Driver)

LED Power Input Voltage V
LED Power Input Current I
LED Power Consumption P
LED Power Inrush Current I

LED 7.0 12.0 21.0 V 6

LED - 342 - mA 7

LED -4.1-W7

LED_P - - 2000 mA 8

PWM Duty Ratio 6 - 100 % 9
PWM Jitter
PWM Impedance Z

-

PWM 20 40 60 kΩ

0-0.2%10

5

PWM Frequency F
PWM High Level Voltage V

PWM Low Level Voltage V
LED_EN Impedance Z
LED_EN High Voltage V
LED_EN Low Voltage V

PWM 200 - 1000 Hz 11

PWM_H

PWM_L

PWM 20 40 60 kΩ
LED_EN_H 3.0 - 5.3 V
LED_EN_L 0-0.3V

3.0 - 5.3 V
0-0.3V

Life Time 12,000 - - Hrs 12

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Liquid Crystal Display

Product Specification

Note)

1. The measuring position is the connector of LCM and the test conditions are under 25℃, fv = 60Hz,
Black pattern.

2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25℃, fv = 60Hz condition and Mosaic pattern.

3. This Spec. is the max load condition for the cable impedance designing.

4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.

LP140WD2

Rising time
Vcc

0V

10%

90%

3.3V

0.5ms

5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.

6. The measuring position is the connector of LCM and the test conditions are under 25℃.

7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25℃, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).

8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.

Rising time
V

LED

0V

10%

90%

12.0V

0.5ms

9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.

10. If Jitter of PWM is bigger than maximum, it may induce flickering.

11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent

to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.

12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum

value specified in table 7. under general user condition.

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LP140WD2

Liquid Crystal Display

Product Specification

3-2. Interface Connections

This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.

Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)

Pin Symbol Description Notes

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
19
23
24
19
26
27
19
29
30
31
32
33
34
35
36
37
38
39
40

NC No Connection
VCC LCD Logic and driver power (3.3V Typ.)
VCC LCD Logic and driver power (3.3V Typ.)

V EEDID DDC Power (3.3V)

NC No Connection

Clk EEDID DDC Clock

DATA EEDID DDC Data

ORX0- Negative LVDS differential data input

ORX0+ Positive LVDS differential data input

GND LCM Ground

ORX1- Negative LVDS differential data input

ORX1+ Positive LVDS differential data input

GND LCM Ground

ORX2- Negative LVDS differential data input

ORX2+ Positive LVDS differential data input

GND LCM Ground

ORXC- Negative LVDS differential clock input
ORXC+ Positive LVDS differential clock input

GND LCM Ground

ERX0- Negative LVDS differential data input

ERX0+ Positive LVDS differential data input

GND LCM Ground

ERX1- Negative LVDS differential data input

ERX1+ Positive LVDS differential data input

GND LCM Ground

ERX2- Negative LVDS differential data input

ERX2+ Positive LVDS differential data input

GND LCM Ground

ERXC- Negative LVDS differential clock input

ERXC+ Positive LVDS differential cloc k input

GND LCM Ground (LED Backlight Ground)
GND LCM Ground (LED Backlight Ground)
GND LCM Ground (LED Backlight Ground)

NC

No Connection

PWM System PWM Signal input for dimming

LED_EN LED Backlight On/Off

NC

No Connection
VLED LED Backlight Power (7V-21V)
VLED LED Backlight Power (7V-21V)
VLED LED Backlight Power (7V-21V)

[Interface Chip]

1. LCD :
SiW, SW0646(LCD Controller)
Including LVDS Receiver.

2. System : SiW LVDSRx or equivalent

* Pin to Pin compatible with LVDS

[Connector]

LSMtron GT05Q-40S-H10 or equivalent

[Mating Connector]

Mating of IPEX 20455-040 or equivalent

[Connector pin arrangement]

40

[LCD Module Rear View]

1

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Product Specification

3-3. LVDS Signal Timing Specifications

3-3-1. DC Specification

LP140WD2

Liquid Crystal Display

Description

LVDS Differential Voltage |V
LVDS Common mode Voltage V
LVDS Input Voltage Range V

3-3-2. AC Specification

Description Symbol Min Max Unit Notes

LVDS Clock to Data Skew Margin

Symb

ol

| 100 600 mV -

ID

CM

IN

t

SKEW

t

SKEW

Min Max Unit Notes

0.6 1.8 V -

0.3 2.1 V -

- 400 + 400 ps

- 600 + 600 ps

85MHz > Fclk ≥

65MHz > Fclk ≥

65MHz

25MHz

LVDS Clock to Clock Skew Margin (Even
to Odd)

Maximum deviation
of input clock frequency during SSC

Maximum modulation frequency
of input clock during SSC

Ver. 0.0 Nov. 26. 2010

t

SKEW_EO

F

DEV

F

MOD

-1/7 + 1/7 T

clk

-

- ± 3% -

-200KHz -

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