LG Display LD470DUP-SEH1 Specification

LD470DUP

Product Specification

SPECIFICATION

FOR

APPROVAL

)

(
(

Preliminary Specification

●

)

Final Specification

Title 47.0” WUXGA TFT LCD

BUYER General
MODEL

APPROVED BY

/

/

/

SIGNATURE

DATE

SUPPLIER LG DISPLAY Co., Ltd.

MODEL LD470DUP
SUFFIX SEH1

APPROVED BY

K. S. Nah

/ Chief Senior Engineer

REVIEWED BY

K.N. Kim

/ Chief Senior Engineer

PREPARED BY

J.H. Kim

/ Senior Engineer

SIGNATURE

DATE

Please return 1 copy for your confirmation with

your signature and comments.

Ver 0.3

PD Product Design Dept.

LG Display Co., Ltd

1 /37

Product Specification

CONTENTS

LD470DUP

Number ITEM

COVER
CONTENTS
RECORD OF REVISIONS

1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS
3-4 LVDS SIGNAL SPECIFICATIONS
3-5 COLOR DATA REFERENCE
3-6 POWER SEQUENCE

4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY

Page

1
2

3
4
5
6
7
8
9

10
11
12
13
22
25

7 INTERNATIONAL STANDARDS

7-1 SAFETY
7-2 EMC
7-3 Environment

8 PACKING

8-1 INFORMATION OF LCM LABEL

8-2 PACKING FORM

9 PRECAUTIONS
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM
9-7 APPROPRATE CONDITION FOR PUBLIC DISPLAY

Ver 0.3

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Product Specification

RECORD OF REVISIONS

Revision No. Revision Date Page Description

0.0 Dec, 22, 2011 - Preliminary specification (first draft)

0.1 Jan. 17. 2012 7 Updated max. value of power consumption
7 Added the typ. value of the LED lifetime

26 Changed contents of the safety
30 Added the No.5 in “9-7. Appropriate Condition for Public Display”

0.2 Mar. XX. 2012 5 Updated the absolute maximum rating with notes

4,7 Updated the electrical characteristics (current spec. and so on)

16 Updated power sequence with notes
18 Updated the description with notes
22 Updated the max. value of weight

23,24 Updated the drawing (Front view, Rear view)

31,32,33 Updated the pallet ass’y and label

0.3 Jun. 09. 2012 5 Added the temperature condition for bottom chassis
8 Fixed local dimming mode with note5

18 Fixed Contrast Ratio specification

LD470DUP

Ver 0.3

3 /37

LD470DUP

Product Specification

1. General Description

The LD470DUP is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)

Local Block backlight system. The matrix employs a-Si Thin Film Transistor as the active element.

It is a transmissive display type which is operating in the normally black mode. It has a 46.96 inch diagonally

measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).

Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.

Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors. It has been designed to apply the 10-bit 4-port
LVDS interface. It is intended to support Public Display where high brightness, super wide viewing angle, high
color gamut, high color depth and fast response time are important.

Mini-LVDS(RGB)

Source Driver Circuit

LVDS

CN2

(41pin)

EEPROM

2Port

LVDS

2Port

LVDS
Select

Bit
Select

EXTVBR-B

+12.0V

CN1

(51pin)

LVDS 3,4

LVDS 1,2

Option
signal

I2C

SCL

SDA

Timing Controller

LVDS Rx + OPC + DGA + ODC

+ Local Dimming

Integrated

Power Circuit

Power Signals

Control
Signals

S1 S1920

G1

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

G1080

Block

Ext VBR-B

+24.0V, GND, Status

General Features

Active Screen Size 46.96 inch (1192.78mm) diagonal

LED Driver

Local Dimming : 80Block

V : 10Block

Outline Dimension 1070.8(H) x 615.2(V) x 69.9 mm(D) (Typ.)
Pixel Pitch 0.5415 mm x 0.5415 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

Color Depth 10Bit (D), 1.07 Billion colors
Luminance, White 2000 cd/m2 (Center 1point ,Typ.)
Viewing Angle Viewing angle free (CR>10) : R/L 178 (Min.), U/D 178 (Min.)
Power Consumption

Total 222 Watt (Typ.) [Logic=8 Watt, Backlight=214Watt]

Weight 12.0Kg (Typ.) (TBD)
Display Mode Transmissive mode, Normally black
Surface Treatment

Possible Display Type Landscape and Portrait Enabled

Hard coating(3H), Anti-reflection treatment of the front polarizer (Reflectance〈 2%), QWP

H : 8Block

Ver 0.3

4 /37

LD470DUP

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or damage to the

LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit Remark

Min Max

Value

Power Input
Voltage

ON/OFF Control Voltage VON/OFF -0.3 +5. 5 VDC
Brightness Control Voltage VBR 0 +5.5 VDC
Operating Temperature TOP 0 +50

Storage Temperature TST -20 +60
Front Panel Temperature TSUR - +68 °C 4

Bottom Chassis Temperature TBot - 65 %RH 5
Operating Ambient Humidity HOP 10 90 %RH 2,3
Storage Humidity HST 10 90 %RH 2,3

LCM VLCD -0.3 +14.0 VDC

Backlight inverter VBL -0.3 +27.0 VDC

°C

°C

2,3
2,3

Note 1. Ambient temperature condition (Ta = 25  2 °C )

2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 50°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.

5. Active cooling system is required for panel cooling and stable operation

Ver 0.3

Wet Bulb
Temperature [°C]

30

20

10

0

10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]

40

50

60

90%

60%

40%

10%

Storage

Operation

Humidity [(%)RH]

5 /37

LD470DUP

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter Symbol

Min Typ Max

Circuit :
Power Input Voltage VLCD 10.8 12.0 13.2 VDC

Power Input Current ILCD

Power Consumption PLCD 8.04 10.4 Watt 1
Rush current IRUSH - - 5.0 A 3

Note

1. The specified current and power consumption are under the V

- 670 870

-

Value

970

Unit Note

mA 1

1260 mA 2

=12.0V, Ta=25  2°C, fV=120Hz

LCD

condition whereas mosaic pattern(8 x 6) is displayed and fV is the frame frequency.

2. The current is specified at the maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

White : 1023 Gray
Black : 0 Gray

Ver 0.3

Mosaic Pattern(8 x 6)

6 /37

Product Specification

Table 3. ELECTRICAL CHARACTERISTICS (Continue)

Parameter Symbol

Min Typ Max
LED Driver :
Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1

Values

Unit Notes

LD470DUP

Power Supply Input Current IBL - 8.89 9.6 A Ext V

BR-B

= 100%

VBL = 22.8V

Power Supply Input Current (In-Rush) Irush - - 13 A

Ext

VBR-B

= 100%

4

Power Consumption PBL -

On/Off

On V on 2.5 - 5.0 Vdc
Off V off -0.3 0.0 0.7 Vdc

10 - 100 %

Brightness Adjust ExtVBR-B

1 - 100 %

Input Voltage for

Control System

Signals

PWM Frequency for
NTSC & PAL

Pulse Duty Level
(PWM)

VSYNC, SIN, SCLK ,
Reverse

(Local Dimming)

PAL 100 Hz 3

NTSC 120 Hz 3

High Level 2.5 - 5.0

Low Level 0.0 - 0.7

High Level 2.7 3.3 3.6

Low Level -0.3 0.0 0.4

Life Time 30,000 50,000 Hrs

214 231

W Ext

VBR-B

(With Local Dimming)

(W/O Local Dimming)

Vdc
Vdc

HIGH : on duty

LOW : off duty

Vdc
Vdc

= 100%

On Duty

On Duty

2

Notes :

1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (Ext V

: 100%), it is total power consumption.

BR-B

2. The life time is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (Ext V

:100%) on condition of continuous operating in LCM state at

BR-B

25±2°C.

3. LGD recommend that the PWM freq. is synchronized with One time harmonic of Vsync signal of system.
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.

4. The duration of rush current is about 200ms.

5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.

6. Ext_PWM Signal have to input available duty range.
Between 99% and 100% ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%)
But Ext V

High

0% and 100% is possible.

BR-B

Ver 0.3

Low

0%

1%

Available duty range

99% 100%Ext_PWM Input Duty

7 /37

LD470DUP

Product Specification

3-2. Interface Connections

This LCD module employs three kinds of interface connection, 51-pin, 41-pin and 10-pin connector is used for
the module electronics and 14-pin, 12-pin connector is used for the integral backlight system.

3-2-1. LCD Module

- LCD Connector : FI-R51S-HF(manufactured by JAE) or compatible

- Mating Connector : FI-R51HL(JAE) or compatible

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No Symbol Description No Symbol Description

1
2
3
4

5
6

7
8

9

10
11 GND

12 R1AN
13 R1AP
14 R1BN
15
16 R1CN
17 R1CP
18 GND
19 R1CLKN
20

21 GND
22 R1DN
23 R1DP
24 R1EN
25 R1EP
26

NC
NC
NC
NC

NC
NC

LVDS Select

NC
NC

L-DIM Enable ‘H’ Only, Note 5

R1BP

R1CLKP

NC or GND

No Connection or Ground
Note 4
Note 4
Note 4

Note 4
Note 4

‘H’ =JEIDA , ‘L’ or NC = VESA
Note 4

Note 4

Ground
FIRST LVDS Receiver Signal (A-)

FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)

Ground
FIRST LVDS Receiver Clock Signal(-)

FIRST LVDS Receiver Clock Signal(+)
Ground

FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)

FIRST LVDS Receiver Signal (E+)
NC or Ground

27

Bit Select

28
29
30

31
32

33
34
35
36
37
38
39

40 R2EN
41 R2EP
42
43
44
45
46

47
48
49
50
51

- - -

R2AN
R2AP
R2BN

R2BP

R2CN

R2CP

GND
R2CLKN
R2CLKP

GND

R2DN

R2DP

NC or GND
NC or GND

GND Ground

GND Ground

GND Ground

NC No connection
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V

‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)

SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)

SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)

SECOND LVDS Receiver Signal (C+)
Ground

SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)

Ground
SECOND LVDS Receiver Signal (D-)

SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)

No Connection or Ground
No Connection or Ground

Note:

1. All GND (ground) pins should be connected together to the LCD module’s metal frame.

2. All VLCD (power input) pins should be connected together.

3. All input levels of LVDS signals are based on the EIA 644 Standard.

4. These pins are reserved only for LGD (Do not connect)

5. All evaluation was verified based on L-DIM “H” and should keep “H” status during the operation.

Ver 0.3

8 /37

Product Specification

LCD Connector (CN2) : FI-RE41S-HF (manufactured by JAE) or compatible-

- Mating Connector : FI-RE41HL or compatible

Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION

No Symbol Description No Symbol Description

1 NC No connection 22 RE3N
2
3
4 NC
5
6
7
8

9
10 RA3N
11 RA3P
12 RB3N
13 RB3P
14 RC3N
15 RC3P
16 GND
17 RCLK3N
18 RCLK3P
19 GND
20 RD3N
21 RD3P

NC
NC

NC
NC
NC
NC

GND

No connection 23 RE3P
No connection 24 GND Ground

No connection
No connection

No connection 27 RA4P
No connection 28 RB4N
No connection 29 RB4P

Ground
THIRD LVDS Receiver Signal (A-)

THIRD LVDS Receiver Signal (A+)
THIRD LVDS Receiver Signal (B-)
THIRD LVDS Receiver Signal (B+)
THIRD LVDS Receiver Signal (C-)
THIRD LVDS Receiver Signal (C+)

Ground
THIRD LVDS Receiver Clock Signal(-)

THIRD LVDS Receiver Clock Signal(+)
Ground

THIRD LVDS Receiver Signal (D-)
THIRD LVDS Receiver Signal (D+)

25 GND Ground
26 RA4N

30 RC4N
31 RC4P
32 GND
33 RCLK4N
34 RCLK4P
35 GND
36 RD4N
37 RD4P
38 RE4N
39 RE4P
40 GND Ground
41 GND Ground

-

THIRD LVDS Receiver Signal (E-)
THIRD LVDS Receiver Signal (E+)

FORTH LVDS Receiver Signal (A-)
FORTH LVDS Receiver Signal (A+)
FORTH LVDS Receiver Signal (B-)
FORTH LVDS Receiver Signal (B+)
FORTH LVDS Receiver Signal (C-)
FORTH LVDS Receiver Signal (C+)

Ground
FORTH LVDS Receiver Clock Signal(-)

FORTH LVDS Receiver Clock Signal(+)
Ground

FORTH LVDS Receiver Signal (D-)
FORTH LVDS Receiver Signal (D+)
FORTH LVDS Receiver Signal (E-)
FORTH LVDS Receiver Signal (E+)

LD470DUP

Note : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.

2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.

CN3

CN1 CN2

#1

CN3

#1 #8

#1 #51 #1 #41

#8

CN1 CN2

#1 #51

#1 #41

Rear view of LCM

Ver 0.3

9 /37

3-2-2. Backlight Module

LD470DUP

Product Specification

Master / Slave

LED Driver Connector -

: 20022WR-14B2(Yeonho) / 20022WR-12B2(Yeonho)

Table 5. INVERTER CONNECTOR PIN CONFIGULATION

Pin No Symbol Description

1
2
3
4
5
6
7
8

9
10
11

VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL
VBL Power Supply +24.0V VBL VBL

VBL Power Supply +24.0V VBL VBL
GND B/Light Ground GND GND
GND B/Light Ground GND GND
GND B/Light Ground GND GND
GND B/Light Ground GND GND
GND B/Light Ground GND GND

Status Status Status - 5

Mating Connector

: 20022HS-14 / 20022HS-12

Master Slave

14pin 12pin

Note

1

12
13
14

VON/OFF B/Light ON/OFF control VON/OFF Don’t care 4

EXT VBR-B

GND - GND

External PWM

EXT VBR-B

Notes : 1. GND should be connected to the LCD module’s metal frame.

2. High : on duty / Low : off duty, Pin#13 can be opened. ( if Pin #13 is open , EXTVBR-B is 100% )

3. #14 of Input CNT Must be Connected to Backlight Ground.

4. Each impedance of pin #12 and 13 is over 50 [KΩ] and over 50 [KΩ].

5. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)

◆ Rear view of LCM

PCB

PCB

…

14

1

…

…

1

<Master>

Ver 0.3

12

<Slave>

10 /37

LD470DUP

Product Specification

3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings
should be satisfied with the following specification for normal operation.

Table 6. TIMING TABLE (DE Only Mode)

ITEM Symbol Min Typ Max Unit Note

Horizontal

Vertical

Frequency

Display

Period

Blank tHB 40 70 200 tCLK 1

Total tHP 520 550 680 tCLK

Display

Period

Blank tVB

Total tVP

ITEM Symbol Min Typ Max Unit Note

DCLK fCLK 66.97 74.25 78.00 MHz

Horizontal fH 121.8 135 140 KHz 2

Vertical fV

tHV 480 480 480 tCLK 1920 / 4

tVV 1080 1080 1080 Lines

20

(228)
1100

(1308)

108
(95)

45

(270)

1125

(1350)

120

(100)

86

(300)

1166

(1380)

122

(104)

Lines 1

Lines

NTSC :

Hz

108~122Hz

(PAL : 95~104Hz)

2

Note:

1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency

※ Timing should be set based on clock frequency.

Ver 0.3

11 /37

3-4. LVDS Signal Specification

3-4-1. LVDS Input Signal Timing Diagram

LD470DUP

Product Specification

DCLK

First data

Second data

Third data

Forth data

DE(Data Enable)

tCLK

0.5 VDD

Invalid data

Invalid data

Invalid data

Invalid data

DE, Data

Valid data

Pixel 0

Valid data

Pixel 1

Valid data

Pixel 2

Valid data

Pixel 3

Pixel 4

Pixel 5

Pixel 6

Pixel 7

0.7VDD

0.3VDD

Invalid data

Invalid data

Invalid data

Invalid data

DE(Data Enable)

Ver 0.3

1 1080

tVV

tVP

* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP

12 /37