LG XCute125 Training Manual

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PLASMA TV

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LG Electronics

Display Division CS Gr

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CONTENTS

1.PLASMA Overview

2.Basic Knowledge of PLASMA

3.PLASMA Check Point

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4.MODULE Change History

5.S/W Download

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1. PLASMA Overview

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PLASMA Overview

Structure of PDP module

< Front >

Operation Principle

# PLASMA MODULE has PANEL part and DRIVE part.

Panel : Electrode, Phosphor, Dielectrics, Gas.

Drive : Electronic circuit & PCB.

(X , Y-sus, Z sus, Y drv,PSU,CTRL B/D)

Y drv

CTRL

Y-B/D

< Back > <Cross section view of PDP panel >

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Z-B/D

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PLASMA Overview

Safety & Handling Regulations

1. About 10 minute preparation is required before adjustment.

2. Higher voltage than is required for the product shouldn’t be applied.

3. Be cautious of electric shock for PDP module since PDP module uses high voltage, and it is recommended that should one touch the drive circuit after one minute because of residual current.

4. Circuit drive has c-mos circuit which should be protected from static electricity.

5. Module must be carried by two people.

6. Be careful of short circuit when measuring voltage.

7. Be cautious of screws and other metal objects to pervent short in circuit part.

Safety Rules

Checking Point before Requesting MODULE Repair

1. Check the appearance of Panel and board.

2. Check the model label if model names and board model matches.

3. Check details of defective condition and history.

Ex) COF long 2-1 fail, address 1 line open, Y b/d trouble, Maldischarge on screen.

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Configuration

50PB2DR

Control Board

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Digital Board

Tuner Board

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2. Principle of

PLASMA Operation

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Basic Information

◆

. In charge of all signal process (Contour noise declined ISM...) and

creating ON/OFF order of all FET on DRIVER B/D by receiving 8 bit R, G, B input.

◆

. Power : 3.3V/5V

Temperature diode

Flash ROM

Control Board(50X3)

# Temperature display diode

Regulator

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Weight

D15 - 8 D16 - 4 D17 - 2 D18 - 1

Temperature display diode can

be checked. Left picture shows 7 periods

which means normal temperature

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Basic Information

1. Check LED ( Normal status lightening or not )

Control Board(42V7)

LED

2. If not CHECK OSC X1 output.

3. Check CTRL input voltage

(CONNECTOR P10)

4. CHECK each FET 3.3V, 5V,1.8V.

OSC(X1)

Probe

Touching

point

Input voltage

Check FET

5 V

Check oscillating state.

Be careful with physical shock.

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20 / 32

3.3 V

DMM – (GND)

1..8 V

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Basic Information

▶

Main Defect : MCM , connector, oscilator, LVDS poor connection

▶

Voltage used : 5V/3.3V/1.8V/2.5V 4 kind of voltage.

Control Board

Defect part

MCM

Connector

Description of

defect

Regular vertical

lines

No display or

Partly no display

No pictureOscilator

Part

< MCM >

< Connector >

< Oscillator >

Defect display

< Partly no display >

LVDS

Abnormal display

poor connection

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< Poor connection >

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Basic Information

◆

. Generates SUSTAIN Waveform, RESET Waveform,

VSC(SCAN) Voltage and supplies to Y DRIVER B/D.

◆

. Composed of IPM, DIODE, Electrolysis CAPACITOR, and FET.

Y sustain Board

< Probe connect point to Oscilloscope to check Z wave form >

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50X3 Y Waveform

110V

200V

110V

V s

200V

80V

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Basic Information

▶

Main Defect : IPM fail, FET fail, fuse

▶

Voltage used: Vs/Va/-Vy/Vsc 4 kind of voltage.

Y sustain Board

IPM Fail

FET fail

No display

( If the ER IPM failed,

The screen can display normal picture for few

minutes)

No display

( there is many FETs on

Y sustain board)

PartDescription of defectDefect name

Defect display

< No display >

No display

Fuse

* 5V- SMT fuse

* Va, Vs fuse-ceramic

fuse

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< No display >

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Basic Information Y sustain Board

Y sustain board Block Diagram

5V, Va, Vs

Power supply board ( PSU )

Distribute 5V,Va

Receive 5V,Va, Vs

IPM generates

sustain waveform

FET

makes waveform

Transfer waveform

to Y drive board

CTRL Board

Generates Vsc, -Vy from

Vs and Va by transformer.

FET switching signal information

5V, Va

Voltage flow .

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5V, Va

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Basic Information

Generates Sustain pulse and Erase pulse for Sustain discharge on Panel

◆

by receiving Logic signal from Control B/D.

This output waveform is delivered to Panel through FPC(Z).

Composed of IPM, FET, DIODE, Electrolysis CAPACITOR, and E/R COIL.

◆

Z sustain Board

50X3 Y waveform < Probe connect point to Oscilloscope to check Z wave form >

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95 V

95V

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Basic Information

▶

Main Defect : IPM fail, cable connection.

Z sustain Board

Cable

connection

Dark displayIPM Fail

If the cable was not

connected,

There is no display

PartDescription of defectDefect name

Defect display

< Dark display >

< No display >

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Basic Information

1) Works as a path supplying Sustain waveform and Reset waveform

which is made in Y SUSTAIN B/D to the Panel through SCAN DRIVER IC

2) Supplies a waveform which selects horizontal electrode (Y SUSTAIN

electrode) in order.

- Potential difference between DRIVER IC GND and

Vpp in SUSTAIN period is 0V.

- Potential difference between DRIVER IC GND and

Vpp only occurs in SCAN period.

* 50X3 uses 12 DRIVER ICs (TOP, BOTTOM: 6 each)

Y drive Board

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755866

GND

HVO

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Basic Information

▶

Main Defect : SCAN IC fail, cable connection.

Y drive Board

Cable

connection

Horizontal bar SCAN IC fail

If the cable was not

connected,

There is no abnormal

PartDescription of defectDefect name

Defect display

< Horizontal bar >

< Abnormal display >

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Basic Information

◆

. Makes an Address pulse (generates Address discharge) on the panel using FET ON/OFF

after receiving logic signal from CONTROL B/D, and supplies the output waveform to

COF(DATA).

◆

. Composed of FET, FET Drive IC, and Logic IC.

X Board

5V and Va

Voltage

RGB signal

from CTRL B/D

X RIGHT B/D

X Center B/D

X LEFT B/D

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Basic Information

▶

Main Defect : Poor connection, Particle inserted.

X Board

Poor

connection

Vertical abnormal

display

Vertical abnormal

display

PartDescription of defectDefect name

< Poor connection >

Attached particle

Defect display

Vertical line

( similar with IC fail )

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Line created by particle or

insertion defect

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Basic Information

◆

. Connects PAD electrode of PANEL to PCB (Y & Z)

and supplies the Drive waveform of circuit to

PANEL.

*. Y uses single/double-sided

The pattern is on FPC.

*. Z uses single-sided which is Beta type (Copper

plate in the front) without pattern.

FPC (Flexible Printed Circuit)

768 lines ( in case of 50 inch)

Z sus

Common

8. FFC (Flat Flexible Cable)

◆

. Connects the logic signal between B/D

* 0.5mm pitch,50pin type

1mm pitch, 30pin type

< Y drv > < Z board >

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Basic Information

① Replace Y or Z B/D : Most maldischarge is caused by Y or Z.

If one B/D replacement doesn’t work, replace both B/D.

② Replace CTRL B/D : For maldischarge by signal process, replace CTRL B/D or

download S/W.

Types of Maldischarge

Mal discharge by board defect

Mal discharge in specific gray

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Image sticking mal discharge

Non extinguishing mal discharge

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Basic Information

◆

. Most maldischarge is caused by Y drv , Y-sus , Z-sus problems, and

can be checked as stated before.

Checking Order

1. Check Y, Z SUS signal cable

2. Y DRV IC FAIL check

3. Check Y sus b/d voltage (-Vy.Vscw)

4. Check Y ,Z-SUS IPM fail

5. Replace CTRL b/d

Maldischarge

* Maldischarge Picture

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* Maldischarge Picture

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Basic Information

Pacific Digital Board BlockDiagram

/W_PROTECT

3 1

RF_S/W_1

P I N

MNT_R_OUT

C O

MNT_L_OUT

N N

COMP2_SW

E C

COMP1_SW

T O R

AV_ROUT

AV_LOUT

AT_TU_V

PC_SYNC

2 5

M_CVBS

P I N

COMP_HS

COMP_VS

C O

MAIN_Y/G_IN

N N

MAIN_U/B_IN

E C

MAIN_V/R_IN

T O R

SCL_CH2

SDA_CH2

REC_CVBS_OUT

AV_ROUT

AV_LOUT

MNT_R_OUT

MNT_L_OUT

5VST

12V

M_C_IN

CAPTION

AT/NT Tuner

Sound Proc

(MSP4440K)

M_CVBS

M_C_IN

SIF

IIC_CH4

0×80

24LC02

ATSC/NTSC

(TDVS-H701F)

AT_TU_V

(FMS6400)

MAIN_Y/G_IN

MAIN_U/B_IN

MAIN_V/R_IN

COMP_HS

COMP_VS

HV_PC

LPF

I2S I2S_MCLK

ANALOG_L/R

BUFFER

(MC33078)

I2S Out

RXD[0:2]±, RXCLK±

DDC(I2C)

IIC_CH1

0×C2

Tuner

SIF

LPF

Active LPF (FMS6407)

System CPLD1

(XC95288XL)

HV_pol

BSS8

BSS83

$0.14

OR4

2ndIF±(6M)

IF_AGC

TUNER_RF_AGC

MSP 4440

X-tal

(24.576M

)

(uPD64011 A)

K4S161622

SDRAM

2MB

H,V,CLAMP

FID

H_pol

CPU

IIC-CH4_1

0×CC

PWM

MODULATOR

(NSP2100A)

AUDIO ADC

(CS5331)

Buffer

(74LCX244)

IIC-CH3 0×60,6

CLK

X-tal

(25M)

(LGDT3303)

FSA

1156

IIC_CH3

0×B8

(mst9883)

OR2

PWM_L/R

HDMI Rx SiL 9011

Reset

PVSB

RF_AGC

Reg.

VSB_DATA

IIC_CH4_

CPU

RF_AGC_CTRL

NT & Composite

Component & RGB

DTV HDMI

SOUND

YCbCr

H,V,CLK

FID

ADC

IIC-CH2

0×98

System

(XC95288XL)

PWM AMP (TAS5122)

I2S In

I2S Out

HD-II

HD-

RGB

H,V,

RX_HDMI SPDIF

1.8 V

0×1C

OR1

OR4 OR2

YCbCr

H,V, CLK3

CPLD1

OR1

System CPLD1

(XC95288XL)

OR1

OR4

H,V,

CLK

CS8415A

YCbCr

H,V,CLK

FID

OR3

IIC A

IIC B

IIC C

IIC D

H,V,

CLK

TP/D1

REC_CVBS_OUT

RF_S/W_1

/W_PROTECT

CAPTION

PC_SYNC

COMP2_SW

COMP1_SW

EN[0:3(GPIO)]

I2C Hub

(PCA9516

OR4

K4S641632H

SDRAM

32MByte (8MB x4)

64-Bit I/F

1.8V Reg.

HD2_NT2CLK TPN_SYS_CLK EPLD_CLK

VCXO

27Mh

$0.78

HD2_MAIN_PWM

HD-II (Ver2.3)

-TP De-Mux

- MPEG Decoding : MP@HL

-Format Converter

-Host I/F, Memory I/F

-Digital I/F

-Video DAC, NTSC Encoder

-AC-3 Decoder/SPDIF In/out

AH_SPDIFCLK

uCom

(M37151)

)

IIC_CH

0×50

System CPLD1

(XC95288XL)

SEL_I2C

HD2_DAC_SCK/LRCK

SPDIF Receiver.

(CS8415A)

IIC-_CH2

0×20

EEPROM

(AT24LC16)

$2.3

ARM [S3C44BOX]

/ 2

- SDRAM Controller

- Peripheral Controller

- Local BUS I/F

- Serial(2), GPIO, I2Cr

HD2_SYS_CLK

(M37151)

EEPROM

(AT24LC512)

CY2305SC

FR_60

HV,Hact

RGB

DOutClk

HD2_ICE958_OUT

RX_HDMI_SPDIF

uCom

IIC_CH

IIC-CH2

LGDPLL

(LGDT1901A

HD2_VDPClk

(74.25M)

IIC C

0×1E

IEP

LGDT4411

Sil9011

0×50

PCI Bus

Reset

KIA7029 $0.1

74LC14

Peripheral Bus

0×94

0×74

)

DPLL_R[1:3]

XDR_DATA_R/G/B[0:9]

LVDS Tx.

(THC63LVD103)

32Bit Bus I/F

Temp. Sensor (LM75)

Port

Expander

(M62320)

TX[0:4]±

TXC±

IIC C

0×1C

SPDIF_TX

RS-232C

(ST3232)

SDRAM

64MB(32MBx2)

Flash Memory

8MB(4MBx2)

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