LG U250 User Manual

Date: June, 2007 / Issue 1.0

Service Manual

Model : U250/KU250

Service Manual

U250/KU250

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1. INTRODUCTION .............................. 5

1.1 Purpose................................................... 5

1.2 Regulatory Information............................ 5

2. PERFORMANCE...............................7

2.1 System Overview.....................................7

2.2 Usable environment.................................8

2.3 Radio Performance..................................8

2.4 Current Consumption.............................14

2.5 RSSI BAR ..............................................14

2.6 Battery BAR ...........................................15

2.7 Sound Pressure Level............................16

2.8 Charging ................................................16

3. TECHNICAL BRIEF ........................17

3.1 General Description ...............................17

3.2 GSM Mode.............................................19

3.3 UMTS Mode...........................................23

3.4 LO generation and distribution circuits...25

3.5 Off-chip RF Components .......................25

3.6 Digital Baseband(DBB/MSM6245).........34

3.7 Block Diagram(MSM6245).....................36

3.8 Subsystem(MSM6245) ..........................37

3.9 Power Block...........................................45

3.10 External memory interface...................50

3.11 H/W Sub System..................................52

3.12 Main Features......................................68

4. TROUBLE SHOOTING ...................73

4.1 RF Component.......................................73

4.2 SIGNAL PATH_UMTS RF .....................75

4.3 SIGNAL PATH_GSM RF .......................76

4.4 Checking VC-TCXO Block.....................77

4.5 Checking Front-End Module Block ........79

4.6 Checking UMTS Block...........................81

4.7 Checking GSM Block.............................86

4.8 Checking Bluetooth Block......................92

4.9 Power ON Troubleshooting....................94

4.10 Charger Troubleshooting .....................96

4.11 USB Troubleshooting...........................99

4.12 SIM Detect Troubleshooting ..............100

4.13 Camera Troubleshooting ...................102

4.14 Keypad Backlight Troubleshooting ....105

4.15 Main LCD Troubleshooting ................106

4.16 Receiver Path ....................................107

4.17 Headset path......................................109

4.18 Speaker phone path...........................111

4.19 Main microphone ...............................113

4.20 Headset microphone..........................115

4.21 Vibrator ..............................................117

5. DOWNLOAD..................................119

5.1 U250/KU250 DOWNLOAD ..................119

5.1.1 Introduction ...................................119

5.1.2 Downloading Procedure ...............119

5.1.3 Troubleshooting Download Errors 129

5.1.4 Caution .........................................133

6. BLOCK DIAGRAM ........................134

6.1 GSM & UMTS RF Block.......................134

6.2 Interface Diagram ................................136

7. Circuit Diagram ............................143

8. pcb layout .....................................147

9. Calibration & RF Auto Test

Program (Hot Kimchi)..................149

9.1 Configuration of HOT KIMCHI .............149

9.2 How to use HOT KIMCHI.....................152

10. Factory Test Mode .....................154

10.1. Test Program Setting........................154

10.2. WCDMA Test Mode..........................155

10.3. GSM Test Mode................................156

11. EXPLODED VIEW &

REPLACEMENT PART LIST ..... 157

11.1 EXPLODED VIEW ............................ 157

11.2 Replacement Parts

<Mechanic component>.................... 159

<Main component> ........................... 161

11.3 Accessory ......................................... 174

Table Of Contents

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1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the
features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of commoncarrier
telecommunication service of facilities accessed through or connected to it. The manufacturer will not
be responsible for any charges that resultfrom such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the phones or compatibility with the net
work, the telephone company is required to give advanced written notice to the user, allowing the user
to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on the phones must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.

1. INTRODUCTION

1. INTRODUCTION

E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.

G. Interference and Attenuation

A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from
unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system boards.

• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.

1. INTRODUCTION

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2. PERFORMANCE

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2.1 System Overview

2. PERFORMANCE

Item Specification

Shape GSM900/1800/1900 and WCDMA2100 - Bar type Handset

Size 110.9 X 46.7 X 15.6 mm

Weight Under 83 g (with 950mAh Battery)

Power 3.7 V normal, 950 mAh Li-Ion

Talk Time Over 200 min (WCDMA, Tx=12 dBm, Voice)

(with 950mAh) Over 180 min (GSM, Max Tx Power, Voice)

Standby Time Over 350 Hrs (WCDMA, DRX=1.28)

(with 950mAh) Over 450 Hrs (GSM, Paging period=9)

Antenna Internal type

LCD Main 1.76” TFT, QCIF, 262K

LCD Backlight White LED Back Light

Camera 1.3 Mega pixel + VGA Video Call Camera

Vibrator Yes ( Cylinder Type)

LED Indicator No

MIC Yes

Receiver Yes

Earphone Jack Yes (18 pin)

Connectivity Bluetooth, USB

External Memory Yes(Micro SD)

I/O Connect 18 Pin

2.2 Usable environment

1) Environment

2) Environment (Accessory)

* CLA : 12 ~ 24 V(DC)

2.3 Radio Performance

1) Transmitter - GSM Mode

* In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910

2. PERFORMANCE

- 8 -

Item Specification

Voltage 3.7 V(Typ), 3.2 V(Min), [Shut Down : 3.2 V]

Operation Temp -20 ~ +60°C

Storage Temp -20 ~ +70°C

Humidity 85 % (Max)

Reference Spec. Min Typ. Max Unit

TA Power Available power 100 220 240 Vac

No Item GSM DCS & PCS

100k~1GHz -39dBm

9k ~ 1GHz -39dBm

MS allocated 1G~[A]MHz -33dBm

Channel

1G~12.75GHz -33dBm

[A]M~[B]MHz -39dBm

Conducted [B]M~12.75GHz -33dBm

1Spurious 100k~880MHz -60dBm 100k~880MHz -60dBm

Emission 880M~915MHz -62dBm 880M~915MHz -62dBm

Idle Mode

915M~1GHz -60dBm 915M~1GHz -60dBm

1G~[A]MHz -50dBm 1G~[A]MHz -50dBm

[A]M~[B]MHz -56dBm [A]M~[B]MHz -56dBm

[B]M~12.5GHz -50dBm [B]M~12.5GHz -50dBm

2. PERFORMANCE

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* In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910

No Item GSM DCS & PCS

30M ~ 1GHz -36dBm

30M~1GHz -36dBm

MS allocated 1G~[A]MHz -30dBm

Channel

1G ~ 4GHz -30dBm

[A]M~[B]MHz -36dBm

Radiated [B]M~4GHz -30dBm

2Spurious 30M ~ 880MHz -57dBm 30M~880MHz -57dBm

Emission 880M ~ 915MHz -59dBm 880M~915MHz -59dBm

Idle Mode

915M~1GHz -57dBm 915M~1GHz -57dBm

1G~[A]MHz -47dBm 1G~[A]MHz -47dBm

[A]M~[B]MHz -53dBm [A]M~[B]MHz -53dBm

[B]M~4GHz -47dBm [B]M~4GHz -47dBm

3 Frequency Error ±0.1ppm ±0.1ppm

4 Phase Error

±5(RMS) ±5(RMS)

±20(PEAK) ±20(PEAK)

3dB below reference sensitivity 3dB below reference sensitivity

Frequency Error RA250 : ±200Hz RA250: ±250Hz

5 Under Multipath and HT100 : ±100Hz HT100: ±250Hz

Interference Condition TU50 : ±100Hz TU50: ±150Hz

TU3 : ±150Hz TU1.5: ±200Hz

0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB

200kHz -30dB 200kHz -30dB

250kHz -33dB 250kHz -33dB

Due to 400kHz -60dB 400kHz -60dB

Output RF

modulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB

6 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -65dB

Spectrum

3000 ~ 6000kHz -71dB ≥6000kHz -73dB

≥6000kHz -77dB

Due to

400kHz -19dB 400kHz -22dB

Switching

600kHz -21dB 600kHz -24dB

transient

1200kHz -21dB 1200kHz -24dB

1800kHz -24dB 1800kHz -27dB

2. PERFORMANCE

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No Item GSM DCS & PCS

Frequency offset 800kHz

7 Intermodulation attenuation –

Intermodulation product should

be Less than 55dB below the

level of Wanted signal

Power control

Power Tolerance

Power control

Power Tolerance

Level (dBm) (dB) Level (dBm) (dB)

533±3 030±3

631±3 128±3

729±3 226±3

827±3 324±3

925±3 422±3

10 23 ±3 5 20 ±3

8Transmitter Output Power 11 21 ±3 6 18 ±3

12 19 ±3 7 16 ±3

13 17 ±3 8 14 ±3

14 15 ±3 9 12 ±4

15 13 ±3 10 10 ±4

16 11 ±5 11 8 ±4

17 9 ±5 12 6 ±4

18 7 ±5 13 4 ±4

19 5 ±5 14 2 ±5

15 0 ±5

9 Burst timing Mask IN Mask IN

2. PERFORMANCE

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2) Transmitter - WCDMA Mode

No Item Specification

1 Maximum Output Power Class 3 : +24dBm(+1/-3dB)

2Frequency Error ±0.1ppm

3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme

Adjust output(TPC command)

cmd 1dB 2dB 3dB

+1 +0.5/1.5 +1/3 +1.5/4.5

4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5

-1 -0.5/-1.5 -1/-3 -1.5/-4.5

Group (10 equel command group)

+1 +8/+12 +16/+24

5 Minimum Output Power -50dBm(3.84MHz)

Qin/Qout : PCCH quality levels

6Out-of-synchronization handling of output power Toff@DPCCH/Ior : -22 -> -28dB

Ton@DPCCH/Ior : -24 -> -18dB

7 Transmit OFF Power -56dBm(3.84MHz)

8 Transmit ON/OFF Time Mask

±25us

PRACH,CPCH,uplinlk compressed mode

±25us

9 Change of TFC

Power varies according to the data rate

DTX : DPCH off

(minimize interference between UE)

10 Power setting in uplink compressed ±3dB(after 14slots transmission gap)

11 Occupied Bandwidth(OBW) 5MHz(99%)

-35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz,30k

12 Spectrum emission Mask

-35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz,1M

-39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz,1M

-49dBc@∆f=8.5~12.5MHz,1M

3)Receiver - GSM Mode

2. PERFORMANCE

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No Item Specification

13 Adjacent Channel Leakage Ratio(ACLR)

33dB@5MHz, ACP>-50dBm

43dB@10MHz, ACP>-50dBm

-36dBm@f=9~150KHz, 1K BW

-36dBm@f=50KHz~30MHz, 10K BW

-36dBm@f=30MHz~1000MHz, 100K BW

14

Spurious Emissions -30dBm@f=1~12.5GHz, 1M BW

(*: additional requirement) (*)-41dBm@f=1893.5~1919.6MHz, 300K

(*)-67dBm@f=925~935MHz, 100K BW

(*)-79dBm@f=935~960MHz, 100K BW

(*)-71dBm@f=1805~1880MHz, 100K BW

15 Transmit Intermodulation

-31dBc@5MHz,Interferer -40dBc

-41dBc@10MHz, Interferer -40dBc

16 Error Vector Magnitude (EVM)

17.5%(>-20dBm)

(@12.2K, 1DPDCH+1DPCCH)

17 Transmit OFF Power

-15dB@SF=4.768Kbps, Multi-code

transmission

No Item GSM DCS & PCS

1

Sensitivity (TCH/FS Class II) -105dBm -105dBm

2

Co-Channel Rejection

C/Ic=7dB Storage -30 ~ +85

(TCH/FS Class II, RBER, TU high/FH)

3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB

Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB

Wanted Signal :-98dBm 1st Wanted Signal :-96dBm 1st

4

Intermodulation Rejection interferer:-44dBm 2nd interferer:-44dBm 2nd

interferer:-45dBm interferer:-44dBm

5

Blocking Response Wanted Signal :-101dBm Wanted Signal :-101dBm

(TCH/FS Class II, RBER)

Unwanted : Depend on Frequency Unwanted : Depend on Frequency

2. PERFORMANCE

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4) Receiver - WCDMA Mode

No Item Specification

1 Reference Sensitivity Level -106.7 dBm(3.84 MHz)

-25dBm(3.84MHz)

2Maximum Input Level -44dBm/3.84MHz(DPCH_Ec)

UE@+20dBm output power(Class3)

3 Adjacent Channel Selectivity (ACS)

33dB

UE@+20dBm output power(Class3)

-56dBm/3.84MHz@10MHz

4In-band Blocking UE@+20dBm output power(Class3)

-44dBm/3.84MHz@15MHz

UE@+20dBm output power(Class3)

-44dBm/3.84MHz@f=2050~2095 and

2185~2230MHz

UE@+20dBm output power(Class3)

-30dBm/3.84MHz@f=2025~2050 and

5 Out-band Blocking 2230~2255MHz

UE@+20dBm output power(Class3)

-15dBm/3.84MHz@f=1~2025 and

2255~12500MHz

UE@+20dBm output power(Class3)

6Spurious Response

-44dBm CW

UE@+20dBm output power(Class3)

-46dBm CW@10MHz

7Intermodulation Characteristic -46dBm/3.84MHz@20MHz

UE@+20dBm output power(Class3)

-57dBm@f=9KHz~1GHz, 100K BW

8 Spurious Emissions -47dBm@f=1~12.5GHz, 1M BW

-60dBm@f=1920MHz~1980MHz, 3.84M BW

-60dBm@f=2110MHz~2170MHz, 3.84M BW

2. PERFORMANCE

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2.4 Current Consumption

1) U250/KU250 Current Consumption

(Stand by and Voice Call Test Condition : Bluetooth off, LCD backlight off,Neighbor Cell off) (VT Test
Condition : Speaker off, LCD backlight On)

2.5 RSSI BAR

Stand by Voice Call VT

WCDMA

Under 2.80 mA Under 290 mA Under 410mA

(DRX=1.28) (Tx=12dBm) (Tx=12dBm)

Under 2.12 mA Under 320 mA

GSM Paging=9 period (Max Tx Power)

Level Change WCDMA GSM

BAR 4 → 3 -85 ± 2 dBm -90 ± 2 dBm

BAR 3 → 2 -95 ± 2 dBm -95 ± 2 dBm

BAR 2 → 1-106 ± 2 dBm -100 ± 2 dBm

BAR 1 → 0-111 ± 2 dBm -106 ± 2 dBm

2.6 Battery BAR

2. PERFORMANCE

- 15 -

Indication Standby

Bar 4 Over 3.83 ± 0.05V

Bar 4 → 3 3.82 ± 0.05V

Bar 3 → 2 3.73 ± 0.05V

Bar 2 → 1 3.68 ± 0.05V

Bar 1 → Empty 3.58 ± 0.05V

Low Voltage, 3.58± 0.05V (Stand-by) / 3.58 ± 0.05V (Talk)

Warning message+ Blinking [Interval : 3min(Stand-by) / 1min(Talk)]

Power Off 3.20 ± 0.05V

2. PERFORMANCE

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2.7 Sound Pressure Level

2.8 Charging

• Charging Method : CC & CV (Constant Current and Constant Voltage)

• Maximum Charging Voltage : 4.2 V

• Maximum Charging Current : 700 mA

• Normal Battery Capacity : 950 mAh

• Charging Time : Max 3 hours (except for trickle charging time)

• Full charging indication current (charging icon stop current) : 80 mA

• Cut-off voltage : 3.20 V

No Test Item Specification

1 Sending Loudness Rating (SLR) 8 ±3 dB

2 Receiving Loudness Rating (RLR)

Nor -4 ± 3 dB

Max -15 ± 3 dB
3 Side Tone Masking Rating (STMR) Min 17 dB
4 Echo Loss (EL) Min 40 dB
5 Idle Noise-Sending (INS) Max -64 dBm0p

6 Idle Noise-Receiving (INR)

Nor Under -47 dBPA

Max Under -36 dBPA
7 Sending Loudness Rating (SLR) 8±3dB

8 Receiving Loudness Rating (RLR)

Nor -1 ±3 dB

Max -12 ±3 dB
9 Side Tone Masking Rating (STMR) Min 25 dB

10 Echo Loss (EL) Min 40 dB
11 Idle Noise-Sending (INS) Max -55 dBm0p

12 Idle Noise-Receiving (INR)

Nor Under -45 dBPA

Max Under -40 dBPA

TDMA Noise

-. GSM : Power Level : 5
DCS/PCS : Power Level : 0
(Cell Power : -90 ~ -105 dBm)

13

-. Acoustic (Max Vol.)
MS/Headset SLR : 8 ±3dB
MS/Headset RLR : -15 ± 3dB/-12
(SLR/RLR : Mid-value setting)

MS

Headset

MS and

Headset

Max

Under -62 dBm

3. TECHNICAL BRIEF

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3.1 General Description

The U250/KU250 supports UMTS-2100, GSM-900, DCS-1800, and PCS-1900 based
GSM/GPRS/UMTS. All receivers and the UMTS transmitter use the radio One1Zero-IF architecture to
eliminate intermediate frequencies, directly converting signals between RF and baseband. The quad­band GSM transmitters use a baseband-to-IF upconversion followed by an offset phase-locked loop
that translates the GMSK-modulated signal to RF.

UMTS (2100)
GSM (900, 1800, 1900)
Bluetooth

1. RTR6275 for GSM Tx
and WCDMA Tx

2. RTR6275 for GSM Rx
and WCDMA Rx

3. Bluetooth RF module

4. PM6650 for power
management

1

QUALCOMM’s branded chipset that implements a Zero-IF radio architecture.

3. TECHNICAL BRIEF

[Fig 1.1] Block diagram of RF part

A generic, high-level functional block diagram of U250/KU250 is shown in Figure 1-1. One antenna
collects base station forward link signals and radiates handset reverse link signals. The antenna
connects with receive and transmit paths through a FEM(Front End Module).

The UMTS receive path each include a LNA, a RF band-pass filter, and a downconverter that translate
the signal directly from RF-to-baseband using radioOne ZIF technique. The RFIC Rx analog baseband
outputs, for the receive chains, connect to the MSM IC. The UMTS and GSM Rx baseband outputs
share the same inputs to the MSM IC.

For the transmit chains, the RTR6275 IC directly translates the Tx baseband signals (from the MSM
device) to an RF signal using an internal LO generated by integrated on-chip PLL and VCO. The
RTR6275 IC outputs deliver fairly high-level RF signals that are first filtered by Tx SAWs and then
amplified by their respective UMTS PA. The high- and low-band UMTS RF transmit signals emerge
from the RTR6275 transceiver.

In the GSM receive paths, the received RF signals are applied through their band-pass filters and
down-converted directly to baseband in the RTR6275 transceiver IC. These baseband outputs are
shared with the UMTS receiver and routed to the MSM IC for further signal processing.

The GSM transmit paths employ one stage of up-conversion and, in order to improve efficiency.

1. The on-chip quadrature up-converter translates the GMSK-modulated signal to a constant envelope
phase signal at RF;

2. The amplitude-modulated (AM) component is applied to the ramping control pin of power amplifier
from a DAC within the MSM

U250/KU250 power supply voltages are managed and regulated by the PM6650 Power Management
IC. This versatile device integrates all wireless handset power management, general housekeeping,
and user interface support functions into a single mixed signal IC. It monitors and controls the external
power source and coordinates battery recharging while maintaining the handset supply voltages using
low dropout, programmable regulators.

The device’s general housekeeping functions include an ADC and analog multiplexer circuit for
monitoring on-chip voltage sources, charging status, and current flow, as well as userdefined off-chip
variables such as temperature, RF output power, and battery ID. Various oscillator, clock, and counter
circuits support IC and higher-level handset functions. Key parameters such as under-voltage lockout
and crystal oscillator signal presence are monitored to protect against detrimental conditions.

3. TECHNICAL BRIEF

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3. TECHNICAL BRIEF

- 19 -

3.2 GSM Mode

3.2.1 GSM Receiver

The Dual-mode U250/KU250’s receiver functions are split among the three RFIC’s as follows:

• GSM-900, DCS-1800, and PCS-1900 UMTS-2100 modes use the RTR6275 IC only. Each mode has
independent front-end circuits and down-converters, but they share common baseband circuits (with
only one mode active at a time). All receiver control functions are beginning with SBI2-controlled
parameters.

RF Front end consists of antenna, antenna switch module(D5011) which includes three RX saw
filters(GSM900, DCS and PCS). The antenna switch module allows multiple operating bands and
modes to share the same antenna. In U250/KU250, a common antenna connects to one of six paths:

1) UMTS-2100 Rx/Tx, 2) GSM-900 Rx, 3) GSM-900 Tx, 4) DCS-1800 Rx, and 5) DCS-1800 Tx, PCS-

1900 Tx(High Band Tx’s share the same path), 6) PCS-1900 Rx. UMTS operation requires
simultaneous reception and transmission, so the UMTS Rx/Tx connection is routed to a duplexer that
separates receive and transmit signals. The GSM900, DCS, and PCS operation is time division
duplexed, so only the receiver or transmitter is active at any time and a frequency duplexer is not
required.

2

The RFIC operating modes and circuit parameters are MSM-controlled through the proprietary 3-line Serial Bus Interface (SBI). The Application
Programming Interface (API) is used to implement SBI commands. The API is documented in AMSS Software - please see applicable AMSS
Software documentation for details.

[Table 1.1] Antenna Switch Module Control logic

GSM 1800 / GSM1900 RX

GSM 900 RX

GSM 900 TX / WCDMA

GSM 1800 / GSM 1900 TX

The GSM900, DCS, and PCS receiver inputs of RTR6275 are connected directly to the transceiver
front-end circuits(filters and antenna switch module). The GSM900, DCS, and PCS receiver inputs use
differential configurations to improve common-mode rejection and second-order non-linearity
performance. The balance between the complementary signals is critical and must be maintained from
the RF filter outputs all the way into the IC pins

Since GSM900, DCS, and PCS signals are time-division duplex (the handset can only receive or
transmit at one time), switches are used to separate Rx and Tx signals in place of frequency duplexers ­this is accomplished in the switch module.

The GSM900, DCS, and PCS receive signals are routed to the RTR6275 through band selection filters
and matching networks that transform single-ended 50-Ω sources to differential impedances optimized
for gain and noise figure. The RTR input uses a differential configuration to improve second-order inter­modulation and common mode rejection performance. The RTR6275 input stages include MSM­controlled gain adjustments that maximize receiver dynamic range.

The amplifier outputs drive the RF ports of the quadrature RF-to-baseband downconverters.
The downconverted baseband outputs are multiplexed and routed to lowpass filters (one I and one Q)
having passband and stopband characteristics suitable for GMSK processing. These filter circuits
include DC offset corrections. The filter outputs are buffered and passed on to the MSM6245 IC for
further processing (an interface shared with the RFR6275 UMTS receiver outputs).

3. TECHNICAL BRIEF

- 20 -

3. TECHNICAL BRIEF

- 21 -

[Fig 1.2] RTR6275 RX feature

3.2.2 GSM Transmitter

The RTR6275 transmitter outputs(DA_HB2_OUT and DA_LB1_OUT)include on-chip output matching
inductors. The 50ohm output impedance is achieved by adding a series capacitor at the output pins.
The capacitor value may be optimized for specific applications and PCB characteristics based on pass­band symmetry about the band center frequency, the suggested starting value is shown in Figure1.3.

The RTR6275 IC is able to support GSM 900 and GSM 1800/1900 mode transmitting. This design
guideline shows a tri-band GSM application.

Both high-band and low band outputs are followed by resistive pads to ensure that the load presented
to the outputs remains close to 50ohm. The low-band GSM Tx path also includes a Tx-band SAW filter
to remove noise-spurious components and noise that would be amplified by the PA and appear in the
GSM Rx band

3. TECHNICAL BRIEF

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[Fig 1.3] GSM Transmitter matching

6pF

Ω

12pF

Ω

51

39

Ω

9191

Ω

Ω

Ω

100100

3. TECHNICAL BRIEF

- 23 -

3.3 UMTS Mode

3.3.1 Receiver

The UMTS duplexer receiver output is routed to LNA circuits within the RTR6275 device. The UMTS Rx
input is provided with an on-chip LNA that amplifies the signal before a second stage filter that provides
differential downconverter. This second stage input is configured differentially to optimize second-order
intermodulation and common mode rejection performance. The gain of the UMTS frontend amplifier and
the UMTS second stage differential amplifier are adjustable, under MSM control, to extend the dynamic
range of the receivers. The second stage UMTS Rx amplifiers drive the RF ports of the quadrature RF­tobaseband downconverters. The downconverted UMTS Rx baseband outputs are routed to lowpass
filters having passband and stopband characteristics suitable for UMTS Rx processing. These filter
circuits allow DC offset corrections, and their differential outputs are buffered to interface shared with
GSM Rx to the MSM IC. The UMTS baseband outputs are turned off when the RTR6275 is
downconverting GSM signals and on when the UMTS is operating.

3.3.2 Transmitter

The UMTS Tx path begins with differential baseband signals (I and Q) from the MSM device. These
analog input signals are amplified, filtered, and applied to the quadrature up-converter mixers. The up­converter output is amplified by multiple variable gain stages that provide transmit AGC control. The
AGC output is filtered and applied to the driver amplifier; this output stage includes an integrated
matching inductor that simplifies the external matching network to a single series capacitor to achieve
the desired 50-Ω interface.

The RTR6275 UMTS output is routed to its power amplifier through a bandpass filter, and delivers fairly
high-level signals that are filtered and applied to the PA. Transmit power is delivered from the duplexer
to the antenna through the switch module. The transceiver LO synthesizer is contained within the
RTR6275 IC with the exception of the off-chip loop filter components and the VC-TCXO. This provides
a simplified design for multimode applications. The PLL circuits include a reference divider, phase
detector, charge pump, feedback divider, and digital logic generator.

UMTS Tx using PLL1, the LO generation and distribution circuits create the necessary LO signals for
different frequency converters. The UMTS transmitter also employs the ZIF architecture to translate the
signal directly from baseband to RF. This requires FLOto equal FRF, and the RTR6275 IC design
achieves this without allowing F

VCO

to equal FRF.
The RTR6275 IC is able to support UMTS 2100/1900 and UMTS 850 mode transmitting. This design
guideline shows only UMTS 2100 applications.

3. TECHNICAL BRIEF

- 24 -

[Figure 1.4] RTR6275 IC functional block diagram

WCDMA_2100_TX

WCDMA_2100_RX

3.4 LO generation and distribution circuits

The integrated LO generation and distribution circuits are driven by internal VCOs to support various
modes to yield highly flexible quadrature LO outputs that drive all GSM and UMTS band upconverters
and downconverters; with the help of these LO generation and distribution circuits, zero-IF architecture
is employed in all GSM and UMTS band receivers and transmitters to translate the signal directly from
RF to baseband and from baseband to RF.

Two fully functional fractional-N synthesizers, including VCOs and loop filters, are integrated within the
RTR6275 IC. The first synthesizer (PLL1) creates the transceiver LOs that support the UMTS
2100/1900/1800 transmitter, and all four GSM band receivers and transmitters including: GSM 850,
GSM 900, GSM 1800, and GSM 1900. The second synthesizer (PLL2) provides the LO for the UMTS
2100/1900/1800 receiver. An external TCXO input signal is required to provide the synthesizer
frequency reference to which the PLL is phase and frequency locked. The RTR6275 IC integrates
most of PLL loop filter components on-chip except two off-chip loop filter series capacitors, and
significantly reduces off-chip component requirement. With the integrated fractional-N PLL
synthesizers, the RTR6275 has the advantages of more flexible loop bandwidth control, fast lock time,
and low-integrated phase error

3.5 Off-chip RF Components

3.5.1 WCDMA PAM (U103: WS2512-TR1G)

The UMTS PA output power is monitored by l power detector circuits(U100 : RTR6275) .
This detector voltage can be used for transmitter calibration and monitor to meet RF system

3. TECHNICAL BRIEF

- 25 -

[Figure 1.5] WCDMA PAM, Duplexer, Coupler

20dB

Rev_1.0

Rev.B

Rev_1.0

Rev.D

WCDMA

7dB

0.5p

L125

FL102

EFCH1950TDF1

2

G13G2

5

G3

1

IN

4

O1

U102

CP0402A1950DNTR

50OHM

4

3

COUP

2IN1

OUT

L404

1.8nH

45

31

NA

L122

KRX102U

TR100

2

1p

C165

3.3p

C162

C159
15p

R122

130

R11951

1.5p

C154

41

RX
TX

2

FL104

ACMD-7602

ANT

3

PGND

130

R121

0.1u

C170

4.7u

C155

47

R120

2

RFOUT

8

1

VCC1VCC2

10

4

VCONT

5

VREF

WS2512_TR1G U103

11

BGND

GND1

3

GND2

6

7

GND3

9

GND4 RFIN

0.5p

C164

100p

C192

C158

15p

1nH

L123

10nH

C157

+VPWR

PA_R0

+VPWR

PWR_DET

PA_ON

VREG_TCXO_2.85V

3.5.2 VCTCXO (X100 : DSA321SCE-19.2M)

The Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO) provides the
reference frequency for all RFIC synthesizers as well as clock generation functions within the
MSM6245 IC. The oscillator frequency is controlled by the MSM6245 IC.
TRK_LO_ADJ pulse density modulated signal in the same manner as the transmit gain control
TX_AGC_ADJ. A two-pole RC lowpass filter is recommended on this control line.

The PM6650 IC controls the handset power-up sequence, including a special VCTCXO warm-up
interval before other circuits are turned on. This warm-up interval (as well as other TCXO controller
functions) is enabled by the MSM TCXO_EN line . The PM6650 IC VREG_TCXO regulated output
voltage is used to power the VCTCXO and is enabled before most other regulated outputs.
Any GSM mode power control circuits within the MSM6245 IC require a reference voltage for proper
operation and sufficient accuracy. Connecting the PM6650 IC REF_OUT directly to the MSM6245 IC
GSM_PA_PWR_CTL_REF provides this reference. This sensitive analog signal needs a 0.1 •ÏF low
frequency filter near to MSM side, and isolate from digital logic and clock traces with ground on both
sides, plus ground above and below if routed on internal layers.

3.5.3 Front-End Module (U500 : D5011)

This equipment uses a single antenna to support all handset operating modes, with an antenna switch
module select the operating frequency and band. UMTS operation requires simultaneous reception
and transmission, so the UMTS Rx/Tx connection is routed to a duplexer that separates receive and
transmit signals. The active connection is MSM-selected by three control lines (GPIO[9], GPIO[10]).
Two GPIO are programmed to be ANT_SEL0_N, ANT_SEL1_N) respectively.

3. TECHNICAL BRIEF

- 26 -

[Table 1.2] Front End Module control logic

GSM 1800 / GSM1900 RX

GSM 900 RX

GSM 900 TX / WCDMA

GSM 1800 / GSM 1900 TX

3. TECHNICAL BRIEF

- 27 -

3.5.4 PMIC Functional Block Diagram (U300 : PM6650-2M)

• Input power management

- Valid external supply attachment and removal detection

- Supports unregulated (closed-loop) external charger supplies and USB supplies as input power
sources

- Supports lithium-ion main batteries

- Trickle, constant current, constant voltage, and pulsed charging of the main battery

- Supports coin cell backup battery (including charging)

- Battery voltage detectors with programmable thresholds

- VDD collapse protection

- Charger current regulation and real-time monitoring for over-current protection

- Charger transistor protection by power limit control

- Control drivers for two external pass transistors and one external battery MOSFET - MOSFET is
optional

- Voltage, current, and power control loops

- Automated recovery from sudden momentary power loss

• Output voltage regulation

- One boost (step-up) switched-mode power supply (SMPS) for driving white LEDs and hosting
USBOTG

- Three buck (step-down) switched-mode power supplies that efficiently generate MSMC, MSME,
and PA (or second MSMC) supply voltages

- Supports dynamic voltage scaling (DVS) for MSMC and PA

- Eleven low dropout regulator circuits with programmable output voltages, implemented using three
different current ratings: 300 mA (two), 150 mA (six), and 50 mA (three). These can be used to
power MSMA, MSMP, RFRX1, RFRX2, RFTX, SYNT, TCXO, WLAN, MMC, USB, and RUIM
circuits.

- All regulators can be individually enabled/disabled for power savings

- Low power mode available on MSMA and MSMP regulators

- All regulated outputs are derived from a common bandgap reference-close tracking

• Integrated handset-level housekeeping functions reduces external parts count, size, cost

- Analog multiplexer selects from 8 internal and up to 18 external inputs

- Multiplexer output’s offset and gain are adjusted, increasing the effective ADC resolution

- Adjusted multiplexer output is buffered and routed to an MSM device ADC

- Dual oscillators - 32.768 kHz off-chip crystal and on-chip RC assures MSM device sleep clock

- Crystal oscillator detector and automated switch-over upon lost oscillation

- Real time clock for tracking time and generating associated alarms

- On-chip adjustments minimize crystal oscillator frequency errors

- Circuits control TCXO warm-up and synchronize, deglitch, and buffer the TCXO signal

- TCXO buffer control for optimal QPH/catnap timing

- Three-stage over-temperature protection (smart thermal control)

• Integrated handset-level user interfaces

- Four programmable current sinks recommended as keypad backlight, LCD backlight, camera flash,
and general-purpose drivers

- Vibration motor driver programmable from 1.2 to 3.1V in 100 mV increments

- Speaker driver with programmable gain, turn-on time, and muting; differential operation (drives
external 8 Ω speakers with volume controlled 500 mW)

• IC-level interfaces

- MSM device-compatible 3-line SBI for efficient initialization, status, and control

- Supports the MSM device’s interrupt processing with an internal interrupt manager

- Many functions monitored and reported through real-time and interrupt status signals

- Dedicated circuits for controlled power-on sequencing, including the MSM device’s reset signal

- Several events continuously monitored for triggering power-on/power-off sequences

- Supports and orchestrates soft resets

- USB-OTG transceiver for full-speed (12 Mb/s) and low speed (1.5 Mb/s) interfacing of the MSM
device to computers as a USB peripheral, or connecting the MSM device to other peripherals ­RUIM level translators enable MSM device interfacing with external modules

• Twelve multi-purpose pins that can be configured as digital or analog I/Os, bi-directional I/Os, or
current sinks. Default functions support the RUIM level translators, power-on circuits, analog
multiplexer inputs, an LED driver, and a reference voltage buffer.

• Highly integrated functionality in a small package - 84-pin BCCS with a large center slug for electrical
ground, mechanical stability, and thermal relief

3. TECHNICAL BRIEF

- 28 -

[Figure 1.6] MSM6245 Interface

3. TECHNICAL BRIEF

- 29 -

[Figure1.7] PM6650 Block Diagram

3.5.5 GSM PAM (U101 : SKY77318)

The SKY77318 is an extremely small (6 x 6 mm), GSM PAM for handset applications. This module
has been optimized for excellent efficiency and Pout while maintaining high GSM/GPRS efficiency.
The small size and high performance is achieved with high-reliability GaAs HBT technology.
With 50Ω and output, no external matching or bias components are required. The module incorporates
two highly-integrated GaAs power amplifier die with a BiCMOS controller.
Each amplifier has three gain stages with on-die inter-stage matching implemented with a high Q
passives technology for optimal performance. The CMOS controller implements a fully integrated
power control within the module for GSM operations, and serves as the GPRS operations. This
eliminates the need for any external couplers, power detectors, current sensing etc., to assure the
output power level. The module has Tx enable and band select inputs. Module construction is a low­profile overmolded land-grid array on laminate.

3. TECHNICAL BRIEF

- 30 -

[Figure 1. 8] GSM PAM Schematic

GSM_PA_BAND MODE

8.86dB

HIGH

Rev.D

EGSM

GSM

DCS/PCS

Rev.1.0

LOW

7.5dB

C136

0.01u

10nH

L116

L406 2.7nH

100p

C438

C124
100p

100ohm

R114

NA

5.6p

C441

1.5nH

L403

L115
18nH

100ohm

100ohmR113

R117

100ohm

R107

C153
15p

3

G2

5

G3

1

IN

4

O1

R11091

EFCH897MTDB1

FL101

2

G1

C123

0.01u

39

R112

L111

5.6nH

68p

C139C137

NA

C134

0.01u

GND39GND410GND5

GND612GND713GND814GND9

16

21

P_GND

19

RSVD_GND

VAPC

20

17

VBATT

2

VCC1A

6

VCC1B

BS

1

DCS_PCS_IN

315

DCS_PCS_OUT

EGSM_IN

4

EGSM_OUT

11

ENABLE

18

GND15GND2

7

8

SKY77318

U101

C149
15p

100ohm

R115

91 R111

C121
33u

C138
NA

R108

51

GSM_TX

DCS_PCS_TX

+VPWR

GSM_PA_BAND

GSM_PA_EN

GSM_PA_RA

3. TECHNICAL BRIEF

- 31 -

3.5.6 UMTS Duplexer(FL104:ACMD-7602)

A UMTS duplexer splits a single operating band into receive and transmit paths. Important
performance requirements include;

• Insertion loss. this component is also in the receive and transmit paths ; In the U250/KU250 typical
losses : UMTS2100_ Tx = 1.2 dB, UMTS2100_ Rx = 1.4 dB

• Out-of-band rejection or attenuation. the duplexer provides input selectivity for the receiver, output
filtering for the transmitter, and isolation between the two. Rejection levels for both paths are
specified over a number of frequency ranges. Two Tx-to-Rx isolation levels are critical to receiver
performance:

• Rx-band isolation. the transmitter is specified for out-of-band noise falling into the Rx band. This
noise leaks from the transmit path into the receive path, and must be limited to avoid degrading
receiver sensitivity. The required Rx-band isolation depends on the PA out of-band noise levels and
Rx-band losses between the PA and LNA. Minimum duplexer Rx band isolation value is about 51 dB.

• Tx-band isolation. the transmit channel power also leaks into the receiver. In this case, the leakage is
outside the receiver passband but at a relatively high level. It combines with Rx band jammers to
create cross-modulation products that fall in-band to desensitize the receiver. The required Tx-band
isolation depends on the PA channel power and Tx-band losses between the PA and LNA. Minimum
duplexer Tx-band isolation value is about 58dB.

• Passband ripple. the loss of this fairly narrowband device is not flat across its passband. Passband
ripple increases the receive or transmit insertion loss at specific frequencies, creating performance
variations across the band.s channels, and should be controlled.

• Return loss. minimize mismatch losses with typical return losses of 10 dB or more (VSWR <2:1).

• Power handling. high power levels in the transmit path must be accommodated without degraded
performance. The specified level depends on the operating band class and mobile station class (per
the applicable standard), as well as circuit losses and antenna EIRP. Several duplexer characteristics
depend upon its source and load impedances. QUALCOMM strongly recommends an isolator be
used between the UMTS PA and duplexer to assure proper performance.

3.5.7 UMTS Rx RF filter (FL103 : EFCH2140TDE1)

• Frequency range : 2110 ~ 2170MHz
An RF filter is located between the UMTS LNA and mixer. Insertion loss is important, but not as
critical as losses before the LNA. The most important parameters of this component include:

• Out-of-band rejection or attenuation levels, usually specified to meet these conditions:

- FFar out-of-band signals - ranging from DC up to the first band of particular concern and from the
last band of particular concern to beyond three times the highest passband frequency.

- Tx-band leakage - the transmitter channel power, although attenuated by the duplexer, still
presents a cross-modulation threat in combination with Rx-band jammers. The RF filter must
provide rejection of this Tx-band leakage.

- Other frequencies of particular concern . bands known to include other wireless transmitters that
may deliver significant power levels to the receiver input.

3. TECHNICAL BRIEF

- 32 -

Table 1.3 WCDMA Rx SAW Filter Specification

3. TECHNICAL BRIEF

- 33 -

3.5.8 Bluetooth (M100 : LBRQ-2B43A)

The MSM6245 includes BT baseband embedded BT 1.1 compliant baseband core, so the other
bluetooth components are an bluetooth RF module and Antenna. Figure1.9 shows the bluetooth
system architecture in the U250/KU250.

[Figure1.9] Bluetooth system architecture

MSM6245

Bluetooth

baseband

3.6 Digital Baseband(DBB/MSM6245)

3.6.1 General Description

A. Features(MSM6245)

• Support for multimode operation - tri-band WCDMA (UMTS), quad-band GSM/GPRS/EDGE

• Support for WCDMA (UMTS) uplink data rate up to 384 kbps

• High-performance ARM926EJ-S running at up to 225 MHz

• ARM Jazelle Java hardware acceleration for faster Java-based games and other applets

• QDSP4000 high-performance DSP cores

• Integrated Bluetooth 1.2 baseband processor for wireless connectivity to peripherals

• Qcamera™ with 30 fps QCIF viewfinder resolution, and support for 2 MP camera sensors

• Direct interface to digital camera module with video front end (VFE) image processing

• True 3D graphics for advanced wireless gaming

• SecureMSM v2.0 includes support for Open Mobile Alliance (OMA) DRM v2.0, SIM-lock and IMEI
integrity. Support for Q-fuse. Only trusted boot is supported

• Audio that is on par with portable music players

• Vocoder support (AMR, FR, EFR, HR)

• Advanced 14 x 14 mm, 0.5 mm pitch, 409-pin lead-free CSP packaging technology

• SD/SDIO hardware support

3. TECHNICAL BRIEF

- 34 -

3. BB Technical Description

3. TECHNICAL BRIEF

- 35 -

Front

End

Module

Duplexer

RTR6275

WCDMA

PAM

MSM6245

WCDMA

TX SAW

WCDMA

RX SAW

PM6650

-2M

GSM
PAM

GSM

TX SAW

COUPLER

VCTCXO

Bluetooth

RF Module

U-SIM

1.3M CAM

USB

MIC

SPK/RCV

KEYPAD

NAND, SDRAM

FLASH

MAIN LCD

VGA CAM

GSM900 Rx

GSM1800 Rx

GSM1900 Rx

GSM900 Tx

GSM1800/1900 Tx

AntSW Logic

WCDMA2100 Tx

WCDMA2100 Rx

GSM
VCO

WCDMA

VCO

HDET

GSM Block

WCDMA Block

Figure 1.10 Simplified Block Diagram

3. TECHNICAL BRIEF

- 36 -

3.7 Block Diagram(MSM6245)

Figure 1.11 Simplified Block Diagram of MSM6245

Camera 1.3M

VGA camera

CAMERA

PROCESSING

(Default 8bit

Interface)

GRAPHICS

Open GL ES

3D, 2D

VIDEO

MPEG-4

H.263, H.264

AUDIO

MP3, AAC,

EVRC, QCELP

AMR, CMX, MIDI

SDRAM
512Mbit

EBI 1 EBI 2

DUAL MEMORY BUS

MSM6245

Modem QDSP 4000

PLL

QDSP 4000

CONNECTIVITY

JTAG

Keypad I/F

NAND Flash

512Mbit

ARM 926ejs
With Jazelle

USB

UART1

LCD

(1.76inch)

GSM/GPRS/EDGE

processor

UMTS, WCDMA

BT 1.2

processor

Rx ADC

UART2 / RUIM1

UART3 / PMIC SBI

Tx DAC

GPIO

RF SBI

PM6650

I/O Conn

US

B

USIM

3. TECHNICAL BRIEF

- 37 -

3.8 Subsystem(MSM6245)

3.8.1. ARM Microprocessor Subsystem

The MSM6245 device uses an embedded ARM926EJ-S microprocessor. This microprocessor,
through the system software, controls most of the functionality for the MSM, including control of the
external peripherals such as the keypad, LCD, RAM, ROM, and EEPROM devices. Through a Generic
single-wire serial bus interface (SSBI) the ARM926EJ-S configures and controls the functionality of the
RTR6275, RFR6275 and PM6650 devices.

3.8.2. WCDMA R99 features

The MSM6245 device supports release 99 June 2004 of the W-CDMA FDD standard, including the
following features:

■ All modes and data rates for W-CDMA frequency division duplex (FDD), with the following
restrictions:

❏ The downlink supports the following specifications:

- Up to four physical channels, including the broadcast channel (BCH), if present

- Up to three dedicated physical channels (DPCHs)

- Spreading factor (SF) range support from 4 to 256

- The following transmit diversity modes are supported:

❏ Space time transmit diversity (STTD)
❏ Time-switched transmit diversity (TSTD)
❏ Closed-loop feedback transmit diversity (CLTD)

■ The uplink supports the following specifications:

❏ The uplink provides the following UE support:

- One physical channel, eight TrCH, and 16 TrBks starting at any frame boundary

- A maximum data rate of 384 kbps

❏ Full SF range support from 4 to 256

■ SMS (CS and PS)

■ PS data rate - 384 kbps DL / 384 kbps UL

■ CS data rate - 64 kbps DL / 64 kbps UL

■ AMR (all rates)

3. TECHNICAL BRIEF

- 38 -

3.8.3. GSM features

The following GSM modes and data rates are supported by the MSM6245 device hardware. Support
modes conform to release '99 specifications of the sub-feature.

■ Voice features
❏ FR
❏ EFR
❏ AMR
❏ HR
❏ A5/1, A5/2, and A5/3 ciphering

■ Circuit-switched data features
❏ 9.6k
❏ 14.4k
❏ Fax
❏ Transparent and non-transparent modes for CS data and fax
❏ No sub-rates are supported.

3.8.4. GPRS features

■ Packet switched data (GPRS)
❏ DTM (Simple Class A) operation
❏ Multi-slot class 12 data services
❏ CS schemes: CS1, CS2, CS3, and CS4
❏ GEA1, GEA2, and GEA3 ciphering

■ Maximum of four Rx timeslots per frame

3.8.5. EDGE features

■ EDGE E2 power class for 8 PSK

■ DTM (simple Class A), multi-slot class 12

■ Downlink coding schemes - CS 1-4, MCS 1-9

■ Uplink coding schemes - CS 1-4, MCS 1-9

■ BEP reporting

■ SRB loopback and test mode B

■ 8-bit, 11-bit RACH

■ PBCCH support

■ 1 phase/2 phase access procedures

■ Link adaptation and IR

■ NACC, extended UL TBF.

3. TECHNICAL BRIEF

- 39 -

3.8.6. MSM6245 device audio processing features

■ Integrated wideband stereo CODEC
❏ 16-bit DAC with typical 88 dB dynamic range
❏ Supports sampling rates up to 48 kHz on the speaker path and 16 kHz on the microphone path

■ VR- Voice mail + voice memo

■ Acoustic echo cancellation

■ Audio AGC

■ Audio Codecs: AMR-NB, AAC, AAC Plus, Enhanced AAC Plus, Windows Audio v9, Real Audio 8

(G2)

■ Internal vocoder supporting AMR, FR, EFR, and HR

3.8.7. MSM6245 microprocessor subsystem

■ Industry standard ARM926EJ-S embedded microprocessor subsystem
❏ 16 kB instruction and 16 kB data cache
❏ Instruction set compatible with ARM7TDMI®
❏ ARM version 5TEJ instructions
❏ Higher performance 5 stage pipeline, Harvard cached architecture
❏ Higher internal CPU clock rate with on-chip cache

■ Java hardware acceleration

■ Enhanced memory support
❏ 75 MHz and 90 MHz bus clock for SDRAM
❏ 32-bit SDRAM
❏ Dual memory buses separating the high-speed memory subsystem (EBI1) from low-speed

peripherals (EBI2) such as LCD panels

❏ 1.8 memory interface support for EBI1 and 1.8 V or 2.6 V memory interface support EBI2
❏ NAND FLASH memory interface

- 8/16-bit data I/O width NAND flash support

- 1- or 4-bit ECC

- 512-byte/2KB page-size support

- 2 chip selects supported for NAND Flash

❏ Boot from NAND
❏ Low-power SDRAM (LP-SDRAM) interface

■ Internal watchdog and sleep timers

3.8.8. Supported interface features

■ USB On-the-Go core supports both slave and host functionality

■ Three universal asynchronous receiver transmitter (UART) serial ports

■ USIM controller (via UART)

■ Integrated 4-bit secure digital (SD) controller for SD and Mini SD cards

■ Parallel LCD interface

■ General-purpose I/O pins

■ External keypad interface

3. TECHNICAL BRIEF

- 40 -

3.8.9. Supported multimedia features

■ Provide additional general purpose MIPS by using:
❏ Two QDSP4000s
❏ Dedicated hardware accelerators and compression engines

■ Improve Java, BREW, and game performance
❏ Integrated Java and 2D/3D graphics accelerator with Sprite engine

■ Enable various accessories via USB host connectivity.
❏ Integrated USB host controller functionality

■ Enable compelling visual and audio applications.

Qcamera

TM

■ High-quality digital camera processing, supporting CCD or CMOS image sensors up to 2MP

■ 30 fps QCIF viewfinder

Qtv

TM

■ Audio and video decoder that supports VOD, MOD and Broadcast multimedia services.

■ Audio codecs supported: AMR-NB, AMR-WB, AMR-WB+, AAC, AAC Plus, Enhanced AAC Plus,

Windows® Media Audio v9, RealAudio® v8

■ Integrated stereo wideband codec for music/digital clips

■ CMX

■ Video codecs supported: MPEG-4, H.263, H.264, Windows Media® v9 and RealNetworks® v10

Video telephony services: Qvideophone

TM

■ A two-way mobile video conferencing solution that delivers 15 fps @ QCIF, 64kbps

■ Video codecs supported: MPEG-4 and H.263

■ Audio codecs supported: AMR-NB.

Qcamcorder

TM

■ Real time mobile video encoder

■ Video codecs supported: MPEG-4, H.263.H.264

■ Audio codecs supported: AMR-NB

■ Recording performance: 15 fps @ QCIF, 192 kbps

CMXTM(MIDI and still image, animation, text, LED/vibrate support)

■ 72 simultaneous polyphonic tones

■ 44 kHz sampling rate

■ 512 kB wave table

■ Support of universal file formats
❏ Standard MIDI Format (SMF)
❏ SP-MIDI
❏ SMAF Audio playback (MA-2, MA-3, MA-5)
❏ XMF/OLS
❏ MFi (requires Docomo license)

3. TECHNICAL BRIEF

- 41 -

■ PNG decoder

■ Pitch bend range support

■ LED/vibrate support

■ Scalable Vector Graphics (SVG- Tiny 1.1 + SVG Tiny 1.2)

■ MLZ decoder

■ Integrated PNG/SAF A.T.

Note:

1. At this time, only 32-bit SDRAM is supported on the MSM6245 device. There are potential MIPS
issues when running Bluetooth and video telephony concurrently with any other memory configuration.
16-bit SDRAM and NOR FLASH are currently being evaluated and documentation will be updated
accrdingly in the next revision.

Table 1-1 Summary of MSM6245 device features

3. TECHNICAL BRIEF

- 42 -

Table 1-2 Description of RF configurations

3. TECHNICAL BRIEF

- 43 -

3.8.10. Stereo Wideband CODEC

The MSM6245 device integrates a wideband voice/audio CODEC into the mobile station modem
(MSM). The CODEC supports two differential microphone inputs, one differential earphone output, one
single-ended earphone output, and a differential analog auxiliary interface.
The CODEC integrates the microphone and earphone amplifiers into the MSM6245 device, reducing
the external component count to just a few passive components.
The microphone (Tx) audio path consists of a two-stage amplifier with the gain of the second stage set
externally. The Rx/Tx paths are designed to meet the ITU-G.712 requirements for digital transmission
systems.

3.8.11. Vocoder Subsystem

The MSM6245 device’s QDSP4000 supports AMR,FR,EFR and HR. In addition, the QDSP4000 has
modules to support DTMF tone generation, DTMF tone detection, Tx/Rx volume controls, Tx/Rx
automatic gain control (AGC), Rx Automatic Volume Control (AVC), ear seal echo canceller (ESEC),
Acoustic Echo Canceller (AEC), Noise Suppression (NS), and programmable, 13-tap, Type-I, FIR,
Tx/Rx compensation filters. The MSM6245 device’s integrated ARM9TDMI processor downloads the
firmware into the QDSP4000 and configures QDSP4000 to support the desired functionality.

3.8.12. ARM Microprocessor subsystem

The MSM6245 device uses an embedded ARM926EJ-S microprocessor. This microprocessor,
through the system software, controls most of the functionality for the MSM device, including control of
the external peripherals such as the keypad, LCD, RAM, ROM, and EEPROM devices. Through a
generic single serial bus interface (SSBI) the ARM926EJ-S configures and controls the functionality of
the RFR6275, RTR6275, and PM6650 devices.

3.8.13. Mode Select and JTAG Interfaces

The mode pins to the MSM6245 device determine the overall operating mode of the ASIC. The options
under the control of the mode inputs are Native mode, which is the normal subscriber unit operation,
ETM mode, which enables the built-in trace mode, and test mode for factory testing. The MSM6245
device meets the intent of the ANSI/IEEE 1149.1A-1993 feature list. The JTAG interface can be used
to test digital interconnects between devices within the mobile station during manufacture.

3. TECHNICAL BRIEF

- 44 -

3.8.14. General-Purpose Input/Output Interface

The MSM62450 device has general-purpose bidirectional input/output pins. Some of the GPIO pins
have alternate functions supported on them. The alternate functions include USB interface, additional
RAM, ROM, general-purpose chip selects, parallel LCD interface, and a UART interface. The function
of these pins is documented in the various software releases.

3.8.15. UART

The MSM6245 device employs three UARTs. UART1 has dedicated pins while UART2 and UART3
share multiplexed pins.

3.8.16. USB

The MSM6245 device integrates a universal serial bus (USB) controller that supports both
unidirectional and bidirectional transceiver interfaces. The USB controller acts as a USB peripheral
communicating with the USB host. MSM6245 supports the 3-wire functionality.

3. TECHNICAL BRIEF

- 45 -

3.9 Power Block

3.9.1. General

MSM6245, included RF, is fully covered by PM6650(Qualcomm PMIC). PM6650 cover the power of
MSM6245, MSM memory, RF block, Bluetooth, USIM and TCXO. Major power components are :

3.9.2. PM6650

The PM6650 device (Figure 1-1) integrates all wireless handset power management. The power
management portion accepts power from all the most common sources - battery, external charger,
adapter, coin cell back-up - and generates all the regulated voltages needed to power the appropriate
handset electronics. It monitors and controls the power sources, detecting which sources are applied,
verifying that they are within acceptable operational limits, and coordinates battery and coin cell
recharging while maintaining the handset electronics supply voltages.

Eight programmable output voltages are generated using low dropout voltage regulators, all derived
from a common trimmed voltage reference. A dedicated controller manages the TCXO warm-up and
signal buffering, and key parameters (under-voltage lockout and crystal oscillator signal presence) are
monitored to protect against detrimental conditions.

MSM device controls and statuses the PM6650 IC using Single Serial Bus Interface (SSBI)
supplemented by an Interrupt Manager for time-critical information. Another dedicated IC Interface
circuit monitors multiple trigger events and controls the power-on sequence.

3. TECHNICAL BRIEF

- 46 -

Figure 1.12 PM6650 Functional Block Diagram

3. TECHNICAL BRIEF

- 47 -

3.9.3. Charging control

A programmable charging block in PM6650 is used for battery charging. It is possible to set limits for
the charging current. The external supply typically connects directly to pin (VCHG). The voltage on this
pin (VCHG) is monitored by detection circuitry to ascertain whether a valid external supply is applied or
not. For additional accuracy or to capture variations over time, this voltage is routed internally to the
housekeeping ADC via the analog multiplexer. PM6650 circuits monitor voltages at VCHARGER and
ICHARGE pins to determine which supply should be used and when to switch between the two
supplies. These pins are connected to the Source (or emitter) and Drain (or collector) contacts of the
pass transistor respectively.

Figure 1.13 U250/KU250 Battery Bar Display(Stand By Condition)

4.2V~3.82V
100~70 (%)

3.81V~3.74V
69~45 (%)

3.73V~3.69V
44~20 (%)

3.68V~3.59V
19~3 (%)

3.58V~3.20V
2~0 (%)

Trickle Charging

Trickle Charging of the main battery, enabled through SBI control and powered from VDD, is provided
by the PM6650 IC, The trickle charger is on-chip programmable current source that supplies current
from VDDto pin (VBAT). Trickle charging can be used for lithium-ion and nickelbased batteries, with its
performance specified below (3.2V). The charging current is set to 80mA.

3. TECHNICAL BRIEF

- 48 -

Parameter Min Typ Max Unit

Trickle Current 60 80 100 mA

3. TECHNICAL BRIEF

- 49 -

Constant Current Charging

The PM6650 IC supports constant current charging of the main battery by controlling the charger pass
transistor and the battery transistor. The constant current charging continues until the battery reaches
its target voltage, 4.2V.

Constant Voltage Charging

Constant voltage charging begins when the battery voltage reaches a target voltage, 4.2V. The end of
constant voltage charging is commonly detected 10% of the full charging current.

•

Charging Method : CC & CV (Constant Current & Constant Voltage)

•

Maximum Charging Voltage : 4.2V

•

Maximum Charging Current : 600mA

•

Nominal Battery Capacity : 950mAh

•

Charger Voltage : 5.1V

•

Charging time : Max 3h (Except time trickle charging)

•

Full charge indication current (icon stop current) : 100mA

•

Low battery POP UP : Idle - 3.58V, Dedicated(GSM/WCDMA) - 3.58V

•

Low battery alarm interval : Idle - 3 min, Dedicated - 1min

•

Cut-off voltage : 3.20V

3.10 External memory interface

The MSM6245 device was designed to provide two distinct memory interfaces. EBI1 was targeted for
supporting high speed synchronous memory devices. EBI2 was targeted towards supporting slower
asynchronous devices such as LCD, NAND flash, SDRAM, etc.

•

EBI1 Features

- 16 bit static and dynamic memory interface

- 32 bit dynamic memory interface

- 24 bits of address for static memory devices which can support up to 32MBytes on each chip select

- Synchronous burst memories supported (burst NOR, burst PSRAM)

- Synchronous DRAM memories supported

- Byte addressable memory supporting 8 bit, 16 bit and 32 bit accesses

- Pseudo SRAM (PSRAM) memory support

•

EBI2 Features

- Support for asynchronous FLASH and SRAM(16bit & 8bit).

- Interface support for byte addressable 16bit devices (UB_N & LB_N signals).

- Support for 8 bit/16bit wide NAND flash.

- Support for parallel LCD interfaces, port mapped of memory mapped(18 or 16 bit).

•

512Mb NAND(8bit) flash memory + 512Mb SDRAM (32bit)

3. TECHNICAL BRIEF

- 50 -

Interface Spec

Device Part Name Maker Read Access Time Write Access Time

FLASH HYC0UEH0MF3P hynix 60 ns 60 ns

SDRAM HYC0UEH0MF3P hynix 7 ns 7 ns

Table#1. External memory interface

3. TECHNICAL BRIEF

- 51 -

Figure 1.14 Simplified Block Diagram of Memory Interface

SDRAM

512Mb

EBI1

ADDRESS[14:

DATA[31:0]

WE*

CS*

CAS*

RAS*

CLK_EN

CLK

DQM[3:0]

0]

MSM6245

EBI2

NAND_CS*

NAND_RE*

NAND_WE*

NAND_CLE

NAND_WP*

NAND_ALE

NAND_READY

DATA[7:0]

NAND

512Mb

(64MB)

3.11 H/W Sub System

3.11.1. RF Interface

A. RTR6275(WCDMA_Tx, GSM_Tx/Rx)

MSM6245 controls RF part(RTR6275) using these signals.

•

SBST : SSBI I/F signals for control Sub-chipset

•

PA_ON1 : Power AMP on RF part

•

RX0_I/Q_M/P,TX_I/Q_M/P : I/Q for T/Rx of RF

•

TX_AGC_ADJ : control the gain of the Tx signal prior to the power amplifier

•

DAC_REF : Reference input to the MSM Tx data DACs

3. TECHNICAL BRIEF

- 52 -

Figure 1.15 Schematic of RF Interface of MSM6245

Close to MSM

RF

XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77

UART2_DP_RX_DATA_GPIO89

H6

UART3_RFR_N_GPIO87

L25

D16

TCK

F19

TCXO_EN_GPIO94

TDI

D15
A17

TDO

F15

TMS

L13

TRK_LO_ADJ

TRST_N

H15

TX_AGC_ADJ

H13

H12

TX_ON_GRFC10

SYNTH0_GP_PDM0_GPIO92

F18

H16

RTCK

H18

SBST1_GPIO93

F17

PA_ON0

Q_IM_CH0

AA25

W23

Q_IM_CH1

Q_IP_CH0

Y25

V23

Q_IP_CH1

Q_OUT

B12

Q_OUT_N

A12

I_IM_CH0

AB25

I_IM_CH1

V25

I_IP_CH0

AC25

I_IP_CH1

W25

B13

I_OUT

A13

I_OUT_N

D17

GRFC0_GPIO3

B8

GRFC1_AUX_SBDT_GPIO4

A8

GRFC2_GPIO5

D9

GRFC3_GPIO6

F10

H10

GRFC4_AUX_SBCK_GPIO7

GRFC5_AUX_SBST_GPIO8

D11

T23

GRFC7_GPIO10

GRFC8_GPIO11

B4

T19

GRFX6_GPIO9

GP_PDM1_PA_RAN_GE0

H17

GP_PDM2_PA_RAN_GE1

DAC_REF

F12

BT_DATA_GPIO20

BT_SBCK_GPIO23

E26
E25

BT_SBDT_GPIO22

BT_SBST_GPIO24

F23

H21

BT_TX_RX_N_GPIO21

K19

AUX_PCM_CLK_GRFC14_GPIO80

AUX_PCM_DIN_GRFC13_GPIO14

N21
G4

AUX_PCM_DOUT_GRFC12_GPIO103

J8

AUX_PCM_SYNC_GRFC11_GPIO102

BT_CLK_GPIO25

G23

R19

33nF C246

R2132K

TX_AGC_ADJ

PA_R0

RCV_EN_N

SPK_AMP_EN

GSM_PA_EN

GSM_PA_BAND

ANT_SEL1
ANT_SEL0

LCD_IF_MODE_1

RX_QM
RX_QP
RX_IM
RX_IP

PA_ON

TRK_LO_ADJ

TCXO_EN

TX_ON

BT_SBST
BT_SBCK

BT_TX_RX_N
BT_DATA

BT_SBDT

BT_CLK

DAC_REF

TX_QM
TX_QP
TX_IM
TX_IP

3. TECHNICAL BRIEF

- 53 -

B. the others

•

TRK_LO_ADJ : TCXO(19.2M) Control

•

PA_ON : WCDMA(2100) TX Power Amp Enable

•

ANT_SEL[0-2] : Ant Switch Module Mode Selection(WCDMA,GSM Tx/Rx,DCS-PCS Tx/Rx)

•

GSM_PA_BAND : GSM/DCS-PCS Band Selection of Power Amp

•

GSM_PA_RAMP : Power Amp Gain Control of APC_IC

•

GSM_PA_EN : Power Amp Gain Control Enable of APC_IC

3.11.2. MSM Sub System

3.11.2.1. USIM Interface

SIM interface scheme is shown in Figure.

And, there control signals are followed

•

USIM_CLK : USIM Clock

•

USIM_Reset : USIM Reset

•

USIM_Data : USIM Data T/Rx

3.11.2.2. UART Interface

UART signals are connected to MSM GPIO through IO connector with 115200 bps speed.

3. TECHNICAL BRIEF

- 54 -

Figure 1.16 SIM Interface

Table. UART Interface

MSM6245

PM6650

USIM

USIM CLK

USIM Reset

USIM Data

USIM Data

USIM Reset

USIM CLK

VREG_UIM 2.85V

GPIO_Map Name Note

GPIO_96 UART_RXD Data_Rx

GPIO_95 UART_TXD Data_Tx

3. TECHNICAL BRIEF

- 55 -

3.11.2.3. USB

The MSM6245 device contains a Universal Serial Bus (USB) interface to provide an efficient
interconnect between the mobile phone and a personal computer (PC). The USB interface of the
MSM6245 was designed to comply with the definition of a peripheral as specified in USB Specification,
Revision 1.1. Therefore, by definition, the USB interface is also compliant as a peripheral with the USB
Specification, Revision 2.0. The USB Specification Revision 1.1 defines two speeds of operation,
namely low-speed (1.5 Mbps) and full-speed (12 Mbps), both of which are supported by the
MSM6245.

Table. USB Signal Interface

Figure 1.17 Schematic of USB block(MSM6245 Side & PM6650 Side)

Name Note

USB_DAT Data to/from MSM
USB_SE0 Data to/from MSM
USB_OE_N Out-Put Enable of Transceiver
USB_VBUS USB_Power From Host(PC)
USB_D+ USB Data+ to Host
USB_D- USB Data- to Host

LCD DRV N

12

UART2_DP_TX_DATA_GPIO88

UART2_RFR_N_GPIO91

UART3_CTS_N_GPIO86

UART3_DP_RX_DATA_GPIO85

UART2_CTS_N_GPIO90

F4

G6

USIM_CLK

USIM_RST_N

UART3_DP_TX_DATA_GPIO84

E4

L23

M21

USIM_DATA

M19

D6

GPIO40

GPIO42

D7

PS_HOLD

PM_INT_N

USB_DAT_VP

USB_OE_TP_N

USB_SE0_VM

N26

N25

N23

USB_SE0

USB_DAT

USB_OE_N

MMC_CLK_SDCC_CLK_GPIO31

MMC_CMD_GPIO30

MMC_DATA_SDCC_DAT0_GPIO32

L14

H14

M16

MMC_CLK

MMC_CMD

MMC_DATA

USB_OE_N

USB_CTL_N

USB_VBUS

USB_DAT

USB_D+

USB_SE0

USB_D-

R309 2.2K

C336

1608

4.7u

VREG_5V

13

USB_OE_N

14

VSW_5V

15

USB_CTL_N

16

USB_VBUS

17

USB_DAT

18

USB_D_P

19

USB_SE0

20

USB_D_M

21

GP1_DRV_N(

22

3.11.3 HKADC(House Keeping ADC)

The MSM6245 device has an on-chip 8-bit analog-to-digital converter (HKADC) which is tended to
digitize DC signals corresponding to analog parameters such as battery voltage, temperature, and RF
power levels. The MSM6245 device has six analog input pins which are multiplexed to the input of the
internal HKADC.

3. TECHNICAL BRIEF

- 56 -

Figure 1.18 MSM6245 HKADC Block diagram

Table. HKADC channel table

Channel Signal Note

HKADC0 AMUX_OUT RF PAM Temperature Check

HKADC1 VBATT_SENSE Battery voltage level

HKADC2 NC NC

HKADC3 NC NC

HKADC4 PCB_Rev_ADC PCB Version Check

HKADC5 Battery_THERM Battery Temperature Check

3. TECHNICAL BRIEF

- 57 -

3.11.4. Key Pad

There are 23 main key buttons in Figure.
Shows the Keypad circuit. ‘END’ Key is connected to PMIC(PM6650).

Table. Key Matrix Mapping Table

Figure 1.19 Main Keypad Circuit

Figure 1.20 END Keypad Circuit

COL0 COL1 COL2 COL3 COL4

ROW(0) - CLR MENU
ROW(1) 1 2 3 LEFT UP
ROW(2) 4 5 6 OK RIGHT
ROW(3) 7 8 9 SEND SEARCH
ROW(4) * 0 # DOWN BACK

VREG_MSMP_2.7V

KEY_ROW(0)

KEY_ROW(1)

KEY_ROW(2)

KEY_ROW(3)

KEY_ROW(4)
KEY_COL(0)
KEY_COL(1)
KEY_COL(2)
KEY_COL(3)
KEY_COL(4)

R423

100K

RA400

246

135

8

7

100K

400

1

403

4

406

7

HOT400

HOT4

KEY MAP

2

5

407

8

409

0

402

3

405404

6

408

9

HOT401

HOT3

END

CLR

OK

SND

DN

MENU

UP401 LEFT

RIGHT

SEARCH

BACK

PM_ON_SW_N

END

3.11.5 Camera Interface

U250/KU250 Installed a 1.3M Pixel and 0.3Mega Camera. Below figure shows the camera socket type
connector and camera I/F signal.

3. TECHNICAL BRIEF

- 58 -

Figure 1.21 Camera Socket Type Connector

VT_CAMERA_CONNECTOR

REV_1.0

REV_1.0

MEGA CAMERA CONNECTOR

CAMERA

REV_1.0

INOUT_A4

4

INOUT_B1

9
8

INOUT_B2
INOUT_B3

7
6

INOUT_B4

FL408

ICVE21184E150R500FR

5

G110G2

1

INOUT_A1
INOUT_A2

2
3

INOUT_A3

ICVE21184E150R500FR

FL407

5

G110G2

1

INOUT_A1
INOUT_A2

2
3

INOUT_A3

4

INOUT_A4

INOUT_B1

9
8

INOUT_B2
INOUT_B3

7
6

INOUT_B4

G15G2

10

INOUT_A1

1
2

INOUT_A2
INOUT_A3

3
4

INOUT_A4

9

INOUT_B1
INOUT_B2

8
7

INOUT_B3
INOUT_B4

6

ICVE21184E150R500FR

FL406

C41310p

P13

13

14

P14

P15

15

P16

16

17

P17

P18

18

19

P19

P2

2

P20

20

3

P3
P4

4
5

P5

P6

6

7

P7

P8

8

9

P9

CN404

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

1

P1

P10

10

11

P11

12

P12

R437 20

NA C449

0R436

10p C415

NA C448

EVL14K02200VA430

0.1uF C411

C424NA

1u C412

C4140.1u

VSYNC

19
18

HSYNC

7

MCLK

20

PCLK

PGND1

32

31

PGND2

PGND3

30

29

PGND4

PGND5

28

27

PGND6

PGND7

26

25

PGND8

9

RESETB

11

SCK
SDA

10

STANDBY

12

14

VDDIO

AGND16AGND2

17

16

AVDD

22

D0
D1

23
24

D2
D3

1
2

D4
D5

3
4

D6
D7

5

8

DGND1

DGND2

15

21

DGND3

DVDD

13

MEGA_CAM_PWR_DOWN

I2C_SDA

I2C_SCL

MEGA_CAM_RESET_N

CAM_VSYNC_OUT

CAM_HSYNC_OUT

VREG_CAM_AVDD_2.8V

CN403

VREG_CAM_DVDD_1.8V

VREG_CAM_AVDD_2.8V

CAM_PCLK

CAM_MCLK

COMMON_CAM_MCLK

CAM_PCLK

CAM_DATA_OUT(3)

CAM_DATA_OUT(2)

CAM_DATA_OUT(0)

CAM_DATA_OUT(4) CAM_DATA_OUT(5)

CAM_DATA_OUT(6)

CAM_DATA_OUT(7)

CAM_HSYNC_OUT

I2C_SDA

VGA_CAM_RESET_N

VREG_CAM_DVDD_1.5V

CAM_DATA_OUT(1)

CAM_DATA(6)

CAM_DATA_OUT(0)

CAM_DATA_OUT(2)

CAM_DATA_OUT(5)

CAM_DATA_OUT(3)
CAM_DATA_OUT(4)

CAM_DATA_OUT(1)

CAM_DATA_OUT(7)

CAM_DATA_OUT(6)

COMMON_CAM_MCLK

I2C_SCL

CAM_VSYNC_OUT

CAM_DATA(1)
CAM_DATA(2) CAM_DATA_OUT(2)

CAM_DATA(3)

CAM_DATA(5)

CAM_DATA(4)

CAM_DATA_OUT(3)

CAM_DATA_OUT(5)

CAM_DATA(0)

CAM_DATA_OUT(1)

CAM_DATA_OUT(0)

CAM_DATA_OUT(4)

CAM_DATA(7)

CAM_VSYNC
CAM_HSYNC

CAM_DATA_OUT(6)
CAM_DATA_OUT(7)

CAM_VSYNC_OUT
CAM_HSYNC_OUT

3. TECHNICAL BRIEF

- 59 -

The MEGA Camera module is connected to socket type connector with 24 pin (F95M08). Its interface
is dedicated camera interface port in MSM6245. The camera port supply 24.576MHz master clock to
camera module and receive 49.152MHz pixel clock (15fps), vertical sync signal, horizontal sync signal,
reset signal and 8bits data from camera module. The camera module is controlled by I2C port from
MSM6245.

Table. Interface between MEGA Camera Module and MAIN PCB (in camera module)

Pixel Clock (49.152M)OCAM_PCLK20

Vertical SyncO CAM_VSYNC_OUT19

Horizontal SyncO CAM_HSYNC_OUT18

GNDGNDGND17

GNDGNDGND15
AVDDI

VREG_CAM_AVDD_2.8V

16

GNDGNDGND21

DataOCAM_DATA_OUT(5)3
DataOCAM_DATA_OUT(6)4
DataOCAM_DATA_OUT(7)5
GNDGNDGND6

MCLK7

GNDGNDGND8
Camera reset signalIMEGA_CAM_RESET_N9

I2C_SDA10

VDDIOIVREG_CAM_AVDD_2.8V14

DVDDIVREG_CAM_DVDD_1.8V13

Camera power downIMEGA_CAM_PWR_DN12

I2C_SCL11

DataOCAM_DATA_OUT(4)2

DataOCAM_DATA_OUT(3)1

NotePortNameNo

DataOCAM_DATA_OUT(0)22
DataOCAM_DATA_OUT(1)23
DataOCAM_DATA_OUT(2)24

I

Master Clock(24.576M)

O

I2C Data

O

I2C Clock

3. TECHNICAL BRIEF

- 60 -

The VGA Camera module is connected to socket type connector with 20 pin (CLE9120-2761E). Its
interface is dedicated camera interface port in MSM6245. The camera port supply 24.576MHz master
clock to camera module and receive 12.288MHz pixel clock (15fps), vertical sync signal, horizontal
sync signal, reset signal and 8bits data from camera module.
The camera module is controlled by I2C port from MSM6245.

Table. Interface between VGA Camera Module and MAIN PCB (in camera module)

NotePortNameNo

VREG_CAM_DVDD_1.8V

1

I

DVDD

Master Clock(24.576M)ICAM_MCLK2

GNDGNDGND3

Clock for Camera Data Out(12.288M)OCAM_PCLK4

DataOCAM_DATA(0)5

DataOCAM_DATA(1)6

DataO CAM_DATA(2)7

DataOCAM_DATA(3)8

DataOCAM_DATA(4)9

DataOCAM_DATA(5)10

DataOCAM_DATA(6)11

DataOCAM_DATA(7)12

Vertical SyncOCAM_VSYNC13

Horizontal SyncOCAM_HSYNC14

GNDGNDGND15

I2C DataI I2C_SDA16

I2C ClockII2C_SCL17

Camera reset signalI VGA_CAM_RESET_N18

Camera I/O PowerIVREG_AVDD_2.8V19

Camera I/O PowerIVREG_AVDD_2.8V20

3. TECHNICAL BRIEF

- 61 -

3.11.6 Keypad Light

There are 8 Blue LEDs in Main key backlight circuit, which are driven by KYDB_BACKLIGHT line from
PM6650.

Figure 1.22 Schematic of KEY back light circuit (KEY side)

KEY_BACK_LIGHT LED(8EA)

REV_B : EDLH0013501 --> EDLH0006001

R418

100ohm

100ohm

R415

100ohm

R411

R413 100ohm

LD408

LEBB-S14H

LEBB-S14HLD405

LD406 LEBB-S14H

R414

100ohm

LD400 LEBB-S14H

100ohm

R417

LD404 LEBB-S14HLEBB-S14HLD403

100ohmR416

LEBB-S14HLD402

R419 100ohm

LEBB-S14HLD407

+VPWR

KYBD_BACKLIGHT

3. TECHNICAL BRIEF

- 62 -

3.11.7. LCD Module (NM176CN1 : Tovis)

- The NM176CN1 model is a Color TFT Main supplied by Tovis. This LCD Module has a 1.76 inch
diagonally measured active display area with 176(RGB)X220 resolution. each pixel is divided into
Red, Green and Blue sub-pixels and dots which are arranged in vertical stripes.

* Features

- Display mode(Main LCD) : Normally White, Transmissive TN mode 265K colors.

- LCD Driver IC: NT3916 (NOVATEK).

- 16 bit CPU interface Parallel

3.11.8. Display & LCD FPC Interface

LCD module is connected to LCD KEY FPCB with 35 pin (XF2B-3545-31A / OMROM) The LCD
module is controlled by 16-bit EBI2 in MSM6245.

Figure 1.23 Interface between LCD Module and MAIN PCB.

CN400

LCD CONNECTOR

ICVE21184E150R500FR

9

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VA410

EVL14K02200

EVL14K02200

VA409

LCD_RESET_N
LCD_IF_MODE_0
LCD_IF_MODE_1
LCD_VSYNC

ICVE21184E150R500FR

INOUT_B1

INOUT_A1

1

INOUT_B2

INOUT_A2

2

INOUT_B3

INOUT_A3

3

INOUT_B4

INOUT_A4

4

G15G2

10

FL401

9
8
7
6

LCD_CS_N
LCD_ADS
EBI2_WE_N
EBI2_OE_N

INOUT_B1

8

INOUT_B2

7

INOUT_B3

6

INOUT_B4

ICVE21184E150R500FR

9

INOUT_B1

8

INOUT_B2

7

INOUT_B3

6

INOUT_B4

ICVE21184E150R500FR

INOUT_A1

1

INOUT_A2

2

INOUT_A3

3

INOUT_A4

4

ICVE21184E150R500FR

INOUT_A1

1

INOUT_A2

2

INOUT_A3

3

INOUT_A4

4

5

INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4

G2

10

INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4

INOUT_B1
INOUT_B2
INOUT_B3
INOUT_B4

G15G2

10

INOUT_B1
INOUT_B2
INOUT_B3
INOUT_B4

G1

10

G1

5

G110G2

5

G2

FL405

FL400

FL402

1
2
3
4

1
2
3
4

9
8
7
6

FL403

9
8
7
6

C409 0.1u

D402

PLW0501H-LF

EBI2_DATA(0)
EBI2_DATA(1)
EBI2_DATA(2)
EBI2_DATA(3)

EBI2_DATA(4)
EBI2_DATA(5)
EBI2_DATA(6)
EBI2_DATA(7)

EBI2_DATA(8)
EBI2_DATA(9)
EBI2_DATA(10)
EBI2_DATA(11)

EBI2_DATA(12)
EBI2_DATA(13)
EBI2_DATA(14)
EBI2_DATA(15)

LCD_MAKER_ID
VREG_LCD_2.8V

WLED_1
WLED_2
WLED_3
WLED_PWR

INSTPAR

3. TECHNICAL BRIEF

- 63 -

3.11.8.1. Audio Signal Processing & Interface

Audio signal processing is divided uplink path and downlink path. The uplink path amplifies the audio
signal from MIC and converts this analog signal to digital signal and then transmits it to DBB Chip
(MSM6245). This transmitted signal is reformed to fit in GSM & WCDMA frame format and delivered to
RF Chipset. The downlink path amplifies the signal from DBB chip (MSM6245) and outputs it to
receiver (or speaker).

The receive path can be directed to either one of two earphone amplifiers or the auxiliary output. The
outputs earphone1 (EAR1OP, EAR1ON) and auxiliary out (LINE_P, LINE_N) are differential outputs.
Earphone2 (HPH_L, HPH_R) is a single-ended output stage designed to drive a headset speaker.

The microphone interface consists of two differential microphone inputs, one differential auxiliary input
and a two-stage audio amplifier.

Figure 1.24 Audio Interface Detailed Diagram(MSM6245)

(+16.5dB)

3. TECHNICAL BRIEF

- 64 -

MSM6245 CODEC pins

MSM pin W18

(CODEC VSS)

AUDIO

Place near

Near to MSM

10%

C201 47p

F25

SDCC_DAT1_GPIO99

SDCC_DAT2_GPIO100

M25
M26

AF20

MIC1N

AE20

MIC1P

MIC2N

AF21

AF22

MIC2P

T15

MICBIAS

AC21

LINE_L_IN

LINE_L_IP

AC22

LINE_ON

AC18

AC17

LINE_OP

LINE_R_IN

AC20

AC19

LINE_R_IP

W17

HPH_L

HPH_R

AA17

HPH_VREF

AA19

AE18

EAR1ON

AF18

EAR1OP

AA20

CCOMP

AUXIN

AF19

AUXIP

AE19

AA18

AUXOUT

220n

36R202

C203

10p

C204

220nC202

C211 22n

C212

0.1u

22n

C210

47pC200

LINE_N

LINE_P

MIC2N

MIC1N

MIC1P

MIC2P

HPH_R

HPH_L

RCV-

RCV+

MICBIAS

Figure 1.25 Audio part schematics

Figure 1.26 Audio part schematics

I/O CONNECTOR

R4021M

C400

0.1u

C401 33u

100KR405

100ohmR406

U400

NCS2200SQ2T2G

2

GND

1

OUT

VCC

5

3

VIN+

VIN-

4

R403

51K

8
9

19

2

21

3
4
5
6
7

CN401

HSEJ-18S04-25R

1

33uC402 R407 100ohm

R404

10K

R400

2.2K

R401

5.1K

MIC2N
MIC2P

MICBIAS

VREG_MSMP_2.7V

HPH_L

USB_D-

EAR_SENSE_N

USB_D+

VREG_MSMP_2.7V

HOOK_KEY

HPH_R

3. TECHNICAL BRIEF

- 65 -

AUDIO

Figure 1.27 Audio part schematics

C410

0.01u

SPK-

RCV-

SELECT_SPK&RCV

U401

R422 10

VA414EVL14K02200

NLAS5223BMNR2G

VCC

2

NO1

3

COM1

4

IN1

5

NC1

NO2

COM2

GND

101

9

8

IN2

7

NC2

6

SPK++VPWR

SPK_RCV+

RCV_EN_NSPK_RCV-

R42110

VA412EVL14K02200

RCV+

REV_B

MIC

REV_B : SUMY0010301 --> SUMY0003802

MIC400

OB4-15L42-C33L

1
2

REV_B : EDTY0008606 --> EDTY0008601

INSTPAR

INSTPAR

PSD05-LF

PSD05-LF

D403

D404

C420 39p

R424

2.2K

C421 39p

C418 0.1u

C419 0.1u

R425 2.2K

C416
10u

C417
47p

MICBIAS

MIC1P

MIC1N

3. TECHNICAL BRIEF

- 66 -

Audio part schematics

REV_C : 20K --> 3K

Audio AMP

REV_E : For Antenna Radiation

5.6KR430

C423

C428
1u

0.1u

R427 1K
R429 1K

C431
NA

C422 0.1u

2

4

INM

INP

3

OUTA

5

8

OUTB

VM

7

VP

6

1

_SD

NCP2890DMR2

U402

BYPASS

5600p

C426

RCVP

10u

C425

C4291000p

R4285.6K

RCVN

C430

1000p

R426

20K

100nHL402

L401

100nH

C4275600p

R431

20K

SPK_RCV+

SPK_RCV-

LINE_P

LINE_N

+VPWR

SPK+

SPK_AMP_EN

SPK-

3. TECHNICAL BRIEF

- 67 -

3.11.8.2. Audio Mode

There are three audio modes (Voice call, speaker phone, MIDI/MP3).

Audio & Sound Main Component

There are 6 main components in U250/KU250.

Table. Audio Mode

Table. Audio main component list

Headset MP3Headset

Headset MIDI BellHeadset

Speaker MP3Loud Mode

MP3

Speaker MIDI BellLoud Mode

MIDI

Speaker PhoneLoud Mode

Headset Voice CallHeadset

Speaker PhoneLoud Mode

Speaker phone

Receiver Voice Call

Description

Receiver Mode

Voice Call

DeviceMODE

Speaker/ReceiverEMS1810TPSpeaker/Receiver4

-42 dB microphoneOB4-15L42-C33LMIC400MIC5

Ear jackRMBLGG080STSBEar jack6

Dual Analog SwitchNLAS5223BMNR2GU401Analog Switch3

1W Audio Amp

Base-Band Modem

Note

NCP2890DMR2

MSM6245

Maker Part No.

U402

U201

Design No.

Audio amp

MSM6245

Component

2

1

3. TECHNICAL BRIEF

- 68 -

3.12 Main Features

1. LG-U250/KU250 Main features

- Bar Type

- WCDMA(2100) + GSM Tri-Band (900/1800/1900)

- Color LCD (Main:262K TFT, 1.76”)

- Dual Camera (1.3Mega + VGA(0.3M))

- 1810 speaker/receiver

- Stereo Headset

- Speaker phone (in GSM and WCDMA)

- MP3/AAC decoder and play

- MPEG4 encoder/decoder and play/save

- JPEG en/decoder

- Supports Bluetooth, USB

- 950 mAh (Li-Ion)

3. TECHNICAL BRIEF

- 69 -

2. U250/KU250 Main Component

Logic

/Audio

RF

Main board (Top)

Bluetoot

h

Logic

Main board (Bottom)

3. TECHNICAL BRIEF

- 70 -

RF

Reference Description Reference Description

SW100 Ant. Switch module FL104 W2100 Duplex

U500 Front End module U103 WCDMA PAM

U101 GSM PAM X100 VCTCXO

FL101 GSM SAW BT module

U100 RTR6275

U101

FL101

SW100

U500

U100

FL104

U103

X100

3. TECHNICAL BRIEF

- 71 -

Logic / Audio

Reference Description Reference Description

BAT300 Backup Battery CN401 MMI connector (18pin)

U303 1.3M Cam. LDO CN403 1.3M Cam. Connector

U402 Audio AMP

BAT300

U303

CN403

CN401

U402

3. TECHNICAL BRIEF

- 72 -

Logic

Reference Description Reference Description

U201 MSM6245_A U300 PMIC

U301 Memory MCP J300 U-SIM socket

CN400 Main To LCD Connector S300 T-FLASH socket

U300

CN400

U201

U301

J300

S300

4. TROUBLE SHOOTING

- 73 -

4.1 RF Component

4. TROUBLE SHOOTING

LGMC

4. TROUBLE SHOOTING

- 74 -

Block

Diagram

Block

Ref. Name

UMTS

Part Name Function Comment

4. TROUBLE SHOOTING

- 75 -

4.2 SIGNAL PATH_UMTS RF

Common Tx/Rx

UMTX 2100 Tx/Rx

UMTX 2100 Tx

UMTX 2100 Rx

Tx I/Q

LO

RX I/Q

4.3 SIGNAL PATH_GSM RF

4. TROUBLE SHOOTING

- 76 -

Common Tx/Rx

GSM900 Tx

DCS/PCS Tx

EGSM900 RX

PCS Rx

DCS RX

Tx I/Q

LO

RX I/Q

4. TROUBLE SHOOTING

- 77 -

4.4 Checking VC-TCXO Block

The reference frequency (19.2MHz) from X100 (VC-TCXO) is used in UMTS
TX part, GSM part and BB part.

TCXO

24

VCC

5

TC7SH04FU

U104

GND

3

100pC185

0.1u

C181

R124100ohm

1000p

C182

R128 100K

C183

0.01u

1000p

C186

DSA321SCE-19.2M

X100

GND

2

5

NC1

NC2

67

NC3
NC4

8

OUTPUT

3

4

VCC1VCONT

19.2MHz

0.01uC188C187 1000p

VREG_TCXO_2.85V

TRK_LO_ADJ

TCXO_BT

VREG_BT_2.85V

TCXO_PM

RTR6275_TCXO

TP2

TP1

TP3

TP4

Schematic of the VC-TCXO Block

Test Point of the VC-TCXO Block

TP1

TP4

TP3

TP2

4. TROUBLE SHOOTING

- 78 -

T

Check C312 of PMIC (U300)

Check R213 of MSM (U201)

4. TROUBLE SHOOTING

- 79 -

4.5 Checking Front-End Module Block

Rev.D

Rev.B

Rev.C

R1011K

R1001K

L108

15nH

C117

10p

C110

33p

21

14

GSM18001900_TX

GSM1800_RX1

1

GSM1800_RX2

2

GSM1900_RX1

3
4

GSM1900_RX2

GSM900_RX1

5
6

GSM900_RX2

16

GSM900_TX

VDD

19

WCDMA2100

9

ANT

11

CTRL1

18

CTRL2

22

7

GND1

GND10

23

GND2

8

GND3

10

GND4

12

GND5

13
15

GND6

17

GND7
GND8

20

GND9

U500

D5011

33p

C109

VREG_RF_SMPS

ANT_SEL1

ANT_SEL0

ANT_SEL0

ANT_SEL1

TP1

Schematic of the Front-End Module Block

Test Point of the Front-End Module Block

TP1

4. TROUBLE SHOOTING

- 80 -

Logic Table of the FEM

GSM 1800 / GSM1900 RX

GSM 900 RX

GSM 900 TX / WCDMA

GSM 1800 / GSM 1900 TX

TP1 VREG RF SMPS

4. TROUBLE SHOOTING

- 81 -

4.6 Checking UMTS Block

4.6.1 Checking Tx level

1

For testing, Max power of UMT 2100 is needed.

TP1

TP2

TP3

TP4

TP1

TP2

WCDMA

Rev.D

L404

1.8nH

0.5p

L125

FL104

41

PGND

RX

2

3

TX

ANT

ACMD-7602

ANT101

C437

C162

3.3p

1p

ANT102

OUT

20dB

50OHM

4

R11951

C450

22p

L101

NA

2IN1

COUP

U102

3

CP0402A1950DNTR

R120

R121

47

130

7dB

TP3

TP4

L102
100nH

C159
15p

C192
100p

C101

56p

U500

+VPWR

TR100

KRX102U

45

PA_R0

2

31

11

C154

L122
NA

PA_ON

VREG_TCXO_2.85V

C170

0.1u

Rev_1.0

1.5p

FL102

EFCH1950TDF

5

4

G3

O1

1

C157

IN

G13G2

10nH

2

Rev.B

SW100

G2

ANT

RF

G1

C102
NA

KMS-507

Rev.D

+VPWR

PWR_DET

R122

130

C155

C158

4.7u
15p

WS2512_TR1G U103

10

L123

1nH

C164

0.5p

Rev_1.0

C165
1p

9

8

7
6

11

GND4 RFIN

RFOUT

GND1

VCONT

GND3
GND2
BGND

1

VCC1VCC2

2

3

4

5

VREF

4. TROUBLE SHOOTING

- 82 -

4. TROUBLE SHOOTING

- 83 -

4.6.2 Checking UMTS PAM Control Block

• PAM control signal

1. PWR_DET : UMTS Tx Power Detected value (Check R120)

2. TX_AGC_ADJ : UMTS RTR6275 Tx Amp Gain Control

3. VREG_TCXO_2.85V : UMTS PAM enable (C170) (about 2.85V)

4. +VPWR : UMTS PAM Main Voltage ( 3V < +VPWR < 4.2V)

5. PA_ON : Turns the PA on and off

6. PA_R0 : Control signals that step the active PA mode and bias

VREG_TCXO_2.85

+VPWR

PWR_DET

4. TROUBLE SHOOTING

- 84 -

4.6.3 Checking RF Rx Level

TP1

TP2

TP3

Vbias

TP4

TP1

TP2

TP4

Rev.D

L404

1.8nH

0.5p
L125

WCDMA

FL104

41

RX

PGND

2

3

TX

ANT
ACMD-7602

Vbias

ANT101

ANT102

C450

22p

1p

C437

C162

3.3p

2IN1

OUT

20dB

50OHM

COUP

U102

4

3

CP0402A1950DNTR

R11951

PWR_DET

R120

R121

R122

47

130

130

7dB

+VPWR

L101

NA

C158

C155

4.7u

15p

L123

Rev_1.0

1nH

C165

C164

1p

0.5p

WS2512_TR1G U103

10

9

GND4 RFIN

8

RFOUT

7

VCONT

GND3

6

GND2

11

BGND

C102
NA

VCC1VCC2

GND1

VREF

1

2

3

4

5

C159
15p

C192
100p

TP3

G2

ANT

G1

+VPWR

TR100

KRX102U

45

SW100

RF

KMS-507

PA_R0

2

31

L122
NA

C170

0.1u

Rev_1.0

C154

1.5p

C157
10nH

PA_ON

VREG_TCXO_2.85V

FL102

EFCH1950TDF1

5

4

G3

O1

1

IN

G13G2

2

Rev.B

L128

1.8nH

L102
100nH

L407

2.7nH

C101

56p

U500

VDD_RX

C174
10p

Rev.D

C156

L121

100p

1nH

Rev.D

C161

2.2p

5

G2

1

IN

G1

2

L408
10nH

Rev.D

C444

L409

2.2p

4.7nH

4

L411

O2

FL103
EFCH2140TDE1

4.7nH

O1

3

C445

L410

2.2p

4.7nH

4. TROUBLE SHOOTING

- 85 -

4. TROUBLE SHOOTING

- 86 -

4.7 Checking GSM Block

1

32

4. TROUBLE SHOOTING

- 87 -

4.7.1 Checking RF Tx level

4.7.2 Schematic of RF Tx level

0

TP1

TP2

TP3

TP1

TP3

TP2

C101

56p

L102
100nH

U500

19

VDD

7

GND1

8

GND2

10

GND3

12

GND4

13

GND5

15

GND6

17

GND7

20

GND8

21

GND9

23

GND10

C102
NA

L108

15nH

SW100

G2

ANT

RF

G1

KMS-507

Rev.D

C117

10p

ANT

D5011

GSM18001900_TX

11

GSM900_RX1

GSM900_RX2
GSM1800_RX1
GSM1800_RX2
GSM1900_RX1
GSM1900_RX2

WCDMA2100

CTRL1
CTRL2

GSM900_TX

Rev.C

5
6
1
2
3
4
9

33p

100ohm

C139C137
68p

16

R1001K

ANT_SEL

R1011K

ANT_SEL1

C123

0.01u

GSM_PA_RAMP

R107

C134

0.01u

20

17

6

VAPC

VBATT

VCC1A

VCC1B

DCS_PCS_IN

EGSM_IN

U101

SKY77318

GND39GND410GND5

GND612GND713GND814GND9

8

C121
33u

2

ENABLE

GND15GND2

7

315

4

18

1

BS

18
22

16
14

C124
100p

L115

18nH

C441

5.6p

NA

L403

1.5nH

C438

100p

C138
NA

L116

10nH

C110

33p

Rev.D

DCS_PCS_OUT

11

EGSM_OUT

19

RSVD_GND

21

P_GND

C109

4.7.3 Checking RF Tx level

4. TROUBLE SHOOTING

- 88 -

4. TROUBLE SHOOTING

- 89 -

4.7.4 Checking PAM Block

TP1. GSM_PA_RAMP : Power Amp Gain Control. typically, 0.2V < Vramp < 1.6V
TP2. GSM_PA_EN : Power Amp Enable

(Power ON : higher than 1.25V , Power OFF : lower than 0.4V)

TP3. GSM_PA_BAND : Power Amp Band Selection Control

(GSM Mode : -0.2V < VBS < 0.4V , DCS/PCS Mode : 1.25V < VBS < 3.0V)

TP4. +VPWR : PAM Supply Voltage Vcc higher than 3.0V

Schematic of GSM PAM Block

TP1

TP2

TP3

TP4

Rev.D

EGSM

C136

0.01u

10nH

L116

100p

C438

L403

100ohm

100ohmR113

R117

100ohm

R107

C153
15p

EFC

FL1

C123

0.01u

68p

C139

C134

0.01u

GND39GND410GND5

GND612GND7

13

GND814GND9

16

21

P_GND

19

RSVD_GND

VAPC

20

17

VBATT

2

VCC1A

6

VCC1B

BS

1

DCS_PCS_IN

315

DCS_PCS_OUT

EGSM_IN

4

EGSM_OUT

11

ENABLE

18

GND15GND2

7

8

SKY77318

U101

C149
15p

C121
33u

C138
NA

+VPWR

GSM_PA_BAND

GSM_PA_EN

GSM_PA_RAMP

TP2

TP4

TP3

TP1

4.7.5 Checking RF Rx Block

Schematic of GSM900/DCS/PCS Rx Block

4. TROUBLE SHOOTING

- 90 -

TP1

TP2

TP3

TP1

TP2

TP3

TP1. DCS RX INPUT

TP2. PCS RX INPUT

TP3. GSM RX INPUT

L102
100nH

Rev.C

U500

19

VDD

7

GND1

8

GND2

10

GND3

12

GND4

13

GND5

15

GND6

17

GND7

20

GND8

21

GND9

23

GND10

11

ANT

D5011

GSM18001900_TX

GSM900_RX1

GSM900_RX2
GSM1800_RX1
GSM1800_RX2
GSM1900_RX1
GSM1900_RX2

WCDMA2100

CTRL1
CTRL2

GSM900_TX

Rev.C

5
6
1
2
3
4
9

18
22

16
14

C124

L403

100p

L115
18nH

1.5nH
L116

10nH

C109

33p

33p

Rev.D

GSM_PA_RAMP

R1001K
R1011K

C123

0.01u

ANT_SEL0
ANT_SEL1

C121
33u

+VPWR

DCS

PCS

EGSM

C105
NA

C440

C116
NA

C120

NA

L406 2.7nH

5pC439

5p

C442 5.6p

5.6pC443C110

2.7nHL405

L111

5.6nH

C190

0.5p

C191

NA

4. TROUBLE SHOOTING

- 91 -

4.8 Checking Bluetooth Block

Test Point of the Bluetooth Block

Test Point of the Bluetooth Block

Schematic of the Bluetooth Block

4. TROUBLE SHOOTING

- 92 -

TP4

TP1

TP3

TP2

TP2

TP1. VREG_BT_2.85V

TP1

VREG_MSMP_2.7V

VREG_BT_2.85V

BT_CLK

TP3

R123

0

TP2. VREG_MSMP_2.7V

TP3. TCXO_BT

TP4. BT ANT Output

TP4

BLUETOOTH

L126

NA

M100

C173 2.2u

C179 100p

C177 0.1uF

LBRQ-2B43A

1000pC171

9

CLK_REF

1uC172

3

VCC_OUT

2

VDD_INT

10

VDD_MSM

14

VDD_BAT

100pC178

C180 2.2u

PGND4

ANT

SYNC_DET_TX_EN

RX_BB_TX_BB

PGND1

PGND2

PGND3

17

18

19

20

16

GND4

SBST
SBCK
SBDT

XTAL_IN

GND2

GND3

8

15

GND1

6

4
11
12

5

13

7

1

R118

0

1000p C176

ACS2450HBAXX

FEED

ANT103

NA

C169

NC1
NC2

BT_SBST
BT_SBCK
BT_SBDT

BT_TX_RX_N

BT_DATA

TCXO_BT

4. TROUBLE SHOOTING

- 93 -

Start

TP1,TP2

YES

YES

YES

Signals exits?

TP3

Is clock ok? 19.2M

TP4

Signals exits?

Change the Main board

NO

Change the Main board

NO

Change the X100

NO

Change the M100

4.9 Power ON Troubleshooting

Power On sequence of U250/KU250 is :

PWR key press → PM_ON_SW_N go to low, PM6650 KPDPWR_N (pin24) → PM6650 Power Up →

VREG_MSMC_1.2V, VREG_MSME_1.8V, VREG_MSMP_2.7V, VREG_MSMA_2.6V,

VREG_TCXO_2.85V power up and system reset assert to MSM6245 → Phone booting and

PS_HOLD assert to PMIC

4. TROUBLE SHOOTING

- 94 -

Start

Battery voltage. higher

than 3.20V?

YES

Key press?

YES

VREG_MSMC_1.2V,VREG_MSMP_2.7V,
VREG_MSME_1.8V, VREG_TCXO_2.85V,
VREG_MSMA_2.6V power up?

YES

Is clock ok?
R306 : 19.2M
X300 : 32.768Khz

YES

NO

NO

Change or charging the

Battery

Check the Key Dome

NO

Change the Main board

NO

Check the TXCO

Change the Main board

4. TROUBLE SHOOTING

- 95 -

VREG_MSMC

[U250/KU250 Main PCB BOTTOM]

VREG_MSME

VREG_MSMP

VREG_MSMA

X300 : 32.768Khz

R306 : 19.2Mhz

4. TROUBLE SHOOTING

- 96 -

4.10 Charger Troubleshooting

Charging Procedure

- Connect TA or USB Cable

- Control the charging current by PM6650 IC

- Charging current flows into the battery

Troubleshooting Setup

- Connect TA and battery to the phone

Check Point

- Connection of TA or USB Cable

- Charging current path

- Battery

Troubleshooting Procedure

- Check the charger (TA or USB Cable) connector

- Check the charging current Path

- Check the battery

CHARGER

Differential lines, route as equal length as possible !! --> ICHARGE , ICHARGEOUT

G

S

SI3493DV-E3

D1 D2 D3 D4

Q301

Q302

QST4

3

B

1

C1 C2

2

564

0.1

R313

2

C2

564

QST4

B

3C1

1

Q300

USB_VBUS

ICHARGEOUT

VBATT

BATT_FET_N

+VPWR

ICHARGE

CHG_CTL_N

+5V_PWR

USB_CTL_N

4. TROUBLE SHOOTING

- 97 -

[ Charger Troubleshooting Flow ]

Start

Check the pin and battery
Connect terminals of I/O
connector

Connection OK?

NO

Change I/O connector

Yes

Is the TA (or USB Cable)

voltage 5.1V (or 5.0V)?

Yes

Is it charging properly

After turning on Q301(or Q302)

, Q302?

NO

Change the board

NO

Change TA

(or USB Cable)

Yes

END

4. TROUBLE SHOOTING

- 98 -

[ Charging part ( Main PCB Front ) ]

Q302

Q300

R313

Q301

4. TROUBLE SHOOTING

- 99 -

4. BB Trouble Shooting

4.11 USB Troubleshooting

USB Initial sequence of U250/KU250 is :
USB connected to U250/KU250 power on → USB_VBUS(Q300) go to 5V → USB_D+ go to 3.3V →
USB_DAT is triggered → USB work.

Start

Q400 pin 4 is 5V?

USB_D+ is 3.3V?

Change the Main board

Check Q300 (pin 4)

Check VA401

NO

YES

YES

NO

Cable is inserted?

YES

Insert cable

NO

Power is on?

YES

Go to power on trouble shooting

NO

4. TROUBLE SHOOTING

- 100 -

4.12 SIM Detect Troubleshooting

USIM Initial sequence of U250/KU250 is :
USIM_CLK,USIM_RST,USIM_DATA triggered → VREG_UIM_2.85V go to 2.8V → USIM IF work

Start

Work well?

VREG_UIM_2.85V is 2.85V?

USIM_P_CLK is run?

Change the Main board

End

Check J300

Yes

No

YES

NO

Re-insert the SIM card

Change SIM card

Work well?

End

Yes

No

4. TROUBLE SHOOTING

- 101 -

Figure. USIM part schematics

USIM

7

3

6

2

R317

10

J300

5

GND1

6

VPP

7

IO

8

RSV2

9

GND2
GND3 GND4

5

1

15K

HSSC-8P-18

VCC
RST
CLK

RSV1

GND5

VREG_USIM_2.85V

1

USIM_P_RST_N

2

3

USIM_P_CLK

USIM_P_DATA

7

1
2
3
4
11
12

VREG_USIM_2.85V
USIM_P_RST_N
USIM_P_CLKUSIM_P_DATA

EVLC18S02003

VA300

L302
56nH

C352

33p

smd_1005h_5_r

C3530.1u

smd_1005h_5_r

VA301

EVL14K02200

VA302

EVLC18S02003