LG ME240 Service Manual
Service Manual
Model : LG240_ME240
Service Manual
LG240_ME240
Date: September, 2006 / Issue 1.0
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1. Introduction ..................................... 5
1.1 Purpose................................................... 5
1.2 Regulatory Information............................ 5
2. Performance .................................... 7
2.1 HW Feature............................................. 7
2.2 Technical Specification ........................... 9
3. Circuit Description........................ 14
3.1 General Description .............................. 14
3.2 RF Part.................................................. 14
3.3 Digital Baseband................................... 20
3.4 Analog Baseband.................................. 26
3.5 Bluetooth Interface................................ 34
4. TROUBLE SHOOTING .................. 37
4.1 RF Part Technical Brief......................... 37
4.2 RF Part Trouble shooting...................... 43
4.3 Bluetooth Trouble Shooting .................. 51
4.4 Baseband Part Troubleshooting ........... 55
4.5 LCD Display Trouble............................. 61
4.6 Camera Trouble Shooting..................... 65
4.7 MOD Key Trouble Shooting .................. 67
4.8 SIM Detect Trouble Shooting................ 71
4.9 Folder On/Off and Trouble Shooting..... 73
4.10 Speaker Trouble Shooting .................. 75
4.11 Receiver Trouble Shooting ................. 78
4.12 MIC Trouble Shooting ......................... 79
4.13 Transflash Trouble Shooting............... 81
4.14 Keypad Backlight LED Trouble
Shooting.............................................. 83
4.15 Vibrator Trouble Shooting................... 85
4.16 Ear-Mic Jack Detection
Trouble Shooting..................................86
4.17 Ear-Mic Hook Detection
Trouble Shooting..................................87
4.18 Ear-Mic Headset MIC
Trouble Shooting..................................88
4.19 Ear-Mic Headset HSOR/HSOL
Trouble Shooting..................................89
5. Downloading Software ................. 91
5.1 The purpose of downloading software.. 91
5.2 The Environment of Downloading
Software................................................ 91
5.3 Download Procedure .............................93
6. BLOCK DIAGRAM ......................... 97
7. CIRCUIT DIAGRAM ....................... 99
8. PCB LAYOUT............................... 106
9. RF Calibration
...................................
109
9.1 RF Calibration Equipment Setup
.......
109
9.2 RF Calibration Procedure
..................
109
12. EXPLODED VIEW &
REPLACEMENT PART LIST ..... 113
12.1 EXPLODED VIEW ............................ 113
12.2 Replacement Parts
<Mechanic component>.................... 115
<Main component> ........................... 118
12.3 Accessory ......................................... 132
Table of Contents
1. Introduction
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1.1. Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2. Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
1. Introduction
1. Introduction
- 6 -
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
2. PERFORMANCE
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2.1 HW Feature
2. Performance
Item Feature Comment
Form Factor Clamshell with External Display
1) Capacity
Battery Standard : Li-Ion, 900mAh (LGC)
2) Packing Type : Soft Pack
Size
Standard :
89.0 X 47.0 X 22 mm
Weight 90g With Battery
Volume 75cc
PCB Staggered 8 Layers , 0.8t
Stand by time 250 hrs @Paging Period 9
Charging time 3 hrs @ Power Off / 900mAh
Talk time Min : 2.5 hrs @ Power Level 5 @ GSM850 / 900mAh
GSM 850 : -105 dBm
RX sensitivity
EGSM : -105 dBm
DCS 1800 : -105 dBm
PCS 1900 : -105 dBm
GSM/ GSM 850 : 33 dBm Class4 (GSM850)
GPRS EGSM : 33 dBm Class4 (EGSM)
DCS 1800 : 30 dBm Class1 (PCS)
TX output power
PCS 1900 : 30 dBm Class1 (DCS)
EDGE GSM 850 : 27 dBm E2 (GSM850)
EGSM : 27 dBm E2 (EGSM)
DCS 1800 : 26 dBm E2 (PCS)
PCS 1900 : 26 dBm E2 (DCS)
GPRS compatibility GPRS Class 10
EDGE compatibility EDGE Class 10
SIM card type
Plug-In SIM
3V /1.8V
Main LCD
256K Color TFT (128 X160)
Display Backlight : White LED
Sub LCD
65K CSTN (96X64)
2. PERFORMANCE
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Item Feature Comment
Status Indicator Indicator LED in MOD KEY
Alphanumeric Key : 12 Function Key:
Function Key : 12 4 Key Navigation, OK,
Mod Key : 3 F1, F2, Camera, CLR,
Keypad Side Key : 3 SND, END/PWR, MP3
Total No of Keys :30 Player
Mod Key :
RW, Play/Pause, FW
ANT
Main : External Fixed Type
Blue tooth : Intenna
System connector 24 Pin
Ear Phone Jack 4 Pole (2.5mm), Stereo
PC synchronization Yes
Memory
Flash : 512Mbit
SDRAM : 256Mbit
Speech coding FR, EFR, HR,AMR
Data & Fax Built in Data & Fax support
Vibrator Built in Vibrator
Blue Tooth
V2.0(Except EDR support)
A2DP, HFP, BPP support
MIDI (for Buzzer Function) SW Decoded 64Poly
Music Player MP3/ AAC/AAC+ With Graphic EQ
Camcorder MPEG4+AMR
Voice Recording Yes
Speaker Phone mode
Yes
Support
Travel Adapter Yes
CDROM Yes
Stereo Headset Yes Optional
Data Cable Yes Optional
T-Flash (External Memory)
Yes Optional
2. PERFORMANCE
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2.2 Technical Specification
Item Description Specification
GSM850
TX: 824 + n ¢• 0.2 MHz (n=1 ~ 124)
RX: TX + 45 MHz
GSM900
TX: 890 + n ¢• 0.2 MHz (n=1 ~ 124)
890 + (n-1024) ¢• 0.2 MHz (n=975 ~ 1023)
RX: TX + 45 MHz
1Frequency Band
DCS1800
TX: 1710 + ( n-511 ) ¢• 0.2 MHz (n = 512 ~ 885)
RX: TX + 95 MHz
PCS1900
TX: 1850 + ( n-511 ) ¢• 0.2 MHz
RX: 1930 + ( n-511 ) ¢• 0.2 MHz (n = 512 ~ 810)
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1ppm
GSM850/GSM900
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS1800/PCS1900
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
2. PERFORMANCE
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Item Description Specification
GSM850/GSM900
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
5
Output RF Spectrum 6,000 -71
(due to modulation) DCS1800/PCS1900
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65
6,000 -73
GSM850/GSM900
Offset from Carrier (kHz) Max. (dBm)
Output RF Spectrum 400 -19
6
(due to switching transient) 600 -21
1,200 -21
1,800 -24
2. PERFORMANCE
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Item Description Specification
DCS1800/PCS1900
Offset from Carrier (kHz). Max. (dBm)
Output RF Spectrum 400 -22
6
(due to switching transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
8 Bit Error Ratio BER (Class II) < 2.439% @-102dBm
9 Rx Level Report accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500
*
-5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
*
Mean that Adopt a straight line in between 300 Hz and
1,000 Hz to be Max. level in the range.
2. PERFORMANCE
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Item Description Specification
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
18
<Change> System frequency
2.5ppm
(13 MHz) tolerance
19 <Change>32.768KHz tolerance 30ppm
GSM850/Lvl 7 (Battery Capacity 900mA) : 180 min
20 Talk Time
GSM850/Lvl 12 (Battery Capacity 900mA) : 240 min
Under conditions, at least 200 hours:
1. Brand new and full 900mAh battery
2. Full charge, no receive/send and keep GSM in idle mode.
21 Standby Time
3. Broadcast set off.
4. Signal strength display set at 3 level above.
5. Backlight of phone set off.
At least 55 dB under below conditions:
22 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 100 cm
23 Charge Voltage
Fast Charge : < 550 mA
Slow Charge: < 100 mA
Antenna Bar Number Power
5 -85 dBm ~
4 -90 dBm ~ -86 dBm
24 Antenna Display 3 -95 dBm ~ -91 dBm
2 -100 dBm ~ -96 dBm
1 -105 dBm ~ -101 dBm
0~ -105 dBm
2. PERFORMANCE
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Item Description Specification
Antenna Bar Number Power
0 3.62V 0.03V
25 Battery Indicator 1 3.70V 0.03V
2 3.78V 0.03V
3 3.91V 0.03V
4 3.92V 0.03V↑
26 Low Voltage Warning
3.62V↓ 0.03V (Call)
3.50V↓ 0.03V (Standby)
27 Forced shut down Voltage 3.35 0.03 V
1 Li-ion Battery
28 Battery Type
Standard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 900mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60Hz
Out put: 4.8V, 900mA
3. Circuit Description
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3.1 General Description
The RF part consists of a transmitter, a receiver, a synthesizer, a voltage supply and a VC-TCXO part.
The main RF Chipset MMM6000 is a transceiver for the GSM, GPRS, and EDGE standards, providing
antenna-todigital- bits functionality. The transceiver functions over the GSM850, EGSM900, DCS1800,
and PCS1900 transmit and receive frequency bands. The MMM6000 transceiver includes a VLIF/DCR
receive architecture and a polar modulation transmit architecture with direct modulation of the VCO by
a fractional-N synthesizer. Both the RX and TX VCOs are fully integrated. The polar architecture
allows for a filter-free transmit lineup. An on-chip transmit/receiver sequencer generates appropriate
timing events for the transmitter calibration and the EDGE / GMSK transmit/receive burst, therefore,
limiting the RF hardware dependency of the L1 engine software to an absolute minimum. The DigRF
standard defines the digital interface between the MMM6000 and the base band processor IC,
allowing maximum industry compatibility.
3.2 RF Part
3.2.1 Receiver Part
The Receiver part in MMM6000 contains all active circuits completely, full receiver chain with the
exception of discrete front-end RF SAW filters. The filtered and amplified signal is down converted in
the RF-mixer to the ba se-band output. The receive path is supported by internal channel filtering.
3. Circuit Description
<Fig.1> Receiver Part Block Diagram
3. Circuit Description
- 15 -
3.2.1.1 Front End Part
The RF front end consists of Antenna Switch, quad saw filters and LNAs integrated in transceiver .
Antenna switch is integrated in MMM6027 (Raptor) and quad saw filters are integrated in saw filter
bank. The Received RF signals (GSM850,900, PCS, DCS) are fed into the antenna and Mobile
switch. An antenna matching circuit is between the antenna and the mobile switch. The Antenna
Switch in Raptor is used to control the Rx and Tx paths. And, the input signals TX_ANT_SW_EN,
LB_HB and US_EURO of Raptor are connected to transceiver controller to switch either Tx or Rx
path on. Antenna Switch supports for quad band.
The FEM control logics given below Table 1
The receiver part uses a very low-IF (VLIF) conversion architecture that allows for the on-chip
integration of the DC offset compensation system, eliminating DC offset from the demodulated signal.
The MMM6000 integrates quad differential input LNAs that are matched to the 200 ohm with
balanced-output SAW filter bank through LC matching networks in SAW filter bank.
3.2.1.2 Demodulator and base-band processing
The RX architecture is digital VLIF/DCR. There are four separate LNAs providing functionality for
GSM850, EGSM900, DCS1800 and PCS1900 frequency bands. The LNAs are differential and
provide 30 dB of dynamic range as digital steps, eliminating the need for RX AGC gain. The
quadrature down mixer converts the RF signal to base band. Passive differential and common mode
filtering at the mixer output limits out of band signals in the active stages of the base band section
and results in an IP2 of 55 dBm (including processor gain). The I and Q analog base band signals are
passed through low pass anti-aliasing filters and dc offset correction circuits before being processed
by the analog-to-digital converters.
Switch Mode TX_ANT_SW_EN LB_HB US_EURO
GSM850 Rx Low Low Low
EGSM Rx Low Low High
DCS Rx Low High High
PCS Rx Low High Low
GSM850 Tx High Low Low
EGSM Tx High Low High
DCS Tx High High High
PCS Tx High High Low
<Table 1> Control Logics
3. Circuit Description
- 16 -
3.2.2 Synthesizer Part
Both the RX and TX VCO run at 3296 to 3820 MHz and have integrated resonators with 32 states of
digital course tuning. The frequency synthesizer is a 24-bit, 3rd order fractional N synthesizer with
digital AFC and a lock time of less than 80µs. A 26 MHz TCXO provides a stable frequency
reference. The VCO output signal runs through a divide-by-two for operation in the DCS/PCS bands
and a divide-by-four for operation in the 850GSM and EGSM bands. Operation at 2 or 4 times the LO
frequency provides good immunity to remodulation. VCO feedback to the “divide-by-N” is through a
fixed divide-by-3. The output of the divide-by-N is compared to a 26 MHz reference in the phase
comparator and error output is passed through the loop filter before being applied to the VCO.
The corrected clock module is a 22-bit digital phase-locked loop used to provide an accurate 26 MHz
reference, synchronized to the GSM system, when the system is operated from an uncorrected
TCXO. The 26 MHz reference TCXO provides a stable frequency reference for the major functions in
the radio system. The TCXO output can also be routed to two auxiliary reference pins to provide a
reference clock for RF accessories such as Bluetooth, GPS, and WLAN.
3.2.3 Transmitter Part
The Transmitter part contains polar modulator part of RF main chipset [MMM6000] and Power
Amplifier Module [MMM6027]
3.2.3.1 Polar Modulator Part
The TX architecture is a polar modulator with direct digital modulation of the VCO. The module can
transmit in GMSK (phase modulation) or 8PSK (phase and amplitude modulation) mode. In GMSK
mode, the dual port TX VCO is phase modulated by the dual port synthesizer and the signal is fed to
the PA input at a fixed level. In 8PSK mode, the additional amplitude modulation is performed via a
commuting switch mixer. The mixer core drives a resistive digital step attenuator, which provides 0 to
45 dB of dynamic range in 3 dB steps, allowing the required full dynamic range to cover all EDGE
power steps with only 20 dB of dynamic range from the modulator. Two DACs provide signals to the
modulator. One DAC is dedicated to the amplitude component of the 8PSK wave form and the other
to driving the VCO high port input.
3. Circuit Description
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3.2.3.2 Power Amplifier Part
The Power Amplifier Module [MMM6027] is a quad-band Class 10 GSM, GPRS, EDGE Power
Amplifier Front End Module (FEM) functioning over the GSM850, EGSM900, DCS1800, and
PCS1900 transmit and receive frequency bands.
To simplify radio front-end design, power amplification, power coupling, power detection, low-pass
filtering output power control, and antenna switching functions are integrated into the Power Amplifier
FEM.
The Power Amplifier Module [MMM6027] is specified to operate with both GMSK and 8PSK
modulation schemes and is intended to be used in combination with the transceiver [MMM6000]. Two
modes of power control are supported with the MMM6027: bias control for GMSK modulation and
input power control for 8PSK modulation.
DigRF
<Fig.2> MMM6000 & MMM6027 Block Diagram
<Fig.3> Schematic of PAM circuit
MM M6000
Quad-Band
GSM/GPRS/EDGE
TRA NSCEIVER
Digital Radio
Receiver
RF
Synthesizer
Transmit
Modulator
PA Control
(PAC)
LPF
LO-PORT
TX VCO
LPF
PHASE MODULATION
RX VCO
HI
PORT
LPF
AMP LITUD E MODULATION
˜4
90
°
˜2
90
°
˜2
˜2
SAW
Filter
Module
PA Bias Control
Power Detection
Power Control
Switch Control
Power Amplification
Power Detection & Conrol
Antenna Switching
Couplers
+
Harmonic
Filters
Anten na
Switch
3. Circuit Description
- 18 -
3.2.4 Digital Core
The digital core of the MMM6000 consists of four major functional blocks:
• Receive coprocessor (RxCPROC)
• DigRF
• Transmit module (TXM)
• Transmit/receiver timing sequencer (TRXQ)
3.2.4.1 Receive coprocessor (RxCPROC)
The digital portion of the RX signal processing chain, consisting of decimation filters, a digital LO
generator, complex mixers, adjustable channel filters, and a DC adapt module. The initial conversion
is done by the sigma-delta modulator and the results are passed into the RxCPROC. Processed
signals are sent serially to the baseband IC through the DigRF interface port.
<Fig.4> Block Diagram of Rx coprocessor
3. Circuit Description
- 19 -
3.2.4.2 DigRF
Interface to the baseband IC using the DigRF standard. The DigRF standard specifies the logical,
electrical, and timing details of the RF/Baseband interface. Figure 5 shows the DigRF standard RFbaseband interface.
3.2.4.3 Transmit Module (TXM)
The EDGE/GMSK digital transmit module (TXM) contains two modulation schemes (GMSK and
8PSK) and supports amplitude/phase (polar pair), or amplitude/frequency modulation.
3.2.4.4 Transmit/Receiver Timing Sequencer (TRXQ)
This module generates appropriate timing events for the transmitter calibration and the EDGE/GMSK
transmit/receive burst, therefore, limiting the RF hardware dependency of the L1 engine software to
the absolute minimum.
3.2.5 26MHz Clock
The 26MHz clock consists of a TCXO, which oscillates at a frequency of 26 MHz. It is used within the
RF Main Chip [MMM6000], ABB [Triton], DBB [Neptune] and B/T [BRF6150].
3.2.6 Power Supplies [LDO]
The external LDOs are used to provide DC power to TCXO, RF Main Chip [MMM6000] and PAM
[MMM6027]
<Fig.5> DigRF Standard RF-BaseBand Interface
Baseband
IC
RF IC
RxTxData
RxTxEn
CtrlData
CtrlEn
CtrlClk
Strobe
SysClk
SysClkEn
3. Circuit Description
- 20 -
3.3 Digital Baseband
3.3.1 General description
The OMAPV1030 E-GPRS multimedia device belongs to the Texas Instruments OMAP-Vox_
processors family. It combines both a modem engine and an application engine. Memory and CPU
resources are shared between modem and application processing.
The OMAPV1030 chip is based on the OMAP3.4 architecture and integrates two processor
subsystems:
- An MPU subsystem based on an ARM926EJ-S
- A DSP subsystem based on a UMA 2.6 architecture integrating a C55x DSP core
The OMAPV1030’s silicon process technology is a c027.0 90-nm digital CMOS.
<Fig.6> OMAPV1030 Block Diagram
SDRAM
Flash and
SRAM
OMAPV1030 EDGE multimedia platform
Test:
E2TLM, BCM, SCM,DielD
JTAG, FuseFarm
LCD
controller
MPU private peripherals
Timers (x3)
WD timers
System DMA handler
MPU level 2 INTH
Secure watchdog
32k watchdog
OMAPV1030 config.
DES/3DES
SHA1/MDS5
AES
PKA
LCDCONV
RNG
MPU public peripherals
uWire
HDQ/1-Wire
MMC/SDIO1
Keyboard controller
Memory stick
OMAPV1030 OS timer
LPG (x2)
PWT
Enhanced LCD
Camera core
USB controller
Host
Device
OTG
OCP-I OCP-T2 OCP-T1 EMIFSEMIFF
MPU/DSP shared peripherals
ULPDR
CIPHER A5
TPU
TSP
GEA 1/2/3
USIM
MCSI (x2)
Traffic controller
MPU
subsystem
TIPB bridge (x2)
OCP static switchesTIPB static switches
GP timer (x2)
Serial radio IF
McBSP1
McBSP RF
MMC/SDIO2
Nand flash ctrl
UART (x3)
I C(x2)
Internal SRAM
SPI
2
System
DMA
controller
Dynamic switches
32k Sync timer
Frame counter
GPIO (x2)
Boot ROM
Secure eFuse
Secure RAM
Security layer
DSP MMU
MPUI
DSP
subsystem
Static switches
ULPDR
APLL
DSP private
peripherals
Timers (x3)
WD timer
DSP DMA handler
DSP interrupt
handler
3. Circuit Description
- 21 -
3.3.2 Block Description
The OMAPV1030 E-GPRS multimedia device is based on an OMAP3.4 platform that integrates:
- The MPU subsystem
- The DSP subsystem
- A system DMA
- A traffic controller providing:
- External memory interfaces with:
- A slow interface (EMIFS) to ROM, SRAM, FLASH memories
- A fast interface (EMIFF) to SDRAM memories
- Layer 3 (L3) interconnect made of two OCP target ports (OCP-T1 and OCP-T2) and one OCP
initiator port (OCP-I)
- Layer 4 (L4) interconnect made of two DSP peripheral busses (private DSP TIPB and shared DSP
TIPB) and two MPU peripheral busses (public MPU TIPB and private MPU TIPB)
- Clock management
- A set of processor peripherals:
- Three 32-bit timers, a 16-bit Watchdog timer, and an interrupt handler for the MPU
- Three 32-bit timers, a 16-bit Watchdog timer, and a 2nd-level interrupt handler for the DSP
- Test and debug interfaces (JTAG, Window Tracer)
- Trace capabilities: ETM9 and Ctools
The other OMAPV1030 modules or subsystems are connected to the OMAP3.4 platform through the
L3 and L4 interconnects.
<Fig.7> OMAPV1030 Top-Level Architecture Overview
OMAPV1030
device
OMAP3.4 platform
L3interconnect
MPU
subsystem
System DMA
DSP
subsystem
Peripheral
subsystem
Internal memory
subsystem
Secure RAM
boot ROM
eFUSE
Memory
interfaces
USB interface
System
components
L4interconnect
Test interfaces
Debug interfaces
Voltage regulator
Clock generator
Audio interfaces
Video interfaces
Bluetooth
Serial interfaces
External
memories
External
device
External interface
3. Circuit Description
- 22 -
The OMAP3.4 platform is the computing core of the device. The other OMAPV1030 components are
organized as follows:
- The internal memory subsystem is made of a single-port 256K-bit shared internal SRAM.
- The security subsystem is a set of several components, including dedicated a secure mode to run
secure applications.
- A master-slave USB module provides an external interface supporting high data transfer rates
between the OMAPV1030 and external application
- The memory interfaces provide access to external memories. There are two types of memory
controllers:
- SDRAM controller supporting SDR and DDR modes
- General-purpose controller supporting asynchronous and synchronous
- The system components are used to manage system interactions such as interrupts, clock control,
reset control, and idle management.
- The peripheral subsystem refers to all the peripherals accessible by the MPU and/or the DSP. They
are all OCP- or TIPB-compliant and are connected to the OMAP3.4 platform through the traffic
controller or the TIPB busses.
3.3.3 RF Interface (Digital RF Interface)
The OMAPV1030 radio interface module of OMAPV1030 device is an interface that carries the
following information:
- Transmit symbols from DBB to RF IC
- Receive samples from RF IC to DBB
- Bidirectional information control
- Real-time and activation signals from DBB to RF IC
- System clock
The OMAPV1030 radio interface module of OMAPV1030 device supports two types of radio
interfaces.
They differ mainly in the type of data interface:
- The first interface is based on a standard six-wire scheme: three wires for transmit and three for
receive.
- The second one is based on a two-wire bidirectional scheme: one wire for data in/out, and one for
control receive/transmit.
3. Circuit Description
- 23 -
This implementation is based on the following:
- The time processing unit (TPU) module is a real-time sequencer dedicated to monitoring GSM
baseband processing.
- The serial port of the time serial port (TSP) module controls both interfaces.
- The real-time TSPACT signal of the TSP module
- The McBSP digital RF module is used for the six-wire data interface.
- The serial radio interface module is used for the two-wire data interface.
- A system clock interface receives a squared 26-MHz clock from the RF IC.
3.3.4 SIM interface
SIM interface scheme is shown in below.
SIM_IO, SIM_CLK, SIM_RST, SIM_PWRCTRL ports are used to communicate DBB via ABB with
plugged sim card and the LDO (VRSIM) in ABB enables operate 1.8V to 2.5V to search SIM card
<Fig.8> OMAPV1030 Radio Interface
ULPDR
GSM_clock_13M
GSM_clock_26M
MPU public
CLKM1
TIPB
DSP
shared
TIPB
ARMPER_CK
OMAPV1030 Radio I/F
TPU
TPU BUS
TSP
McBSP
digital
RF
Serial
Radio
PODIGRFDO
IF
TSPCLK
TSPEN
TSPDO
TSPDI
TSPACT3
TSPACT4
TSPACT5
CLKR
DR
FSR
CLKX
DX
FSX
PIRXEN
POTXEN
PIDIGRFDI
PICLKM
I/O
CORE
MUX
OMAPV1030 device
digitalrf_rf_clk
digitalrf_rf_cs
digitalrf_rf_data
digitalrf_tx_start
digitalrf_enr
digitalrf_rxen
digitalrf_rx_clk
digitalrf_rx_data
digitalrf_rx_cs
digitalrf_tx_clk
digitalrf_tx_cs /
digitalrf_enable
digitalrf_tx_data /
digitalrf_data
digitalrf_sysclk
RF CTRL IF
RF real-
time IF
RF DATA IF
3.3.5 UART Interface
LG240 has Three UART Drivers as follow :
- UART1 : USB
- UART2 : ETM, Calibration
- UART3 : AT command, Fax_modem, Bluetooth
3.3.6 GPIO Map
In total 21 allowable resources, LG240 is using 17 resources except 4 resources dedicated to
Sysboot and Memory. LG2400 GPIO(General Purpose Input/Output) Map, describing application, I/O
state, and enable level, is shown in below table 3.
3. Circuit Description
- 24 -
UART1(USB)
Resource Name Description
USB_DP DP Data
USB_DM DM Data
USB_PWR POWER USB_POWER
VBUS VBUS USB_Detect
UART2 (ETM)
DEBUG_RX RX Receive Data(UART2)
DEBUG_TX TX Transmit Data(UART2)
UART3 (Bluetooth)
UART3_RXD UART3_RXD Receive Data
UART3_TXD UART3_TXD Transmit Data
UART3_RTS UART3_RTS Request To Send
UART3_CTS UART3_CTS Clear To Send
<Table.2> UART Interface Spec
3. Circuit Description
- 25 -
Note 1 : LCD Back Light Control
LCD B/L LCD_DIMCTRL1 LCD_DIMCTRL2
On High High
Dimming High Low
Off Low Don’t care
I/O # Net Name I/O
Resource Inactive Active
State State State
I/O (1) DPD1 O GPIO LOW LOW
I/O (2) I Sysboot HIGH LOW
I/O (3) DP_IO_ON O GPIO HIGH LOW
I/O (4) USB_BOOT_SEL I Sysboot LOW (Giant Plus) HIGH (Nanya)
I/O(5) FOLDER_2 I GPIO LOW HIGH
I/O (6) DPD0 I GPIO LOW LOW
I/O (7) LCD_BL_EN O GPIO LOW HIGH
I/O (8) BT_NRST O GPIO LOW (LCD B/L Of f ) HIGH (LCD B/L On)
I/O (9) KEY_LED_EN O GPIO LOW HIGH
I/O (10) E_MA0 O GPIO LOW HIGH
I/O (13) HANDFREE O GPIO HIGH LOW
I/O (16) PWROK I Sysboot LOW HIGH
I/O (17) BOOT_SEL I GPIO HIGH HIGH
I/O (18) E_MA1 O GPIO LOW HIGH
I/O(19) NFCS_1 O NFCS HIGH LOW
I/O (21) DP_PWON O GPIO LOW HIGH
I/O (23) MINT I GPIO LOW HIGH
I/O(32) RESET_B O GPIO HIGH LOW
I/O(46) HOOKDET I GPIO LOW HIGH
I/O (47) MOD_LED O GPIO LOW HIGH
I/O (63) SPK_EN O GPIO LOW HIGH
<Table.3> GPIO Map
3.4 Analog Baseband
3.4.1 General Description
The TRITON chip is the analog and power management part of the Texas Instruments next
generation wireless terminal. These GSM/GPRS/E-GPRS, 3G W-CDMA, CDMA2000 platforms are
composed of a digital baseband processor, a RF chip, an application processor OMAP and of
different peripheral devices like a LCD panel, a Multi-Media Card, a Bluetooth modem, a GPS
modem. The purpose of the Triton device is to provide to platforms the following resources:
3. Circuit Description
- 26 -
<Fig.9> TWL3029 Architecture
- A power management system
- Power supply resources
- A voice and audio interface
- A battery charger
- A monitoring system
- A real time clock resource
- A USB 2.0 OTG transceiver with a carkit
interface
- Three White-LEDs drivers
- A vibrator driver
- A SIM-Card detection
- A thermal shutdown
- An I2C interface
- A JTAG and boundary scan
3. Circuit Description
- 27 -
3.4.2 Audio Signal Processing & Interface
The Audio module consists of a Voice Codec dedicated to mobile telephone terminal application and
a Stereo path.
- The Voice Codec circuit processes analog audio components in the uplink path and transmits the
converted data to the DSP speech coder through the voice serial port (VSP). In the downlink path,
the Voice Codec converts the digital samples of speech data received from the DSP via the VSP
port into analog audio signals.
The Voice Codec supports a 8kHz (default narrowband mode) to a 16kHz(wideband mode)
sampling frequency.
- The Stereo path converts audio digital samples received from the I2S serial interface into analog
audio. It supports all standard frequencies from 8kHz to 48kHz (8, 11.025, 12, 22.05, 24, 32, 44.1
and 48kHz).
- Two included PLLs provide the suitable system clocks to the Voice and Stereo circuitry (ADC,
DACS, Digital Filters, Digital interfaces). The Audio module supports 3 possible input master clocks
: 12MHz, 13MHz and 19.2MHz.
3.4.3 Power Resources
The power supply module of Triton generates the different power supplies required by Triton, the
processors and the external peripherals.
3. Circuit Description
- 28 -
<Fig.10> Power Supply Scheme
3. Circuit Description
- 29 -
3.4.4 Monitoring ADC
The monitoring ADC (MADC) consists of a 10-bit analog-to-digital converter (ADC) combined with an
11- input analog multiplexer. The ADC implementation consists of a successive approximation
conversion.
Five of the eleven inputs are available externally (ADIN1..5), and the remaining six inputs are
dedicated to die temperature measurement, main battery voltage, backup battery voltage, charger
voltage, charger current monitoring and USB Vbus voltage. Three external inputs (ADIN1..3) are
standard inputs. The two others (ADIN4..5) which are associated with current sources, are intended
for battery temperature and battery type measurements.
3.4.5 Switch ON/OFF
LG240 Power State : Defined 4cases as follow
- Power-ON : mobile is powered by main battery or backup battery.
- Power-OFF : mobile isn’t any battery.
- Switch-ON : mobile is powered and waken up from switch-off state.
- Switch-OFF : mobile is powered to maintain only the permanent function(ULPD).
To enter into Switch-ON state, one of following 4 condition is satisfied.
- PWR-ON pushed after a debouncing time of 30ms.
- ON_REMOTE : After debouncing, when a falling edgeis detected on RPWON pin.
- IT_WAKE_UP : When a rising edge is detected on RTC_ALARM pin.
- CHARGER_IC :When a charger voltage is above VBAT+0.4V on VCHG.
<Table.4> ADC Channel Spec
ADC 8 channels
Resource Name Description
VCHG VCHG
VBAT VBAT
ICTL ICTL Charging Management
ADIN1 TEMP_SENSE Temperature Sensing
ADIN2 MOD MOD Key
ADIN3
ADIN4
ADIN5 BATT_TEMP Battery Detect
3.4.6 Memories
- 512Mbit NOR Flash + 256Mbit DDR SDRAM
- Address and Data Muxed type
(Data : FDATA0 ~ FDATA15, address : FDATA0 ~ FDATA15 and FADD17 ~ FADD24 )
3.4.7 LCD module pin description
LCD module is connected to main board with 40 pin FPCB. The LCD module includes receiver &
vibrator
3. Circuit Description
- 30 -
3. Circuit Description
- 31 -
Pin # NAME Descri ption
1
GND GN D
2
_WR Data Write Enable
3
M_CS Main LCD Select
4
_LCD_RESET Main/Sub LCD Reset
5
_S_CS Sub LCD Select
6
D(0) LCD Data
7
D(1) LCD Data
8
D(2) LCD Data
9
D(3) LCD Data
10
D(4) LCD Data
11
D(5) LCD Data
12
D(6) LCD Data
13
D(7) LCD Data
14 W-LED_An ode W-LED Anode Connect
15
W-LED_Cathode(1) W-LED Cathode(1) Connect
16
W-LED_Cathode(2) W-LED Cathode(2) Connect
17
W-LED_Cathode(3) W-LED Cathode(3) Connect
18
Vsy nc o ut F o r CDMA Solut io n
19
MOTP Vibrator
20
GND GN D
21
GND GN D
22
SP K P Sp e ak er P ositive ( CE200 : MOD Key Input)
23
SP K N Sp eaker Negative (CE200 : MOD LED Cat hode)
24
RCVP Receiver P osit ive
25
RCVN Receiver Negative
26
D(8) LCD Data
27
D(9) LCD Data
28
D(10) LCD Data
29
D(11) LCD Data
30
D(12) LCD Data
31
D(13) LCD Data
32
D(14) LCD Data
33
D(15) LCD Data
34
VCC 1_ I /O 1.8V Power
35
VCC2_CORE 2.8V 2.8V Power
36
ADS(RS) Select Data or Instruction
37
IFMODE_MAIN Main Lcd Color Bit Select
38
ID_MAKER_HIGH LCD ID(LGIT/Neodis)
39
_RD Data Read Enable
40
GND GN D
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