0.5Mar. 27 20111Model Name change(LP101WX1-SLN1→LP101WX1-SLN2)-
4,6
14R,G, B Color Coordinates Spec update-
15Gray Scale Spec update.-
Logic Power Consumption update
(1.16W max. White Pattern→1.15W max @White Pattern)
4Pixel Pitch change-
EDID
ver
-
25~27
1.0Apr. 25 2011-Final CAS-
25~27EDID update-
19Rear Dimension update.-
22Packing Form update-
11Dclk Spec update(Dclk(Max.) : 74.5Mhz→77.0Mhz
1.1Mayr. 11 201119Mechanical Drawing Label P/N is corrected
11Dclk typ. Is corrected. (71Mhz → 69.3Mhz)
Ver. 1.1May. 15, 2011
EDID update
4Luminance update(TBD→350 cd/m2)
-
3 / 27
LP101WX1
User connector
COG(Chip On Glass)
Userconnector
COG(ChipOnGlass)
Liquid Crystal Display
Product Specification
1. General Description
The LP101WX1 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 10.1inches diagonally measured active display area with HD
resolution(1280 horizontal by 800 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors.
The LP101WX1 has been designed to apply the interface method that enables low power, high speed, low
EMI.
The LP101WX1 is intended to support applications where thin thickness, low power are critical factors and
graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the
LP101WX1 characteristics provide an excellent flat display for office automation products such as Notebook
PC.
EDID
CN
BLOCK
1
40
Pin
POWER
BLOCK
LVDS &
Timing
Control
1
TFT-LCD Panel
(1280 x 800)
1280
Source Driver Circuit
Block
LED Driver
Block
General Features
Active Screen Size10.1 inches diagonal
Outline Dimension
Pixel Pitch
Pixel Format1280 horiz. By 800 vert. Pixels RGB strip arrangement
Color Depth6-bit, 262,144 colors
Luminance, White350 cd/m2(Typ.5 point)
Power ConsumptionTotal 3.33 W(Max.) (Logic :1.15 W (max. @ White), B/L : 2.18W (max.@ VLED 12V)
Weight160g (Max.)
Display Operating ModeTransmissive mode, normally Black
Surface TreatmentGlare treatment of the front polarizer(Anti-Reflection≤1.5%)
RoHS ComplianceYes
BFR / PVC / As Free Yes for all
Control & DataPowerEDID signal & Power
229.46(H) ×149.2(V)x5.2(D,Max.) [mm]
0.1695mm × 0.1695 mm
LED Backlight Ass’y
1
800
Ver. 1.1May. 15, 2011
4 / 27
LP101WX1
90%80
%
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
ParameterSymbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
VCC-0.34.0Vdcat 25 ± 5°C
TOP050°C1
HST-2060°C1
HOP1090%RH1
HST1090%RH1
Values
UnitsNotes
MinMax
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39°C Max, and no condensation of water.
60%
Humidity[(%)RH]
Storage
40%
Operation
20%
10%
Wet Bulb
Temperature [
20
10
0
℃℃℃℃
60
50
]
40
30
-20
Ver. 1.1May. 15, 2011
10
20304050
Dry Bulb Temperature [
℃℃℃℃
6070800
]
5 / 27
LP101WX1
Liquid Crystal Display
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
The LP101WX1 requires two power inputs. One is employed to power the LCD electronics and to drive the
TFT array and liquid crystal. The second input which powers the LED BL.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
MinTypMax
LOGIC :
Power Supply Input VoltageVCC3.03.33.6V1
Power Supply Input CurrentWhiteICC-303348mA2
Power ConsumptionPCC-1.01.15W2
Power Supply Inrush CurrentICC_P-1500mA3
LVDS ImpedanceZLVDS90100110Ω4
BACKLIGHT : ( with LED Driver)
LED Power Input VoltageVLED5.012.021.0V5
LED Power Input CurrentILED-170181mA6
LED Power ConsumptionPLED-2.042.18W6
LED Power Inrush CurrentILED_P-2000mA7
PWM Duty Ratio1-100%8
PWM Jitter-0-0.2%9
PWM ImpedanceZPWM204060kΩ
PWM FrequencyFPWM200-1000Hz
Values
UnitNotes
PWM High Level VoltageV
PWM Low Level VoltageV
LED_EN ImpedanceZPWM204060kΩ
LED_EN High Voltage
LED_EN Low Voltage
Life Time12,000--Hrs10
Ver. 1.1May. 15, 2011
PWM_H
PWM_L
VLED_EN
_H
VLED_EN
_L
2.2-5.3V
0-0.3V
2.2-5.3V
0-0.3V
6 / 27
Liquid Crystal Display
0.5ms
Product Specification
Note)
1. The measuring position is the connector of LCM and the test conditions are under 25℃, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25℃, fv = 60Hz condition and White pattern.
3. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
LP101WX1
Rising time
Vcc
0V
10%
90%
3.3V
4. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
℃
5. The measuring position is the connector of LCM and the test conditions are under 25
.
6. The current and power consumption with LED Driver are under the Vled = 12.0V , 25℃, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
7. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
Rising time
VLED
0V
10%
90%
12.0V
0.5ms
8. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
9. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
10. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
Ver. 1.1May. 15, 2011
7 / 27
LP101WX1
17
ORXC
-
Negative LVDS differential clock input
Liquid Crystal Display
Product Specification
3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
PinSymbolDescriptionNotes
1NCNo Connection
2VCCLCD Logic and driver power (3.3V Typ.)
3VCCLCD Logic and driver power (3.3V Typ.)
4V EEDIDDDC Power (3.3V)
5NCNo Connection
6Clk EEDIDDDC Clock
7DATA EEDIDDDC Data
8ORX0-Negative LVDS differential data input
9ORX0+Positive LVDS differential data input
10GNDHigh Speed Ground
11ORX1-Negative LVDS differential data input
12ORX1+Positive LVDS differential data input
13GNDHigh Speed Ground
14ORX2-Negative LVDS differential data input
15ORX2+Positive LVDS differential data input
16GNDHigh Speed Ground
[Interface Chip]
1. LCD :
SiW, SW0624(LCD Controller)
Including LVDS Receiver.
2. System :
* Pin to Pin compatible with LVDS
[Connector]
UJU IS050-L40B-C10
LSMtron GT05Q-40S-H10 or equivalent
[Mating Connector]
20345-#40E-## series or equivalent
[Connector pin arrangement]
40
1
18ORXC+Positive LVDS differential clock input
19GNDHigh Speed Ground
20
21
22GNDHigh Speed Ground
23
24
25GNDHigh Speed Ground
26
27
28GNDHigh Speed Ground
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
GNDLED Backlight Ground
GNDLED Backlight Ground
GNDLED Backlight Ground
NC
PWMSystem PWM Signal input for dimming
LED_EN
NC
VLEDLED Backlight Power (5V-21V)
VLEDLED Backlight Power (5V-21V)
VLEDLED Backlight Power (5V-21V)
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
LED Backlight On/Off
No Connection
[LCD Module Rear View]
Ver. 1.1May. 15, 2011
8 / 27
Product Specification
3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
LP101WX1
Liquid Crystal Display
Description
Symb
ol
MinMaxUnitNotes
LVDS Differential Voltage|VID|100600mV-
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
CM
IN
0.61.8V-
0.32.1V-
3-3-2. AC Specification
DescriptionSymbolMinMaxUnitNotes
85MHz > Fclk ≥
65MHz > Fclk ≥
LVDS Clock to Data Skew Margin
t
SKEW
t
SKEW
- 400+ 400ps
- 600+ 600ps
65MHz
25MHz
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 1.1May. 15, 2011
t
SKEW_EO
F
DEV
F
MOD
- 1/7+ 1/7T
-
± 3
clk
%-
-200KHz-
-
9 / 27
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