( ) Preliminary Specification
◆
( ) Final Specification
Title 10.1” WSVGA TFT LCD
LP101WSA
Liquid Crystal Display
Product Specification
SPECIFICATION
FOR
APPROVAL
Customer Acer
MODEL
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APPROVED BY SIGNATURE
/
/
/
SUPPLIER LG Display Co., Ltd.
*MODEL LP101WSA
Suffix TLA1
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
G. J. Kwon/ Manager
REVIEWED BY
C. J. Jun / Manager
PREPARED BY
P. A. Choi / Engineer
SIGNATURE
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0 Feb. 12, 2009
Products Engineering Dept.
LG Display Co., Ltd
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Product Specification
Contents
LP101WSA
Liquid Crystal Display
No ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTREISTICS
3-2 INTERFACE CONNECTION
3-3 LVDS SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING SPECIFICATIONS
3-5 SIGNAL TIMING WAVEFORMS
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3-6 COLOR INPUT DATA REFERNECE
3-7 POWER SEQUENCE
4 OPTICAL SFECIFICATIONS
Page
1
2
3
4
5
6
7
8
10
10
11
12
13
5 MECHANICAL CHARACTERISTICS
6 RELIABLITY
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
9 PRECAUTIONS
A APPENDIX. Enhanced Extended Display Identification Data
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Product Specification
RECORD OF REVISIONS
LP101WSA
Liquid Crystal Display
Revision No Revision Date Page Description
0.0 Oct. 16. 2008 All First Draft (Preliminary Specification) -
0.1 Nov. 10. 2008 16~19 Mechanical Characteristics -
1.0 Feb. 12.2009 7 BL_ON pin(@ Pin Map) -
26~28 EDID update -
13 Color Coordinates 14 Gray Scale Specification -
4 Power Consumption -
19 Mechanical Characteristics -
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EDID
ver
Ver. 1.0 Feb. 12, 2009
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LP101WSA
Liquid Crystal Display
Product Specification
1. General Description
The LP101WSVGA is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system.
The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display
operating in the normally white mode. This TFT-LCD has 10.1inches diagonally measured active display
area with WSVGA resolution(1024 horizontal by 600 vertical pixel array). Each pixel is divided into Red,
Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the
sub-pixel color is determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more
than 262,144 colors.
The LP101WS1 has been designed to apply the interface method that enables low power, high speed, low
EMI.
The LP101WS1 is intended to support applications where thin thickness, low power are critical factors and
graphic displays are important. In combination with the vertical arrangement of the sub-pixels, the
LP101WS1 characteristics provide an excellent flat display for office automation products such as Notebook
PC.
CN
1
User connector
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40
Pin
Control & Data Power EDID signal & Power
EDID
BLOCK
POWER
BLOCK
LVDS &
Timing
Control
Block
PWM & VBL
1
Source Driver Circuit
LED Backlight Ass’y
General Features
Active Screen Size 10.1 inches diagonal
Outline Dimension
Pixel Pitch 0.2175mmx0.2088mm
Pixel Format 1024 horiz. By 600 vert. Pixels RGB strip arrangement
Color Depth 6-bit, 262,144 colors
Luminance, White 200 cd/m2(Typ.5 point)
Power Consumption
Weight 190g (Max.)
Display Operating Mode Transmissive mode, normally white
Surface Treatment Glare treatment of the front polarizer
RoHS Comply Yes
235(H) × 143(V) × .5.2(D,Max.) [mm]
Total 2.55 Watt(Typ.) @ LCM circuit 0.82 Watt(Typ.), B/L input 1.73 Watt(Typ.)
(W/O LED Driver)
TFT-LCD Panel
(1024 x 600)
1024
1
GIP(Gate In Panel)
600
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LP101WSA
Liquid Crystal Display
Product Specification
2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39C Max, and no condensation of water.
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Wet Bulb
Temperature[℃]
20
10
0
VCC -0.3 4.0 Vdc
TOP 0 50
HST -20 60
HOP 10 90 %RH 1
HST 10 90 %RH 1
50
40
30
Values
Min Max
90% 80%
60
Units Notes
C
C
60%
Humidity[(%)RH]
Storage
40%
Operation
20%
10%
at 25 5C
1
1
-20
Ver. 1.0 Feb. 12, 2009
10
20 30 40 50
Dry Bulb Temperature [℃]
60 70 800
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LP101WSA
Liquid Crystal Display
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
The LP101WS1 requires two power inputs. One is employed to power the LCD electronics and to drive the
TFT array and liquid crystal. The second input which powers the LED BL.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
MODULE :
Power Supply Input Voltage VCC 3.0 3.3 3.6 V
Power Supply Input Current I
Power Consumption Pc - 0.82 0.93 Watt 1
Differential Impedance
LED Backlight ( With LED Driver ) :
LED Driver (@12V ) P
Operating Voltage V
Operating Current per string I
Power Consumption P
Life Time 10,000 - - Hrs 5
Note)
1. The specified current and power consumption are under the Vcc = 3.3V , 25℃, fv= 60Hz condition
whereas Mosaic pattern is displayed and fv is the frame frequency.
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CC
Zm
DRIVER
LED
LED
BL
Min Typ Max
- 250 280 mA 1
90 100 110 Ohm 2
- 28.8 30.6 V
- 20 mA 3
- 1.73 1.84 Watt 4
Values
0.12 0.14 Watt
Unit Notes
DC
2. This impedance value is needed to proper display and measured form LVDS Tx to the mating connector.
3. The typical operating current is for the typical surface luminance (LWH) in optical characteristics.
I
is the current of each LED‟s string, LED backlight has 3 strings on it.
LED
4. The LED power consumption shown above does not include power of external LED driver circuit
for typical current condition.
5. The life time is determined as the time at which brightness of LED is 50% compare to that of initial value
at the typical LED current.
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LP101WSA
Liquid Crystal Display
Product Specification
3-2. Interface Connection
This LCD employs one interface connection, a 40 pin connector is used for the module electronics interface.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin Symbol Description Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CT1/NC Connector Test/No Connection(Reserved)
VDD +3.3V Power Supply
VDD +3.3V Power Supply
V
EDID
NC No Connection
CLK
EDID
DATA
EDID
RxIN0- LVDS differential data input
RxIN0+ LVDS differential data input
GND Ground
RxIN1- LVDS differential data input
RxIN1+ LVDS differential data input
GND Ground
RxIN2- LVDS differential data input
RxIN2+ LVDS differential data input
GND Ground
RxCLKIN- LVDS differential clock input
RxCLKIN+ LVDS differential clock input
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GND Ground
NC No Connection
NC No Connection
GND Ground
NC No Connection
NC No Connection
GND Ground
NC No Connection
NC No Connection
GND Ground
NC No Connection
NC No Connection
VLED_GND LED Ground
VLED_GND LED Ground
VLED_GND LED Ground
CT2/NC Connector Test/No Connection(Reserved)
S_PWMIN System PWM signal input
BL_ON LED Enable[Note 1]
NC No Connection
VLED +4.5V~+21V LED Power Supply
VLED +4.5V~+21V LED Power Supply
VLED +4.5V~+21V LED Power Supply
+3.3V EDID Power
EDID Clock Input
EDID Data Input
1, Interface chips
1.1 LCD : SiW, 1port including
LVDS Receiver
1.2 System :
* Pin to Pin compatible with LVDS
2. Connector
2.1 LCD :I-PEX 20455-040E-0*
(Locking type)
or equivalent
2.2 Mating :
2.3 Connector pin arrangement
40
[LCD Module Rear View]
[Note 1]
On: 2.0V↑,Off:0~0.4V
1
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Product Specification
LVDS +
LVDS -
0V
V
CM
# |VID| = |(LVDS+) – (LVDS-)|
# VCM = {(LVDS+) + (LVDS-)}/2
|VID|
V
IN_MAXVIN_MIN
LVDS Data
t
SKEW
LVDS Clock
T
clk
t
SKEW (Fclk
= 1/T
clk
)
1) 85MHz > Fclk ≥ 65MHz : -400 ~ +400
2) 65MHz > Fclk ≥ 25MHz : -600 ~ +600
3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
LP101WSA
Liquid Crystal Display
Description
Symb
ol
Min Max Unit Notes
LVDS Differential Voltage |VID| 100 600 mV LVDS Common mode Voltage V
LVDS Input Voltage Range V
3-3-2. AC Specification
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CM
IN
0.6 1.8 V -
0.3 2.1 V -
Description Symbol Min Max Unit Notes
t
SKEW
- 400 + 400 ps
85MHz > Fclk ≥
LVDS Clock to Data Skew Margin
t
SKEW
- 600 + 600 ps
65MHz > Fclk ≥
65MHz
25MHz
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 1.0 Feb. 12, 2009
t
SKEW_EO
F
DEV
F
MOD
- 1/7 + 1/7 T
clk
- ± 3 % -
- 200 KHz -
-
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LVDS Even Data
LVDS Odd Clock
LVDS Even Clock
t
SKEW_EO
T
clk
T
clk
Freq.
F
max
F
center
F
min
Product Specification
< Clock skew margin between channel >
LP101WSA
Liquid Crystal Display
F
* F
center
DEV
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3-3-3. Data Format
- LVDS 1 Port
RCLK+
RA+/-
RB+/-
RC+/-
RD+/-
R3 R2
G4 G3
B5 B4
G7 G6
R1 R0
G2 G1
B3 B2
R7 R6
1
F
MOD
< Spread Spectrum >
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VSYNC HSYNC B5 B4 B3 B2
X B7 B6 G7 G6 R7 R6
Time
G0
B1
DE
VSYNC HSYNC
X
R5 R4
B0 G5
B7 B6
Ver. 1.0 Feb. 12, 2009
Previous (N-1)th Cycle Next(N+1)th Cycle
Current (Nth) Cycle
< LVDS Data Format >
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