1.0Oct,10,20123Updated General features
5Updated Table 2
7Added SSR spec
15Updated Table 7
25Updated Table 10
Final Specification
LC420EUJ
Ver. 1.0
3/40
LC420EUJ
Product Specification
1. General Description
The LC420EUJ is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 41.92 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7Milion colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
LVDS
2Port
LVDS
Select
OPC
Enable
ExtVBR-B
+12.0V
CN1
(51pin)
LVDS 1,2
Option
signal
I2C
EEPROM
SCL
Timing Controller
LVDS Rx + OPC + DGA
SDA
Integrated
Power Circuit
Block
EPI(RGB)
Control
Signals
Power Signals
S1S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
G1080
General Features
Active Screen Size41.92 inches(1064.77m) diagonal
Outline Dimension946.9(H) x 542.1 (V) x 1.50 mm(D) (Typ.)
Pixel Pitch0.4833 mm x 0.4833 mm
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth
Drive IC Data Interface
Transmittance (With POL)6.35%(Typ.)
8-bit, 16.7 M colors (※ 1.06B colors @ 10 bit (D) System Output )
Source D-IC : 8-bit EPI, gamma reference voltage, and control signals
Gate D-IC : Gate In Panel
Source Driver Circuit
[Gate In Panel]
Viewing Angle (CR>10)Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Weight1.50Kg (Typ.)
Display ModeTransmissive mode, Normally black
Surface Treatment (Top)Hard coating(2H), Anti-glare treatment of the front polarizer (Haze <1%)
Ver. 1.0
4/40
LC420EUJ
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
ParameterSymbol
UnitRemark
MinMax
Value
Power Input voltageVLCD-0.3+14.0V [DC]
Panel Front TemperatureTSUR-+68
1. Ambient temperature condition (Ta = 25 2 °C )
2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature
should be Max 39 °C and no condensation of water.
3. Gravity mura can be guaranteed below 40℃ condition.
4. The maximum operating temperature is based on the test condition that the surface temperature
of display area is less than or equal to 68 ℃ with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in final product design to prevent the surface
temperature of display area from being over 68 ℃. The range of operating temperature may
degrade in case of improper thermal management in final product design.
It requires two power inputs. One is employed to power for the LCD circuit.
Table 2. ELECTRICAL CHARACTERISTICS
LC420EUJ
ParameterSymbol
Circuit :
Power Input VoltageVLCD10.812.013.2VDC
Power Input CurrentILCD
Power ConsumptionPLCD5.407.02Watt1
Rush currentIRUSH--5.0A3
ExtV
BR-B
Brightness Adjust for Back Light
Pulse Duty Level
(PWM)
ExtV
BR-B
Frequency
High Level
Low Level
MinTypMax
-450585mA1
-685890mA2
5-100%
1-100%
4050/6080Hz
2.5-3.6Vdc
0-0.8Vdc
Notes : 1. The specified current and power consumption are under the V
Value
UnitNote
=12.0V, 25 2°C, fV=60Hz
LCD
HIGH : on duty
LOW : off duty
condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ± 5% of typical voltage.
White : 255Gray
Black : 0Gray
On Duty
4
Ver. 1.0
Mosaic Pattern(8 x 6)
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LC420EUJ
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or compatible
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
‘H’ =JEIDA , ‘L’ or NC = VESA
External PWM (from System)
No Connection (Note 4)
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
No Connection
No Connection
No Connection or Ground
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
No Connection
No Connection
No Connection or Ground
No Connection or Ground
Note
Ver. 1.0
1. All GND(ground) pins should be connected together to the LCD module‟s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #1~#6 & #8~#10 NC (No Connection): These pins are used only for LGD (Do not connect)
5. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
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LC420EUJ
Product Specification
3-3. Signal Timing Specifications
Table 4 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 4. TIMING TABLE (DE Only Mode)
ITEMSymbolMinTypMaxUnitnotes
Horizontal
Vertical
Frequency
Display
Period
BlanktHB100140240tCLK1
TotaltHP106011001200tCLK
Display
Period
BlanktVB
TotaltVP
ITEMSymbolMinTypMaxUnitnotes
DCLKfCLK63.0074.2578.00MHz
HorizontalfH57.367.570KHz2
VerticalfV
tHV960960960tCLK1920 / 2
tVV108010801080Lines
20
(228)
1100
(1308)
57
(47)
45
(270)
1125
(1350)
60
(50)
69
(300)
1149
(1380)
63
(53)
Lines1
Lines
Hz
NTSC
(PAL)
2
notes: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
3. Spread Spectrum Rate (SSR) for 50KHz ~ 100kHz Modulation Frequency(FMOD) is calculated by
(7 – 0.06*Fmod), where Modulation Frequency (FMOD) unit is KHz.
LVDS Receiver Spread spectrum Clock is defined as below figure
※ Timing should be set based on clock frequency.
Ver. 1.0
8/40
LC420EUJ
Product Specification
※ Please pay attention to the followings when you set Spread Spectrum Rate(SSR) and Modulation
Frequency(FMOD)
1. Please set proper Spread Spectrum Rate(SSR) and Modulation Frequency (FMOD) of TV system LVDS
output.
2. Please check FOS after you set Spread Spectrum Rate(SSR) and Modulation Frequency(FMOD) to avoid
abnormal display. Especially, harmonic noise can appear when you use Spread Spectrum under FMOD 30
KHz.
Ver. 1.0
9/40
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LC420EUJ
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
0.5 VDD
Invalid data
Invalid data
DE(Data Enable)
Valid data
Pixel 0,0Pixel 2,0
Valid data
Pixel 1,0Pixel 3,0
tHP
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 1.0
11080
tVV
tVP
10/40
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
LC420EUJ
Product Specification
# VCM= {( LVDS +) + ( LVDS -)}/2
0V
V
CM
V
IN _ MAXVIN _ MIN
DescriptionSymbolMinMaxUnitNote
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
CM
IN
1.01.5V-
0.71.8V-
Change in common mode VoltageΔVCM-250mV-
2) AC Specification
T
clk
LVDS Clock
A
LVDS Data
(F
= 1/T
)
clk
A
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
t
SKEW_mintSKEW_max
tSKEW
clk
T
clk
80%
20%
t
RF
DescriptionSymbolMinMaxUnitNote
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skewt
LVDS Clock/DATA Rising/Falling timet
Effective time of LVDSt
LVDS Clock to Clock Skew (Even to Odd)t
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
Note
2. If t
isn‟t enough, t
RF
should be meet the range.
eff
V
TH
V
TL
SKEW
RF
eff
SKEW_EO
3. LVDS Differential Voltage is defined within t
Ver. 1.0
100300mV
-300-100mV
-|(0.20*T
260|(0.3*T
|± 360|
-|1/7* T
eff
)/7|ps-
clk
)/7|ps2
clk
-ps-
|ps-
clk
3
11/40
Product Specification
LC420EUJ
LVDS Data
0V
(Differential)
LVDS CLK
0.5tui
360ps
tui
VTH
VTL
360ps
teff
tui : Unit Interval
0V
(Differential)
* This accumulated waveform is tested with differential probe
Ver. 1.0
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