LG L343i Service Manual
Date: August, 2006 / Issue 1.0
Service Manual
Model : L343i
Service Manual
L343i
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1. INTRODUCTION...................................5
1.1 Purpose ..................................................... 5
1.2 Regulatory Information ............................... 5
1.3 Abbreviations .............................................. 7
2. PERFORMANCE ..................................9
2.1 H/W Features...............................................9
2.2 Technical Specification ..............................10
3. TECHNICAL BRIEF............................15
3.1 Transceiver (SI4210, U401).......................15
3.2 PAM (SKY77328, U500)........................... 19
3.3 26 MHz Clock (VCTCXO, X400)................20
3.4 Power Supplies for RF Circuits
(RF LDO, U403).........................................20
3.5 Digital Main Processor (AD6527, U102)....22
3.6 Analog Main & Power Management
Processor (AD6537B, U101) .....................28
3.7 LCD MODULE ...........................................38
3.8 Camera ......................................................39
3.9 Keypad Switch and Scanning ....................41
3.10 Microphone ..............................................42
3.11 Main Speaker...........................................42
3.12 Headset Interface ....................................43
3.13 Key Back-light Illumination.......................44
3.14 VIBRATOR ..............................................45
3.15 Bluetooth Section Description (M201) .....46
4. TROUBLE SHOOTING.......................48
4.1 RF Component ..........................................48
4.2 RX Trouble.................................................49
4.3 TX Trouble .................................................55
4.4 Power On Trouble......................................62
4.5 Bluetooth Section Trouble Shooting ..........63
4.6 Charging Trouble .......................................68
4.7 Vibrator Trouble .........................................70
4.8 LCD Trouble ..............................................72
4.9 Camera Trouble.........................................74
4.10 Speaker Trouble ......................................76
4.11 SIM Card Interface Trouble .....................78
4.12 Earphone Trouble ....................................80
4.13 KEY backlight Trouble .............................82
4.14 Receiver Trouble .....................................84
4.15 Microphone Trouble.................................86
4.16 RTC Trouble ............................................88
4.17 Folder on/off Trouble ...............................89
4.18 Camera Flash Trouble .............................90
5. DOWNLOAD.......................................93
5.1 Download Setup ........................................93
5.2 Download Procedure .................................94
6. BLOCK DIAGRAM ...........................101
7. Circuit Diagram................................103
8. pcb layout.........................................111
9. ENGINEERING MODE......................115
9.1 BB Test [MENU 1] ...................................116
9.2 RF Test [MENU 2] ...................................118
9.3 MF mode [MENU 3] .................................118
9.4 Trace option [MENU 4] ............................119
9.5 Call timer [MENU 5] .................................119
9.6 Fact. Reset [MENU 6]..............................119
9.7 S/W version[MENU 7]..............................119
10. STAND ALONE TEST ....................120
10.1 Introduction ............................................120
10.2 Setting Method.......................................120
10.3 Means of Test ........................................121
11. AUTO CALIBRATION.....................123
11.1 Calibration..............................................123
11.2 Hotkimchi Calibration Program ..............126
12. EXPLODED VIEW & REPLACEMENT
PART LIST ..................................... 139
12.1 Exploded View ...................................... 139
12.2 Replacement Parts ................................141
12.3 Accessory ............................................. 159
Table Of Contents
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1. INTRODUCTION
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1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
1. INTRODUCTION
1. INTRODUCTION
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E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
1. INTRODUCTION
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1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current - Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
1. INTRODUCTION
- 8 -
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
2. PERFORMANCE
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2.1 H/W Features
2. PERFORMANCE
Item Feature Comment
Classification : Li-on
Standard Battery
Capacity min 830mAh
Voltage :3.7V
Cell Weight : 22g
Under the minimum current consumption environment
Stand by Current (such as paging period 9), the level of standby current
is below 4mA.
Talk time Up to 2.5 hours (GSM TX Level 5)
Stand by time Up to 200 hours (Paging Period: 9, RSSI: -85 dBm)
Charging time Approx. Under 3 hours
RX Sensitivity GSM, EGSM: -107dBm, DCS: -107dBm
TX output power
GSM, EGSM: 33dBm(Level 5),
DCS, PCS: 30dBm(Level 0)
GPRS compatibility Class 10
SIM card type 3V Small
Display
Main LCD : 128 x 160 260K TFT, 1.77”
Sub LCD : 96 x 64 65K OLED,1.04”
Hard icons. Key Pad
0 ~ 9, #, *, Up/Down Navigation Key
Status Indicator Menu Key, Clear Key
Send Key, END/PWR Key
Soft Key(Left/Right)
ANT Internal
EAR Phone Jack Yes (mono)
PC Synchronization Yes
Speech coding EFR/FR/HR
Data and Fax Yes
Vibrator Yes
Loud Speaker Yes
Voice Recoding Yes
Microphone Yes
Speaker/Receiver One way dual speaker
Travel Adapter Yes
Bluetooth / USB Yes
MIDI 64 Poly (Mono SPK)
Options Data Kit , CD
Camera Module Yes (VGA, CMOS)
2. PERFORMANCE
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2.2 Technical Specification
Item Description Specification
EGSM
TX: 890 + (n-1024) x 0.2 MHz
RX: 935 + (n-1024) x 0.2 MHz (n=975~1024)
DCS
1Frequency Band TX: 1710 + (n-512) x 0.2 MHz
RX: 1805 + (n-512) x 0.2 MHz (n=512~885)
PCS
TX: 1810 + (n-512) x 0.2 MHz
RX: 1905 + (n-512) x 0.2 MHz (n=512~810)
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM, EGSM
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS, PCS
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
2. PERFORMANCE
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Item Description Specification
GSM, EGSM
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
5
Output RF Spectrum 6,000 -71
(due to modulation) DCS, PCS
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65
6,000 -73
GSM, EGSM
Offset from Carrier (kHz) Max. (dBm)
Output RF Spectrum 400 -19
6
(due to switching transient) 600 -21
1,200 -21
1,800 -24
2. PERFORMANCE
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Item Description Specification
DCS, PCS
Offset from Carrier (kHz). Max. (dBm)
Output RF Spectrum 400 -22
6
(due to switching transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
GSM, EGSM
8 Bit Error Ratio
BER (Class II) < 2.439% @-102 dBm
DCS, PCS
BER (Class II) < 2.439% @-100 dBm
9 RX Level Report Accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500
*
-5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
*
Mean that Adopt a straight line in between 300 Hz and
1,000 Hz to be Max. level in the range.
2. PERFORMANCE
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Item Description Specification
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
18
System frequency
2.5ppm
(13 MHz) tolerance
19 32.768KHz tolerance 30ppm
At least 65 dBspl under below conditions:
20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
21 Charge Current
Fast Charge : < 450 mA
Pre Charge : < 100 mA
Antenna Bar Number Power
5 -85 dBm ~
4 -90 dBm ~ -86 dBm
22 Antenna Display 3 -95 dBm ~ -91 dBm
2 -100 dBm ~ -96 dBm
1 -105 dBm ~ -101 dBm
0~ -105 dBm
Battery Bar Number Voltage
0 3.51 ~ 3.61 V
23 Battery Indicator 1 3.62 ~ 3.69 V
2 3.70 ~ 3.77 V
3 3.78 ~ 3.91 V
4 3.92 V ~
24 Low Voltage Warning
3.62 0.03V (Call)
3.50 0.03V (Standby)
2. PERFORMANCE
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Item Description Specification
25 Forced shut down Voltage 3.35 0.03 V
1 Li-ion Battery
26 Battery Type
Standard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 830mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60 Hz
Output: 5.2 V, 800 mA
3. TECHNICAL BRIEF
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3.1 Transceiver (SI4210, U401)
The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part, a voltage
supply part, and a VCTCXO part.
The Aero 2 transceiver is the integrated RF front end for multi-band GSM/GPRS digital cellular
handsets and wireless data modems. The integrated solution eliminates the IF SAW filter, external low
noise amplifier (LNAs) for three bands, transmit and RF voltage controlled oscillator (VCO modules,
and other discrete components found in conventional designs.)
3. TECHNICAL BRIEF
Figure. 3-1 RECEIVER FUNCTIONAL BLOCK DIAGRAM
3. TECHNICAL BRIEF
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(1) Receiver Part
The Aero 2 transceiver uses a low-IF receiver architecture which allows for the on chip integration of the
channel selection filters, eliminating the external RF image reject filters and the IF SAW filter required in
conventional super-heterodyne architectures.
A. RF front end
RF front end consists of Front End Module(FL400) and dual band LNAs integrated in transceiver (U401).
The Received RF signals(GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz PCS 1905MHz ~
1980MHz) are fed into the antenna or Mobile switch.
The Front End Module(FL500) is used to control the Rx and Tx paths. And, the input signals ANT_SW1,
ANT_SW2 of a FL400 are directly connected to baseband controller to switch either Tx or Rx path on.
The logic and current is given below Table 3-1
Three differential-input LNAs are integrated in SI4205. The GSM input supports the GSM 850 (864894MHz) or E-GSM 900 (925-960MHz) bands. The DCS input supports the DCS 1800 (1805-1880 MHz)
band. The PCS input supports the PCS 1900 (1930-1990 MHz) band.
The LNA inputs are matched to the 150 balanced output SAW filters through external LC matching
networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in register 05h (Figure 3-2).
ANT_SW1 ANT_SW2
GSM Tx 2.5 ~ 3.0 0 V 0V
DCS, PCS Tx 0V 2.5 ~ 3.0 V
GSM Rx 0V 0 V
DCS, PCS Rx 0V 0 V
Table 3-1 THE LOGIC AND CURRENT
3. TECHNICAL BRIEF
- 17 -
B. Intermediate frequency (IF) and Demodulation
A quadrature image-reject mixer downconverts the RF signal to a 100KHz intermediate frequency (IF) with
the RFLO from the frequency synthesizer. The RFLO frequency is between 1737.8 to 1989.9 MHz, and is
internally divided by 2 for GSM 850 and E-GSM 900 modes. The mixer output is amplified with an analog
programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register 05h (Figure3-2).
The quadrature IF signal is digitized with high resolution A/D converters (ADCs).
The ADC output is downconverted to baseband with a digital 100KHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to remove blocking and reference interference signals.
The selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1). The low selectivity filter has a flatter
group channelization filter is in the baseband chip. After channel selection, the digital output is scaled with a
digital PGA, which is controlled with the DGAIN [5:0] bits in register 05h.
The amplified digital output signal go through with DACs that drive a differential analog signal onto the
RXIP,RXIN,RXQP and RXQN pins to interface to standard analog ADC input baseband ICs. No special
processing is required in the baseband for offset compensation or extended dynamic range.
Compared to a direct-conversion architecture, the low-IF architecture has a much greater degree of
immunity to dc offsets that can arise from RF local oscillator(RFLO) self-mixing, 2nd order distortion of
blockers, and device 1/f noise.
Figure. 3-2 SI4210 RECEIVER PART
3. TECHNICAL BRIEF
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(2) Transmitter Part
The transmit (Tx) section consists of an I/Q baseband upconverter, and offset phase-locked loop (OPLL)
and two output buffers that can drive external power amplifiers (PA), one for the GSM 850 (824-849 MHz)
and E-GSM 900 (880-915 MHz) bands and one for the DCS 1800 (1710-1785 MHz) and PCS 1900 (18501910MHz) bands.
A. IF Modulator
The baseband converter(BBC) within the GSM chipset generates I and Q baseband signals for the Transmit
vector modulator. The modulator provides more than 40dBc of carrier and unwanted sideband rejection and
produces a GMSK modulated signal. The baseband software is able to cancel out differential DC offsets in
the I/Q baseband signals caused by imperfections in the D/A converters. The Tx-Modulator implements a
quadrature modulator. A quadrature mixer upconverts the differential in-phase (TXIP, TXIN) and quadrature
(TXQP, TXQN) signals with the IFLO to generate a SSB IF signal that is filtered and used as the reference
input to the OPLL.
The IFLO frequency is generated between 766 and 896 MHz and internally divided by 2 to generate the
quadrature LO signals for the quadrature modulator, resulting in an IF between 383 and 448 MHz.
For the E-GSM 900 band, two different IFLO frequencies are required for spur management.
Therefore, the IF PLL must be programmed per channel in the E-GSM 900 band.
Figure. 3-3 SI4210 TRANSMITTER PART
3. TECHNICAL BRIEF
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B. OPLL
The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated TXVCO. The
TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by 2 for the
GSM 850 and E-GSM 900 bands. The RFLO frequency is generated between 1272 and 1483 MHz. To
allow a single VCO to be used for the RFLO, high-side injection is used for the GSM 850 and E-GSM 900
bands, and low-side injection is used for the DCS 1800 and PCS 1900 bands. The I and Q signals are
automatically swapped when switching bands. Additionally, the SWAP bit in register 03h can be used to
manually exchange the I and Q signals.
Low-pass filters before the OPLL phase detector reduce the harmonic content of the quadrature modulator
and feedback mixer outputs. The cutoff frequency of the filters is programmable with the FIF[3:0] bits in
register 04h (Figure 3-3), and should be set to the recommended settings detailed in the register
description.
3.2 PAM (SKY77328, U500)
The SKY77328 Power Amplifier Module (PAM) is designed in a low profile (1.2 mm), compact form factor
for quad-band cellular handsets comprising GSM850/900, DCS1800, and PCS1900 operation. The PAM
also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation.
The module consists of separate GSM850/900 PA and DCS1800/PCS1900 PA blocks, impedancematching circuitry for 50 Ω input and output impedances, and a Power Amplifier Control (PAC) block with an
internal current-sense resistor.
Figure. 3-4 SKY77328
3. TECHNICAL BRIEF
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3.3 26 MHz Clock (VCTCXO, X400)
The 26 MHz clock(X400) consists of a VCTCXO(Temperature Compensated Crystal Oscillator) which
oscillates at a frequency of 26 MHz. It is used within the Si4205, analog base band chipset (U101,
AD6537B), digital base band chipset (U102, AD6527)
3.4 Power Supplies for RF Circuits (RF LDO, U403)
Two regulators are used for RF circuits. One is MIC5255 (U403), and the other is one port of AD6537B
(U101). MIC5255 (U403) supplies power to transceiver (SI4210, U401). One port of AD6537B supplies
power to VVCXO (X400). Main power (VBAT) from battery is used for PAM (SKY77328, U400) because
PAM requires high power.
NA
100
C443
R416
1000p
C441
2V75_VVCXO
GND
2
OUT
3
4
VCC
1
VCONT
R417
15K
X400
26MHz
C442
2.2u
AFC
Figure 3-5 VCTCXO CIRCUIT DIAGRAM
Supplier Voltage Powers enabled signal
U403(RF) 2.85 V U401 CLKON
U102(VVCXO) 2.75 V X400
Battery(VBAT) 3.4 ~ 4.2 V U400, U403
Table 3-2 RF POWER SUPPLIERS
3. TECHNICAL BRIEF
- 21 -
Figure 3-6 RF LDO CIRCUIT DIAGRAM
CLKON
VBAT
U403
1
IN5OUT
2
GND
3
MIC5255-2.85BM5
R419
100K
C444
1u
RF2V85
4
BYPEN
C445
0.01u
C446
4.7u
3. TECHNICAL BRIEF
- 22 -
3.5 Digital Main Processor (AD6527, U102)
Figure 3-7. SYSTEM INTERCONECTION OF AD6527 EXTERNAL INTERFACE
3. TECHNICAL BRIEF
- 23 -
• AD6527 is an ADI designed processor.
• AD6527 consists of
1. Control Processor Subsystem
• 32-bit ARM7TDMI Control Processor
• 58.5 MHz operation at 1.7V
• On-board 16KB instruction/Data Cache
• 1 Mbits of on-chip System SRAM
2. DSP Subsystem
• 16-bit Fixed Point DSP Processor
• 91 MIPS at 1.7V
• 16K word Data and 16K word Program SRAM
• 4K word Program Instruction Cache
• Architecture supports Full Rate, Enhanced Full Rate, Half Rate, and AMR Speech
Encoding/Decoding Algorithms
3. Peripheral Subsystem
• Shared on-chip peripheral and off-chip interface:
• Support for Burst and Page Mode Flash
• Support for Pseudo SRAM
• Ciphering module for GPRS supporting GAE1 and GAE2 encryption algorithms
• Parallel and Serial Display Interface
• 8 x 8 Keypad Interface
• Four independent programmable backlight plus One Service Light
• 1.8V and 3.0V, 64 kbps SIM interface
• Universal System Connector Interface
• Slow, Medium and Fast IrDA transceiver interface
• Enhanced Generic Serial Port
• Dedicated SPI interface
• Thumbwheel Interface
• JTAG Interface for Test and In-Circuit Emulation
4. Other
• Supports 13 MHz and 26 MHz Input Clocks
• 1.8V Typical Core Operating Voltages
• 204-Ball LFBGA(mini-BGA) Package
5. Applications
• GSM900/DCS1800/PCS1900/PCS850 Wireless Terminals
• GSM Phase 2+ Compliant
• GPRS Class 12 Compliant
• Multimedia Services(MMS)
• Extended Messaging System(EMS)
3. TECHNICAL BRIEF
- 24 -
3.5.1 Interconnection with external devices
A. RTC block interface
Countered by external X-TAL
The X-TAL oscillates 32.768KHz
B. LCD module interface
The LCD module is controlled by CAMERA IC, CL765A
If CL765A is in the state of by-pass mode, the LCD control signals from AD6527 are by-passed
through CL765A.
In operating mode, the CL765A controls the LCD module through L_MAIN_LCD_CS,
L_SUB_LCD_CS, LCD_RESET, LCD_RS, LCD_WR, LCD_RD, L_DATA[15-00], 2V8_MV,1.8_MV.
Signals Description
L_MAIN_LCD_CS MAIN LCD driver chip enable. MAIN LCD driver IC has own CS pin
L_SUB_LCD_CS SUB LCD driver chip enable. SUB LCD driver IC has own CS pin
LCD_RESET (GPIO 15) This pin resets LCD module. This signal comes from DBB directly.
LCD_WR Enable writing to LCD Driver.
LCD_RD Enable reading to LCD Driver.
LCD_RS This pin determines whether the data to LCD module are display
data or control data. LCD_RS can select 16 bit parallel bus.
2V8_MV,1V8_MV 2.85V voltage is supplied to LCD driver IC.
LCD_SIGNAL1
(GPIO_16)
For the future.
LCD_SIGNAL2
(GPIO_17)
Table 3-3. LCD CONTRON SIGNALS DISCRIPTION
3. TECHNICAL BRIEF
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C. RF interface
The AD6527 control RF parts through PA_BAND, ANT_SW1, ANT_SW2, CLKON , PA_EN, SEN,
SDATA, SCLK, RF_PWR_DWN.
D. Key interface
Include 5 column , 5 row and additional GPIO 35 for KEY_ROW5. The AD6527 detects whether key
is pressed or not by using interrupt method.
E. AD6537B Interrupt
AD6537B provides an active-high interrupt output signal. Interrupt signals are generated by the
Auxiliary ADC, audio, and charger modules.
Signals Description
PA_BAND (GPO 17) PAM Band Select
ANT_SW1 (GPO 9) Antenna switch Band Select
ANT_SW2 (GPO 11) Antenna switch Band Select
CLKON RF LDO Enable/Disable
PA_EN (GPO 16) PAM Enable/Disable
S_EN (GPO 19) PLL Enable/Disable
S_DATA (GPO 20) Serial Data to PLL
S_CLK (GPO 21) Clock to PLL
RF_EN (GPO 4) Power down Input
Table 3-5. SIM CONTROL SIGNALS DESCRIPTION
3. TECHNICAL BRIEF
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F. SIM interface
The AD6527 provides SIM Interface Module. The AD6527 checks status periodically during
established call mode whether SIM card is inserted or not, but it doesn't check during deep Sleep
mode. In order to communicate with SIM card, 3 signals SIM_DATA, SIM_CLK,
SIM_RST(GPIO_23)
are required. The descriptions about the signals are given by bellow Table 3-6 in detail.
Signals Description
SIM_DATA This pin receives and sends data to SIM card. This model can support
1.8volt and 3.0 volt interface SIM card.
SIM_CLK Clock 3.25MHz frequency.
SIM_RST
Reset SIM block
(GPIO_23)
Table 3-6. SIM CONTRON SIGNALS DISCRIPTION
Figure 3-8. SIM Interface of AD6527
(KDS, 1.6T)
SIM CONNECTOR
C324
NA
C325 22p
R369
20K
2V85_VSIM
1000pC326
J301
CLK
3
GND
4
6
I_O
RST
2
1
VCC
5
VPP
2V85_VSIM
220nC318
SIM_DATA
SIM_RST
SIM_CLK
3. TECHNICAL BRIEF
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3.5.2 AD6527 Architecture
The internal architecture of AD6527 is shown above Figure 3-10. AD6527 regroups three main subsystems
connected together through a dynamic and flexible communication bus network. It also includes onboard
system RAM (SRAM) and interfaces with external Flash Memory, Baseband converter functions, and
terminal functions like MMI, SIM and Universal System Connector (USC).
The Digital Signal Processing (DSP) subsystem primarily hosts all the speech processing, channel
equalization and channel codec functions. The code used to implement such functions can be stored in
external Flash Memory and dynamically downloaded on demand into the DSP’s program RAM and
Instruction Cache.
The micro-controller subsystem supports all the GSM terminal software, including the layer 1, 2 and 3 of the
GSM protocol stack, the MMI, and applications software such as data services, test and maintenance. It is
tightly associated with on-chip system SRAM and also includes boot ROM memory with a small dedicated
routine to facilitate the initialization of the external Flash Memory via code download using the on-chip serial
interface to the external Flash Memory interface.
The peripheral subsystem is composed of system peripherals such as interrupt controller, real time clock,
watch dog timer, power management and a timing and control module. It also includes peripheral interfaces
to the terminal functions: keyboard, battery supervision, radio and display. Both the DSP and the MCU can
access the peripheral subsystem via the peripheral bus (PBUS).
For program and data storage, both the MCU subsystem and the DSP subsystem can access the on chip
system SRAM and external memory such Flash Memory. The access to the SRAM module is made through
the RAM Bus (RBUS) under the control of the bus arbitration logic. Similarly, access to the Flash Memory is
through the parallel External Bus (EBUS).
Figure 3-9. AD6527 Architecture
3. TECHNICAL BRIEF
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3.6 Analog Main & Power Management Processor
(AD6537B, U101)
Figure 3-10. AD6537B FUNCTIONAL BLOCK DIAGRAM
B
3. TECHNICAL BRIEF
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• AD6537B is an ADI designed Analog Baseband processor. AD6537B covers the processing GMSK
modulation interface, Aux ADC, Voice signal processing and Power Management.
• AD6537B consists of
1. BB Transmit section
• GMSK Modulation
• I-channel & Q-channel Transmit DACs and Filters
• Power Ramping DAC
2. BB Receive section
• I-channel & Q-channel Receive ADCs and Filters
3. Auxiliary section
• Voltage Reference
• Automatic Frequency Control DAC
• Auxiliary ADC
• Light Controllers
4. Audio Section
• 8 kHz & 16 kHz Voiceband Codec
• 48 kHz Monophonic DAC
• Power Amplifiers
5. Power Management section
• Voltage Regulators
• Battery Charger
• Battery Protection
6. Digital Processor section
• Control, Baseband, and Audio Serial Ports
• Interrupt Logic
3. TECHNICAL BRIEF
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3.6.1 Baseband Transmit Section
1. The AD6537B Baseband Transmit Section is designed to support GMSK for both single-slot and
multi-slot application.
2. The transmit channel consists of a digital GMSK modulator, a matched pair of 10-bit DACs and a
matched pair of reconstruction filter.
3.6.2 Baseband Transmit Section
1. This section consists of two identical ADC channels that process baseband in-phase(I) and
quadrature(Q) input signals.
Figure 3-11. AD6537B BASEBAND TRANSMIT SECTION
Figure 3-12. AD6537B BASEBAND RECEIVER SECTION
3. TECHNICAL BRIEF
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3.6.3 Auxiliary Section
1. This section includes an Automatic Frequency Control(AFC) DAC, voltage reference buffers, an
Auxiliary ADC, and light controllers.
• AFC DAC: 13 bits
2. This section also contains AUX ADC and Voltage Reference
• IDAC: 10 bits
• The Auxiliary ADC provides :
- Two differential inputs for temperature sensing.
- A differential input for the battery charger current sensor
Figure 3-13. AD6537B AUXILIARY SECTION
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