LG KG800 Service Manual

Date: April, 2006 / Issue 1.0

Service Manual

KG800/MG800c

Service Manual

Model : KG800/MG800c

- 3 -

1. INTRODUCTION ...............................5

1.1 Purpose .................................................. 5

1.2 Regulatory Information............................ 5

1.3 Abbreviations .......................................... 7

2. PERFORMANCE...............................9

2.1 H/W Features...........................................9

2.2 Technical Specification ..........................10

3. TECHNICAL BRIEF ........................15

3.1 Power Transceiver ................................15

3.2 13 MHz Clock.........................................22

3.3 Switchplexer for Triband ........................22

3.4 Digital Main Processor ...........................24

3.5 Analog Main & Power Management

Processor...............................................30

3.6 Charging IC............................................37

3.7 CAMERA IC ...........................................40

3.8 MIDI IC...................................................42

3.9 Keypad Switches and Scanning ............46

3.10 Microphone ..........................................47

3.11 Main Speaker.......................................47

3.12 IO Interface ......................................... 48

3.13 EL DRIVER IC .....................................49

3.14 MEMORY.............................................50

3.15 BLUETOOTH .......................................51

3.16 LCD BACKLIGHT, FLASH LED

CHARGE PUMP ..................................52

3.17 SLIDE SWITCH (U205) .......................53

3.18 VIBRATOR...........................................54

3.19 MULTIMEDIA MIC ...............................55

4. TROUBLESHOOTING ....................56

4.1 RX Trouble.............................................56

4.2 TX Trouble .............................................62

4.3 Power On Trouble..................................69

4.4 Charging Trouble ...................................71

4.5 Vibrator Trouble .....................................73

4.6 LCD Trouble.......................................... 75

4.7 BT Trouble .............................................78

4.8 Speaker Trouble ....................................81

4.9 SIM Card Interface Trouble....................84

4.10 Earphone Trouble ................................86

4.11 EL Trouble ...........................................89

4.12 Receiver Trouble..................................91

4.13 Microphone Trouble .............................94

4.14 RTC Trouble ........................................96

4.15 Navigation KEY Problem .....................98

5. DOWNLOAD.....................................100

6. BLOCK DIAGRAM ........................106

7. Circuit Diagram ............................107

8. pcb layout .....................................120

9. ENGINEERING MODE ..................135

9.1 BB Test [MENU 1]................................136

9.2 RF Test [MENU 2]................................138

9.3 MF mode [MENU 3] .............................138

9.4 Trace option [MENU 4] ........................139

9.5 Call timer [MENU 5] .............................139

9.6 Fact. Reset [MENU 6] ..........................139

9.7 S/W version..........................................139

10. STAND ALONE TEST .................140

10.1 Introduction ........................................140

10.2 Setting Method...................................140

10.3 Means of Test ....................................141

11. CALIBRATION.............................143

12. EXPLODED VIEW &

REPLACEMENT PART LIST ..... 151

12.1 Exploded View .................................. 151

12.2 Replacement Parts ............................153

12.3 Accessory ......................................... 173

Table Of Contents

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1. INTRODUCTION

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1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the
features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on this model must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.

1. INTRODUCTION

1. INTRODUCTION

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E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.

G. Interference and Attenuation

Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system boards.

• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.

1. INTRODUCTION

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1.3 Abbreviations

For the purposes of this manual, following abbreviations apply:

APC Automatic Power Control

BB Baseband

BER Bit Error Ratio

CC-CV Constant Current - Constant Voltage

DAC Digital to Analog Converter

DCS Digital Communication System

dBm dB relative to 1 milli watt

DSP Digital Signal Processing

EEPROM Electrical Erasable Programmable Read-Only Memory

ESD Electrostatic Discharge

FPCB Flexible Printed Circuit Board

GMSK Gaussian Minimum Shift Keying

GPIB General Purpose Interface Bus

GSM Global System for Mobile Communications

IPUI International Portable User Identity

IF Intermediate Frequency

LCD Liquid Crystal Display

LDO Low Drop Output

LED Light Emitting Diode

OPLL Offset Phase Locked Loop

1. INTRODUCTION

- 8 -

PAM Power Amplifier Module

PCB Printed Circuit Board

PGA Programmable Gain Amplifier

PLL Phase Locked Loop

PSTN Public Switched Telephone Network

RF Radio Frequency

RLR Receiving Loudness Rating

RMS Root Mean Square

RTC Real Time Clock

SAW Surface Acoustic Wave

SIM Subscriber Identity Module

SLR Sending Loudness Rating

SRAM Static Random Access Memory

PSRAM Pseudo SRAM

STMR Side Tone Masking Rating

TA Travel Adapter

TDD Time Division Duplex

TDMA Time Division Multiple Access

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

VCTCXO Voltage Control Temperature Compensated Crystal Oscillator

WAP Wireless Application Protocol

2. PERFORMANCE

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2.1 H/W Features

2. PERFORMANCE

Item Feature Comment

Li-Poly, 800mAh

Standard Battery Battery Size : 40 (W) × 60(H) × 4.6(T) [mm]

Battery Weight : TBD

Under the minimum current consumption environment

Stand by Current (such as paging period 9), the level of standby current

is below 4mA.

Talk time Up to 3 hours (GSM TX Level 7)

Stand by time Up to 200 hours (Paging Period: 9, RSSI: -85 dBm)

Charging time Approx. Under 3.75 hours

RX Sensitivity GSM, EGSM: -104dBm, DCS: -104dBm

TX output power

GSM, EGSM : 33dBm(Level 5),
DCS, PCS : 30dBm(Level 0)

GPRS compatibility Class 10

SIM card type 3V Small Only

Display Main LCD : TFT 176 × 220 pixel 265K Color

Hard icons. Key Pad : 0 ~ 9, #, *,
Touch key : Send, Clear, Confirm, menu, contacts,

Status Indicator

Left, Right, Up, Down key.
Side Key : Volume up, down, End Key, MP3 Key

ANT Internal

EAR Phone Jack Yes (stereo)

PC Synchronization Yes

Speech coding EFR/FR/HR

Data and Fax Yes

Vibrator Yes

Loud Speaker Yes

Voice Recoding Yes

Microphone Yes

Speaker/Receiver Speaker/Receiver

Travel Adapter Yes

MIDI 64 Poly (Stereo SPK)

MP3/AAC Yes

Options Multi Link Data Cable

2. PERFORMANCE

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2.2 Technical Specification

Item Description Specification

EGSM

TX: 890 + (n-1024) x 0.2 MHz
RX: 935 + (n-1024) x 0.2 MHz (n=975~1024)

DCS

1Frequency Band TX: 1710 + (n-512) x 0.2 MHz

RX: 1805 + (n-512) x 0.2 MHz (n=512~885)

PCS

TX: 1810 + (n-512) x 0.2 MHz
RX: 1905 + (n-512) x 0.2 MHz (n=512~885)

2 Phase Error

RMS < 5 degrees
Peak < 20 degrees

3 Frequency Error < 0.1 ppm

GSM, EGSM

Level Power Toler. Level Power Toler.

5 33 dBm 2dB 13 17 dBm 3dB

6 31 dBm 3dB 14 15 dBm 3dB

7 29 dBm 3dB 15 13 dBm 3dB

8 27 dBm 3dB 16 11 dBm 5dB

9 25 dBm 3dB 17 9 dBm 5dB

10 23 dBm 3dB 18 7 dBm 5dB

11 21 dBm 3dB 19 5 dBm 5dB

4 Power Level 12 19 dBm 3dB

DCS, PCS

Level Power Toler. Level Power Toler.

0 30 dBm 2dB 8 14 dBm 3dB

1 28 dBm 3dB 9 12 dBm 4dB

2 26 dBm 3dB 10 10 dBm 4dB

3 24 dBm 3dB 11 8 dBm 4dB

4 22 dBm 3dB 12 6 dBm 4dB

5 20 dBm 3dB 13 4 dBm 4dB

6 18 dBm 3dB 14 2 dBm 5dB

7 16 dBm 3dB 15 0 dBm 5dB

2. PERFORMANCE

- 11 -

Item Description Specification

GSM, EGSM

Offset from Carrier (kHz). Max. dBc

100 +0.5

200 -30

250 -33

400 -60

600~ <1,200 -60

1,200~ <1,800 -60

1,800~ <3,000 -63

3,000~ <6,000 -65

5

Output RF Spectrum 6,000 -71

(due to modulation) DCS, PCS

Offset from Carrier (kHz). Max. dBc

100 +0.5

200 -30

250 -33

400 -60

600~ <1,200 -60

1,200~ <1,800 -60

1,800~ <3,000 -65

3,000~ <6,000 -65

6,000 -73

GSM, EGSM

Offset from Carrier (kHz) Max. (dBm)

Output RF Spectrum 400 -19

6

(due to switching transient) 600 -21

1,200 -21

1,800 -24

2. PERFORMANCE

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Item Description Specification

DCS, PCS

Offset from Carrier (kHz). Max. (dBm)

Output RF Spectrum 400 -22

6

(due to switching transient) 600 -24

1,200 -24

1,800 -27

7 Spurious Emissions Conduction, Emission Status

GSM, EGSM

8 Bit Error Ratio

BER (Class II) < 2.439% @-102 dBm

DCS, PCS

BER (Class II) < 2.439% @-100 dBm

9 RX Level Report Accuracy 3 dB

10 SLR 8 3 dB

Frequency (Hz) Max.(dB) Min.(dB)

100 -12 -

200 0 -

300 0 -12

11 Sending Response 1,000 0 -6

2,000 4 -6

3,000 4 -6

3,400 4 -9

4,000 0 -

12 RLR 2 3 dB

Frequency (Hz) Max.(dB) Min.(dB)

100 -12 -

200 0 -

300 2 -7

500

*

-5

13 Receiving Response 1,000 0 -5

3,000 2 -5

3,400 2 -10

4,000 2

*

Mean that Adopt a straight line in between 300 Hz and

1,000 Hz to be Max. level in the range.

2. PERFORMANCE

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Item Description Specification

14 STMR 13 5 dB

15 Stability Margin > 6 dB

dB to ARL (dB) Level Ratio (dB)

-35 17.5

-30 22.5

-20 30.7

16 Distortion

-10 33.3

0 33.7

7 31.7

10 25.5

17 Side Tone Distortion Three stage distortion < 10%

18

System frequency

2.5ppm

(13 MHz) tolerance

19 32.768KHz tolerance 30ppm

At least 65 dBspl under below conditions:

20 Ringer Volume 1. Ringer set as ringer.

2. Test distance set as 50 cm

21 Charge Current

Fast Charge : < 430 mA
Slow Charge : < 160 mA

Antenna Bar Number Power

5 -85 dBm ~

4 -90 dBm ~ -86 dBm

22 Antenna Display 3 -95 dBm ~ -91 dBm

2 -100 dBm ~ -96 dBm

1 -105 dBm ~ -101 dBm

0~ -105 dBm

Battery Bar Number Voltage

0 3.36 ~ 3.54 V

23 Battery Indicator 1 3.55 ~ 3.66 V

2 3.67 ~ 3.72 V

3 3.73 ~ 3.84 V

4 3.85 V ~

24 Low Voltage Warning

3.55 0.03V (Call)

3.48 0.03V (Standby)

2. PERFORMANCE

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Item Description Specification

25 Forced shut down Voltage 3.35 0.03 V

1 Li-Poly Battery

26 Battery Type

Standard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 800mAh

Switching-mode charger

27 Travel Charger Input: 100 ~ 240 V, 50/60 Hz

Output: 4.8 V, 900 mA

3. TECHNICAL BRIEF

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3.1 Power Transceiver (SKY74400, U401)

The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part, a voltage
supply part, and a VCTCXO part. The SKY74400 power transceiver is a highly integrated device for
quad-band Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS),
and Enhanced Data for GSM Evolution (EDGE) handsets. The device supports GSM850, EGSM900,
DCS1800, and PCS1900 applications.
The power transceiver consists of a direct conversion receiver and power amplifier (PA) with an
integrated PA Control (iPAC) function, fully integrated into a single module. All RF inputs and outputs
of the device are fully matched to 50Ω.
The receiver path implements a direct down-conversion architecture that eliminates the need for
Intermediate Frequency(IF) components. Four integrated Low Noise Amplifiers (LNAs) are internally
matched to 50 Ω, which eliminates the need for external matching components. The receiver path also
contains a quadrature demodulator, selectable receiver baseband filter bandwidths, low droop DC­offset correction sequencer, and integrated 2nd order Intercept Point (IP2) calibration circuitry.
The SKY74400 also features an integrated, fully programmable, sigma-delta fractional-N synthesizer
suitable for EGPRS multi-slot operation. The reference frequency for the synthesizer is supplied by an
integrated Voltage Controlled Crystal Oscillator (VCXO) circuit that enables the use of a low-cost
crystal.
The VCXO also provides a buffered output to supply other devices in the system.
The transmit path uses a translation loop architecture. This architecture consists of an In-phase and
Quadrature (I/Q) modulator and a frequency translation loop to perform frequency up-conversion with
high spectral purity. The translation loop also contains a phase-frequency detector, charge pump,
mixer, programmable dividers, and high power transmit Voltage Controlled Oscillators (VCOs) with no
external tank required. The transmit loop is directly connected to the PA section of the power
transceiver, which consists of separate GSM850/EGSM900 and DCS1800/PCS1900 blocks fabricated
on a single GaAs Heterojunction Bipolar Transistor (HBT) die, impedance matching circuitry for 50 Ω
output, and a custom BiCMOS PA control block with an internal current-sense resistor.

• Receive section. Includes four integrated LNAs with 50 Ωinputs, quadrature demodulator circuitry
that performs direct down-conversion, baseband amplifier circuitry with I/Q outputs, baseband filter
with programmable bandwidths, five stages of DC offset correction, and IP2 calibration circuitry.

• Synthesizer section. Includes an integrated VCO locked by a fractional-N synthesizer loop, a crystal
oscillator to supply the reference frequency, a reference frequency output buffer, and an integrated
loop filter.

• Transmit section. The transmit section is designed with a translation loop architecture that consists of
an I/Q modulator, integrated high power VCOs, offset mixer, programmable divider,
Phase/Frequency Detector (PFD), charge pump, and loop filter. The transmit section also includes a
PA for GSM850/EGSM900 and DCS1800/PCS1900 operation with common power supply pins, 50

Ω
output impedance matching circuitry, and a Power Amplifier Controller (PAC) block with an internal
current-sense resistor.

3. TECHNICAL BRIEF

3. TECHNICAL BRIEF

- 16 -

Figure. 3-1 SKY74400 FUNCTIONAL BLOCK DIAGRAM

3. TECHNICAL BRIEF

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(1) Receiver Part

A. LNA and Quadrature Demodulator

Four separate LNAs are integrated in the SKY74400 to address different bands of operation. These LNAs
have separate singleended 50 Ω inputs. The LNA gain is switchable between high and low settings using
the three-wire bus. The LNA outputs feed into a quadrature demodulator that downconverts the RF signals
directly to baseband. The baseband I and Q paths consist of cascaded amplifiers and low pass filter
sections. The baseband section provides eight programmable bandwidth settings ranging between 90 kHz
and 160 kHz to allow for added flexibility when interfacing to any mixed signal baseband device.
No external capacitors are required for baseband filtering. The filter chain consists of two fixed real poles,
two fixed conjugate pole pairs, and one programmable conjugate pole pair. The result is a flat passband
with minimal group delay distortion at any bandwidth setting.

B. DC Offset Correction

Five DC offset correction loops ensure that DC offsets generated in the SKY74400 do not overload the
baseband chain at any point. After correction, the corrected voltages are held digitally for the duration of the
receive slot(s). The positive edge of the RXENA signal starts the digital DC offset correction. Since the
correction is digital, a system clock is required.
To generate the clock, the reference frequency is divided down internally. A special, fast DC offset
correction is carried out every time the receiver gain is programmed while RXENA is high. This ensures that
a DC offset correction is complete in the time available, even if the gain is changed between slots in
multislot mode.

C. AM Suppression and IP2 Calibration

For direct conversion GSM applications, it is imperative to have extremely low second-order distortion.
Mathematically, secondorder distortion of a constant tone generates a DC term proportional to the square of
the amplitude. In general, a strong interfering Amplitude Modulated (AM) signal is, therefore, demodulated
by second-order distortion, which generates an Acinterfering baseband signal. The SKY74400 can
effectively handle such AM-modulated interferers. A commonly used measure for receiver second-order
distortion is the second-order intercept point, IP2. For example, to ensure that the unwanted baseband
signals are 9 dB below the wanted signal required under the AM suppression test for type approval (see
3GPP TS 51.010-1), an input IP2 of 43 dBm is required. The SKY74400 RF transceiver includes a circuit
that minimizes second-order distortion. This IP2 calibration circuit effectively compensates for any second­order distortion in the receive chain that would otherwise generate unwanted baseband signals in the
presence of strong interfering signals. When calibrated correctly, the SKY74400 IP2 meets the GSM AM
suppression test requirements in all bands with good margin.
A one-time factory calibration procedure produces a set of I/Q compensation coefficients that are
programmed in the device to minimize the DC voltage shift resulting from the second-order distortion. The
IP2 performance is optimized when the DC due to the interfering signal is minimized.
The determined coefficients are transmitted to the serial interface, stored in nonvolatile memory, and
programmed to the SKY74400 upon each power-up as part of device initialization. The optimization process
is performed internal to the SKY74400.

3. TECHNICAL BRIEF

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D. Flexible Receiver Bandwidth Control

The receive baseband filters have programmable bandwidths with eight possible settings.

(2) Synthesizer Section

The SKY74400 includes a fully integrated UHF VCO and 3rd order loop filter. A single sigma-delta
fractional-N synthesizer phaselocks the Local Oscillator (LO) used in both transmit and receive paths to a
precision frequency reference input. Fractional-N operation offers low phase noise and fast settling times,
allowing for multiple slot applications such as GPRS.
The SKY74400 frequency stepping function with a 3 Hz resolution allows quad band operation in both
transmit and receive bands using a fully integrated UHF VCO. The fine synthesizer resolution allows direct
compensation or adjustment for reference frequencyerrors.
The generated frequency is given by the following equation:

where: fvco = Generated VCO frequency
N = N-divider ratio, integer part
FN = Fractional setting
R = R-divider ratio
fref = Reference frequency

A. UHF VCO Frequency Setting

To tune the receiver’s receive frequency (fRX), the VCO frequency (fVCO) is set according to the following
equations:

GSM850/EGSM900:

DCS1800/PCS1900:

B. Digital Frequency Centering

The SKY74400 re-centers the UHF VCO frequency range each time the synthesizer is programmed. This
proprietary Skyworks technique, called Digital Frequency Centering (DFC) extends the VCO frequency
coverage, speeds up settling time, and ensures robust performance since the VCO is always operated at
the center of its tuning range. Each time the synthesizer is programmed, the DFC circuit is activated and the
VCO is centered to the programmed frequency in less than 20 µs. After this, normal Phase Locked Loop
(PLL) operation is resumed and the fine settling of the frequency is finalized. DFC typically adjusts the VCO
center frequency to within a few MHz and no more than 5 MHz offset, and presets the tuning voltage to the
center of the range before the PLL takes over.

3. TECHNICAL BRIEF

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This speeds up frequency settling and ensures that the PLL control voltage never operates close to the
rails. DFC is the result of an adaptive circuit that corrects for any VCO center frequency errors caused by
variations of the integrated VCO circuit such as temperature, supply voltage, or aging. The VCO can be
centered at any frequency in the range from 990 MHz to 1550 MHz. Once centered, the VCO has a
minimum analog tuning range of 20 MHz. No calibration or data storage is needed for DFC operation. It is
activated by one of two events:

• When the synthesizer is programmed, the rising edge of the LE signal starts the DFC cycle

• When the SXENA signal level is changed from low to high, which enables the synthesizer, the rising edge
of the SXENA signal starts the DFC cycle.

C. Integrated Loop Filters

Both loop filters (for the UHF PLL and for the transmit PLL) are fully integrated. Several adjustments can be
made to the loop filter transfer functions. The UHF loop filter has two synchronized charge pumps. The
frequency of the “zero“ factor (z1) in the PLL phase transfer function can be adjusted by varying the charge
pump currents, and the values of the internal R3 resistor and C3 capacitor.
Charge Pump Current Compensation for Constant PLL Bandwidth The VCOs in the SKY74400 use
Skyworks DFC technique. The nature of the DFC circuit increases the VCO control sensitivity (KVCO) as

the VCO frequency is increased. Without any compensation, this leads to an increase in the PLL loop gain
and an increased loop bandwidth for higher frequencies. In a classical PLL design, KVCO is typically
regarded as a constant. In this case, the loop gain decreases with increased frequency as the division ratio
of the loop is increased proportionally to frequency. Since it is usually desirable to keep the loop bandwidth
constant over the frequency range of interest, the SKY74400 includes a circuit that compensates the charge
pump current to keep the overall loop gain constant.
Charge pump current compensation for the UHF PLL can be programmed to one of three settings (nominal,
high, or low) or the charge pump current can be programmed to a constant value without compensation.
Refer to the Skyworks Programming Guide SKY74117 RF Transceiver for Standalone Devices or
Embedded MCMs for details.

D. Crystal Oscillator

A 26 MHz crystal oscillator provides the reference frequency for the synthesizer. the oscillator uses an
external 26 MHz crystal to generate an accurate oscillation frequency. The reference frequency can be
changed through coarse-tuning with an integrated capacitor array or fine-tuning with the integrated varactor
diode. The oscillator is coarse-tuned by switching in and out (using a digital word programmed with the
serial interface) the capacitor network (CAP_A and CAP_B) located at the input of the integrated buffer. The
oscillator is fine-tuned by providing a tuning voltage to the integrated varactor diode.
An output buffer is provided to drive the baseband circuitry. The frequency of the output is determined by
the FREQ_SEL signal. When this signal is connected to ground, the output is 13 MHz; when connected to
VCC or left floating, the output is 26 MHz. The oscillator core powers up when the SXENA signal is set to
logic 1.

3. TECHNICAL BRIEF

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(3) Transmitter Part

To minimize the post-PA filtering requirements and any additional post-power amp losses, the transmit
path consists of a vector modulator and a frequency translation loop. The translation loop consists of
the following:

•

PFD and charge pump

•

In-loop modulator

•

One programmable divider

•

Integrated transmit loop filter

•

Two transmit VCOs and output buffers

A. Translation Loop

The translational loop includes a vector modulator and a frequency translation loop to minimize the post-PA
filtering requirements. the loop functions as a PLL with a mixer in the feedback path and a modulator in the
reference path. The loop provides a PFD and charge pump, integrated loop filters, two transmit VCOs,
down-conversion mixer in the feedback path, a frequency divider for frequency plan flexibility, and the
modulator. The mixers in the feedback path provide either high side or low side injection to provide flexibility
in the frequency plan. The modulator in the reference path uses a vector summing technique to reject the
unwanted image and to also sufficiently attenuate the 3rd and 5th harmonics. Therefore, no external IF
filters are required. The loop filter required for the transmit VCOs is integrated in the SKY74400.

B. Transmit VCOs

Two integrated transmit VCOs are designed to meet GSM850, EGSM900, DCS1800, and PCS1900
requirements. The transmit VCOs use the same DFC technique as the synthesizer section to lock the
translation loop. The rising edge on TXENA initializes the transmit DFC. The output buffers feed the signal
to the PAs. Two transmit buffers are provided, one for the low band VCO and the other for the high band
VCO.

Figure. 3-2 Crystal Oscillator BLOCK DIAGRAM

3. TECHNICAL BRIEF

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C. Power Amplifier (PA)

The PA functionality of the SKY74400 consists of separate GSM850/EGSM900 and DCS1800/PCS1900
blocks, impedancematching circuitry for 50 Ω output impedances, and a PAC block with an internal
currentsense resistor. The custom BiCMOS integrated circuit provides the internal PAC function and
interface circuitry. Fabricated onto a single Gallium Arsenide (GaAs) die, one Heterojunction Bipolar
Transistor (HBT)
PA block supports the GSM850 and EGSM900 bands, and the other supports the DCS1800 and PCS1900
bands. Both PA blocks share common power supply pins to distribute current. The RF output ports of the
SKY74400 are internally matched to a 50 Ω load to reduce the number of external components for a quad­band design. The PA also contains band-select switching circuitry to select GSM (logic 0) or DCS/PCS
(logic 1) as determined from the BAND_SELECT signal. The VBAT pin connects to an internal current­sense resistor and interfaces to an iPAC function, which is insensitive to variations in temperature, power
supply, and process.
The ENABLE input allows initial power-on of PA circuitry to minimize battery drain.

(4) Low Drop-Out (LDO) Linear Voltage Regulators

The SKY74400 includes integrated LDO linear voltage regulators to eliminate the need for a separate
power management integrated circuit or discrete voltage regulators. Each functional block in the
SKY74400 includes a separate, internal LDO voltage regulator.

3. TECHNICAL BRIEF

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3.2 13 MHz Clock (VCTCXO, X400)

The 13 MHz clock(X400) consists of a TCXO(Temperature Compensated Crystal Oscillator) which
oscillates at a frequency of 13 MHz. It is used within the SKY74400, analog base band chipset (U100,
AD6535), digital base band chipset (U101, AD6527B).

3.3 Switchplexer for Triband(FL400)

13MHz

2V75_VVCXO

R404

100

1000p

C407

2

GND

3

OUT

4

VCC

1

VCONT

13MHz

X400

C408

1u

C405

1000p

10K

R403

AFC

Figure 3-3 VCTCXO CIRCUIT DIAGRAM

Vc1 Vc2 Vc3 Current

EGSM-Tx 0.0-0.1V 0.0-0.1V 2.3-3.0V 10mA Max

EGSM-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

DCS/PCS-Tx 0.0-0.1V 2.3-3.0V 0.0-0.1V 10mA Max

DCS-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

PCS-Rx 2.3-3.0V 0.0-0.1V 0.0-0.1V 10mA Max

Table 3-1 FEM CONTROL LOGIC

3. TECHNICAL BRIEF

- 23 -

Figure 3-4 FEM CIRCUIT DIAGRAM

ANT_SW3
ANT_SW2
ANT_SW1

27p

C415
27p

C416C414
27p

LMSP54LA-445TEMP

VC3

12

VC2

9

VC1

11

GND7

16

GND6

15

GND5

14

GND4

7

GND3

5

GND2

3

GND1

1

FL400

GSM1900_RX
GSM1800_RX

GSM900_RX

GSM18001900_TX

GSM900_TX

ANT

13

6
4
2

8
10

3. TECHNICAL BRIEF

- 24 -

3.4 Digital Main Processor (AD6527B, U101)

Figure 3-5. SYSTEM INTERCONECTION OF AD6527 EXTERNAL INTERFACE

3. TECHNICAL BRIEF

- 25 -

• AD6527 is an ADI designed processor.

• AD6527 consists of

1. Control Processor Subsystem

• 32-bit ARM7TDMI Control Processor

• 58.5 MHz operation at 1.7V

• On-board 16KB instruction/Data Cache

• 1 Mbits of on-chip System SRAM

2. DSP Subsystem

• 16-bit Fixed Point DSP Processor

• 91 MIPS at 1.7V

• 16K word Data and 16K word Program SRAM

• 4K word Program Instruction Cache

• Architecture supports Full Rate, Enhanced Full Rate, Half Rate, and AMR Speech
Encoding/Decoding Algorithms

3. Peripheral Subsystem

• Shared on-chip peripheral and off-chip interface:

• Support for Burst and Page Mode Flash

• Support for Pseudo SRAM

• Ciphering module for GPRS supporting GAE1 and GAE2 encryption algorithms

• Parallel and Serial Display Interface

• 8 x 8 Keypad Interface

• Four independent programmable backlight plus One Service Light

• 1.8V and 3.0V, 64 kbps SIM interface

• Universal System Connector Interface

• Slow, Medium and Fast IrDA transceiver interface

• Enhanced Generic Serial Port

• Dedicated SPI interface

• Thumbwheel Interface

• JTAG Interface for Test and In-Circuit Emulation

4. Other

• Supports 13 MHz and 26 MHz Input Clocks

• 1.8V Typical Core Operating Voltages

• 204-Ball LFBGA(mini-BGA) Package

5. Applications

• GSM900/DCS1800/PCS1900/PCS850 Wireless Terminals

• GSM Phase 2+ Compliant

• GPRS Class 12 Compliant

• Multimedia Services(MMS)

• Extended Messaging System(EMS)

3. TECHNICAL BRIEF

- 26 -

3.4.1 Interconnection with external devices

A. RTC block interface

Countered by external X-TAL
The X-TAL oscillates 32.768KHz

B. LCD module interface

The LCD module is controlled by AD6527B(U101),DBB.
In operating mode, the AD6527B(U103) controls the LCD module through _LCD_CS,
LCD_DIM_CTRL, LCD_RESET, _WR, 2V8_VMEM, LCD_ID, LCD_BL_EN.

Signals Description

_LCD_CS MAIN LCD driver chip enable. MAIN LCD driver IC has own CS pin

LCD_DIM_CTRL It controls dimming mode of LCD module.(GPIO_5)

LCD_RESET

This pin resets LCD module. This signal comes from DBB directly.

(GPIO 15)

_WR Enable writing to LCD Driver.

2V8_VMEM 2.8V voltage is supplied to LCD driver IC.

LCD_ID(GPIO_16) It determines the maker of LCD module.

LCD_BL_EN It controls back-light of LCD module.(GPO_23)

3. TECHNICAL BRIEF

- 27 -

The backlight of LCD module is controlled by DBB via AAT2806IXN-4.5-T1 , U402. The control
signals related to Backlight LED are given bellow.

C. RF interface

The AD6527B control RF parts through PA_BAND, ANT_SW1, ANT_SW2, ANT_SW3 , CLKON ,
PA_EN, S_EN, S_DATA, S_CLK, RF_PWR_DWN.

Signals Description

LCD_DIM_CTL

Control LCD backlight level in 16 steps

(GPO 5)

LCD_LED_CTL Control LCD LED

LCD_LED_GND

LCD_BL_EN It controls back-light of LCD module.(GPO_23)

Table 3-3. DESCRIPTION OF LCD BACKLIGHT LED CONTROL

Signals Description

PA_BAND (GPO 17) PAM Band Select

ANT_SW1 (GPO 9) Antenna switch Band Select

ANT_SW2 (GPO 10) Antenna switch Band Select

ANT_SW3 (GPO 11) Antenna switch Band Select

CLKON RF LDO Enable/Disable

PA_EN (GPO 16) PAM Enable/Disable

S_EN (GPO 19) PLL Enable/Disable

S_DATA (GPO 20) Serial Data to PLL

S_CLK (GPO 21) Clock to PLL

RF_PWR_DWN(GPO 4) Power down Input

Table 3-4. RF CONTRON SIGNALS DISCRIPTION

3. TECHNICAL BRIEF

- 28 -

D. SIM interface

The AD6527B provides SIM Interface Module. The AD6527 checks status periodically during
established call mode whether SIM card is inserted or not, but it doesn't check during deep Sleep
mode. In order to communicate with SIM card, 3 signals SIM_DATA, SIM_CLK, are required. The
descriptions about the signals are given by bellow Table 3-6 in detail.

E. Key interface

Include 5 column , 5 row and additional GPIO 35 for KEY_ROW5. The AD6527B detects whether
key is pressed or not by using interrupt method.

F. AD6535 Interrupt

AD6535 provides an active-high interrupt output signal. Interrupt signals are generated by the
Auxiliary ADC, audio, and charger modules.

Signals Description

SIM_DATA

This pin receives and sends data to SIM card.

This model can support only 3.0 volt interface SIM card.

SIM_CLK Clock 3.25MHz frequency.

SIM_RST

Reset SIM block

(GPIO_23)

Figure 3-6. SIM Interface of AD6527B

2V85_VSIM

1
2
3
78

VA202

C210

C209

C204
220n

1000p

22p

EVLC18S02003

SIM_RST
SIM_CLKSIM_DATA

VA201

EVLC18S02003

2V85_VSIM

R202
20K

J201

4

VCC

GND

5

RST

VPP

6

CLK

I_O

GND1

GND2

3. TECHNICAL BRIEF

- 29 -

3.4.2 AD6527B Architecture

The internal architecture of AD6527B is shown above Figure 3-7. AD6527 regroups three main subsystems
connected together through a dynamic and flexible communication bus network. It also includes onboard
system RAM (SRAM) and interfaces with external Flash Memory, Baseband converter functions, and
terminal functions like MMI, SIM and Universal System Connector (USC).
The Digital Signal Processing (DSP) subsystem primarily hosts all the speech processing, channel
equalization and channel codec functions. The code used to implement such functions can be stored in
external Flash Memory and dynamically downloaded on demand into the DSP’s program RAM and
Instruction Cache.
The micro-controller subsystem supports all the GSM terminal software, including the layer 1, 2 and 3 of the
GSM protocol stack, the MMI, and applications software such as data services, test and maintenance. It is
tightly associated with on-chip system SRAM and also includes boot ROM memory with a small dedicated
routine to facilitate the initialization of the external Flash Memory via code download using the on-chip serial
interface to the external Flash Memory interface.
The peripheral subsystem is composed of system peripherals such as interrupt controller, real time clock,
watch dog timer, power management and a timing and control module. It also includes peripheral interfaces
to the terminal functions: keyboard, battery supervision, radio and display. Both the DSP and the MCU can
access the peripheral subsystem via the peripheral bus (PBUS).
For program and data storage, both the MCU subsystem and the DSP subsystem can access the on chip
system SRAM and external memory such Flash Memory. The access to the SRAM module is made through
the RAM Bus (RBUS) under the control of the bus arbitration logic. Similarly, access to the Flash Memory is
through the parallel External Bus (EBUS).

Figure 3-7. AD6527B Architecture

3. TECHNICAL BRIEF

- 30 -

3.5 Analog Main & Power Management Processor
(AD6535, U100)

Figure 3-8. AD6535 FUNCTIONAL BLOCK DIAGRAM

3. TECHNICAL BRIEF

- 31 -

• AD6535 is an ADI designed Analog Baseband processor. AD6535 covers the processing GMSK
modulation interface, Aux ADC, Voice signal processing and Power Management.

• AD6535 consists of

1. BB Transmit section

• GMSK Modulation

• I-channel & Q-channel Transmit DACs and Filters

• Power Ramping DAC

2. BB Receive section

• I-channel & Q-channel Receive ADCs and Filters

3. Auxiliary section

• Voltage Reference

• Automatic Frequency Control DAC

• Auxiliary ADC

• Light Controllers

4. Audio Section

• 8 kHz & 16 kHz Voiceband Codec

• 48 kHz Monophonic DAC

• Power Amplifiers

5. Power Management section

• Voltage Regulators

• Battery Charger

• Battery Protection

6. Digital Processor section

• Control, Baseband, and Audio Serial Ports

• Interrupt Logic

3. TECHNICAL BRIEF

- 32 -

3.5.1 Baseband Transmit Section

1. The AD6537B Baseband Transmit Section is designed to support GMSK for both single-slot and
multi-slot application.

2. The AD6535 includes a digital GMSK modulator which is used for GSM application. The GMSK
modulator uses a ROM lookup table to modulate the serial data stream ffrom the BSPORT. The
GMSK modulator is based on 3GPP TS 45.004 ver.5.1.0 Release 5

3.5.2 Baseband Receive Section

1. This section consists of two identical ADC channels that process baseband in-phase(I) and
quadrature(Q) input signals.

Figure 3-9. AD6535 BASEBAND TRANSMIT SECTION

Figure 3-10. AD6535 BASEBAND RECEIVER SECTION

3. TECHNICAL BRIEF

- 33 -

3.5.3 Auxiliary Section

1. This section includes an Automatic Frequency Control(AFC) DAC, voltage reference buffers, an
Auxiliary ADC, and light controllers.

• AFC DAC: 13 bits

2. This section also contains AUX ADC and Voltage Reference

• IDAC: 10 bits

• The Auxiliary ADC provides :

- Two differential inputs for temperature sensing.

- A differential input for the battery charger current sensor

Figure 3-11. AD6535 AUXILIARY SECTION

3. TECHNICAL BRIEF

- 34 -

3.5.4 Audio Section

1. The AD6535 Audio section supports communications and personal audio applications.

2. The Audio Section provides an audio codec with two digital-to-analog converter, a ring tone
volume controller, a microphone interface, and analog input and output channels.

Figure 3-12. AD6535 AUDIO SECTION

3. TECHNICAL BRIEF

- 35 -

3.5.5 Power Management

1. Power up sequence logic

1. The AD6535 controls power on sequence

2. Power on sequence

- If a battery is inserted, the battery powers the 8 LDOs.

- Then if PWRONKEY is detected, the LDOs output turn on.

- REFOUT is also enabled

- Reset is generated and send to the AD6527B

Figure 3-13. AD6535 POWER MANAGEMENT SECTION

2. LDO Block

1. There are 8 LDOs in the AD6535.

- VCORE : supplies Digital baseband Processor core and AD6535 digital core

- VMEM : supplies external memory and the interface to the external memory on the digital

baseband processor (1,8V or 2.8V, 150mA)

- VEXT : supplies Radio digital interface and high voltage interface (2.8V, 170mA)

- VSIM : supplies the SIM interface circuitry on the digital processor and SIM card

(2.85V, 20mA)

- VRTC : supplies the Real-Time Clock module (1.8 V, 20 µA)

- VABB : supplies the analog portions of the AD6537B

- VMIC : supplies the microphone interface circuitry (2.5 V, 1 mA)

- VVCXO : supplies the voltage controlled crystal oscillator ( 2.75 V, 10 mA)

- VBACK : charges the backup battery and supplies the RTC regulator (2.8V, 1.8V)

- VAPP : supplies application co-processors such as a touch screen digitizer (3.0V, 1.8V)

- VUSB : supplies the USB interface.

- 36 -

3. TECHNICAL BRIEF

Figure 3-14. AD6535 POWER MODE LOGIC

3. TECHNICAL BRIEF

- 37 -

3.6 Charging IC (ISL6299, KEY PCB U201)

The ISL6299 is designed for a single-cell Li-ion or Li-polymer battery charging circuit that accepts both a
USB port and a desktop cradle as its power source.

Input Auto Selection

When both input sources are present, the charger selects only one power source to charge the battery.
When the CRDL input is higher than the POR threshold, CRDL is selected as the power source. Otherwise
the USB input is selected. If the CRDL input voltage is below the battery voltage but the USB input voltage
is higher than the battery voltage, then the USB input is used to charge the battery. The control circuit
always breaks both internal power devices before switching from one power source to the other to avoid a
cross conduction of both power MOSFETs.

USB Charge Current

When the USB port is selected as the power source, the charge current enabled by the logic input at the
USBON pin. When the USBON is driven to logic LOW, the charger is disabled. When the USBON is driven
to logic HIGH, the charge current is fixed at a typical value of 380mA. Thus for the USB input, the USBON
pin has a similar function as the EN pin. The following table describes the USB charge control by both the
USBON pin and EN pin The USBON pin is equivalent to a logic LOW when left floating. Typically the P­channel MOSFET for the USB input has an rDS(ON) of 700m at room temperature. With a 380mA charge
current, the typical head room is 260mV. Thus, if the input voltage drops to a level that the voltage
difference between the USB pin and the BAT pin is less than 260mV, the rDS(ON) becomes a limiting factor
of the charge current; and the charger drops out the constant current regulation.

Figure 3-15. CIRCUIT FOR BATTERY CHARGING

VUSBIN

VCHARGE

2V8_VMEM

VBAT

BAT

_PPR

_CHG

GND

PGND

10

C216

R208

1u

10K

3
4

8
11

CHG_STAT

CUR_MON

CHG_EN

R212

R210 C218

30K

(1%)

100K

R209
10K

R213

10K

C217

1u

1

CRDL

2

USB

U201

6

IMIN

9

ICDL

7

USBON

5

_EN

ISL6299

R211

100K

1u

3. TECHNICAL BRIEF

- 38 -

Cradle Charge Current

The cradle charge current is enabled by the EN pin only, the USBON pin has no control on the cradle
charge current. The cradle charge current is programmed with the external resistor connected
between the ICDL pin and the GND pin. The current can be calculated with one of the equations given
in the ICDL pin description. Two equations are used for the cradle current calculation, each
corresponds to a different range of currents. The typical rDS(ON) of the P-channel MOSFET for the
CRDL input is 600mΩ at room temperature. When the head room between the input and output
voltages is small, the actual charge current, similar to the USB case, could be limited by the rDS(ON).
On the other hand, if the head room between the input and output voltages is large, the charge current
may be limited by the thermal foldback threshold.

Floating Charge Voltage

The floating voltage during the constant voltage phase is 4.2V. The floating voltage has an 1%
accuracy over the ambient temperature range of -40˚C to 70˚C.

Figure 3-15. BLOCKDIAGRAM

3. TECHNICAL BRIEF

- 39 -

Trickle Charge Current

When the battery voltage is below the minimum battery voltage VMIN given in the electrical specification,
the charger operates in a trickle/preconditioning mode, where the charge current is typically 14% of the
programmed charge current for the cradle input. If power comes from the USB input, the trickle mode
current is approximately 53mA.

End-of-Charge Indication

threshold, which is programmable for the cradle input and fixed for the USB input. Once the end-of charge­current is reached, the CHG status will be latched. The latch can be reset at one of the following conditions:

1. The part is disabled and re-enabled

2. The selected input source has been removed and reapplied

3. The USBON turns LOW and turns back to HIGH for the USB input

4. The BAT pin voltage falls below the CV mode threshold
Regardless of the CHG pin status, however, the charger does not turn off as long as an input power source
is attached.

Power Presence Indication

When either the USB or the cradle input voltage is above the POR threshold, the PPR pin internal open­drain MOSFET turns on indicating the presence of input power.

Power-Good Range

Even if there is a power present, the charger will not deliver any current to the output if the powergood
conditions are not met. The following two conditions together define the power-good voltage range:

1. VCDRL or VUSB > VPOR

2. VCDRL or VUSB - VBAT > VOS
where the VOS is the offset voltage for the input and output voltage comparator, discussed shortly.
Both VPOR, VOS have hysteresis, as given in the Electrical Specification table.
The charger will not charge the battery if the input voltage does not meet the power-good conditions.

Thermal Foldback (Thermaguard™)

The thermal foldback function reduces the charge current when the internal temperature reaches the
thermal foldback threshold, which is typically 100˚C. This protects the charger from excessive thermal stress
at high input voltages.

3. TECHNICAL BRIEF

- 40 -

3.7 CAMERA IC(AIT811, MAIN ,U202)

Figure 3-15. AIT811 APPLICATION BLOCKDIAGRAM

3. TECHNICAL BRIEF

- 41 -

3V3_MULTI_USB

Figure 3-24. AIT811 CIRCUIT

C211
1u

C212

_LCD_CS _RD

33p

2V8_MV

100K

MULTI_BYPASS

ADD01

_MULTI_INT

_WAIT

13MHz

R202

2V8_MV

R205

75K

_MULTI_RST

MULTI_USB-

MULTI_USB+

_WR

DATA00
DATA01
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15

TP200

C222 1000p

2V8_MV

C223
1u

A3
A2
A1
B3
B2
B4
B5
B1

B6
C1
C2
C3
D1
C4
C5
D2
D3
E1
D5
E2
A7
E3
B7
E4

F1
F2

C7
D6

F3

G1

F4
G2
A5
C6
D4

PUSBDN
PUSBDP
VDD_IO3

_PHCS
_PHRD
_PHWE
_PRST

PHD0
PHD1
PHD2
PHD3
PHD4
PHD5
PHD6
PHD7
PHD8
PHD9
PHD10
PHD11
PHD12
PDH13
PHD14
PHD15
PHD16
PHD17

PHLCD_BY
PHLCD_A0
_PHLCD2_CS
PHINT
_PHGPIO_CS
_PHWAIT
PMCLK
VDD_IO0
GND_IO0

PHSYNC

F5

C_HS

F12

G11

PCONFIG1

PCONFIG2

PD0

PVSYNC

G3

G4

C_VS

A8

K9

PCONFIG0

PSCAN_EN

PD1

PD2

H1

H2

C_CD00

C202

39p

A4

A9

VSS_PLL

PTEST_EN

PD3

PD4

H4

G5

C_CD02

C_CD01

2V8_MV

C203

1u

A6

H7

VDD_PLL

PD5

J1

C_CD03

C204

39p

J8

E8

SVSS2

SVDD_IO

PD6J2PD7J4PD8

K2

C_CD05

C_CD04

E7

SVDD

SVSS1

PD9

K1

C_CD07

C_CD06

1V8_MV

C205

1u

H6

E5

VDD_CORE1H8VDD_CORE2

GND_CORE1

GND_CORE2

C_SDA

CAM_PWR_EN

E6

L1

K11

PSCKJ5PSDAJ3PSEN

J6

C_SCK

2V8_AMV

J10

K12

AVSS

AVDD

U202

AIT811T

PPXL_CLK

PDCLK

H3

M2

C_PCLK

C_MCLK

I2S_SCK

I2S_WS

I2S_SDO

H11

G12

PI2S_WS

PI2S_SCK

PI2S_SDO

VDD_IO1

GND_IO1

H5

C200

1u

J12

M11

POUT1_P

POUT1_N

PLCD0

PLCD1

L2

M1

L_DATA00

L_DATA01

C201

39p

H12

L11

M10

POUT0_P

POUT0_N

PLCD2M3PLCD3K3PLCD4

L3

L_DATA02

L_DATA03

0.1u

C208

L10

K10

J11

PVREF_P

PVREF_N

PMIC_BIAS_P

PMIC_BIAS_N

PLCD5K4PLCD6

PLCD7

J7

L4

L_DATA04

L_DATA05

L_DATA06

L_DATA07

N_IO(3)

N_IO(7)

N_IO(5)

N_IO(6)

N_IO(4)

MULTI_MIC_P

MULTI_MIC_N

0.01u

C207

C206

0.01u

L12

M12

A10

B9

C8

D7

B8

PVIN_P

PVIN_N

PGPIO26

PGPIO27

PGPIO28

PGPIO29

PLCD8

PLCD9

K6

K5

L_DATA08

L_DATA09

PGPIO30

PLCD10

PLCD11K7PLCD12

L5

M4

L_DATA10

L_DATA11

PLCD13K8PLCD14

L_DATA12

L_DATA13

_PLCD2_CS
_PLCD1_CS

_PLCD_WE

PLCD15

L6

M5

L_DATA14

L_DATA15

PGPIO25
PGPIO24
PGPIO23GND_IO3
PGPIO22
PGPIO21
PGPIO20
PGPIO19
PGPIO18
PGPIO17
PGPIO16
PGPIO15
PGPIO14
PGPIO13
PGPIO12
PGPIO11
PGPIO10

PGPIO9
PGPIO8
PGPIO7
PGPIO6
PGPIO5
PGPIO4
PGPIO3
PGPIO2
PGPIO1
PGPIO0

GND_IO2

VDD_IO2

_PLCD_RD

PLCD_A0

PLCD17
PLCD16

D8

N_IO(2)

C9

N_IO(1)

B10

N_IO(0)

D9

_N_WP

C10

_N_WE

A11

N_ALE

A12

N_CLE

B11

_NAND_CS

C11

_N_RE

E9

R_B

F9
D10

VSYNCOUT

B12
E10
D11

C_RST

C12
F10
G9
E11
D12
H9
G10
F11
H10
E12
J9

F8
G8
M8
M9
M7
L9
L8
M6
L7

C224
39p

2V8_MV

R204

C225
1u

NA

2V8_MV

C219

C218

1u

39p

L_MAIN_LCD_CS

LCD_RS
LCD_WR

3.8 MIDI IC(YMU787,U300)

Figure 3-24. YMU787 BLOCKDIAGRAM

3. TECHNICAL BRIEF

- 42 -

3. TECHNICAL BRIEF

- 43 -

CPU INTERFACE

CPU interface is an 8-bit parallel.
4 control signal(/wr,/rd,/cs,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ), totaling 13 pins are
connected to the external CPU. This block controls the writing and reading of data by the input polarity
of control signal

INTERFACE REGISTER

This registeris able to access directly ffrom the external CPU. There are 2 bytes spaces. The
Intermediate register can be accessed through the interface register.

INTERMEDIATE REGISTER

This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register.
This register is called “Intermediate register” since this exists in the middle of the interface register and
the Control register.
In the Intermediate register, there are some registers to control various functions.

C324

Figure 3-24. YMU787 CIRCUIT DIAGRAM

1V8_MV

0.1u

100p
C300

82K

82K

R301

R300

C301

1000p

27K

_MIDI_IRQ

DATA12

DATA11

DATA10

DATA09

DATA08

TP300

H2D0G3D1G2

F3

G1

D4

D2

D3

_IRQ

B4

_MIDI_RST

13MHz

I2S_SCK

I2S_WS

I2S_SDO

2V8_MV

R312

0

C327

C325

0.1u

1u

_RST

1000p

G5

CLKI

C307

D2

BLCK

D3

LRCK

D1

SDI

D6

GPIO0

C5

GPIO1

C1

GPIO2

C4

GPIO3

B1

LED2_GPIO5

C2

LDE1_GPIO4

C3

LED0

B2

MTR

VBAT

C328

C330

C329

0.1u

1u

1u

IOVDD1

H1

C326

10u

B3

IOVDD2

DVSS1

DVDD1J4DVDD2

J3

A2

D4

DATA14

DATA13

D5F2D6E3D7

DVDD3

F1

E2

DATA15

DVSS2

A3

_WR

_RD

H4

J2

G4

_RD

_WR

U300

YMU787

AVDD

DVSS3

E1

G8

ADD00

A0

F8

AVSS

_MIDI_CS

H3

_CS

SPVDDL

A6

R305

R307

0.01u

3.3K

C304

B6

B5

J5

A4

G6

A5

H5

C6

RXIN

PLLC

EQ1L

EQ2L

EXTIN

SPVSSL

SPVSSR1

SPVSSR2

SPVDDR

J7

J6

H7

A7

H6

EQ3L

EQ1R

EQ2R

EQ3R

B8

SPOUT2L

B7

SPOUT1L

H8

C311

SPOUT2R

J8

SPOUT1R

E8

TXOUT

D7

EXTOUT

G7

EXC

E6

BBL

C8

HPOUTL

E7

BBR

C7

HPOUTR

VREF

NC1

NC2J1NC3

HPVSS

HPC

F7

F6

A1

A8

D8

C323

C322

1u

0.1u

C312

47p

47p

C316

C317

C315

0.1u

1u

0.1u

SPK_N

C310

470p

R311

3.3
SPK_P

MIDI_HP_L

MIDI_HP_R

3. TECHNICAL BRIEF

- 44 -

CONTROL REGISTER;ROM/SRAM

The Control register and ROM/SRAM are accessed from”Instantaneous write register”,”Delayed write
register”, and “Instantaneous read register”in the intermediate register.
In the control register, there is a register to control the following synthesizer mainly.
The voice parameter for FM(GM 128 voices+DRUM 40 voices)and wave data for WT are stored in
ROM. SRAM is used at the download of arbitary FM voice parameter and Wave data for WT.
moreover, it is used as storing buffer at the stream playback of PCM/ADPCM.

FIFO

This is an abbreviation of “First Input First Output” means the memory from which data is read in order
of data written.
There are 2 paths to write into FIFO in the Intermediate register.The”instantaneous write path” is for
accessing the control register and ROM/SRAM immediately,also “Delayed write path”is for accessing
the control register after managing time through the sequencer.FIFO size of Instantaneous path is 64
byte, and its size of Delayed path is 512-byte.

SEQUENCER

This is for interpreting the contents of data which is written into the “Delayed write path” Generally,
“Music data” is written into the Delayed write path. It interprets the contents of music data and controls
the synthesizer after sequencer, and then plays the music.

Hybrid synthesizer

This device contains a built in polyphonic synthesizer that adopts a stereophonic hybrid system that
generate up to 64tones.
FM synthesizer, WT synthesizer, stream playback, HV synthesizer, and AL synthesizer are available.

DIGITAL AUDIO INPUT INTERFACE

This is a three wires type serial interface.The data length is 16bits.

DPLL SECTION/SAMPLING RATE CONVERTER SECTION

Sampling frequencies of signals from the digital audio interface section are changed into 48Khz.

DIGITAL EQUALIZER SECTION

This is a digital equalizer. Voice of signals from the Hybrid Synthesizer section and voice of digital
audio signals are adjusted.

DVX ARITHMETIC CONTROL

Two-channel virtual speaker image function that is based on DVX technology makes it possible to
create natural stereo sound under the two closely spaced speakers.

OVER SAMPLING FILTER

4 Times of over sampling filter. It converts a signal of sampling frequency 48Khz into a signal of
192Khz,and then send to DAC

GENERAL PARALLEL I/O PORT SECTION(GPIO)

There are six general parallel I/O ports. It is possible to read and write from the Intermediate register.

3. TECHNICAL BRIEF

- 45 -

LED,VIBRATOR CONTROL

It is possible to synchronize an LED and vibrator with a play, and to control. Asynchronous control
With a play is also supported. It supports 3 color LED control and it is possible to display 7 colors In
maximum.

CLOCK GENERATING BLOCK

This device supports a clock input ranging from 1.5Mhz to 27Mhz.
It is a block to generate a clock which is needed inside of LSI in the PLL.

DAC

It converts digital signals from a synthesizer and a digital audio section into analog signals.
Its resolution is 16bits.

ANALOG LINE INPUT SECTION(EXTIN,RXIN)

External audio signal and receiver audio signal are inputted.
There is a Volume to adjust the level in each.

MIXER SECTION

Selection of an input source(DAC output, RXIN, and EXTIN) against each analog output(SPOUT,
HPOUT,EXTOUT,TXOUT) and mixing are performed.

EQ AMPLIFIER SECTION

The change of filter characteristic and gain is possible by adjusting the resistors and external parts.

SPEAKER AMPLIFIER SECTION

The two digital speakers amplifier, which has a maximum output power of 500mW at SPVDDL/R=3.6V
and RL=8ohm, is integrated in this device. There is a volume to adjust output level in the first stage of
amplifier.

HEADPHONE AMPLIFIER SECTION(HPOUT)

This is an amplifier for stereophonic headphone(RL=16ohm)output.
When it is used as a monaural output, Rch becomes power-down.
In the previous part of it, there are a volume and a bass-boost circuit.

EXTERNAL OUTPUT AMPLIFIER SECTION(EXTOUT)

This is an amplifier for external output(RL=600ohm)
In the previous part of it, there is a volume to adjust the output level

ANALOG LINE OUTPUT SECTION(TXOUT)

This is monaural line output(RL=10kohm)
There is a volume to adjust the output level.

3. TECHNICAL BRIEF

- 46 -

3.9 Keypad Switches and Scanning

Figure 3-27. Keypad Switches and Scanning

NUMERIC KEY MATRIX

CN101

VOLUME

DOWN

UP

4

END

MP3

123

12345

CN102

KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW3

KEY_ROW4

KEY_COL0
KEY_COL1
KEY_COL2

SW101

1

SW104

4

SW107

7

SW110

*

PG05DBTFC

VA101

SW102

2

SW105

5

SW108

8

SW111

0

PG05DBTFC

VA102

SW103

3

SW106

6

SW109

9

SW112

#

15P

PG05DBTFC

VA103

R102

10K

VBAT

680

R103

POWERKEY

3.10 Microphone

The microphone is placed to the rear cover and contacted to top of Key PCB. The audio signal is
passed to AIN1P and AININ pins of AD6535. The voltage supply VMIC is output from AD6535, and is
a biased voltage for the AIN2P. The AIN2P and AIN2N signals are then A/D converted by the
voiceband ADC part of AD6535.The digitized speech (PCM 8KHz ,16KHz) is then passed to the DSP
section of AD6527B for processing (coding, interleaving etc).

3.11 Main Speaker

3. TECHNICAL BRIEF

- 47 -

Figure 3-28. Connection between Microphone and AD6535

E8

TXOUT

B7

SPOUT1L

SPOUT1R

J8

B8

SPOUT2L

H8

SPOUT2R

H6

EQ3R

EXTOUT

D7

EQ1R

EQ2R

G6

3.3

R311

C311

47p 47p

C312

470p

C310

SPK_N

SPK_P

2V5_VMIC

R201

1K

C201

C202

R204

2.2K

39p

2.2K

R207

C214
NA

47u

C212

39p

C215
NA

VA204

EVLC18S02003

MIC201

1
2

SMA-568-0C-R2

VA205

EVLC18S02003

VINNORP

VINNORN

C211

39p

R205

100

R206

100

C213

0.1u

3. TECHNICAL BRIEF

- 48 -

3.12 IO Interface

LG-KG90 has only one I/O interface, 18pin MMI Connector, which is connected with Charger, Ear-Mic
and USB cable.
U310 is Quad Analog Switch, it change signal paths depend on connecting what.

USC4
USC5

C336

2V8_VEXT

1u

HEADSET_SPK_L

HEADSET_SPK_R

MULTI_USB+

MULTI_USB-

A1
C1
B1

B4
B2
B3

NO1
NO2
VCC

GND
EP1
EP2

JACK_DETECT

C331

USB+

USB-

MAX4764EBC+TU402

COM1
COM2

C313

C314 220u

RPWRON

DEBUG_TX
DEBUG_RX

1u

C4

A4

C1

A1

2V8_VEXT

A4

IN1

C4

IN2

A2
C2
A3

NC1

C3

NC2

220u

DSR

VUSBIN

NO1

NO2

NC1

NC2

RPWRON

DBUGTX

DBUGRX

B4

V+

IN1

IN2

COM1

COM2

GND

B1

MAX4717EBC-T

HEADSET_EN

FL300

INOUT_B4

6

INOUT_B3

7

INOUT_B2

8

INOUT_B1

9

FL302

ICVE10094E300FR

10KR320

INOUT_B4

6

INOUT_B3

7

INOUT_B2

8

INOUT_B1

9

ICVE10094E300FR

USC0

VUSBIN

C2

A2

C3

A3

U302

10

G15G2

INOUT_A4

INOUT_A3

INOUT_A2

INOUT_A1

ICVE10094E300FR

5G110

G2

INOUT_A4

INOUT_A3

INOUT_A2

INOUT_A1

FL301

INOUT_B4

6

INOUT_B3

7

INOUT_B2

8

INOUT_B1

9

USB_PATH_SEL

C338

1u

4

3

2

1

4

3

2

1

10

G15G2

INOUT_A4

INOUT_A3

INOUT_A2

INOUT_A1

EAR_REM_INT

EAR_REM_ADC

C339

0.01u

USC1

VUSBIN

U307

VINC3VOUT

BYPASS

A3

LP3985IBLX-2.8

C341
1u

4

3

2

1

STF203-22-TCTU303

D+16D+IC

GND25VBUS

D-IC

2V6_JACK

C1

GND

B2

VEN

A1

AUXIN

AUXIP

3D-4

4.7K

R315

C340

1u

R304

100

R309

100

1

NC1

2

IN1_IN2

3

NO2

4

COM2

5

NC2

6

GND

7

NO3

8

COM3

17

PGND

JACK_LDO_EN

2V6_JACK

R302

1K

C302

0.1u
C305

C306

22u

39p

C309

C308

C337

27p

47n

39p

MAX4701ETE+TU301

16

COM1

15

NO1

14

V+

13

NC4

12

COM4

11

NO4

10

IN3_IN4

9

NC3

2V8_VEXT 2V8_VEXT

C342
1u

1.5K
EAR_MIC

R308

R319

EAR_MIC

NA

2V8_VMEM

VA300

PG05DBTFC

C318

1u

USC2

USB_EN

10K

R313

DG3000DBU308

B1

IN

NO

B2

COM

V+

B3

NC

GND

2V8_VEXT

R316

R317

100K

100K

VA301

PG05DBTFC

USB_EN(IN3_4)

0

1

0

R318

A1

A2

A3

VBAT

C320

C319

10u

2012

Jack_Det(IN1_2)

3.6K

VCHARGE

1u

U301

R303

1K

EAR_MICJACK_LDO_EN

HOOK_DETECT

C303

0.1u

R306

30K

CHG_DET

R310

30K

CN300

21
19

1
2
3

3 : USC0

4

4 : USC4

5

5 : USC5

6

6 : USC2

7

7 : USC1

8

9
10
11
12
13
14

14 : DSR

15
16
17
18

20
22

C321
1u

State

1

USC

D/C

USB

0

Jack_ADC

3. TECHNICAL BRIEF

- 49 -

3.13 EL DRIVER IC (D381B, KEY PCB U202)

Figure 3-30. KEY BACK LIGHT, OLED

EL DRIVER IC

VBAT

C223
1u

L201

820uH

ZD201
KDZ100VW

EL_KEY_BACKLIGHT

LOW

R214

68K

C224
47p

EL OFF

EL ONHIGH

C225
6800p

U202 D381B

1

CHF

2

CLF

3

VOUT

E

4

GND

8

V+

7

L+

6
5

L-

EL PAD

N_ALEN_CLE

C226
2200p

1608

R215
33

2012 1/4W

3. TECHNICAL BRIEF

- 50 -

3.14 MEMORY(TOSHIBA, U203)

Figure 3-30. MEMORY

R_B

2V8_VMEM

2V8_VMEM

_NAND_CS

R208

_RAM_CS1

4.7K

_ROM_CS1

ADD01
ADD02
ADD03
ADD04
ADD05
ADD06
ADD07
ADD08
ADD09
ADD10
ADD11
ADD12
ADD13
ADD14
ADD15
ADD16
ADD17
ADD18
ADD19
ADD20
ADD21
ADD22
ADD23

N_IO(0)
N_IO(1)
N_IO(2)
N_IO(3)
N_IO(4)
N_IO(5)
N_IO(6)
N_IO(7)

N_CLE

4.7K R206

N_ALE

_N_RE

_N_WE
_N_WP

RY_BYF

_RESET

_RD

_WR

_LBS
_UBS

R210

NA

TV00578003AABD

G2

A0

F2

A1

E2

A2

D2

A3

F3

A4

E3

A5

D3

A6

C3

A7

C7

A8

E7

A9

F7

A10

C8

A11

D8

A12

E8

A13

F8

A14

D9

A15

G9

A16

F4

A17

E4

A18

D7

A19

E6

A20

E9

A21

F9

A22

L6

IO1

L7

IO2

L8

IO3

L9

IO4

K9

IO5

K10

IO6

J10

IO7

H10

IO8

H1

CLE

J1

ALE

C1

RY__BYN

D1

_REN

E1

_CEN

K1

_WEN

K2

_WPN

H3

_OE

C6

_WE

C4

_LB

D4

_UB

J2

_CE1PS

D6

CE2PS

H2

_CEF

E5

RY__BYF

C5

_WP_ACC

D5

_RESET

U203

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VCCF1
VCCF2

VCCPS

VCCN1
VCCN2

VSS1
VSS2
VSS3
VSS4

NC1

NC2

NC3

NC4

NC5

NC6

NC7

NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34

J3
G4
K4
H5
H6
K7
G7
J8
K3
H4
J4
K5
J7
H7
K8
H8

H9
J5

J6

F1
F10

G1
G3
G10
J9

A1
A2
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C2
C9
C10
D10
E10
F5
F6
G5
G6
G8
K6
L1
L2
L3
L4
L5
L10
M1
M2
M9
M10

R207

0

DATA00
DATA01
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15

2V8_VMEM

1u

C213

_ROM_CS2

27pC214

2V8_VMEM

1uC216

C215 1u

3. TECHNICAL BRIEF

- 51 -

3.15 BLUETOOTH(LBMA-2C67B2, KEY PCB, M101)

Figure 3-30. BT MODULE

(BT ANT -> TRANSFER TO FETCH ANT)

3.3nHR101

ANT1

GND1

_BT_RST

C103

NA

SPI101
SPI102
SPI103
SPI104

( 903015 )

M101 LBMA-2C67B2

16

RESETB

1

PIO0

2

PIO1

7

PIO2

8

PIO3

9

PIO4

10

PIO5

28

NC

13

SPI_CLK

14

SPI_CSB

12

SPI_MOSI

15

SPI_MISO

5

VDD_1_8V

ANT

VDD_VREGIN

UART_RTS
UART_CTS

PCM_OUT

PCM_SYNC

PCM_CLK

VDD_DIG

GND1
GND2
GND3
GND4

UART_TX
UART_RX

PCM_IN

C101
NA

22
21
3

4
6
11
25

27
24
23
26

19
17
18
20

L101 22nH

R110
100K

C102

NA

C105

15p

R104
47K

2V8_VBT

DEBUG_RX
DEBUG_TX

PCM_TX
PCM_RX

USC0

C106

1u

TC7SH08FS

CLOSED TO BT MODULE

C104
1u

2V8_VBT

5

VCC

4

GND

2

U101

1

3

USC3

PCM_TX

3. TECHNICAL BRIEF

- 52 -

3.16 LCD BACKLIGHT, FLASH LED CHARGE PUMP
(AAT2807AIXN-4.5-T1, SLIDE PCB U100)

Figure 3-30. CHAGE PUMP

C_FLASH

LCD_DIM_CTRL

1.5KR109

R102 330

R107

7.5K

C103

22u

VBAT

C100

1u

4

9

17

16

10

U100
AAT2807AIXN-4.5

R108

7.5K

VIN

GND
PGND

EN_FLSH

EN_SET

C101
1u

11

12

14

C1-

C1+

C2+

2

15

C2-

C3+

VOUT_FL

VOUT_BL

1

NC

ISINK1
ISINK2
ISINK3

C3-

C102

1u

3

13

8

5
6
7

C104

27p

C105

FB100

FB101

C106

C107

27p

1u

1u

FLASH_LED

MLED

MLED1
MLED2
MLED3

3. TECHNICAL BRIEF

- 53 -

3.17 SLIDE SWITCH (U205)

2V8_VEXT

C230

0.1u

VDD

SLIDE

51KR211

1

OUT

U205
A3212EELLT-T

G1 G2

SLIDE

C231
10p

3. TECHNICAL BRIEF

- 54 -

3.18 VIBRATOR

The vibrator is placed in the Slide upper and contacted to SLIDE PCB. The vibrator is driven from
VIBRATOR from AD6527B.

Figure 3-32. MOTOR

100

R206

27p

C209

R207

10K

1SS352-TPH3_F

D201

R204

0

C208

4.7u

VBAT

OUT204

27nH

R209

27nH

R208

0

R203

23

64

1

5

VBAT

EMZ2

Q201

47K

R205

OUT203

VIBRATOR

3. TECHNICAL BRIEF

- 55 -

3.19 MULTIMEDIA MIC(OSF213,SLIDE PCB MIC100)

Figure 3-32. MULTIMEDIA MIC

C118

0.1u

2V8_VMEM

C117

0.1u

STBY

1

3

VIN4VOUT

2V5_MULTI_VMIC

U101
BH25FB1WHFV

6

BGND

2

GND

5

NC

MIC_PATH_SEL

R106

2.2K

C112
39p

1

2

MIC100

OSF213-42DC

2V5_MULTI_VMIC

C111

2.2K

R104

39p

EVL5M02200

VA101

C114

39p

39p

C113

C110

EVL5M02200

VA100

22u

R103

R105

1K

0

MULTI_MIC_N

MULTI_MIC_P

4. TROUBLESHOOTING

- 56 -

4.1 RX Trouble

4. TROUBLESHOOTING

SKY74400

FEM

13Mhz OSCILLATOR

Figure 4-1(a)

TEST POINT

4. TROUBLESHOOTING

- 57 -

Checking Flow

START

HP8960 : Test mode

62 CH, 7 level setting (TCH)

62CH, -60dBm setting (BCCH)

Spectrum analyzer setting

Oscilloscope setting

Check

VCTCXO

Check

FEM &

Mobile SW

Check
RX IQ

Redownload SW or

Do calibration again

(1) Checking VCTCXO Circuit

4. TROUBLESHOOTING

- 58 -

TEST POINT

CIRCUIT

Waveform

Graph 4-1(a) Graph 4-1(b)

Checking Flow

R404

AFC

R403

10K

C407

1000p

C408

X400

1

2

13MHz

VCONT

GND

Check Pin 3.

Refer to Graph 4-1(b)

Check Pin 4.

Refer to Graph 4-1(a)

2V75_VVCXO

3

OUT

4

VCC

13 MHzO.K?

2.75V OK?

Check U101

C405

100

R404

C408

1u

1000p

No

No

No

Yes

Yes

13MHz

VCTCXO Circuit is OK

VCTCXO Circuit is OK
See next Page to check

See next Page to check
ANT SW & Mobile SW

ANT SW & Mobile SW

Changing X601

4. TROUBLESHOOTING

- 59 -

(2) Checking FEM & Mobile SW

Waveform

FEM Control GSM& DCS

Graph 4-3(a)

FEM Control PCS

Graph 4-3(b)

C414

C415

C416

GND3

7

GND4

GND5

14

GND6

15

16

GND7

GSM18001900_TX

8

GSM1800_RX

4

GSM1900_RX

6

GSM900_RX

2

GSM900_TX

10

VC1

11

9

VC2

VC3

12

LMSP54LA-445TEMP

FL400

13

ANT

1

GND1

GND2

3

5

27p

C415

27p

C416C414

27p

ANT_SW2
ANT_SW1

ANT_SW3

Figure 4-5

TEST POINT

CIRCUIT

4. TROUBLESHOOTING

- 60 -

Checking Flow

Table 4-2

Vc1 Vc2 Vc3 Current

EGSM-Tx 0.0-0.1V 0.0-0.1V 2.3-3.0V 10mA Max

EGSM-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

DCS/PCS-Tx 0.0-0.1V 2.3-3.0V 0.0-0.1V 10mA Max

DCS-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

PCS-Rx 2.3-3.0V 0.0-0.1V 0.0-0.1V 10mA Max

For these 2 test case,

No Call connection is needed

Check SW500 Pin ANT,RF

with RF Cable connected.

Check SW601 Pin ANT,RF

with No RF Cable Connected

Check C616,C617,C618

Check whether FEM

Set as RX mode

Refer to Table 4-2

Check RF Level of

FL601.6 (for GSM) & FL601.4

(for DCS) & FL601.2 (for PCS)

For this RF Level test case,

RX Stand alone Mode is needed

Open

Yes

Short

Yes

VC1 :Low or HIGH

VC2 :Low

VC3:LOW

Yes

Pin6 : ~ -62dBm

Pin 4,2 : ~ -63dBm

Yes

FEM & Mobile SW is OK

See next Page to check

Rx IQ Signal

No

No

No

No

Changing SW601

Changing SW601

Changing the Board.

Changing FL601

4. TROUBLESHOOTING

- 61 -

(4) Checking RX IQ

Redownload software and calibration again

Similar?

No

Replace U602

Yes

Check C619,C620.

Check if there is any

Major difference

Refer to graph 4-4

C413

C417

VBAT

Q+_TX_Q+

5

4

Q-_TX_Q-

VAPC

9

6

VCC1

VCC3

1

PCO2

PCO3

67

68

PCO4

PED_SELECT

7

2

I+_TX_I+

I-_TX_I-

3

PCO1

65

66

10

8

ENABLE

0.1u

C409

33p

C410

33p

C419

VBAT

39p

C417

C418

0.1u 3p

C420

C412
3p

22u

C411

39p

C413

IN

QP

QN

IP

TEST POINT

Checking Flow

Waveform

CIRCUIT

Graph 4-4

4.2 TX Trouble

4. TROUBLESHOOTING

- 62 -

TEST POINT

Figure 4-2

FEM

SKY74400

13Mhz OSCILLATOR

4. TROUBLESHOOTING

- 63 -

Checking Flow

START

Redownload SW or
Do calibration again

HP8960 : Test mode

62 CH, 7 level setting (TCH)

62CH, -60dBm setting (BCCH)

Spectrum analyzer setting

Oscilloscope setting

Check

VCTCXO

Check

TX IQ

Check

FEM &

Mobile SW

Check

PAM

SIGNAL

(1) Checking VCTCXO Circuit

4. TROUBLESHOOTING

- 64 -

TEST POINT

CIRCUIT

Waveform

Checking Flow

Graph 4-1(a)

Graph 4-1(b)

R404

AFC

R403

10K

C407

1000p

C408

X400

1

2

13MHz

VCONT

GND

Check Pin 3.

Refer to Graph 4-1(b)

Check Pin 4.

Refer to Graph 4 -1(a)

2V75_VVCXO

3

OUT

4

VCC

C408

100

R404

1u

13 MHzO.K?

No

No

2.75V OK?

No

Check U101

C405

1000p

Yes

Yes

13MHz

VCTCXO Circuit is OK

VCTCXO Circuit is OK
See next Page to check

See next Page to check
ANT SW & Mobile SW

ANT SW & Mobile SW

Changing X601

4. TROUBLESHOOTING

- 65 -

(3) Checking Ant SW & Mobile SW

VC1 LOW

VC2 LOW

VC3 HIGH

VC1 LOW

VC2 HIGH

VC3 LOW

Waveform

FEM Control EGSM

Graph 4-6(a)

FEM Control DCS & PCS

Graph 4-6(b)

C414

C415

C416

Figure 4-5

TEST POINT

CIRCUIT

GND3

7

GND4

GND5

14

GND6

15

16

GND7

GSM18001900_TX

8

GSM1800_RX

4

GSM1900_RX

6

GSM900_RX

2

GSM900_TX

10

VC1

11

9

VC2

VC3

12

LMSP54LA-445TEMP

FL400

13

ANT

1

GND1

GND2

3

5

27p

C415

27p

C416C414

27p

ANT_SW2
ANT_SW1

ANT_SW3

4. TROUBLESHOOTING

- 66 -

Checking Flow

Table 4-3

Vc1 Vc2 Vc3 Current

EGSM-Tx 0.0-0.1V 0.0-0.1V 2.3-3.0V 10mA Max

EGSM-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

DCS/PCS-Tx 0.0-0.1V 2.3-3.0V 0.0-0.1V 10mA Max

DCS-Rx 0.0-0.1V 0.0-0.1V 0.0-0.1V ≈ 0mA

PCS-Rx 2.3-3.0V 0.0-0.1V 0.0-0.1V 10mA Max

TX Stand alone Mode is needed. (PL=7 for

Check C616,C617,C618

Check whether FEM

Set as TX mode

Rrefer to Graph4-6(a), 4-6(b)

Rrefer to Table 4-3

For the test,

GSM, PL=2 for DCS)

Check VC1, VC2, VC3

Yes

No

Changing board

Check RF Level of

FL601.10 (for GSM) & Pin 8 (for

DCS)

Check SW601.ANT, RF with RF

Cable connected.

Check SW601.ANT,RF

with RF Cable disconnected

Pin10 : ~29.5dBm

Pin 8 : ~26.5dBm

Yes

Open

Yes

Short

Yes

END

No

No

No

Go to 4.3.5 Checking PAM

control signal

Changing SW601

Changing SW601

4. TROUBLESHOOTING

- 67 -

(4) Checking PAM Control Signal

C426

VBAT

55

SXENA

59

52

VCC3

1

XBUFF

54

XTUNE

53

PREQ_SEL

PCO2

PCO3

67

68

PCO4

LE

57

64

NC_RX_I+

NC_RX_I-

63

NC_RX_Q+

62

NC_RX_Q-

61

PCO1

65

66

CHIP_EN

60

58

CLK

56

DATA_IN

0.1u

C409

33p

C410

VBAT

C412
3p

22u

C411

S_EN

SYNTH_EN
RF_PWR_DWN

S_CLK

S_DATA

Go to Next Step

Similar?

Yes

No

Download S/W

Check TX_RAMP and PA_EN
Check if there is
Any Major Difference or not
Refer to Graph 4

7

Go to Next Step

Similar?

Yes

No

Download S/W

Go to Next Step

Similar?

Yes

Download S/WDownload S/W

Check if there is
Any Major Difference or not
Refer to Graph 4

-

TEST POINT

Waveform

Checking Flow

CIRCUIT

Graph 4-7

(6) Checking TX IQ

4. TROUBLESHOOTING

- 68 -

TEST POINT

CIRCUIT

Checking Flow

Waveform

Graph 4-8

64

63

PCO1

NC_RX_I-

NC_RX_I+

67

68

65

66

PCO2

PCO3

PCO4

VCC3

I+_TX_I+

I-_TX_I-

Q-_TX_Q-

Q+_TX_Q+

VCC1

PED_SELECT

ENABLE

VAPC

BAND_SELECT

VBAT

1

2
3
4
5
6

7

8
9
10

C409

0.1u

C410

33p

C412

C411

VBAT

22u

3p

C418

0.1u 3p

C419
33p

C420

C413
39p

C417
39p

IP

IN
QN

QP

Check if there is

Major Difference

Any

Refer to Graph 4

-8

Similar?

Yes

Redownload the Software
And calibrate

No

Replace U602

4. TROUBLESHOOTING

- 69 -

4.3 Power On Trouble

VCORE

VME

M

VRTC

VSIM

VABB

VVCXO

VEXT

enlargement

C118 1u

C122 1u

2.2uC117

2V5_VMIC

1V8_VCORE

C119 1u

C123

2V75_ABB

1u

1uC113

2V85_VSIM

1uC121

VUSB

2V8_VMEM

VMIC

VRTC

T7
T6

VSIM

VUSB

E15

D16

VVCXO

2V75_VVCXO

P1

VCORE1
VCORE2

N1

A4

VEXT1
VEXT2

B4

VMEM1

T3
T2

VMEM2

N16

VABB

H16

F16

VAPP

VAPPGATE

E16

VBACK

T4

VBAT

0.1uC115

1V8_VRTC

1uC116

2V8_VEXT

C114 1u

VBACKUP

TEST POINT

CIRCUIT

U100

ABB

AD6535

4. TROUBLESHOOTING

- 70 -

Checking Flow

START

Check Battery Voltage

> 3.35V ?

YES

Push power-on key

And check the level change

of PWRKEY

YES

Check the voltage of

The LDO outputs at U100

YES

Logic level at KEYON(POWER KEY)

of U101= HIGH

NO

NO

NO

VCORE=1.8V VVCXO=2.75V
VMEM=2.8V VRTC=1.8V
VEXT=2.8V VSIM=2.85V (when sim card is inserted)
VABB=2.75V VMIC=2.5V

NO

Charge or Change Battery

Check the contact of power key

Or dome-switch

Replace U100

Re-download software

YES

Does it work properly?

YES

THE PHONE WILL

POWER ON.

NO

The power-on procedure is

Completed. The problem may

be elsewhere.

Does it work properly?

NO

Replace the main board

4. TROUBLESHOOTING

- 71 -

4.4 Charging Trouble

enlargement

Pin 1

Pin 18

CN300

CN500

U201

CN203

(1%)

CHARGING IC

10K

R209

10K

2V8_VMEM

R213

VUSBIN

VCHARGE

C217

1u

R212

100K

ISL6299

U201

BAT

10

CRDL

1

8

GND

ICDL

9

6

IMIN

PGND

11

2

USB

USBON

7

4

_CHG

_EN

5

_PPR

3

VBAT

30K

R210 C218

1u

R208

10K

100K

R211

1u

C216

CHG_EN

CHG_STAT

CUR_MON

TEST POINT

CIRCUIT

4. TROUBLESHOOTING

- 72 -

Checking Flow

START

MMI Connector (MAIN PCB,CN300)

Is well-soldered ?

YES

60pin connector (MAIN PCB,CN500)

Is well-soldered ?

30pin connector (KEY PCB,CN203)

KEY PCB U201 are

Voltage across KEY PCB R210 is

YES

Is well-soldered ?

YES

well-soldered?

YES

about 1.2V?

YES

NO

NO

NO

NO

NO

Resolder the CN300

Pin 12,13 : VCHARGE

Pin1,18: GND

Resolder the CN500

Resolder the CN203

Resolder the

U201

Replace the

R201

Battery is charged?

YES

Charging is

properly operating

NO

The battery may have

problems.

Change the battery.

4. TROUBLESHOOTING

- 73 -

4.5 Vibrator Trouble

100

R206

27p

C209

R207

10K

1SS352-TPH3_F

D201

R204

0

C208

4.7u

VBAT

OUT204

27nH

R209

27nH

R208

0

R203

23

64

1

5

VBAT

EMZ2

Q201

47K

R205

OUT203

VIBRATOR

TEST POINT

CIRCUIT

4. TROUBLESHOOTING

- 74 -

Checking Flow

SETTING : Enter the engineering mode, and set vibrator on at vibration of BB test menu

START

Is the voltage at R106 at MAIN PCB

near 0.7V?

Yes

Is the voltage at pin 6

of Q401 near VBAT-0.7V?

Yes

Check the soldering of Vibrator

Yes

Replace Vibrator.

No

No

Replace DBB

No

Replace Q401

Resolder vibrator.

Vibrator will work properly

4. TROUBLESHOOTING

- 75 -

4.6 LCD Trouble

U103

C122

FL101~104

FL101~F104:LCD DATA LINE EMI FILTER

( Check the these EMI FILTER

if LCD data is something to strange)

CN100 : LCD CONNECTOR

TEST POINT

4. TROUBLESHOOTING

- 76 -

- IF CONNECTOR

(IF_MODE)

(LCD_RD=íHí)

H

L

TMD

L

SHARP

H

LCD_ID

9671S-35A-GF

IF_MODE

INOUT_A2

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

FL104

ICVE10094E300FR

G15G2

10

INOUT_A1

1

2

C108
1u 1u

C109

R100

NA

6

7

8

9

R101

NA

25

26

27

28

29

3

30

31

32

33

34

35

4

5

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

2V8_VLCD

CN100

1

10

G2

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

ICVE10094E300FR

FL103

5

G1 G1

5

G2

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

4

INOUT_A4

9

INOUT_B1

INOUT_B2

8

7

INOUT_B3

INOUT_B4

6

5

G110G2

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

INOUT_B3

7

6

INOUT_B4

FL102

ICVE10094E300FR

ICVE10094E300FR

FL101

2V8_VLCD

2V8_VLCD

100K

R191

LCD_ID

LCD_RS

L_DATA01

L_DATA03

LCD_WR

L_MAIN_LCD_CS

IF_MODE

L_DATA05

L_DATA07

L_DATA04

L_DATA09

L_DATA11

L_DATA08

L_DATA13

L_DATA15

L_DATA12

L_DATA14

L_DATA00

L_DATA02

L_DATA06

L_DATA10

LCD_RESET

MLED2

MLED

MLED3

MLED1

VSYNCOUT

CIRCUIT DIAGRAM

C121

2.2u

2V8_VLCD

0.01u

C120

2V8_VMEM 1V8_CAM

C122

4.7u

BGND

11

4

BYP

EN1

2

EN2

3

6

GND

5

NC1

NC2

7

8

NC3

1

VIN10VOUT1

VOUT2

9

U103

MIC2211-GMYML

VBAT

1u

C119

CAM_PWR_EN

4. TROUBLESHOOTING

- 77 -

Checking Flow

START

Voltage the pin 9 of U103

Is 2.8V?

Yes

Check the All Connectors

At Main, Slide PCB

Yes

Paths of LCD control

signals are OK?

Yes

FPCB is OK?

Yes

After changing the board,

LCD Display is OK?

Yes

No

No

Re-solder U103

Reconnect

All Connectors

No

the EMI filter

No

Replace the FPCB

No

The board is broken.

Change the board.

Re-solder

LCD Module is out of order.

Change the LCD Module.

4. TROUBLESHOOTING

- 78 -

4.7 BT Trouble

_BT_RST

BT_EN

TEST POINT

47K

R104

100K

R110

BLUETOOTH

(BT ANT -> TRANSFER TO FETCH ANT)

( 903015 )

CLOSED TO BT MODULE

GND1

5

VCC

2V8_VBT

ANT1

TC7SH08FS

U101

GND

2

1

3

4

C104
1u

SPI104

C105

15p

1u

C107

15p

C108

2V8_VBT

C102

NA

C103

NA

NA

C101

VBAT

SPI101

1u

C106

1u

C109

U102

BGND

62

GND

NC

51

STBY

3

VIN VOUT

4

BH28FB1WHFV

3.3nHR101

L101 22nH

SPI102
SPI103

SPI_MISO

SPI_MOSI

12

UART_CTS

26

23

UART_RTS

UART_RX

24

27

UART_TX

VDD_1_8V

22
21

VDD_DIG

3

VDD_VREGIN

2V8_VBT

GND3

25

GND4

NC

28

PCM_CLK

20

19

PCM_IN

17

PCM_OUT

PCM_SYNC

18

1

PIO0
PIO1

2
7

PIO2
PIO3

8
9

PIO4
PIO5

10

RESETB

16

13

SPI_CLK
SPI_CSB

14

15

M101 LBMA-2C67B2

5

ANT

GND1

4

GND2

6
11

BT_EN

PCM_TX

USC3

DEBUG_TX

DEBUG_RX

USC0

PCM_RX

_BT_RST

PCM_TX

CIRCUIT DIAGRAM

B1

GND

C2

IN1

A2

IN2

NC1

C1

A1

NC2

NO1

C4

A4

NO2

B4

V+

U306 MAX4717EBC-T

C3

COM1

A3

COM2

10K

R314

USC_300

C334

0.1u

2V8_VMEM

USC_301

PCM_TX

PCM_RX

USC2

USC1

PCM_EN

USC_2

USC_1

4. TROUBLESHOOTING

- 79 -

Checking Flow

Is BT_RST signal shape similar

to Fig.1 during Powering on Bluetooth

Yes

2V8_VBT at C314=2.8V

Bluetooth

Power off

Is DEBUG_TX signal similar to

Fig.2 during Powering on Bluetooth?

Is DEBUG_RX signal similar to

Fig.2 during Powering on Bluetooth?

Connect BT headset?

No

Establish a call

No

Replace U103

No

BT_EN at R344=2.8V

Replace U102

No

Replace U103

No

Antenna Feeding about 0dBm?

Replace M101

Is RF Power level at

Replace Headset

Yes

No

Replace U103

No

Is RF Power level at

Antenna Feeding about 0dBm?

Replace M101

Are PCM_SYC8,PCM_TX,USC3

signal similar toFig.3?

Is DEBUG_RX signal similar to

Fig.2 during Powering on Bluetooth?

Redownlapd SW

No

No

Replace U103

Replace M101

4. TROUBLESHOOTING

- 80 -

Figure 1_Blue-RST

Figure 2_DEBUG_TX, RX

Figure 3_PCM_SYNCS, TX, RX, USC0

4. TROUBLESHOOTING

- 81 -

4.8 Speaker Trouble

TEST POINT

U300

U305

4. TROUBLESHOOTING

- 82 -

CIRCUIT DIAGRAM

MAIN PCB

SLIDE PCB

H6

G6

EQ2R

EQ3R

SPOUT2L

SPOUT1L

SPOUT2R

SPOUT1R

TXOUT

EXTOUT

B8

B7

H8

J8

E8

D7

C311

47p 47p

EQ1R

C312

C310

470p

R311

3.3

SPK_N

SPK_P

SPK_P

SPK_N

RCV_P

RCV_N

U305

MAX4684EBC_T

C4

NO1

A4

NO2

C1

NC1

A1

NC2

VBAT

B4

V+

COM1

COM2

GND

B1

C2

IN1

A2

IN2

C3

A3

C335

SPK_RCV_SEL

SPK_RCV_P

SPK_RCV_N

1u

SPK_RCV_P

SPK_RCV_N

C202
39p

C201
39p

C203

39p

VA201

EVL5M02200

L201

68nH

OUT201

L202
68nH

OUT202

VA202

EVL5M02200

4. TROUBLESHOOTING

- 83 -

Checking Flow

START

Check Soldering of speaker

Yes

L201,L202,C201,C202
at Slide PCB are Well-

soldered?

Yes

Check

U300 works properly

Yes

Speaker

Works properly?

Yes

Speaker working!

No

No

No

No

Re-solder Speaker

Re-solder L201,L202,C201,C202

Re-solder U300

Change main board

4. TROUBLESHOOTING

- 84 -

4.9 SIM Card Interface Trouble

TEST POINT

CIRCUIT DIAGRAM

Pin 1

2V85_VSIM

20K

R202

EVLC18S02003

VA202

EVLC18S02003

VA201

C210
22p

C209

1000p

220n

C204

2V85_VSIM

CLK

3

4

GND

GND1

78

GND2

I_O

6

2

RST

1

VCC

VPP

5

J201

SIM_RST
SIM_CLKSIM_DATA

4. TROUBLESHOOTING

- 85 -

Checking Flow

START

Does the SIM cards

supports 3V ?

YES

Voltage at pin1 of

J201 is 2.85V?

YES

Change the SIM Card

And try again.

Does it work

Properly?

YES

Change SIM Card

NO

NO

NO

Change the SIM Card. Our phone

supports only 3V SIM card.

Voltage

at VSIM of U101

Is 2.85V?

NO

Redownload SW.

Does it work

Properly?

YES

SIM Card will be detected.

YES

NO

Replace J201 or

check soldering of components

Change the main board

4. TROUBLESHOOTING

- 86 -

4.10 Earphone Trouble

TEST POINT

4. TROUBLESHOOTING

- 87 -

CIRCUIT DIAGRAM

6 : USC2

3 : USC0
4 : USC4

USB

0

2012

Jack_Det(IN1_2)

USC

1

USB_EN(IN3_4)

0

State

Jack_ADC

0

1

7 : USC1

14 : DSR

5 : USC5

D/C

U301

1u

C338

C340

1u

LP3985IBLX-2.8

BYPASS

A3

B2

GND

VEN

A1

VINC3VOUT

C1

2V6_JACK

U307

5G110

G2

1

INOUT_A1

INOUT_A2

2

3

INOUT_A3

INOUT_A4

4

INOUT_B1

9

8

INOUT_B2

7

INOUT_B3

6

INOUT_B4

ICVE10094E300FR

FL302

C314 220u

C321
1u

C320

VBAT

VUSBIN

1u

3
4
5
6
7
8
9

1

10
11
12
13
14
15
16
17
18

19

2

20

21

22

CN300

27p

C309

C336

1u

C337
47n

0.1u

C303

C339

0.01u

COM

A2

B3

GND

B1

IN

A3

NC

NO

A1

V+

B2

DG3000DBU308

3

D-4D-IC

GND25VBUS

STF203-22-TCTU303

D+16D+IC

PG05DBTFC

VA301

C308
39p

10K

R313

G15G2

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

INOUT_A4

4

9

INOUT_B1

INOUT_B2

8

INOUT_B3

7

INOUT_B4

6

2V8_VEXT

FL301

ICVE10094E300FR

1u

4.7K

C341

B3

EP2

B4

GND

A4

IN1
IN2

C4

A3

NC1
NC2

C3

A1

NO1

C1

NO2
VCC

B1

R315

MAX4764EBC+TU402

A2

COM1
COM2

C2

EP1

B2

C313

2V8_VEXT 2V8_VEXT

220u

0.1u

C302

1K

R303

MAX4717EBC-T

COM1

C3

A3

COM2

GND

B1

IN1

C2

IN2

A2

NC1

C1

NC2

A1

NO1

C4

NO2

A4

V+

B4

U302

2V6_JACK

1u

C331

VUSBIN

NO3

7

NO4

11

17

PGND

V+

14

16

COM1

COM2

4

8

COM3

COM4

12

GND

6

2

IN1_IN2

IN3_IN4

10

1

NC1

NC2

5

NC3

9

13

NC4

15

NO1

3

NO2

MAX4701ETE+TU301

3.6K

R318

1u

C342

2V8_VMEM

100K

R317

DBUGTX

2V8_VEXT

PG05DBTFC

30K

R310

VA300

C305
22u

2V8_VEXT

R316

100K

DBUGRX

RPWRON

NA

R319

R304

100

100

R309

R306

30K

C318

1u

9

INOUT_B2

8

INOUT_B3

7

INOUT_B4

6

ICVE10094E300FR

G15G2

10

INOUT_A1

1

2

INOUT_A2

INOUT_A3

3

4

INOUT_A4

INOUT_B1

FL300

10u

C319

C306
39p

10KR320

VCHARGE

1.5K

R308

R302

1K

EAR_MICJACK_LDO_EN

HOOK_DETECT

EAR_MIC

EAR_MIC

USB_EN

HEADSET_SPK_L

HEADSET_SPK_R

EAR_REM_INT

USC1

EAR_REM_ADC

DEBUG_TX

JACK_DETECT

MULTI_USB-

MULTI_USB+

USB-

USB+

USB_PATH_SEL

VUSBIN

RPWRON

DSR

DEBUG_RX

JACK_LDO_EN

HEADSET_EN

USC5

USC4

USC2

USC0

CHG_DET

AUXIN

AUXIP

4. TROUBLESHOOTING

- 88 -

Checking Flow

START

Resolder CN201

Does the audio

profile of the phone

change to the

earphone mode?

YES

Set the audio part of the test

Equipment to echo mode

Can you hear your

voice from

the earphone?

YES

NO

Change the earphone

NO

Can you hear your

Level at

JACK_DETECT signal

is low

YES

and try again

voice from

the earphone?

YES

NO

Replace CN201

Set the audio part of

the test equipment to

PRBS or continuous

wave mode

NO

Can you hear
the sound from
the earphone?

YES

Voltage level check

Of AUX_MIC_P &

AUX_MIC_N

signal.

No

Voltage level check

Of AUX_SPK_L
& AUX_SPK_R

No

Resoler components

signal.

No

YES

Earphone will work properly

Change main board

YES

Check

U202

works properly

YES

No

Resoler U202

4. TROUBLESHOOTING

- 89 -

4.11 EL Trouble

TEST POINT

CIRCUIT DIAGRAM

U202

L201

+

-

EL OFF

2012 1/4W

EL ONHIGH

LOW

1608

EL PAD

N_ALEN_CLE

820uH

L201

6800p

C225

C224
47p

ZD201
KDZ100VW

1u

C223

R215
33

2200p

C226

2

CLF

3

E

4

GND

L+

7

L-

5

8

V+

VOUT

6

U202 D381B

CHF

1

R214

68K

VBAT

EL_KEY_BACKLIGHT

4. TROUBLESHOOTING

- 90 -

Checking Flow

Picture 1-1

Pk to pk : about 220V

Frequecy : about 400Hz

START

EL sheet is torn ?

NO

R214 at KEY PCB

is well-soldered?

YES

Voltage of R214 is high?

YES

Does The wave form pin 6 of U202

at KEY PCB similar picture 1-1?

YES

EL sheet will work properly.

YES

NO

NO

NO

Replace EL sheet

Resolder R214

Replace U103

Replace U700

4.12 Receiver Trouble

4. TROUBLESHOOTING

- 91 -

TEST POINT

U305

U100

C140

C118

C141

C138

R110

R111

4. TROUBLESHOOTING

- 92 -

Checking Flow

Receiver path to SPK&RCV on Slide PCB via FPCB

AGND036

AGND037

AGND4

T16

M12

AGND3

L15

A11

AOUT2P1
AOUT2P2
AOUT2N1
AOUT2N2

AGND1

AGND2

T8

B16

AOUT1P
AOUT1N

AOUT3L
AOUT3R

GPI

DGND

SGND1R8SGND2

M2

N15

J15
K15
R11
T11
T9
R9
J16
K16
C2

LGND

SPK_P

SPK_N

RCV_P

RCV_N

C142

39p

MAX4684EBC_T

R110 4.7

C143

39p

VBAT

U305

C4

NO1

A4

NO2

C1

NC1

A1

NC2

4.7R111

B4

V+

COM1

COM2

GND

B1

IN1

IN2

C138
39p

AUX_OUT_L
AUX_OUT_R

C2

A2

C3

A3

C335

1u

SPK_RCV_SEL

SPK_RCV_P

SPK_RCV_N

C140
39p

C141
39p

RCV_P

RCV_N

SPK_RCV_P

SPK_RCV_N

C202
39p

C201
39p

C203

39p

VA201

EVL5M02200

L201

68nH

OUT201

L202

68nH

OUT202

VA202

EVL5M02200

4. TROUBLESHOOTING

- 93 -

Checking Flow

START

SETTING : After initialize Agilent 8960, Test EGSM, DCS mode

Set the property of audio as PRBS or continuous wave. Set the receiving volume of mobile as Max.

Check the state of

soldering of receiver

YES

NO

Resolder receiver

R110,R111

Are well-solederd?

NO

YES

Resolder R110,R111

Check the all connectors?

NO

YES

RE-Connect All Connectors

Check the contact state of speaker.

Replace the dual mode speaker

The dual mode speaker will work

properly.

No

4. TROUBLESHOOTING

- 94 -

4.13 Microphone Trouble

TEST POINT

CIRCUIT DIAGRAM

CLOSE TO AD6535B

39p

C133

R12

NC_R12

R15

AIN2P

P15

AIN3L

R13
R14

AIN3R

R16

AIN1N

P16

AIN1P

AIN2N

PG05DBTFC

D101

C134

39p

D102

PG05DBTFC

VINNORP
VINNORN

AUXIP
AUXIN

47u

C201

R204

2.2K

VA205

EVLC18S02003

C212

39p

MIC201

SMA-568-0C-R2

1
2

2V5_VMIC

NA

C215

39p

39p

C202

C211

0.1u

C213

R201

1K

C214
NA

2.2K

R207

R206

100

VA204

EVLC18S02003

100

R205

VINNORP

VINNORN

U100

ABB

4. TROUBLESHOOTING

- 95 -

Checking Flow

SETTING : After initialize Agilent 8960, Test EGSM, DCS mode

START

Voltage across C118 at MAIN PCB

= DC 2.5V ?

YES

Check the signal

Level at each side

of MIC.

Is it a few tens

mV AC?

YES

Check the soldering of

R205, R206 at Slide PCB

YES

Microphone will work

properly.

NO

NO

NO

Voltage VMIC of U100

= DC 2.5V?

Replace microphone

Resolder component

NO

Replace U100

4. TROUBLESHOOTING

- 96 -

4.14 RTC Trouble

R105

X100

C115

TEST POINT

C130
NA

R105

10M

C129 1000p

12

3

4

MC-146_7pF

X100

32.768KHz

VUSB

NA

C128

R106

NRESET

V3

E9

OSCIN

OSCOUT

C9

F9

PWRON

V6

NAUXCS1

NGPCS1

N9

GPIO_42_NMAIN_LCD_CS

V7

GPIO_43_NSUB_LCD_CS

L14

GPIO_1_IRDA_RX
GPIO_2_NIRDA_EN

K16

L18

GPIO_0_IRDA_TX

N10

CLKIN

P13

CLKON

13MHz

CLKON

BT_EN

CHG_STAT

CHG_EN

TOUCH_EN

_LCD_CS

_MIDI_CS

PWRON

_RESET

2V5_VMIC

1V8_VCORE

2V75_ABB

1uC113

2V85_VSIM

VUSB

2V8_VMEM

VRTC

T7

2V75_VVCXO

P1

VCORE1
VCORE2

N1

VMEM1

T3
T2

VMEM2

VBAT

0.1uC115

1V8_VRTC

2V8_VEXT

C114 1u

VBACKUP

Mount on the opposit

NBL-414-F9D

C210
1u

BA201

VBACKUP

CIRCUIT DIAGRAM

MAIN PCB

SLIDE PCB

4. TROUBLESHOOTING

- 97 -

Checking Flow

START

Is the voltage

level of BA201

> 1.2V ?

YES

Check

the voltage at

1,4 of X100

YES

Change main board

NO

NO

Charge or change BA201.

Resolder R105 or

Replace X100

4. TROUBLESHOOTING

- 98 -

4.15 Navigation KEY Problem

TEST POINT

P1002

C1002

2.2u

P1001

3V3_VTOUCH

6

VDD

28

VSS1

32

VSS2

12

XREX

17

10

15

P1_4

9

P1_5

P1_6

16

P1_7

8

20

P2_0

5

P2_1

21

P2_2P2_3

4

22

P2_4

3

P2_5

P2_6

23

P2_7

2

18

P3_0

7

P3_1

P3_2

19

P3_3

CY8C21434

U1000

GND

33

24

P0_0

1

P0_1

25

P0_2

31

P0_326P0_4

P0_5

30

27

P0_629P0_7

13

P1_011P1_1

P1_2

14

P1_3

P1003

P1000

SENSE0

SENSE6

SENSE2

SENSE7

TOUCH_DAT

TOUCH_INT

TOUCH_CLK

SENSE8

SENSE4

SENSE1

SENSE5

SENSE3

AXK8L10125G

R1002

1K

G2

3V3_VTOUCH

110
2
3
4
56

7

8

9

G1

CN1000

1KR1001

VBAT

1KR1003

TOUCH_CLK TOUCH_DAT

TOUCH_INT

CIRCUIT DIAGRAM

U1000

R1003
R1002
R1001

4. TROUBLESHOOTING

- 99 -

Checking Flow

TOUCH_INT

TOUCH_CLK

TOUCH_DAT

Figure 1-2Figure 1-1

START

Is Touch PCB glued on

upper case well?

Yes

Check Connector?

Yes

Yes

Navigation Key will work

properly.

No

Re-attach Touch PCB

on Upper case

No

No

Re-solder & Re-Connect

Replace U1000 on touch PCB

CN1000

5. DOWNLOAD

- 100 -

5. DOWNLOAD

1. H/W Tool Setup

1) PIF Jig

2)D/L Cable

RS232

Power Supply
(4.2V)

I/O Cable

Connect Cable

No Battery

[Switch mode]

[Insert! Battery]

D/L Cable

D/L Cable

[No Battery]

TA

5. DOWNLOAD

- 101 -

2. Install & Directory structure

1) Copy! GSMULTI D/L Program in local Disk(C:)

-Folder name : Only “GSMULTI”

-This program and Dll file and SW is on GCSC Website

2) Registry of GSMULTI Program

-Execute by double click :

3)After Install Directory structure