LG F1200 Service Manual
Service Manual
Model : F1200
Service Manual
F1200
P/N : MMBD0045801 Date : Feb, 2005 / Issue 1.0
- 1 -
1. INTRODUCTION
...................................
3
1.1 Purpose
................................................
3
1.2 Regulatory Information
.........................
3
1.3 Abbreviations
........................................
5
2. PERFORMANCE
..................................
7
2.1 H/W Features
.......................................
7
2.2 Technical Specification
.........................
8
3. TECHNICAL BRIEF
..........................
12
3.1 RF Transceiver General Description ..12
3.2 Receiver Part
......................................
12
3.3 Synthesizer Part
.................................
14
3.4 Transmitter Part
..................................
16
3.5 Digital Baseband
................................
18
3.6 Analog Baseband
...............................
31
3.7 LCD & Camera Interface
....................
36
4. TROUBLE SHOOTING
....................
38
4.1 Baseband Part Troubleshooting
.........
38
4.2 Trouble Shooting of Receiver Part
.....
64
4.3 Trouble Shooting Transmitter Part
.....
73
4.4 RF Rx Tx signal flow on Test mode
...
83
5. DISASSEMBLY INSTRUCTION
....
84
6.
DOWNLOAD AND CALIBRATION
....
91
6.1 Download
............................................
91
6.2 Download Procedure
...........................
92
7. BLOCK DIAGRAM
............................
99
8. CIRCUIT DIAGRAM
........................
101
9. PCB LAYOUT
....................................
106
10. ENGINEERING MODE
................
109
11. STAND ALONE TEST
.................
110
11.1 What’s the Standalone Test?
........
110
11.2 Standalone Test Equipment
Setup
............................................
111
11.3 HW Test : Software for Standalone
Test Setup
....................................
112
11.4 Tx Stand alone Test Setting
.........
114
11.5 Rx Stand alone Test Setting
........
116
12.
SERVICE AND CALIBRATION
....
118
12.1 Service S/W
...................................
118
12.2 Calibration
....................................
120
13. EXPLODED VIEW &
REPLACEMENT PART LIST
......
125
13.1 Exploded View
............................
125
13.2 REPLACEMENT PARTS ............
127
Table Of Contents
- 2 -
REVISED HISTORY
The information in this manual is subject to change without notice and should not be construed as a
commitment by LGE Inc. Furthermore, LGE Inc. reserves the right, without notice, to make changes
to equipment design as advances in engineering and manufacturing methods warrant.
This manual provides the information necessary to install, program, operate and maintain the
F1200.
DATE ISSUE CONTENTS OF CHANGES S/W VERSION
JAN/2005 ISSUE1 Initial Release
1. INTRODUCTION
- 3 -
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download
the features of F1200.
1.2 Regulatory Information
(1) Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for
example, persons other than your company’s employees, agents, subcontractors, or person
working on your company’s behalf) can result in substantial additional charges for your
telecommunications services. System users are responsible for the security of own system.
There may be risks of toll fraud associated with your telecommunications system. System users
are responsible for programming and configuring the equipment to prevent unauthorized use.
The manufacturer does not warrant that this product is immune from the above case but will
prevent unauthorized use of common-carrier telecommunication service of facilities accessed
through or connected to it. The manufacturer will not be responsible for any charges that are
resulted from such unauthorized use.
(2) Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and
possibly causing harm or interruption in service to the telephone network, it should disconnect
telephone service until repair can be done. A telephone company may temporarily disconnect
service as long as repair is not done.
(3) Changes in Service
A local telephone company may make changes in its communications facilities or procedure.
If these changes could reasonably be expected to affect the use of this phone or compatibility
with the network, the telephone company is required to give advanced written notice to the user,
allowing the user to take appropriate steps to maintain telephone service.
(4) Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its
authorized agent. Therefore, note that unauthorized alternations or repair may affect the
regulatory status of the system and may void any remaining warranty.
(5) Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by
local regulatory agencies. In accordance with these agencies, you may be required to provide
information such as the following to the end user.
- 4 -
(6) Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look
slightly different.
(7) Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference
from unsuppressed engines or electric motors may cause problems.
(8) Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the
sign.
Following information is ESD handling:
Service personnel should ground themselves by using a wrist strap when exchange system
boards.
When repairs are made to a system board, they should spread the floor with anti-static mat
which is also grounded.
Use a suitable, grounded soldering iron.
Keep sensitive parts in these protective packages until these are used.
When returning system boards or parts like EEPROM to the factory, use the protective
package as described.
1. INTRODUCTION
- 5 -
1. INTRODUCTION
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Rate
CC-CV Constant Current – Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
1. INTRODUCTION
- 6 -
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
2. PERFORMANCE
- 7 -
2. PERFORMANCE
2.1 H/W Features
Item Feature Comment
Standard Battery Li-Ion, 950mAh
AVG TCVR Current 240mA
Standby Current < 5.2mA
Talk time Over 5 hour (@ GSM Tx Level 7)
Standby time Over 250 hour (@ Paging Period 9, RSSI : -85dBm)
Charging time 3 hours
RX Sensitivity GSM900 : -105dBm, DCS/PCS : -105dBm
TX output power GSM, EGSM: 32dBm (Level 5)
DCS/PCS: 29dBm (Level 0)
GPRS compatibility Class 12
SIM card type 3.0V Only
Display Main : 128 x 160 TFT, Sub : 96 x 96 TFT
Status Indicator Key Pad (Main) : 0 ~ 9, #, *, Navigation Key,
Up/Down Side Key,
Camera Side Key, Confirm Key,
Send Key, END/PWR Key
Key Pad (Folder) : Rewind, Fasten Forward, Play
ANT Internal
EAR Phone Jack 12-pin
PC Synchronization Yes
Speech coding EFR / FR
Data and Fax Yes
Vibrator Yes
Buzzer No
Voice Recording Yes
C-Mic Yes
Receiver Yes
Travel Adapter Yes
Options Hands-Free Kit, Data Kit
- 8 -
2.2 Technical Specification
Item Description Specification
GSM900
TX: 890 + n x 0.2 MHz (n=1 ~ 124)
890 + (n-1024) x 0.2 MHz (n=975 ~ 1023)
RX: TX + 45 MHz
DCS1800
1 Frequency Band TX: 1710 + (n-511) x 0.2 MHz (n = 512 x 885)
RX: TX + 95 MHz
PCS1900
TX: 1850 + (n-511) x 0.2 MHz
RX: 1930 + (n-511) x 02MHz (n = 512 x 810)
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1ppm
GSM900
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
12 19 dBm 3dB
4 Power Level DCS1800/PCS1900
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
2. PERFORMANCE
- 9 -
2. PERFORMANCE
Item Description Specification
GSM900
Offset from Carrier (kHz) Max. dBc
100 +0.5
200 –30
250 –33
400 –60
600 ~ 1,200 –60
1,200 ~ 1,800 –60
1,800 ~ 3,000 –63
3,000 ~ 6,000 –65
5 Output RF Spectrum 6,000 –71
(due to modulation)
DCS1800/PCS1900
Offset from Carrier (kHz) Max. dBc
100 +0.5
200 –30
250 –33
400 –60
600 ~ 1,200 –60
1,200 ~ 1,800 –60
1,800 ~ 3,000 –65
3,000 ~ 6,000 –65
6,000 –73
GSM900
Offset from Carrier (kHz) Max. dBm
400 –19
600 –21
1,200 –21
6 Output RF Spectrum 1,800 –24
(due to switching
DCS1800/PCS1900
transient)
Offset from Carrier (kHz) Max. dBm
400 –22
600 –24
1,200 –24
1,800 –27
7 Spurious Emissions Conduction, Emission Status
- 10 -
2. PERFORMANCE
Item Description Specification
GSM900
8 Bit Error Rate
BER (Class II) < 2.439% @–102 dBm
DCS1800/PCS1900
BER (Class II) < 2.439% @–100 dBm
9
RX Level Report Accuracy
3 dB
10 SLR 8 3 dB
Frequency (Hz) Max. (dB) Min. (dB)
100 –12 –
200 0 –
300 0 –12
11 Sending Response 1,000 0 –6
2,000 4 –6
3,000 4 –6
3,400 4 –9
4,000 0 –
12 RLR 2 3 dB
Frequency (Hz) Max. (dB) Min. (dB)
100 –12 –
200 0 –
300 2 –7
500 ❈
–5
13 Receiving Response 1,000 0 –5
3,000 2 –5
3,400 2 –10
4,000 2
* Mean that Adopt a straight line in between 300 Hz
and 1,000 Hz to be Max. level in the range.
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
–35 17.5
–30 22.5
16 Distortion
–20 30.7
–10 33.3
0 33.7
7 31.7
10 25.5
17 Side tone Distortion Three stage distortion < 10%
18
<Change> System
frequency (13 MHz) ≤ 2.5 ppm
tolerance
- 11 -
2. PERFORMANCE
Item Description Specification
19 <Change> 32.768KHz
≤ 30 ppm
tolerance
20
Power consumption
Standby
- Normal, ≤5.2mA (Mix. power)
21 Talk Time
GSM900/Lvl 7 (Battery Capacity 950mA): 321 min
GSM900/Lvl 12 (Battery Capacity 950mA): 499 min
Under conditions, at least 250 hours:
1. Brand new and full 950mAh battery
22 Standby Time
2. Full charge, no receive/send and keep GSM in idle mode.
3. Broadcast set off.
4. Signal strength display set at 3 level above.
5. Backlight of phone set off.
23
Ringer Volume
At least 65 dB under below conditions:
1. Ringer set as ringer.
2. Test distance set as 50 cm
24 Charge Voltage
Fast Charge : < 500 mA
Slow Charge: < 60 mA
Antenna Bar Number Power
5 –85 dBm ~
4 –90 dBm ~ –86 dBm
25 Antenna Display 3 –95 dBm ~ –91 dBm
2 –100 dBm ~ –96 dBm
1 –105 dBm ~ –101 dBm
0 ~ –105 dBm
0 3.62V±0.03V
1 3.70V±0.03V
26 Battery Indicator
2 3.78V±0.03V
3 3.92V±0.03V
4 3.93V±0.03V
27 Low Voltage Warning
3.62V ±0.03V (Call)
3.50V ±0.03V (Standby)
28 Forced shut down
3.35 ± 0.03 V
Voltage
1 Li-ion Battery
29 Battery Type
Standard Voltage = 3.7V
Battery full charge voltage = 4.2V
Capacity : 950mAh
Switching-mode charger
30 Travel Charger Input : 100 ~ 240V, 50/60 Hz
Output : 5.2V, 600 mA
➝
➝➝
- 12 -
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1 RF Transceiver General Description
The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part, a
voltage supply part, and a DCXO part.
The SI4206[U102] is a triple band transceiver IC suitable for GSM 900, DCS 1800 and PCS
1900 GPRS class 12 applications. This device integrated a receiver based on a low IF (100KHz)
architecture and a transmitter based on modulation loop architecture. And, the synthesizer part
are included in the IC, a complete dual band synthesizer with built in VCOs.
The transceiver employed a 3 wire serial interface to allow an external system controller to write
the control registers for dividers, receive path gain, power down setting, and other controls.
3.2 Receiver Part
The receiver part uses a low-IF receiver architecture that allows for the on-chip integration of the
channel selection filters, eliminating the external RF image reject filters and the IF SAW filter
required in conventional super-heterodyne architecture. The Si4206[U102] integrates three
differential input LNAs that are matched to the 200 Ohm balanced-output SAW filters through
external LC matching networks. A quadrature image-rejection mixer downconverts the RF signal
to a 100kHz intermediate frequency (IF) with the RFLO. The mixer output is amplified with an
analog programmable gain amplifier (PGA) and quadrature IF signal is digitized with high
resolution A/D converters (ADCs). The Si4206[U102] downconverts the ADC output to
baseband with a digital 100kHz quadrature LO signal. Digital decimation and IIR filters perform
channel selection to remove blocking and reference interference signals. After channel
selection, the digital output is scaled with digital PGA, which is controlled with the DGAIN[5:0]
bits in register 05h.The amplified digital output signal go through with DACs that drive a
differential analog signal onto the RXIP,RXIN,RXQP and RXQN pins to interface to standard
analog ADC input baseband ICs.
Table 1. Antenna (RSSI) Display
Antenna Bar Number Power (dBm)
5 ≥ -85
4 ≥ -90
Antenna Display
3 ≥ -95
2 ≥ -100
2 ≥ -105
1 < -105
- 13 -
3. TECHNICAL BRIEF
Figure 1. RECEIVER PART Block Diagram
(1) RF Front End
RF front end consists of Antenna Switch Module with SAW filter for triple band (FL100), triple
band LNAs integrated in transceiver (U102).
The Received RF signals (EGSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz, PCS 1850 ~
1990MHz) are fed into the antenna or mobile switch. An antenna matching circuit is between the
antenna and the mobile switch. The Antenna Switch (in FL100) is used for control the Rx and
TX paths. And, the input signals ANT1, ANT2 and ANT3 of a FL100 are directly connected to
baseband controller to switch either TX or RX path on and select bands. Ant S/W module
(FL100) is an antenna switch module for dual band phone. The logic and current is given below.
Table 2. BAND/RTX SELECTION
The receiver part uses a low-IF receiver architecture that allows for the on-chip integration of the
channel selection filters, eliminating the external RF image reject filters and the IF SAW filter
required in conventional super-heterodyne architecture. The Si4206[U102] integrates three
differential input LNAs that are matched to the 200 ohm balanced-output SAW filters through
external LC matching networks.
Mode ANT1 ANT2 ANT3
EGSM TX HL L
DCS/PCS TX L H H
EGSM RX LLL
DCX RX LLL
PCS RX LLH
- 14 -
3. TECHNICAL BRIEF
(2) Low IF
A quadrate image-rejection mixer downconverts the RF signal to a 100kHz intermediate
frequency (IF) with the RFLO. The RFLO frequency is between 1849.8 and 1918.8 MHz, and is
divided by two for EGSM modes. The RFLO frequency is between 1804.9 and 1879.9 MHz, and
is divided by one for DCS modes. The RFLO frequency is between 1929.9 and 1989.9 MHz,
and is divided by one for PCS modes. The mixer output is amplified with an analog
programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register 05h.
The quadrate IF signal is digitized with high resolution A/D converters (ADCs). The
Si4206[U101] down-converts the ADC output to baseband with a digital 100kHz quadrate LO
signal. Digital decimation and IIR filters perform channel selection to remove blocking and
reference interference signals. The response of the IIR filter is programmable to a high
selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1). After channel selection, the
digital output is scaled with digital PGA, which is controlled with the DGAIN[5:0] bits in register
05h.
(3) Demodulator and Baseband Processing
The amplified digital output signal go through with DACs that drive a differential analog signal
onto the RXIP, RXIN, RXQP and RXQN pins to interface to standard analog ADC input
baseband ICs. No special processing is required in the baseband for offset compensation or
extended dynamic range. Compared to a direct-conversion architecture, the low-IF architecture
has a much greater degree of immunity to dc offsets that can arise from RF local oscillator
(RFLO) self-mixing, 2nd order distortion of blockers, and device 1/f noise.
3.3 Synthesizer Part
The Si4206[U101] integrates two complete PLLs including VCOs, varactors, resonators, loop
filters, reference and VCO dividers, and phase detectors. The RF PLL uses two multiplexed
VCOs. The RF1 VCO is used for receive mode, and the RF2 VCO is used for transmit mode.
The IF PLL is used only during transmit mode. All VCO tuning inductors are also integrated. The
IF and RF output frequencies are set by programming the N-Divider registers, NRF1, NRF2, and
NIF. Programming the N-Divider register for either RF1 or RF2 automatically selects the proper
VCO. The output frequency of each PLL is as follows:
FOUT = N x f
A programmable divider in the input stage allows either a 13 or 26 MHz reference frequency
depending on the choice of crystal. A 26 MHz reference clock can be divided by 2 using the
DIV2 bit in Register 31h. The RF PLL phase detector update rate (f) can be programmed with
the RFUP bit in register 31h to either f = 100 kHz or f = 200 kHz. The IF PLL always uses f
= 200 kHz. Receive mode should use f = 100 kHz in DCS 1800 and PCS 1900 bands, and f
= 200 kHz in the E-GSM 900 bands. Transmit modes should always use f = 200 kHz.
- 15 -
3. TECHNICAL BRIEF
Figure 2. SYNTHESIZER PART Block Diagram
(1) DCXO
The Aero I+ transceiver integrates the DCXO circuitry required to generate a precise system
reference clock using only an external crystal resonator. (See Figure 15.) An internal digitally
programmable capacitor array (CDAC) provides a coarse method of adjusting the reference
frequency in discrete steps. An integrated analog varactor (CVAR) allows for a fine and
continuous adjustment of the reference frequency by an external control voltage (XAFC). This
control voltage is supplied by the AFC DAC on the baseband IC. The complete DCXO solution
effectively replaces TCVCXO modules typically required to provide a 13 or 26 MHz reference
clock for the system.
Figure 3. DCXO
- 16 -
3. TECHNICAL BRIEF
3.4 Transmitter Part
The Transmitter part contains Si4206[U102] active parts, Power Amp Module[U100] and
Antenna Switch Module[FL100]. The transmit section of Si4206[U102] consists of an I/Q
baseband pconverter, an offset phaselocked loop (OPLL) and two 50 ohm output buffers that
can drive external power amplifiers. The RF GMSK outputs from the transmit VCO are fed
directly to the RF power amplifiers. The peak output power and the profile of the transmitted
burst are controlled by means of incorporated power control circuits inside of PA and DAC
output from the Baseband Controller. The PA outputs pass to the antenna connector via
Antenna Switch Module.
Figure 4. TRANSMITTER PART Block Diagram
(1) IF Modulator
The baseband converter (BBC) within the GSM chipset generates I and Q baseband signals for
the Transmit vector modulator. The modulator provides more than 40dBc of carrier and
unwanted sideband. Rejection and produces a GMSK modulated signal. The baseband
software is able to cancel out differential DC offsets in the I/Q baseband signals caused by
imperfections in the D/A converters. The TX-Modulator implements a quadrature modulator. A
quadrature mixer upconverts the differential I/Q signals with the IFLO to generate a SSB IF
signal, which is filtered and used as the reference input to the OPLL. The Si4206 [U102]
generates the IFLO frequency. The IFLO is divided by two to generate the quadrature LO
signals for the quadrature modulator.
(2) OPLL
The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated
TXVCO. The TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is
divided by 2 for the E-GSM 900 bands. The Si4206 generates the RFLO frequency between
1327 and 1402 MHz. To allow a single VCO to be used for the RFLO, high-side injection is used
for the E-GSM 900 bands, and low-side injection is used for the DCS 1800 and PCS 1900
bands. Low-pass filters before the OPLL phase detector reduce the harmonic content of the
quadrature modulator and feedback mixer outputs. The cutoff frequency of the filters is
programmable with the FIF[3:0] bits in register 04h. The OPLL requires no external duplexer to
attenuate transmitter noise and spurious signals in the receive band. Additionally, the output of
the transmit VCO (TXVCO) is a constant-envelope signal which reduces the problem of spectral
spreading caused by non-linearity in the PA.
- 17 -
3. TECHNICAL BRIEF
(3) Power Amplifier Module
The SKY77325[U100] is a triple-band GSM/DCS/PCS power amplifier module that incorporates
an indirect closed loop method of power control. The indirect closed loop is fully self-contained
and it does not require loop optimization. It can be driven directly from the DAC output in the
baseband circuit. On-board power control provides typical 50 dB of control range with an analog
voltage input (Vapc). Efficiency is 53% at GSM, DCS and PCS.
Figure 5. POWER AMP
(4) Power Supplies and Control Signals
An external regulator (U104) is used to provide DC power to RF part. Every RF component
except power amp module uses this external regulator.
Figure 6. POWER SUPPLY & CONTROL
C130
1000p
C131
2.2u0.01u
C132
4
BYP EN
3
GND
2
IN
15
OUT
U104MIC5255-2.85BM5
RF2.85V
VBAT
1u
C133
RF_EN
3.5 Digital Baseband
Figure 7. Top level block diagram of the Calypso-Plus
(1) General Description
Calypso-Plus device is an evolution of Calypso (C035) device integrating hardware
enhancements targeting the implementation of a new range of user’s applications. It supports
the digital baseband processing of GSM radio signals in switching circuit mode and packet data
mode up to class 12 in compliance with the ETSI specification of the GPRS protocol. The
functional enhancement of the Calypso-Plus offer an increase computing performance of both
ARM7 based MCU and C54x based DSP sub-system in addition to numerous new connectivity.
The enhanced computing performances mainly rely on :
[MCU Sub-system]
- 5.5Mbit Internal SRAM (with 0.5Mb shared with DSP)
- DMA to internal SRAM
- Page Mode Memory Interface
- Sizable 6 Chip-Select
- 2 Generic Purpose external interrupts
- Patch Unit
- 18 -
3. TECHNICAL BRIEF
- 19 -
3. TECHNICAL BRIEF
[ DSP Sub-system]
- 0.5Mb Program/Data Memory Extension shared with MCU
The new connectivity peripherals are :
- LCD controller parallel physical interface (6800 & 8080 protocol)
- USB client (W2FC)
- Multi Media and Secure Digital Card (MMC/SD) interface
- Memory Stick (MS) interface (using exclusive with MMC/SD)
- Audio and Data interface for external Bluetooth Modem connection
- Audio Codec serial interface (I2S)
- Smart Card physical interface (ISO-7816)
- NAND-Flash Interface
- Enhanced Keyboard controller
(2) Memory Interface
Calypso-Plus has 6-sizable chip select port and can configure as follow :
Table 3. Configuration of addressable ranges
F1200 applies configuration #1 as its external memory interface, the external devices are
connected to as follow.
Table 4. External Device Spec. connected to memory interface
In Mbytes nCS0 nCS1 nCS2 nCS3 nCS4 nCS5
Config #1 8 8 8 16 16 64
Config #2 8 16 16 16 32 32
Config #3 4 8 16 32 32 32
Config #4 4 8 8 8 32 64
nCS External Device nCS External Device
nCS0 32Mbit SRAM nCS3 64Mbit NOR Flash
nCS1 64Mbit SRAM nCS4 Camera (LCD) control IC
nCS2 MIDI (MP3/AAC) Chip nCS5 128Mbit NOR Flash
- 20 -
Calypso-Plus has NAND Flash interface and it allows NAND EEPROM as a mass external
storage facility.
The interface implements a 8-bit parallel data bus in addition to the control signals for selecting
chip, writing/Reading, command and address latching, ready/busy status.
So, F1200 uses this interface as for NAND Flash memory and uses stacked memory (SRAM +
NOR-Flash + NAND-Flash) as shown in (Figure 8.)
Figure 8. Memory interface scheme
3. TECHNICAL BRIEF
MCP
TP509
100K
R354
10KR352
_WPN
L6
_WP_ACC
VSS5
VSS6
P13
VSS7
R8
_CE1PS1
N13
N12
_CE1PS2
_CEF1
N11
N10
_CEF2
_CEN
F10
_LB
L5
M10
_OE
F11
_REN
_RESET
K5
L4
_UB
K6
_WEF
_WEN
F4
_WEPS
J2
F3
T7
T8
NC96
NC97
T9
T10
NC98
NC99
T11
M2
R__BF
R__BN
F12
K10
VCCF1
VCCF2
K11
F8
VCCN1
R7
VCCN2
K12
VCCPS
F7
VSS1
VSS2
G2
G13
VSS3
L13
VSS4
P2
NC80
NC81
R3
R4
NC82
NC83
R5
R6
NC84
NC85
R9
R10
NC86
R11
NC87
R12
NC88
NC89
R13
B1
NC9
T2
NC90
NC91
T3
T4
NC92
NC93
T5
T6
NC94
NC95
NC66
NC67
J12
J13
NC68
NC69
K1
A13
NC7
K2
NC70
NC71
K13
K14
NC72
NC73
L1
L2
NC74
NC75
L3
NC76
L14
NC77
M9
NC78
N9
NC79
P7
NC8
A14
R2
NC51
NC52
E8
E9
NC53
NC54
E10
E11
NC55
NC56
E12
E13
NC57
NC58
F2
F9
NC59
NC6
A12
F13
NC60
NC61
G6
G7
NC62
NC63G8NC64
G10
NC65
J10
J11
NC37
NC38
D8
D9
NC39
NC4
A4
NC40
D10
D11
NC41
NC42
D12
D13
NC43
NC44
D14
E1
NC45
NC46
E2
E3
NC47
NC48
E4
E5
NC49
A11
NC5
NC50
E6
E7
C6
C7
NC23
NC24
C8
C9
NC25
NC26
C10
C11
NC27
NC28
C12
C13
NC29
A3
NC3
NC30
C14
D1
NC31
NC32
D2
D3
NC33
NC34
D4
D5
NC35
NC36
D6
D7
AA2
NC14
B12
AA3
NC140
NC141
AA4
AA11
NC142
NC143
AA12
AA13
NC144
NC145
AA14
B13
NC15
NC16
B14
C1
NC17
NC18
C2
C3
NC19
NC2
A2
NC20
C4
C5
NC21
NC22
NC124
NC125
V10
V11
NC126
NC127
V12
V13
NC128
NC129
V14
B11
NC13
Y1
NC130
NC131
Y2
Y3
NC132
NC133
Y4
Y11
NC134
NC135
Y12
Y13
NC136
NC137
Y14
AA1
NC138
NC139
NC11
U9
NC110
NC111
U10
U11
NC112
NC113
U12
U13
NC114
NC115
U14
V1
NC116
NC117
V2
V3
NC118
NC119
V4
NC12
B4
V5
NC120
NC121
V6
V7
NC122
NC123
V8
V9
P9
P10
IO6
IO7
P11
P12
IO8
A1
NC1
NC10
B2
T12
NC100
NC101
T13
U1
NC102
NC103
U2
U3
NC104
NC105
U4
U5
NC106
NC107
U6
U7
NC108
NC109
U8
B3
DQ12
H11
DQ13
H9
DQ14
G11
DQ15
DQ2
L10
DQ3
L12
J9
DQ4
DQ5
H12
DQ6
H10
DQ7
G12
M12
DQ8
L9
DQ9
IO1
P3
P4
IO2
IO3
P5
P6
IO4
IO5
A22
N4
A3
A4
N3
N2
A5
M6
A6
A7
M5
J5
A8
A9
J6
F5
ALE
K4
CE2PS1
CE2PS2
K3
CLE
F6
DQ0
M11
DQ1
M13
L11
DQ10
DQ11
K9
H13
P8
A0
N6
A1
A10
H2
H3
A11
A12
H4
H5
A13
A14
H6
G3
A15
G9
A16
M4
A17
A18
M3
A19
J4
A2
N5
J3
A20
A21
G4
G5
U301
TV00AC9122_123AOBG
V_FLASH
TP510
TP511
TP512
0.1u
C307
TP520
TP513
R351 10K
R355 10K
V_FLASH
V_FLASH
_WR
FDP
NAND_WP1
D(9)
_RDYMEM
NAND_RnB
_CS0
_CS5
NAND_CE1
_BLE
_RD
NAND_RE
_BHE
NAND_WE
NAND_D(0:7)
D(0:15)
A(1:23)
_CS1
_CS3
A(8)
A(9)
A(10)
NAND_ALE
NAND_CLE
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
A(1)
A(2)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(3)
A(21)
A(22)
A(4)
A(5)
A(6)
A(7)
- 21 -
3. TECHNICAL BRIEF
(3) RF Interface (TPU, TSP block)
Calypso-Plus uses this interface to control ABB Processor and RF Processor with GSM
Time Base.
Table 5. RF Interface Spec.
(4) SIM interface
SIM interface scheme is shown in (Figure 9.). SIM_IO, SIM_CLK, SIM_RST ports are
used to communicate DBB with ABB and the Charge Pump in ABB enables 1.8V/3V
SIM operation.
Figure 9. SIM Interface
SIM_RST
SIM_CLK
SIM_SOCKET
V_SIM V_SIM
J1
SIM_IO
C235
150p
C236
1
2
3
VCC
RST
CLK
GND
VPP
IO
5
C230
0.1u
R230
10K
6
7
22p
TSP (Time Serial Port)
Resource Interconnection Description
TSPDO ABB & RF main Chip Control Data
TSPEN0 ABB ABB Control Data Enable Signal
TSPEN1 RF main Chip RF Control Data Enable Signal
TPU (Time Processing Unit) Parallel Port
TSPACT00 RESET_RF RF main Chip Reset Signal
TSPACT01 PA_ON Power Amp ON signal
SIM_CLK : SIM Card reference clock
SIM_RST : SIM Card async/sync reset
SIM_IO : SIM Card bi-directional data line
SIM_PWCTRL : SIM Card power activation
SIM_RnW : SIM Card data line direction
SIM_CD : SIM Card presence detection
- 22 -
3. TECHNICAL BRIEF
(5) Serial Interface
Calypso-Plus has UART-IRDA and two UART Modem Drivers. (UART Modem2 is not
used at F1200).
Table 6. UART Interface Spec.
(6) USB Interface
The USB_W2FC module supports the implementation of a “Full-Speed” device fully compliant to
USB 1.1 standard. It provides an interface between the MCU and the USB device and handles
USB transactions with minimal MCU intervention.
The USB_W2FC module supports one control endpoint (EP0), up-to fifteen (15) IN endpoints
and up-to fifteen (15) OUT endpoints. The exact endpoint configuration is software
programmable. The specific items configurable for each endpoint are the size in bytes, the
direction (IN, OUT), the type (Bulk/Interrupt or ISO), and the associated endpoint number.
The USB_W2FC module also supports three DMA channels for IN endpoints and three DMA
channels for OUT endpoints for either Bulk/Interrupt or ISO transactions. In operation, the USB
requires a 48MHz clock generated by a dedicated embedded DPLL upon request. The USB
module interface is PVCI compliant. Therefore this module interfaces with the TI MCU RHEA
bus via a RHEA-PVCI bridge.
Calypso-Plus integrates differential drivers to allow a glue-less connection with any host. The
required 3.3V VDD is provided by the VBUS signal taken from the USB connector.
- USB_DP : USB differential (+) line.
- USB_DM : USB differential (-) line.
- USB_PU_EN : USB pull-up enable.
UART MODEM (UART1)
Resource Interconnection Description
TX_MODEM1 TXD Transmit Data
RX_MODEM1 RXD Receive Data
CTS_MODEM1 CTS Clear To Send
RTS_MODEM1 RTS Request To Send
RTS_MODEM1 DSR Data Set Ready
UART IRDA (UART -IRDA)
TXIR_IRDA TXIR_IRDA Infra-Red Transmit Pulse
TX_IRDA TX Transmit Data (UART2)
RXIR_IRDA RXIR_IRDA Infra-Red Receive Pulse
RX_IRDA RX Receive Data (UART2)
SD_IRDA SD_IRDA IRDA transceiver Shut Down Mode
- 23 -
3. TECHNICAL BRIEF
Figure 10. USB interface diagram
(7) Audio Circuits
Figure 11. Audio Circuit Diagram
C536
8200p
C548
0.1u
47p
C528
330
R500
C519
10u
4.7uC543
1u
C511
C534
0.1u
390K
R506
C529
47p
AVLC14S02050
VA507
NA
R519
120R503
C527 10u
R510
33
16
2
3
4
5
6
7
8
9
AVLC14S02050
VA503
CN500
1
10
11
12
13
14
15
10u
C520
MAX4684EBC
U505
COM1
C3
A3
COM2
GND
B1
C2
IN1
A2
IN2
C1
NC1
A1
NC2
C4
NO1
NO2
A4
B4
V+
_SD
A1
C523
47p
A2
GND1
GND2
A3
B3
GND3
GND4
C2
C3
GND5
GND6
D2
D3
GND7
C1
IN+
D1
IN-
NC
B1
VDD1
B4
VDD2
C4
VO+
D4
A4
VO-
TPA2005D1GQYRU501
100nH
L502
47p
C524
0.1u
C535
R529
15K
R504 120
15K
R530
1.5V_CORE
R520
47K
C547
1000p
220n
C541
C538
220n
1K
R518
120R505
1K
R507
NA
C569
C546 1000p
R512100nH
AVL5M02-200
VA500
0.1u
C510
47p
C532
R508
120
C506
47p
C502
1000p
10uC526
47p
C505
2.2K
R513
R511
33
10u
C501
1u
C525
VA509
AVL5M02-200
0
R532
1K
R569
0.1u
TP522
C513
TP521
47K
R534
1uC540
15K
R516
C542 4.7u
C512
8200p
GND1
A2
A3
GND2
GND3
B3
C2
GND4
GND5
C3
D2
GND6
GND7
D3
IN+
C1
IN-
D1
B1
NC
B4
VDD1
C4
VDD2
D4
VO+
VO-
A4
A1
_SD
U503 TPA2005D1GQYR
D503
INSTPAR
C544
UCLAMP0501H
0.1u
0.1u
AVL5M02-200
VA508
C503
R536
56K
10u
C537 1u
C576
C531
680p
VA506
AVLC14S02050
C568
NA
47p
C500
R517
15K
0.1u
C545
R528
62K
62K
R527
47p
C522
VIN1
1
VIN2
5
8
VOUT1
6
VOUT2
_SHDN
4
U504 LM4809LD
9
BGND
BYPASS
23
GND
7
VDD
R531 15K
C530
2.8V_DSP
680p
TM0
C2
F2
TM1
B3
TM2
TM3
A3
B4
TM4
A5
TRSCK
VIB
D9
VREF
E2
WR_B_SCLK
K7
NC6
J9
B10
NC7
NC8
B1
J1
NC9
K3
PO0
PO1
J3
PO2
K4
J4
PO3
PS
B6
RDATA
A4
J7
RD_B_SPIMODE
E9
RESET_B
K1
SHORT_A1
SHORT_A10
K10
SHORT_K1
A1
A10
SHORT_K10
K2
NC13
NC14
C3
D3
NC15
NC16
E3
F3
NC17
NC18
G3
H3
NC19 NC2
D8
D4
NC20
NC21
H5
C6
NC22
NC23
H6
C7
NC24
G8
NC3
NC4
H8
B9
NC5
C8
DVDD3
DVDD4
D10
DVDD5
K9
A6
EGND
C9
EVDD
INT_DSP_B
F8
E10
INT_SG_B
D2
IREF
C10
LED
LINEOUT_L
C1
F1
LINEOUT_R
A8
LRCLK
H7
NC1
NC10
A2
B2
NC11
NC12
J2
H2
CLKIN
J6
CS_B_SCS
D0_SERINIT
K8
J8
D1
D2
H10
D3
H9
G10
D4
G9
D5
D6
F10
D7
F9
C5
DGND1E8DGND2
J10
DGND3
DGND4
K5
A9
DVDD1
DVDD2
C4
A0_DATA_TXD
K6
J5
A1_RXD
A2
H4
D1
AGND1
AGND2
G1
H1
AGND_P
A7
ASI
ASO
B7
AVDD
E1
AVDD_P
G2
BCLK
B8
CLK8K
B5
120R501
U506
UPD9993
1u
C521
R509
390K
C539
1u
L501
100nH
0.1u
C533
47p
C504
R533 15K
2.8V_DSP
R502 120
AVL5M02-200
VA505
VA504
AVLC14S02050
VA501
AVL5M02-200
MIDI_CS
_RD
_WR
HSOL
HSOR
AD
A(2)
A(1)
D(0:7)
MIDI_INT
MCLK
VIBRATOR
DSP_RESET
KBC(5)
KBR(3)
KBR(2)
JACK_TYPE
KBR(1)
MIDI_EN
SPKL_N
SPKL_P
SPKR_N
SPKR_P
HP_AMP_EN
SPK_EN
HSMIC
HSBIAS
JACK_DET
HOOK_DET
- 24 -
A. MIDI and MP3/AAC Decoder (NEC, uPD993)
NEC uPD9993 (U506) is the PCM sound generator and the MP3/AAC decoder LSI that
includes an on-chip real-time wide surround function for mobile phones. The uPD9993
includes a 8-bit parallel host interface, a 3/4 serial peripheral interface (SPI), control ports for
LED, Vibrator, and 4-general purpose I/Os. In F1200, uPD9993 is driven with 13MHz master
clock from DBB (Calypso plus). Stereo Audio signals are transferred to next stage from stereo
lineout ports of uPD9993. uPD9993 has internal analog volume stage. So volume control can
be operated in uPD9993.
Figure 12. Audio Circuit Diagram
3. TECHNICAL BRIEF
C548
0.1u
4.7uC543
1.5V_CORE
R520
47K
C547
1000p
220n
C541
C546 1000p
0
R569
0.1u
TP522
C513
TP521
47K
R534
C542 4.7u
C544
0.1u
R536
56K
0.1u
C545
2.8V_DSP
TM0
C2
F2
TM1
B3
TM2
TM3
A3
B4
TM4
A5
TRSCK
VIB
D9
VREF
E2
WR_B_SCLK
K7
NC6
J9
B10
NC7
NC8
B1
J1
NC9
K3
PO0
PO1
J3
PO2
K4
J4
PO3
PS
B6
RDATA
A4
J7
RD_B_SPIMODE
E9
RESET_B
K1
SHORT_A1
SHORT_A10
K10
SHORT_K1
A1
A10
SHORT_K10
K2
NC13
NC14
C3
D3
NC15
NC16
E3
F3
NC17
NC18
G3
H3
NC19 NC2
D8
D4
NC20
NC21
H5
C6
NC22
NC23
H6
C7
NC24
G8
NC3
NC4
H8
B9
NC5
C8
DVDD3
DVDD4
D10
DVDD5
K9
A6
EGND
C9
EVDD
INT_DSP_B
F8
E10
INT_SG_B
D2
IREF
C10
LED
LINEOUT_L
C1
F1
LINEOUT_R
A8
LRCLK
H7
NC1
NC10
A2
B2
NC11
NC12
J2
H2
CLKIN
J6
CS_B_SCS
D0_SERINIT
K8
J8
D1
D2
H10
D3
H9
G10
D4
G9
D5
D6
F10
D7
F9
C5
DGND1E8DGND2
J10
DGND3
DGND4
K5
A9
DVDD1
DVDD2
C4
A0_DATA_TXD
K6
J5
A1_RXD
A2
H4
D1
AGND1
AGND2
G1
H1
AGND_P
A7
ASI
ASO
B7
AVDD
E1
AVDD_P
G2
BCLK
B8
CLK8K
B5
U506
UPD9993
2.8V_DSP
MIDI_CS
_RD
_WR
AD
A(2)
A(1)
D(0:7)
MIDI_INT
MCLK
VIBRATOR
DSP_RESET
- 25 -
3. TECHNICAL BRIEF
B. Speaker Amplifier (TPA2005)
TPA2005 is a mono power amplifier for loud speaker. Two amplifiers are used for stereo
operation. It drives a speaker up to 1W power in full differential mode. In F1200, input signals
are single-ended mode and output signals are differential mode. Speaker Amplifier is
controlled with SPK_EN signal from DBB (Calypso plus) which can enable or disable the
amplifiers.
Figure 13. Speaker Amplifier circuits
C. Headphone Amplifier (LM4809LD)
LM4809LD is a stereo headphone amplifier. It includes two amplifiers, which can drive a earpiece up to 70mW power. The LM4809LD operates in single-ended mode and controlled with
HP_AMP_EN signal from DBB (Calypso plus).
Figure 14. Headphone Amplifier circuits
C536
8200p
C519
10u
C511
0.1u
10u
C520
_SD
A1
C523
47p
A2
GND1
GND2
A3
B3
GND3
GND4
C2
C3
GND5
GND6
D2
D3
GND7
C1
IN+
D1
IN-
NC
B1
VDD1
B4
VDD2
C4
VO+
D4
A4
VO-
TPA2005D1GQYRU501
47p
C524
0.1u
C535
R529
15K
15K
R530
1K
R518
0.1u
C510
47p
C532
1u
C525
R532
1K
15K
R516
C512
8200p
GND1
A2
A3
GND2
GND3
B3
C2
GND4
GND5
C3
D2
GND6
GND7
D3
IN+
C1
IN-
D1
B1
NC
B4
VDD1
C4
VDD2
D4
VO+
VO-
A4
A1
_SD
U503 TPA2005D1GQYR
R517
15K
47p
C522
1u
C521
0.1u
C533
SPKL_N
SPKL_P
SPKR_N
SPKR_P
SPK_EN
1u
C534
C538
220n
1uC540
C537 1u
C531
680p
R528
62K
62K
R527
VIN1
1
VIN2
5
8
VOUT1
6
VOUT2
_SHDN
4
U504 LM4809LD
9
BGND
BYPASS
23
GND
7
VDD
R531 15K
C530
680p
R533 15K
HP_AMP_EN
- 26 -
D. Analog S/W
Analog S/W selects voice path or music (MP3/AAC) path according to the control signal of
MIDI_EN from DBB (calypso plus). Two voice signals (HSOL, HSOR) are voice signal from
ABB (Syren). And two music signals are from the headphone amplifier which amplify the
music signals from MP3/AAC decoder (uPD9993). The output signals are connected to earset through the 12-pin ear-jack.
Figure 15. Analog S/W Circuits
E. Power Supply Circuits for uPD9993
The uPD9993 needs three power supply 1.5V for digital core, 2.8V for analog core, 2.8V for
external interfaces. In F1200, the power supplies for analog core and external interfaces are
combined with one supply. So dual LDO is used power supply for uPD9993. “1.5V_CORE” is
for digital core of uPD9993 and “2.8V_DSP” is for analog core and external interfaces of
uPD9993. The LDO is controlled with REGEN signal from ABB (SYREN).
Figure 16. LDO Circuits for uPD9993
3. TECHNICAL BRIEF
2
EN1
3
EN2
GND
6
NC1
5
7
NC2
NC3
8
1
VIN VOUT1
10
9
VOUT2
MIC2211-FMBMLU500
11
BGND
BYP
4
2.2u
C508
2.2u
C507
0.01u
C509
HSOL
HSOR
C568
NA
C569
NA
U505
MAX4684EBC
L502
100nH
LD
8
1
6
2
3
D
9
D
L501
100nH
C4
NO1
A4
NO2
C1
NC1
A1
NC2
C539
1u
B4
V+
C2
IN1
A2
IN2
C3
COM1
A3
COM2
GND
R519
B1
NA
MIDI_EN
C528
47p
C529
47p
10uC526
C527 10u
HSBIAS
HSMIC
R511
33
R510
33
- 27 -
3. TECHNICAL BRIEF
(8) Keypad Switching & Scanning
Table 7. Keypad Map
DBB supports 6x6 keymap and Switch-ON Key is connected directly to ABB as (Figure 16.).
Figure 17. Keypad Scanning Scheme
Close to Side-key PAD
RIGHT
5
CLEARSHUT
VA304
AVLC14S02050
STAR 0
8
R338 680
680R339
6
R342 680
680R337
F2
LEFT
680R318
R336 680
1
2
OK
CN301
R341 680
680R334
SHAP SEND
1
7
F1
680R340
F3
9
AVLC14S02050
VA301
R335 680
680R343
R311
100
END
32
680R333
R310
100
UP DOWN
4
KBC(5)
KBR(4)
KBR(1)
KBR(2)
KBR(3)
KBR(0)
KBC(0)
KBC(1)
KBC(2)
KBC(3)
KBC(4)
PWON
KBC0 KBC1 KBC2 KBC3 KBC4 KBC5
KBR0 [ ] [ ] [ ] [ ] [OK] F3
KBR1 [1] [2] [3] SHUT CLEAR
KBR2 [4] [5] [6] [F1] [Vol Up]
KBR3 [7] [8] [9] [F2] [Vol Down]
KBR4 [*] [0] [#] [SEND]
▲
▲
▲
▼
- 28 -
(9) Keypad back-light Illumination
There are 12 Deep Blue LEDs in Main Board for Keypad Backlight. Keypad Back-light is driven
by ‘KEY_BACKLIGHT’ (GPIO0) line from DBB.
Figure 18. Keypad Back-light Scheme
(10) LCD Back-light Illumination
Figure 19. LCD Back-light driving scheme
3. TECHNICAL BRIEF
R360
1.5K
20
R358
100
R320
0
R306
LEBB-S14H
LD301
LD308
LEBB-S14H
R312
0
LD305
LEBB-S14H
VBAT
LD307
LEBB-S14H
0
R302
R314
100
LD300
LEBB-S14H
LEBB-S14H
LD306
100
R322
LD304
LEBB-S14H
LEBB-S14H
LD309
100
R326
R316
100
100
R321
R313
0
R359
100K
25631
4
Q301
IMX9T110
LD302
LEBB-S14H
LD303
LEBB-S14H
LD310
LEBB-S14H
R319
100
100
R332
20
R361
LEBB-S14H
LD311
KEY_BACKLIGHT
1u
C499
ISINK2
11
12
ISINK3
ISINK4
1
OUTCP
5
PGND
13
AAT3152IWPU400
C1+
3
4
C1-
C2+
6
7
C2-
EN_SET
2
9
GND
IN
8
10
ISINK1
1u
C409
C404
1u
0R499
C401
1u
NA
R574
C400
VBAT
1u
LCD_BACKLIGHT
MLED1
MLED2
MLED
MLED3
3. TECHNICAL BRIEF
EN_SET is the serial interface control pin connected to the GPIO of DBB. EN_SET sets the
current sink magnitudes and allows independent group control: ISINK1~4. Four constant current
sink inputs (ISINK1to ISINK4) can drive four individual LEDs with a maximum current of 20mA
each. The unused sink inputs have to be connected to OUTCP (High), otherwise the part will
operate only in 2x charge pump mode.
(11) Vibrator
Figure 19. Vibrator control scheme
- Vibrator is controlled by MIDI Chip (U506)
- When VIBRATOR signal is high, the vibrator is enabled
L301
100nH
R304
1.5K
100nH
L300
56p
C302
15
R303
R305
100K
1SS302
3
1
2
D300
VIBRATOR
MOTOR
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