LG CRD-8485B Service Manual

3

INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible 486SX or Above (With PIO mode 4 recommended)

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Data Transfer Rate..........................................................................................Sustained Data Transfer Rate

20Times Speed (Inner side) : 3,000 kbytes/sec

48 Times Speed (max., Outer side) : 7,200 kbytes/sec

• Data Buffer Capacity .....................................................................................................................128 kbytes

• Access Time ...................................................................................................Random Access Time : 75 ms

4. POWER REQUIREMENTS

• Voltage.......................................................................................................................................+5V DC +5%

+12V DC +5%

• Ripple...................................................................................................................+5V : Less than 100mVp-p

+12V : Less than 100mVp-p

• Current........................................................................................................................+5V : 0.9A (Maximum)

+12V : 1.5A (Maximum)

5. AUDIO PERFORMANCE

• Frequency Response .....................................................................................................20Hz~20KHz(+3dB)

• S/N Ratio (IHF-A+20 KHz LPF)........................................................................85 dB (Typical at 1 KHz 0dB)

80 dB (Limit at 1 KHz 0dB)

• T.H.D. (IHF-A+20 KHz LPF) ............................................................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)

• Channel Separation (IHF-A+20 KHz LPF)..............................................................................80 dB (Typical)

70 dB (Limit)

• Output Voltage (1kHz 0dB) 47KΩ Load .................................................................................0.7Vrms +10%

• Headphone Level (1kHz 0dB) 33Ω Load ...............................................................................0.7Vrms +20%

• Enhanced IDE interface

• Internal 5.25 inch, halfheight CD-ROM Drive

• Fast 75ms Average Access Time

• Max 7,200KB/sec Sustained Transfer rate

• Photo-CD Multisession Disc Spec compliant

• Multimedia MPC-3 Spec compliant

• Power Tray Loading/Ejection Mechanism

• 3 Way Eject support (Software, O/C Button,

Emergency Eject)

• Closed Enclosure

• Built-in ATAPI Interface Controller

• Software Volume Control

• 8 Times Digital Filter for CD Audio

•

Front panel Volume Control for Headphone Output

• Built-in MODE-1 ECC/EDC

• MTBF 125,000h POH (at 10% Utilization)

• PIO Mode 4 & Multi DMA Mode 2 support

• Horizontal or Vertical Mounting

• Digital audio output connector

• Digital audio through ATAPI Interface

• Subcode (P-W) through ATAPI Interface

• Spin-down Mode for energy saving

• MS-DOS Version 3.1 or Higher

• OS/2 Warp (Ver 3.0)

• Windows '95/'98

• Solaris Ver 2.4 or Higher

• Linux slackware Ver 2.3

• Windows NT 4.0 or later

This service manual provides a variety of service
information. It contains the mechanical structure of
the CD-ROM Drive together with mechanical
adjustments and the electronic circuits in schematic

form. This CD-ROM Drive was manufactured and
assembled under our strict quality control standards
and meets or exceeds industry specifications and
standards.

4

LOCATION OF CUSTOMER CONTROLS

(1) Headphone Jack

3.5mm jack for monitoring the audio signal from audio
CDs.

(2) Headphone Volume Control

Adjusts the headphone sound level.

(3) Disc Drawer

Accepts a CD-ROM disc on its tray.

(4) Busy Indicator

The Busy Indicator lights during initialization and data­read operations.

(5) Emergency Eject Hole

Insert a paper clip here to eject the drawer manually or
when there is no power.

(6) Play/Skip Button

When an Audio CD is in the Disc Drawer, pressing
this button will start playing audio CDs from the first
track. If an audio CD is playing, pressing this button
will skip to the next track.

(7) Open/Close/Stop Button

This button is pressed to open or close the CD tray.
If an audio CD is playing, pressing this button will stop
it, and pressing it

again will open the tray.

COMPACT

1

2

54 6 73

Figure 1. Front View

(1) Digital Audio Output Connector

This is a digital audio output connector or Video CD
output connector.
You can connect this to the digital audio system or
Video CD Board.

(2) Analog Audio Output Connector

The Audio Output Connector connects to a sound
card.
The supplied audio cable is a SoundBlaster

®

type
cable. If you have a different sound card, you will
need to contact the sound card manufacturer to obtain
the proper cable for that card.

(3) Master / Slave / CSEL Jumper

These three jumpers are used to set the CD-ROM
Drive to either a Master, Slave, or CSEL drive.

(4) Interface Connector

This 40-pin connector is used to transfer and control
signals between the CD-ROM Drive and your PC.
Connect the 40-pin IDE cable in your PC to this
connector.

(5) Power-in Connector

Attach a power cable from the computer to this
connector.

Figure 2. Back View

DIGITAL ANALOG

INTERFACE POWER

DR CSM

SLA

GLG39 1

+5

+12

GND

40

2

AUDIO AUDIO

1

2

5

4

3

FRONT

REAR

Figure 2. Back View

2. Trouble List (Circuit)

A. LED doesn’t light.
B. Pick-Up doesn’t move to the inner-track.
C. The Laser of Pick-Up doesn’t light.
D. Pick-Up lens doesn’t move up and down.
E. Disc doesn’t rotate.
F. TOC isn’t read. (The LED turns on, but doesn’t flicker.)
G. During Audio CD Play, LED flickers, but Speaker is silent.

20

TROUBLESHOOTING GUIDE

1. Initial Lead-in Operation

Reset or Power-On.

LED Flickers.

Pick-Up moves to the inner-Track.

Laser on the Pick-Up lights.

Focus Search (through moving up and down the lens of Pick-Up)

Focus Servo On (FEO(IC501 Pin 12 ) signal generation)

Rotate disc.

Tracking Servo On (TEO (IC501 Pin 15 ) Signal generation)

Spindle Servo On (DMSO(TP25) Signal generation)

Read TOC Area (LED Flickers)

Search the Start of Data Area and then pause.

21

3. Troubleshooting Guide

A. LED doesn’t light.

Check Power Voltage (TP1:3.3V, TP2:12V)
Reference Voltage

[TP5:V13(1.3V) and GND.]

Does “H” output in IC501 pin ?

Check and replace R705, R706, Q701
and LED701 (LED703 for DELL).

Is the CLOCK Frequency of
IC501 pin 33.86MHz?

Check the power input
pattern.

Check IC501.

Check and replace
X501; 33.86MHz.

Is the CLOCK Frequency of IC501 pin

33.86MHz?

Check and replace IC501.

YES

OK

NG

YES

YES

NO

NO

NO

37

54

54

A-1

A-1

22

B. Pick-Up doesn’t move to the inner track.

Do the signals appear at IC501
pin , ?
(Refer to Fig. B-1.)

Do the signals appear in PN301
pin?
(Refer to Fig. B-2.)

Does “H” output at IC201
pin ?

Is the 1.3V at IC201 pin ?

Check the pattern from

IC501 pin to IC201

pin

.

Check IC501.

Check IC501.

Check the PN301, and then
replace the Sled Motor.

YES

YES

YES

YES

NO

NO

Replace IC201.

NO

NO

173

41

25

174

165

41

CH1
PIN174
FMO

CH2
PIN173
FMO2

CH1 TP4

CH2 TP5

CH3 TP6

CH4 TP7

Fig. B-1. FMO and FMO2 Signals

Fig. B-2. TP4, TP5, TP6 and TP7 Signals

Check the pattern from
IC501 pin to R225
and then replace IC501.

23

Is the voltage of IC501 pin

(LD0) 1V?

Check Pick-Up FFC, PN101.

Check Q101, C101, C102
and then replace IC101.

YES

NO

10

181

Does the focus search signal
appear at F0S0 (TP9)?
(Refer to Fig. D-1.)

Is the 1.3V at IC201 pin ?

Check IC501.

YES

YES

YES

NO

NO

Replace IC201.

NO

25

Does the focus search signal
appear between F+ (TP10)
and F- (TP11)?
(Refer to Fig. D-2.)

C. The Laser of Pick-Up doesn’t light.

D. The Pick-UP lens doesn’t move up and down.

D-1

24

Check the pattern from
pin , of IC201 to
pin , of PN101.

Check the PN101, Pick-Up
FFC.

Replace the Pick-Up.

Replace PN101 or Pick-Up
FFC.

OK

OK

NG

34

35

1

4

CH1
TP9
(FAO)

CH1
TP10(F+)
TP11(F-)

Fig. D-1. F0S0 Signal

Fig. D-2. Focus Search Signal

D-1

25

Does the signal appear at
the DMS0 (TP25)?
(Refer to Fig. E-3.)

Do the signals appear at
IC201 pin (W), (V),
and (U)?

Replace IC501.

Replace IC201.

YES

NO

NO

12

14

13

Check the pattern from
IC201 pin , , to
PN201 , , .

YES

OK

12

13

14

13

12

11

Check Spindle Motor FFC

and then replace the

Spindle Motor.

Does the signal appear at
FEO(IC501 pin ) when
the R126 opened?
(Refer to Fig. E-1.)

YES

YES

YES

NO

NO

Replace IC501.

Replace IC501.

Replace Pick-Up.

NO

Do the signal appear at
FEO (IC501 pin )?
(Refer to Fig. E-2.)

Does the signal appear at
F+(TP10) during focus
search?

E. Disc doesn’t rotate.

12

12

26

Fig. E-2. FEO Signal

CH1
TP15:
FEO

Fig. E-3. DMS0 Signal

CH1
TP25:
DMS0

Fig. E-1. S-Curve

CH1
TP15:
S-Curve

27

Is the Focus Servo ON?
(Does FEO(IC501 pin )
signal appear?)

Does A, B, C, D signal
appear at IC501 pin ,

?

YES

YES

NO

3

12

4

NO

Is the Tracking Servo ON?
(Does TEI (IC501 Pin )
signal appear?)

Does E, F signal appear
at IC501 pin , ?

YES

NO

8

YES

Is TOC area on the disc
read? (Does LED flicker?)

Does the other disc
operate normally?

Normal Disc is defective.

YES YES

NO

9

NO

Does RFAC signal (IC501
Pin ) appear?

Is Spindle Servo ON?
(Does DMS0 signal
(TP25) appear?)

YES YES

NO

NO

NO

Does RFI signal appear
at IC501 pin ?

1

20

Replace IC101.

Replace IC501.

Replace IC501.

Replace Main Circuit
Board or MD Ass’y.

NO

Refer to C.
(The Laser of Pick-Up
doesn’t light.)

F. TOC isn’t read.

15

28

Does Audio signal appear
at IC501 pin , ?
(Refer to Fig. G-1.)

YES

NO

110 112

Replace IC501.

Does “H” signal appear at

IC501 pin ?

YES

NO

25

Check the IC501 pin
and then replace IC501?

108

Check C702.

YES

YES

YES

Are L-ch, R-ch signals
appear at JK701 and
Audio Line out connector
each?

NO

Check JK701 and
L701,L703.

Does Audio signal appear
at IC701 pin , ?

NO

1 7

Is the voltage of IC701
pin ?

6

NO

Replace IC701.

G. During Audio CD play, LED flickers, but Speaker is silent.

G-1

29

Is the connection
between JK801 (or Audio
Line out connector) and
Line (or Jack) normal?

NO

Check the JK801 and
Audio line pattern.

YES

Check your sound card,
Audio Cable, Speaker,
Volume and Headphone
Jack.

Fig. G-1. Audio Signal

CH2
PIN3 of
IC601

CH2
PIN12 of
IC601

G-1

1. CABINET and CIRCUIT BOARD
DISASSEMBLY

1-1. Bottom Chassis

A. Release 4 screws (A) and remove the Bottom

Chassis in the direction of arrow (1). (See Fig. 1-1)

1-2. Front Bezel Assy

A. Insert and Press a rod in the Emergency Eject

Hole and then the CD Tray will open in the
direction of arrow (2).

B. Remove the Tray Door in the direction of arrow (3)

by pushing it outward.

C. Release 3 stoppers and remove the Front Bezel

Assy.

1-3. Cabinet and Main Circuit Board

A. Remove the Cabinet in the direction of arrow (4).

(See Fig. 1-3)
B. Release 2 hooks (a) and remove the CD Tray.
C. Remove the Soldering of the LD- and LD+ (B) for

the Loading Motor, and then remove the Main

Circuit Board.
D. At this time, be careful not to damage the 3

connectors of the Main Circuit Board.

2. MECHANISM ASSY

A. Separate the Pick-Up Unit from the Mechanism

Assy.
B. Release 1 screws (C) and then remove the Pick-

Up ( ).

DISASSEMBLY

(A)

(A)

(A)

(A)

(1)

Bottom Chassis

Fig. 1-1

Fig. 1-2

Fig. 1-3

Fig. 1-4

5

Cabinet

(4)

Hooks (a)

(B)

Main

Circuit Board

Tray Door

(3)

Stoppers

Emergency Eject Hole

(2)

Front Bezel Assy

CD Tray

Pick-up Unit

(C)

Mechanism Assy

10

PHOTO DIODE STRUCTURE OF THE PICK-UP

(1) Focus Error Signal –> (A+C)-(B+D)

(Control the Pick-up’s up and down to focus on the Disc)

(2) Tracking Error Signal –> (E-F)

(Control the Pick-up’s left and right shift to find the track on the Disc)

(3) RF Signal –> (A+B+C+D)

(

RF Signal is converted to Data Signal in One Chip IC (IC501))

Three signals (Focus Error Signal, Tracking Error Signal and RF Signal) above are I-V converted and
amplified at the IC501 and generated the Servo Control Signal and Data Signal.

Red laser

Pick-Up module

Tracking

Focusing

B

C

E

F

D

A

11

IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

• IC201 (M63022FP) : Drive IC (Spindle/Servo Actuator)

Rotates the Spindle Motor by receiving MDP signal from IC501.
Generates the signal to drive Focus Actuator Coil, Tracking Actuator Coil, Sled Motor, and Stepping
Motor by Control Signal input from DSP and u-COM.

Block Diagram

x12

x8

x12

FG

HU+
HU­HV+
HV-

HW+
HW­HB

SPIN

REF

SL1IN

SL2IN

FOIN

TOIN

5Vcc

TO+

TO-

FO+

FO-

GND

LO+

LO-

VM3

LOIN+

BRS

OSC

MU1

S

SS

S

VM1

RSPUV

W

RSL1

RSL2

SL1+

SL1-

SL2+

SL2-

VM2

FG

Reverse
Detect

120ß

MATRIX

Hall Bias

CTL
amp

Direction

comp

Direction

comp

Direction

comp

Current

comp

Current

comp

Current

comp

CTL
amp

CTL
amp

Logic

Logic

TSD

BIAS

Frequency

generator

VM1

Regulator

Reg

Pin Description

Pin No.

Symbol Description

Pin No.

Symbol Description

1 SL1IN Slide control voltage input 1
2 SL2IN Slide control voltage input 2
3 VM2 Motor Power Supply 3 (for Slide)
4 RSL2 Slide current sense 2
5 SL2+ Slide non-inverted output 2
6 SL2- Slide inverted output 2
7 GND GND
8 RSL1 Slide current sense 1

9 SL1+ Slide non-inverted output 1
10 SL1- Slide inverted output 1
11 GND GND
12 W Motor drive output W
13 V Motor drive output V
14 U Motor drive output U
15 RSP Spindle current sensie
16 HW- HW- sensor amp. input
17 HW+ HW+ sensor amp. input
18 HV- HV- sensor amp. input
19 HV+ HV+ sensor amp. input
20 HU- HU- sensor amp. input
21 HU+ HU+ sensor amp. input

22 VM1 Motor Power Supply 1 (for Spindle)
23 HB Bias for Hall Sensor
24 FG Frequency generator output
25 REF Refernce voltage input
26 SPIN Spindle control voltage input
27 FOIN Focus control voltage input
28 TOIN Tracking control voltage input
29 GND GND
30 5VCC 5V Power Supply (for FS, TS)
31 TO- Tracking inverted output
32 TO+ Tracking non-inverted output
33 GND GND
34 FO+ Focus non-inverted output
35 FO- Focus inverted output
36 LO+ Loading non-inverted output
37 LO- Loading inverted output
38 BRS Brake select control terminal
39 VM3 Motor power supply 3.(for Loading)
40 LOIN+ Loading control input( +)
41 MU1 Mute 1
42 OSC PWM carrier oscilation set

Servo

ADC

Servo

DSP

PDM

&

PWM

DAC

Sync

Protection

CLV &

Zone-CLV

& True-

CAV

Control

Reset

Circuitry

IPLL

Decoder & uP

Clock Generator

Mega Interface

and GPIO Control

Host

Interface

Logic

CIRC Error
Correction

EFM & Q-

code

Demodulation

Varipitch

Clock

Generator

DAC &

LPF

Over-sampling

Digital Filter

Digital

Emphasis

Audio

Processing

Unit

RSPC

Sync

Detector

Descrambler

RSPC

Decoding

Logic

Subcode

FIFO/

Parallelizer

Buffer Memory Controller

X'tal Clock
Generator

DSP Data

FIFO/

Parallelizer

8032

Micro processor

&

ICE Interface

Controller

&

Flash Controller

Mega

Interface

and

GPIO

Control

High Speed

Audio

Playback

Logic

Host

Data FIFO

ATAPI
Packet

FIFO

REF

APC

20

RFOP

156 IPLLVDD

155 DD7

154 DD8
153 DGND

152 DD6
151 DD9

150 DD5

149 DVDD
148

DD10
147 DD4

146 DD11
145 DD3

144 DGND
143

DD12
142

DD2
141

DD13
140

DD1
139

DD14
138

DGND

136

137

DD0

DD15
135

134

DMARQ

133

DIOW_

132

DIOR_

131

IORDY

130

DMACK_

129

INTRQ

128

IOCS16_

127

DVDD

126

DA1

125

PDIAG_

124

DVDD3

123

DA0

122

DA2

121

DGND

120

CS1FX_

119

CCS3FX_

118

DASP_

DEVSEL
117 ADGO/VIC

VPVSS

116

VCOCIN

115

VOVDD

114

DACVDD

113
112

LO

111 DACVREF
110

RO
109

DACVSS
108

RA3
107 RA4

106 RA2
105 RA5

208

RGND

207

MDI

10

LDO

2

SVDD

5

SGND

3

FNI

4

FPI

11

FEN

13

FEP

12

FEO

6

CSNI

7

CSPI

17

CSO

8

TPI

9

TNI

14

TEN

15

TEO

16

SBAD

18

TAVSS

21

TMA

22

TAVDD

23

TMB

24

IO1

25

IO2

26

IO3

37

LED

38

EJECT_

39

PLAY_

35

DVDD

36

TEST_EN

27

URD_/IO4

28

UP3_5/UT1

29

UP3_4/UT0

30

DGND

31

UNIT1_/IO5

32

UP3_2/UNIT0_

33

UP3_1/UTXD

34

UP3_0/URXD

40

ICEMODE

41

UWR_/IO6

42

UALE/08

43

UP1_0/UA16

44

UP2_7/UA15

45

UP2_5/UA14

46

UP2_5/UA13

47

UP2_4/UA12

48

UP2_3/UA11

49

UP2_1/UA9

50

UPSEN_/09

51

UP2_0/UA8

52

53

UP2_/UA10

DVDD3

19

RFON1RFI

206

205

OSN

OSP

204

RVDD

203

V20

202

V13

201

V26

200

VOSN

199

VOSP

198

VOSNI

197

VOSPI

196

PLLVDD

195

IREF

194

PLLVSS

193

LPFN

192

LPFOP

191

LPFON

190

SPDON

189

SPDOP

188

PLLVDD

187

ADCVDD

186

RFRO

185

RFRPSLV

184

ADCVSS

183

TEZILP

182

PDMVDD

181

FOO

180

TRO

179

PDMVSS

178

DGND

177

TEBC

176

DVDD3

175

DMO

174

FMO

173

FMO2

172

HRFZC

171

DGND

170

ENDM

169

DVDD

168FG167

POR

166

RESET/O18

165

IO0

164

DVDD3

163

LIMIT_

162

TRCLOSE

161

TROPEN

160

TRAYOUT_

159

TRAYIN_

158

HRST_

157

IPLLVSS

54

XTALI

55

XTALO

56

DGND

57

FWR_

58

IO7/CS_

59

DVDD3

60

UP0_7/UAD7

61

UP0_6/UAD6

62

UP0_5/UAD5

63

UP0_4/UAD4

64

UP0_3/UAD3

65

UP0_2/UAD2

66

UP0_1/UAD1

67

UP0_0/UAD0

68

DGND

69

UXI/O19

70

UA0/O1071UA1/O1172UA2/O1273UA3/O1374UA4/O1475UA5/O1576UA6/O1677UA7/O17

78

RD15/VIO15

79

RD0

80

RD14/VIO14

81

RD1

82

RD13/VIO13

83

RD2

84

RD12/VIO12

85

RD3

86

RD11/VIO11

87

RD4

88

RD10/VIO10

89

RD5

90

RD9/VIO9

91

RD6

92

RD8/VIO8

93

RD7

94

CASL_/CAS_

95

CASH_/RWEH_

96

RWE_/RWEL_

97

RAS_

98

DVDD3

99

RA8

100

RA7

101

RA0

102

RA6

103

RA1

104

DGND

Focusing

Error

Centro_

Servo

Tracking

Error

RF

Data PLL

and

Data Slicer

RFRP

12

• IC501 (MT1199E) : RF+DSP+ATAPI DECODER+µ-COM

Block Diagram

13

• IC501 MT1199E

Pin Description

Pin Numbers Symbol Type Description

RF Interface

208 RGND Ground Ground pin for RF and related analog circuitry.

204 RVDD Analog

Power(3.3V)

Power for RFand related analog circuitry.

1 RFI Analog Input RF signal input.

2 SVDD Analog

Power(3.3V)

Power for servo signal generator and related analog circuitry.

3 FNI Analog Input Main beam I-V amplifier (A+C) input.

4 FPI Analog Input Main beam I-V amplifier (B+D) input.

5 SGND Ground Ground pin for servo signal generator and related analog circuitry.

6 CSNI Analog Input Central Servo input 1

7 CSPI Analog Input Central Servo input 2.

8 TPI Analog Input Sub beam I -V amplifier F input.

9 TNI Analog Input Sub beam I-V amplifier E input.

11 FEN Analog Input Negative input of focusing error amplifier.

12 FEO Analog Output Focusing error output.

13 FEP Analog Input Positive input of focusing error amplifier.

14 TEN Analog Input Negative input of tracking error amplifier.

15 TEO Analog Output Tracking error output.

16 SBAD Analog Output Sub beam adder signal output.

17 CSO Analog Output Central Servo control output.

19 RFON Analog Output Negative RF output.

20 RFOP Analog Output Positive RF output.

206 OSN Analog Output RF offset loop integrating capacitor connecting

205 OSP Analog Output RF offset loop integrating capacitor connecting

APC Interface

10 LDO Analog Output Laser diode control output.

207 MDI Analog Input Voltage for monitoring the laser diode photo power.

21 TMA Analog Input Pin for laser power triming.

23 TMB Analog Input Pin for laser power triming.

18 TAVSS Ground Ground pin .

22 TAVDD Analog

Power(3.3V)

Power for trimming pads and related analog circuitry.

REF Interface

203 V20 Analog output 2.0 V reference voltage output

202 V13 Analog output 1.3 V reference voltage output

201 V26 Analog output 2.6 V reference voltage output

14

Data Slicer & Data PLL Interface

194 PLLVSS Ground Ground pin for data PLL and related analog circuitry.

189 SPDOP Analog Output Vco dac positive output.

190 SPDON Analog Output Vco dac negative output.

191 LPFON Analog Output The negative output of loop filter amplifier.

192 LPFOP Analog Output The positive output of loop filter amplifier.

193 LPFN Analog Input The negative input terminal of loop filter amplifier.

195 IREF Analog Input Current reference input. It generates reference current for data

PLL. Connect an external 15K resistor between this pin and
PLLVSS.

188,196 PLLVDD Analog

Power(3.3V)

Power for data PLL and related analog circuitry.

197 VOSPI Analog Input Positive input for analog slicer

198 VOSNI Analog Input Negative input for analog slicer

199 VOSP Analog Output Positive low pass filter output for analog slicer

200 VOSN Analog Output Negative low pass filter output for analog slicer

Turbo 8032 Interface

27 URD_/IO4 TTL Input

50K pull_up

Read signal input from ICE to MT1199, active low.

Alternate function : Programmable GPIO.

28 UP3_5/UT1 TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : T1. Timer 1 input.

29 UP3_4/UT0 TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : T0. Timer 0 input.

30 DGND Ground Ground pin for internal digital circuitry.

31 UINT1_/IO5 TTL Output Host interrupt output, connected to INT1_ pin of ICE, low active.

Alternate function : Programmable GPIO.

32 UP3_2

/ UINT0_

TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : INT0_. External interrupt 0, low active.

33 UP3_1

/ UTXD

TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : TXD. Serial transmit data.

34 UP3_0

/ URXD

TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : RXD. Serial receive data.

35 DVDD Power(5V) Power pin for internal digital circuitry.

40 ICEMODE TTL Input

50K pull_down

Internal or external P select. “1” indicates disable internal P and

external P is used.

41 UWR_/IO6 TTL I/O, Slew rate

SMT, 50K pull_up

WR_. Data write signal.

Alternate function : Programmable GPIO.

42 UALE

/ O8

TTL I/O

50K pull_up

Address latch enable output, active high.

Alternate function : Programmable output

15

43 UP1_0

/ UA16

TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : A16. Address bit 16 output.

Input 3.3V/5V tolerance, output 3.3V

44,45,46,47,

48,49,51,52

UP2_[7:0]

/ UA[15:8]

TTL I/O, Slew rate

50K pull_up

Programmable bi-directional I/O.

Alternate function : A[15:8]. Upper address bus input/output.

Input 3.3V/5V tolerance, output 3.3V

50 UPSEN_

/ O9

TTL I/O

50K pull_up

Programmable store enable output, active low. PSEN_ enables the

external ROM output port.

Alternate function : Programmable output.

Input 3.3V/5V tolerance, output 3.3V

53 DVDD3 Power(3.3V) 3.3V power pin for digital circuitry.

56 DGND Ground Ground pin for digital circuitry.

57 FWR_ TTL Output output 3.3V, flash write enable.

59 DVDD3 Power(3.3V) 3.3V power pin for digital circuitry.

60,61,62,63,

64,65,66,67

UP0_[7:0]

/ UAD[7:0]

TTL I/O, Slew rate Programmable bi-directional I/O.

Alternate function : AD[7:0]. Lower address/data bus output for

external device.

Input 3.3V/5V tolerance, output 3.3V

68 DGND Ground Ground pin for digital circuitry.

69 UXI/O19 TTL Output

Slew rate

P clock output for external system clock, connected to X1 of ICE.

output 3.3V

70,71,72,73,

74,75,76,77

UA[7:0]

/ O[17 :10]

TTL Oouput,

Slew rate

Lower address bus output for external device.

Alternate function : Programmable output.

output 3.3V

Xtal Interface

54 XTALI Input Xtal input. The working frequency is 33.8688 MHz.

55 XTALO Output Xtal output.

DRAM Interface

78,80,82,84,

86,88,90,92

RD[15:8]

/ VIO[15:8]

TTL I/O, Slew rate

50K pull_up

Buffer RAM Data / Versatile Input/Output. These pins are the bi­directional upper Buffer RAM data bus to the external buffer
memory. When an 8-bit DRAM is used, the RD8–RD15 signals
becomes Versatile I/O pins, VIO8–VIO15.

Input 3.3V/5V tolerance, output 3.3V

79,81,83,85,

87,89,91,93

RD[7:0] TTL I/O, Slew rate

50K pull_up

Bi-directional lower Buffer RAM data bus.

Input 3.3V/5V tolerance, output 3.3V

94 CASL_

/ CAS_

TTL Output

Slew rate

Column Address Strobe Low / Column Address Strobe. When
TWE

63h.RW6

is 0, this pin is the Column Address Strobe Low
signal for accessing the lower bytes of a two-CAS_ 16-bit DRAM.
When TWE

63h.RW6

is 1 or when an 8-bit DRAM is used, this pin

shall be connected to CAS_ of the DRAM.

output 3.3V

16

95 CASH_

/ RWEH_

TTL Output

Slew rate

Column Address Strobe High / RAM Write Enable High. When a
16-bit DRAM is used, this pin functions as Column address Strobe
High for accessing the upper bytes of a two-CAS_ DRAM if
TWE

63h.RW6

is 0, or as Write Enable High for writing the upper

bytes of a two-WE_ DRAM.

output 3.3V

96

RWE_

/ RWEL_

TTL Output RAM Write Enable / RAM Write Enable Low. When TWE

63h.RW6
is 0 or when an 8-bit DRAM is used, this pin is the active-low write
strobe to the external buffer DRAM. When TWE

63h.RW6

is 1, this
pin is the Write Enable Low signal for writing the lower bytes of a
two-WE_ 16-bit DRAM.

output 3.3V

97

RAS_

TTL Output

Slew rate

Row Address Strobe.

This output is the Row Address Strobe signal to the buffer DRAM.

output 3.3V

98 DVDD3 Power(3.3V) 3.3V power pin for digital circuitry.

99~103

105~108

RA[8:0] TTL I/O, Slew rate

50K pull_down

Buffer RAM Address.

These pins are the address bus to the external buffer DRAM.

output 3.3V

104 DGND Ground Ground pin for internal digital circuitry.

Audio Interface

117 ADGO

/ VIO0

TTL I/O, Slew rate

SMT, 50K pull_up

Digital Audio Output / Versatile I/O 0. The signal is either the Digital
Audio Output which supplies the IEC-958 digital audio data when
A0SEL

00h.RW7

=1 and ADOE

2Eh.RW0

=1, or the Versatile I/O 0

pin otherwise.

Internal Audio DAC Interface

109 DACVSS Ground Ground pin for internal DAC circuitry.

110 RO Analog Output Right channel of audio.

111 DACVREF Analog Output Reference voltage for external audio filter circuit.

112 LO Analog Output Left channel of audio.

113 DACVDD Analog

Power(3.3V)

Power pin for internal DAC circuitry.

Varipitch VCO Interface

114 VPVDD Analog

power(3.3V)

Power pin for varipitch VCO circuitry.

115 VCOCIN Analog Input Connect capacitor for compensator loop filter.

116 VPVSS Ground Ground pin for varipitch VCO circuitry.

Host Interface

118 DEVSEL TTL Input

50K pull_up

Device Select. Cleared to zero indicates the MT1199 is master
device. Set to one indicates the MT1199 is slave device.

119 DASP_ TTL I/O

50K pull_up

Device Active / Device 1 Present. This is a time-multiplexed signal
which indicates that a device is active, or that Device 1 is present. A
10K-ohm pull-up resistor shall be connected to this signal
externally.

17

120 CS3FX_ TTL Input, SMT

50K pull_up

Device Chip Select 1. This is the chip select signal from the host to

select the Control Block Registers.

121 CS1FX_ TTL Input, SMT

50K pull_up

Device Chip Select 0. This is the chip select signal from the host to

select the Command Block Registers.

122 DGND Ground Ground pin for internal digital circuitry.

123,127,124 DA[2:0] TTL Input, SMT

50K pull_up

Device Address. This is the 3-bit binary coded address provided by

the host to access an ATA register or data.

125 DVDD3 Power(3.3V) 3.3V power pin for digital circuitry.

126 PDIAG_ TTL Input,

50K pull_up

Passed Diagnostics. This signal is asserted by Device 1 to indicate

to Device 0 that it has completed diagnostics.

128 DVDD Power(5V) Power pin for internal digital circuitry.

129 IOCS16_ TTL Output

Open drain

Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16_
indicates to the host system that the 16-bit data port has been
addressed and that the device is prepared to send or receive a 16­bit data word. The MT1199 will always assert IOCS16_ when the
host reads the ATAPI Data Register.

130 INTRQ TTL I/O

Slew rate

Device Interrupt. This signal is used to interrupt the host system.
INTRQ is driven only when the MT1199 is addressed, i.e.,
DRV1

01h.RW7

=DRV

16h.RW4

. When not driven, INTRQ is in a

high impedance state.

131 DMACK_ TTL Input, SMT

50K pull_up

DMA Acknowledge. This signal shall be used by the host in
response to DMARQ to acknowledge that it is ready for DMA
transfers.

132 IORDY TTL Outout

Slew rate

I/O Channel Ready. This signal is negated (pulled low) during PIO
to extend the host transfer cycle of any host register access (Read
or Write) when the MT1199 is not ready to respond to a data
transfer request. When IORDY is not negated, it is in a high
impedance state. In Ultra DMA transfers, the signal becomes either
DDMARDY_ (Device Ultra DMA Ready) that is asserted by the
MT1199 to indicate to the host that it is ready to receive data, or
DSTROBE (Device Ultra DMA Data Strobe) whose rising edge and
falling edge latch the data from DD0–DD15 into the host.

133 DIOR_ TTL Input, SMT

50K pull_up

Device I/O Read. This is the ATA read strobe signal. In PIO or
multiword-DMA the falling edge of DIOR_ enables data from the
MT1199 onto the host data bus, DD0–DD7 or DD0–DD15. The
rising edge of DIOR_ then latches the data at the host. During Ultra
DMA transfers the signal becomes either HDMARDY_ (Host Ultra
DMA Ready), which is asserted by the host to indicate to the
MT1199 that the host is ready to receive data, or HSTROBE (Host
Ultra DMA Data Strobe), whose rising edge and falling edge latch
the data from DD0–DD15 into the MT1199.

134 DIOW_ TTL Input, SMT

50K pull_up

Device I/O Write. This is the ATA write strobe signal. In PIO or
multiword-DMA the rising edge of DIOW_ latches data from the
host data bus, DD0–DD7 or DD0–DD15, into the ATA registers or
the ATAPI Packet FIFO of the MT1199. In Ultra DMA transfers the
signal becomes STOP (Stop Ultra DMA Data Transfer), which is
negated by the host before data can be transferred by an Ultra
DMA burst, and asserted by the host when it want to terminate an
Ultra DMA burst.

135 DMARQ TTL Output DMA Request. This signal, used for DMA data transfer, is asserted

by the MT1199 when it is ready to transfer data to or from the host.

18

136~137

139~143

145~148

150~152

154~155

DD[15:0]

TTL I/O

pull_up

/ pull_down

Device Data. This is the 8-bit or 16-bit bi-directional data bus to the
host. The lower 8 bits, DD0—DD7, are used for 8-bit data transfers.

Note : All pins except DD7 may be selectively pull up/down with 20k

resistant.

138 DGND Ground Ground pin for digital circuitry.

144 DGND Ground Ground pin for digital circuitry.

149 DVDD Power(5V) Power pin for digital circuitry.

153 DGND Ground Ground pin for digital circuitry.

Reset Interface

158 HRST_ TTL Input, SMT Host reset input. The active low input is used to reset MT1199.

166 RESET/O18 TTL Output Reset signal output(combine HRST_ & POR), active high.

Alternate function : Programmable output.

167 POR TTL Input, SMT Power on reset input, active high.

IPLL VCO Interface

156 IPLLVDD Analog

power(3.3V)

Power pin for IPLL VCO circuitry.

157 IPLLVSS Ground Ground pin for IPLL VCO circuitry.

Extended GPIO Interface

24,25,26 IO[3:1] TTL I/O, Slew rate

50K pull_up

Programmable GPIO.

58 IO7/CS_ TTL I/O

50K pull_up

Programmable GPIO.

Alternate function : Chip select signal for flash ROM selection,
active low.

165 IO0 TTL I/O

50K pull_down

Programmable bi-directional I/O.

Alternate function : Serial bus reserved for MT1136.

Mega Interface

37 LED TTL Output

LED control output. Controlled by P.

38 EJECT_ TTL input Eject/stop key input, active low.

39 PLAY_ TTL input Play/pause key input, active low.

159 TRAYIN_ TTL input Tray_is_in input, A logical low indicates the tray is in. Feedback

flag from tray connector.

160 TRAYOUT_ TTL input Tray_is_out input. A logical low indicates the tray is out. Feedback

flag from tray connector.

161 TROPEN TTL output

Tray open output. Controlled by P.

162 TRCLOSE TTL output

Tray close output. Controlled by P.

163 LIMIT_ TTL input Sledge inner limit input, active low.

164 DVDD3 Power(3.3V) Power pin for internal digital circuitry.

19

Motor and Actuator Driver Interface

168 FG TTL Input, SMT Motor Hall sensor input.

50K pull-up

169 DVDD Power(5V) Power pin for internal digital circuitry.

170 ENDM TTL Output Enable/disable disk motor. A logical high enables disk motor.

171 DGND Ground Ground pin for internal digital circuitry.

172 HRFZC Digital Input High speed mirror signal input

173 FMO2 Analog Output Feed motor control. PWM output.

174 FMO Analog Output Feed motor control. PWM output.

175 DMO Analog Output Disk motor control output. PWM output.

176 DVDD3 Power(3.3V) Power pin for digital circuitry.

177 TEBC Analog Output Tracking error balance control. PWM output.

178 DGND Ground Ground pin for digital circuitry.

179 PDMVSS Ground Ground for PDM circuitry.

180 TRO Analog Output Tracking servo output. PDM output of tracking servo

compensator.

181 FOO Analog Output Focus servo output. PDM output of focus servo compensator.

182 PDMVDD Analog Power for PDM circuitry.

Power(3.3V)

Signal Amplifier Interface

183 TEZILP Analog Input Tracking error zero crossing low pass input.

184 ADCVSS Ground Ground pin for ADC circuitry.

185 RFRPSLV Analog Output RF ripple slice level output.

186 RFRO Analog Output RF ripple detect output

187 ADCVDD Analog Power pin for ADC circuitry.

Power(3.3V)

TEST mode

36 TESTMODE Digital Input Enable test mode high active

A B CD

1

2

3

4

5

+5V

+3.3V3.3V Reg.

M63022FP

MT1199E

FLASH

MEMORY

RF+DSP+Decoder+
System controller

SPINDLE

MOTOR

FOCUS

COIL

SLED

MOTOR

LOADING

MOTOR

33.86MHz

I/F Cable

R-ch

L-ch

Line-out

DRAM

H
O
S
T

TRACKING

COIL

Disc
Motor unit

Optical
Pick-up

MOTOR DRIVE

GND

GND

+12V

+5V

GND

GND

+12V

30

BLOCK DIAGRAM

PBM00 (MAIN C.B.A)

007

002

003

030

020

A02

A01

020

051

032

050

029

434

021

434

434

413

413

413

001

413

430

028

027

026

025

033

435

013

010

009

008

011

012

005

034

014

420

434

031

016

015

004

006

431431

A B C D E F GH

1

2

3

4

5

EXPLODED VIEW

7

8