LG CRD-8402B Service Manual

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Page 1

INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible 486SX or Above (With PIO mode 4 recommended)

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Data Transfer Rate..........................................................................................Sustained Data Transfer Rate

18Times Speed (Inner side) : 2,700 kbytes/sec

40 Times Speed (max., Outer side) : 6,000 kbytes/sec

• Data Buffer Capacity .....................................................................................................................128 kbytes

• Access Time ...................................................................................................Random Access Time : 75 ms

4. POWER REQUIREMENTS

• Voltage.......................................................................................................................................+5V DC +5%

+12V DC +5%

• Ripple...................................................................................................................+5V : Less than 100mVp-p

+12V : Less than 100mVp-p

• Current........................................................................................................................+5V : 0.9A (Maximum)

+12V : 1.5A (Maximum)

5. AUDIO PERFORMANCE

• Frequency Response .....................................................................................................20Hz~20KHz(+3dB)

• S/N Ratio (IHF-A+20 KHz LPF)........................................................................85 dB (Typical at 1 KHz 0dB)

80 dB (Limit at 1 KHz 0dB)

• T.H.D. (IHF-A+20 KHz LPF) ............................................................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)

• Channel Separation (IHF-A+20 KHz LPF)..............................................................................80 dB (Typical)

70 dB (Limit)

• Output Voltage (1kHz 0dB) 47KΩ Load .................................................................................0.7Vrms +10%

• Headphone Level (1kHz 0dB) 33Ω Load ...............................................................................0.7Vrms +20%

• Enhanced IDE interface

• Internal 5.25 inch, halfheight CD-ROM Drive

• Fast 75ms Average Access Time

• Max 6,000KB/sec Sustained Transfer rate

• Photo-CD Multisession Disc Spec compliant

• Multimedia MPC-3 Spec compliant

• Power Tray Loading/Ejection Mechanism

• 3 Way Eject support (Software, O/C Button,

Emergency Eject)

• Closed Enclosure

• Built-in ATAPI Interface Controller

• Software Volume Control

• 8 Times Digital Filter for CD Audio

•

Front panel Volume Control for Headphone Output

• Built-in MODE-1 ECC/EDC

• MTBF 125,000h POH (at 10% Utilization)

• PIO Mode 4 & Multi DMA Mode 2 support

• Horizontal or Vertical Mounting

• Digital audio output connector

• Digital audio through ATAPI Interface

• Subcode (P-W) through ATAPI Interface

• Spin-down Mode for energy saving

• MS-DOS Version 3.1 or Higher

• OS/2 Warp (Ver 3.0)

• Windows '95/'98

• Solaris Ver 2.4 or Higher

• Linux slackware Ver 2.3

• Windows NT 4.0 or later

This service manual provides a variety of service information. It contains the mechanical structure of the CD-ROM Drive together with mechanical adjustments and the electronic circuits in schematic

form. This CD-ROM Drive was manufactured and assembled under our strict quality control standards and meets or exceeds industry specifications and standards.

Page 2

INTRODUCTION

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible 486SX or Above (With PIO mode 4 recommended)

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Data Transfer Rate..........................................................................................Sustained Data Transfer Rate

18Times Speed (Inner side) : 2,700 kbytes/sec

40 Times Speed (max., Outer side) : 6,000 kbytes/sec

• Data Buffer Capacity .....................................................................................................................128 kbytes

• Access Time ...................................................................................................Random Access Time : 75 ms

4. POWER REQUIREMENTS

• Voltage.......................................................................................................................................+5V DC +5%

+12V DC +5%

• Ripple...................................................................................................................+5V : Less than 100mVp-p

+12V : Less than 100mVp-p

• Current........................................................................................................................+5V : 0.9A (Maximum)

+12V : 1.5A (Maximum)

5. AUDIO PERFORMANCE

• Frequency Response .....................................................................................................20Hz~20KHz(+3dB)

• S/N Ratio (IHF-A+20 KHz LPF)........................................................................85 dB (Typical at 1 KHz 0dB)

80 dB (Limit at 1 KHz 0dB)

• T.H.D. (IHF-A+20 KHz LPF) ............................................................................0.05% (Typical at 1 KHz 0dB)

0.15% (Limit at 1 KHz 0dB)

• Channel Separation (IHF-A+20 KHz LPF)..............................................................................80 dB (Typical)

70 dB (Limit)

• Output Voltage (1kHz 0dB) 47KΩ Load .................................................................................0.7Vrms +10%

• Headphone Level (1kHz 0dB) 33Ω Load ...............................................................................0.7Vrms +20%

• Enhanced IDE interface

• Internal 5.25 inch, halfheight CD-ROM Drive

• Fast 75ms Average Access Time

• Max 6,000KB/sec Sustained Transfer rate

• Photo-CD Multisession Disc Spec compliant

• Multimedia MPC-3 Spec compliant

• Power Tray Loading/Ejection Mechanism

• 3 Way Eject support (Software, O/C Button,

Emergency Eject)

• Closed Enclosure

• Built-in ATAPI Interface Controller

• Software Volume Control

• 8 Times Digital Filter for CD Audio

•

Front panel Volume Control for Headphone Output

• Built-in MODE-1 ECC/EDC

• MTBF 125,000h POH (at 10% Utilization)

• PIO Mode 4 & Multi DMA Mode 2 support

• Horizontal or Vertical Mounting

• Digital audio output connector

• Digital audio through ATAPI Interface

• Subcode (P-W) through ATAPI Interface

• Spin-down Mode for energy saving

• MS-DOS Version 3.1 or Higher

• OS/2 Warp (Ver 3.0)

• Windows '95/'98

• Solaris Ver 2.4 or Higher

• Linux slackware Ver 2.3

• Windows NT 4.0 or later

This service manual provides a variety of service information. It contains the mechanical structure of the CD-ROM Drive together with mechanical adjustments and the electronic circuits in schematic

form. This CD-ROM Drive was manufactured and assembled under our strict quality control standards and meets or exceeds industry specifications and standards.

Page 3

LOCATION OF CUSTOMER CONTROLS

(1) Headphone Jack

3.5mm jack for monitoring the audio signal from audio CDs.

(2) Headphone Volume Control

Adjusts the headphone sound level.

(3) Disc Drawer

Accepts a CD-ROM disc on its tray.

(4) Busy Indicator

The Busy Indicator lights during initialization and dataread operations.

(5) Emergency Eject Hole

Insert a paper clip here to eject the drawer manually or when there is no power.

(6) Play/Skip Button

When an Audio CD is in the Disc Drawer, pressing this button will start playing audio CDs from the first track. If an audio CD is playing, pressing this button will skip to the next track.

(7) Open/Close/Stop Button

This button is pressed to open or close the CD tray. If an audio CD is playing, pressing this button will stop it, and pressing it

again will open the tray.

COMPACT

54 6 73

Figure 1. Front View

(1) Digital Audio Output Connector

This is a digital audio output connector or Video CD output connector. You can connect this to the digital audio system or Video CD Board.

(2) Analog Audio Output Connector

The Audio Output Connector connects to a sound card. The supplied audio cable is a SoundBlaster

type cable. If you have a different sound card, you will need to contact the sound card manufacturer to obtain the proper cable for that card.

(3) Master / Slave / CSEL Jumper

These three jumpers are used to set the CD-ROM Drive to either a Master, Slave, or CSEL drive.

(4) Interface Connector

This 40-pin connector is used to transfer and control signals between the CD-ROM Drive and your PC. Connect the 40-pin IDE cable in your PC to this connector.

(5) Power-in Connector

Attach a power cable from the computer to this connector.

Figure 2. Back View

DIGITAL ANALOG

INTERFACE POWER

DR CSM

SLA

GLG39 1

+12

GND

AUDIO AUDIO

FRONT

REAR

Figure 2. Back View

Page 4

2. Trouble List (Circuit)

A. LED doesn’t light. B. Pick-Up doesn’t move to the inner-track. C. The Laser of Pick-Up doesn’t light. D. Pick-Up lens doesn’t move up and down. E. Disc doesn’t rotate. F. TOC isn’t read. (The LED turns on, but doesn’t flicker.) G. During Audio CD Play, LED flickers, but Speaker is silent.

TROUBLESHOOTING GUIDE

1. Initial Lead-in Operation

Reset or Power-On.

LED Flickers.

Pick-Up moves to the inner-Track.

Laser on the Pick-Up lights.

Focus Search (through moving up and down the lens of Pick-Up)

Focus Servo On (FOK Port : H, FEO(TP15) signal generation)

Rotate disc.

Tracking Servo On (TEO(TP14) Signal generation)

Spindle Servo On (MDP(TP25) Signal generation)

Read TOC Area (LED Flickers)

Search the Start of Data Area and then pause.

Page 5

3. Troubleshooting Guide

A. LED doesn’t light.

Check Power Voltage (TP1:3.3V, TP2:12V, TP20:2.7V) Reference Voltage [TP3:DVC(1.4V) and GND.]

Does “H” output in IC401 pin ?

Check and replace R705, R706, Q701 and LED701 (LED703 for DELL).

Is the CLOCK Frequency of IC401 pin 16.93MHz?

Check the power input pattern.

Check IC401.

Check and replace X501; 33.86MHz, X502: 40MHz

Is the CLOCK Frequency of IC501 pin 16.93MHz?

Check and replace R407, C530, R444.

YES

A-1

Page 6

B. Pick-Up doesn’t move to the inner track.

Do the signals appear at IC401 pin , ? (Refer to Fig. B-1.)

Do the signals appear in PN301 pin? (Refer to Fig. B-2.)

Does “H” output at IC201 pin ?

Is the 1.4V at IC201 pin

Check the pattern from IC401 pin to IC201 pin

Check IC401.

Check the R290, R291 and C290 and then replace IC103.

Check the PN301, and then replace the Sled Motor.

YES

Replace IC201.

CH1 PIN94 DA0

CH2 PIN95 DA1

CH1 TP4

CH2 TP5

CH3 TP6

CH4 TP7

Fig. B-1. DA0 and DA1 Signals

Fig. B-2. TP4, TP5, TP6 and TP7 Signals

Page 7

Check the pattern from IC501 pin to R225 and then replace IC501.

Does “Low” or “High” output at IC102 pin ?

Is the voltage of IC102 pin (LD) 2V?

Check Pick-Up FFC, PN101.

Check Q101, C101, C102 and then replace IC102.

Check R118 and replace

IC401.

YES

Does the focus search signal appear at FAO (TP9)? (Refer to Fig. D-1.)

Is the 1.4V at IC201 pin ?

Check the R290, R291 and R290 and then replace IC103.

YES

Replace IC201.

Does the focus search signal appear between F+ (TP10) and F- (TP11)? (Refer to Fig. D-2.)

C. The Laser of Pick-Up doesn’t light.

D. The Pick-UP lens doesn’t move up and down.

D-1

Page 8

Check the pattern from pin , of IC201 to pin , of PN101.

Check the PN101, Pick-Up FFC.

Replace the Pick-Up.

Replace PN101 or Pick-Up FFC.

CH1 TP9 (FAO)

CH1 TP10(F+) TP11(F-)

Fig. D-1. FAO Signal

Fig. D-2. Focus Search Signal

D-1

Page 9

Does the signal appear at the MDP (TP25)? (Refer to Fig. E-4.)

Do the signals appear at IC201 pin (W), (V), and (U)?

Replace IC501.

Replace IC201.

YES

Check the pattern from IC201 pin , , to PN201 , , .

YES

Check Spindle Motor FFC

and then replace the

Spindle Motor.

Does the signal appear at FEO (TP15) when the R505 opened? (Refer to Fig. E-2.)

YES

Replace IC501.

Replace Pick-Up.

Do the signal appear at TP15 (FEO) and TP19 (SENS)? (Refer to Fig. E-3.)

Does the signal appear at FOK (TP18) during focus search? (Refer to Fig. E-1.)

E. Disc doesn’t rotate.

Page 10

Fig. E-3. FEO, SENS Signal

CH1 TP15: FEO

CH2 TP19: SENS

Fig. E-4. MDP Signal

CH1 TP25: MDP

Fig. E-1. FOK, F+ Signal

CH1 TP10: F+

CH2 TP18: FOK

Fig. E-2. S-Curve (R505:Open)

CH1 TP15: S-Curve

Page 11

Is the Focus Servo ON? (Does FEO (TP15) signal appear?)

Does A, B, C, D signal appear at IC102 pin ,

, , ?

YES

7 8 9

Is the Tracking Servo ON? (Does TEO (TP14) signal appear?)

Does E, F signal appear at IC102 pin , ?

YES

Is TOC area on the disc read? (Does LED flicker?)

Does the other disc operate normally?

Normal Disc is defective.

YES YES

Does RFAC signal (TP16) and RFDC signal (TP17) appear?

Is Spindle Servo ON? (Does MDP signal (TP25) appear?)

YES YES

Does A, B, C, D signal appear at IC102 pin ,

, , ?

7 8 9

Replace IC102.

Replace IC501.

Replace Main Circuit Board or MD Ass’y.

Refer to C. (The Laser of Pick-Up doesn’t light.)

F. TOC isn’t read.

Page 12

Does PWM signal appear at IC501 pin , , , ? (Refer to Fig. G-1.)

YES

134 135

142

143

Replace IC501.

Replace IC601.

Does Audio signal appear at IC601 pin , ? (Refer to Fig. G-2.)

YES

Is the voltage of IC601 pin and 2.5V?

Check the R601, R602 and C602.

Does “H” signal appear at IC401 pin ?

YES

Check the IC401 pin and then replace IC401.

Check C702.

YES

Are L-ch, R-ch signals appear at JK701 and Audio Line out connector each?

Check JK701 and L701,L703.

Does Audio signal appear at IC701 pin , ?

1 7

Is the voltage of IC701 pin 2.5V?

Replace IC701.

G. During Audio CD play, LED flickers, but Speaker is silent.

G-1

Page 13

Is the connection between JK801 (or Audio Line out connector) and Line (or Jack) normal?

Check the JK801 and Audio line pattern.

YES

Check your sound card, Audio Cable, Speaker, Volume and Headphone Jack.

Fig. G-1. PWM Signal

CH1 PIN6 of IC601

CH2 PIN10 of IC601

Fig. G-2. Audio Signal

CH2 PIN3 of IC601

CH2 PIN12 of IC601

G-1

Page 14

1. CABINET and CIRCUIT BOARD DISASSEMBLY

1-1. Bottom Chassis

A. Release 4 screws (A) and remove the Bottom

Chassis in the direction of arrow (1). (See Fig. 1-1)

1-2. Front Bezel Assy

A. Insert and Press a rod in the Emergency Eject

Hole and then the CD Tray will open in the direction of arrow (2).

B. Remove the Tray Door in the direction of arrow (3)

by pushing it outward.

C. Release 3 stoppers and remove the Front Bezel

Assy.

1-3. Cabinet and Main Circuit Board

A. Remove the Cabinet in the direction of arrow (4).

(See Fig. 1-3) B. Release 2 hooks (a) and remove the CD Tray. C. Remove the Soldering of the LD- and LD+ (B) for

the Loading Motor, and then remove the Main

Circuit Board. D. At this time, be careful not to damage the 3

connectors of the Main Circuit Board.

2. MECHANISM ASSY

A. Separate the Pick-Up Unit from the Mechanism

Assy. B. Release 1 screws (C) and then remove the Pick-

Up ( ).

DISASSEMBLY

(A)

(1)

Bottom Chassis

Fig. 1-1

Fig. 1-2

Fig. 1-3

Fig. 1-4

Cabinet

(4)

Hooks (a)

(B)

Main

Circuit Board

Tray Door

(3)

Stoppers

Emergency Eject Hole

(2)

Front Bezel Assy

CD Tray

Pick-up Unit

(C)

Mechanism Assy

Page 15

PHOTO DIODE STRUCTURE OF THE PICK-UP

(1) Focus Error Signal –> (A+C)-(B+D)

(Control the Pick-up’s up and down to focus on the Disc)

(2) Tracking Error Signal –> (E-F)

(Control the Pick-up’s left and right shift to find the track on the Disc)

(3) RF Signal –> (A+B+C+D)

(

RF Signal is converted to Data Signal in One Chip IC (IC501))

Three signals (Focus Error Signal, Tracking Error Signal and RF Signal) above are I-V converted and amplified at the IC102, and then are transmitted to One Chip IC (IC501) to generate the Servo Control Signal and Data Signal.

Red laser

Pick-Up module

Tracking

Focusing

Page 16

SUM

VCA

EQ_ON/OFF

RW/ROM

DVC

DVcc

VOFST

AABBCCD

4 3 23 24 26

22 5

VOFST

DVC

AVC

Vcc

APC-OFF (Hi-Z)

(H/L)

APC

Vcc

GND

AVC

DVC

CE20CEI

TE_BAL19FE16FEI

RFDCO

RFDCI

DC_OFST

RFAC

AC_SUM

EQ_IN

RFG

BST

RFC

VFC

Pin No.

Symbol I/O Description

Pin No.

Symbol I/O Description

1 LD O APC Amp Output 16 FE O Focus Error Amp Non-inverted Output

2 PD I APC Amp Input 17 FEI – Focus Error Amp Inverted

3EQ–IN I

RFAC VCA Block, EQ Block Input

18 TE O Tracking Error Signal Output

4AC–SUM O

RFAC RF SUM Output

19 TE_BAL I TE Control

5 GND I GND 20 CE O Center Error Signal Output

6 A I RF Input (A Signal) 21 CEI – CE Amp Inverted

7 B I RF Input (B Signal) 22 Vcc I Vcc

8 C I RF Input (C Signal) 23 RFG I RFAC Low Frequency Gain Control

9 D I RF Input (D Signal) 24 BST I EQ Boost Volume Control

10 E I RF Input (E Signal) 25 VFC I EQ Cut OFF Frequency Control

11 F I RF Input (F Signal) 26 RFC I EQ Cut OFF Frequency Control

12 SW I

Mode Switching Signal Input

27 VC O VC Output

13 DVcc I DVcc 28 RFDCO O RFDC Output

14 DVC O DVC Output 29 RFDCI – RFDC Amp Inverted

15 RFAC O RFAC Summing Equalized Output 30

DC_OFST

– RFDC Signal Output Control

Pin Description

IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

• IC102 (CXA2581N) : RF Amplifier IC

I-V converts and amplifies the signal received from the pick-up and then applies to DSP part of onechip IC (IC501).

Block Diagram

Page 17

• IC201 (M63020FP) : Drive IC (Spindle/Servo Actuator)

Rotates the Spindle Motor by receiving MDP signal from IC501. Generates the signal to drive Focus Actuator Coil, Tracking Actuator Coil, Sled Motor, and Stepping Motor by Control Signal input from DSP and u-COM.

Block Diagram

X12

X5X8

HU+ HUHV+ HV-

HW+ HWHB

SPIN

REF

SL1IN

SL2IN

FOIN

TOIN

TO+

TO-

FO+

FO-

GND

LO+

LO-

5VCC

LOIN+

LOIN-

BRS

OSC

MU1

VM1

RSPUV

RSL1

RSL2

SL1+

SL1-

SL2+

SL2-

VM2

Reverse Detect

120˚

MATRIX

Hall Bias

CTL amp

Direction

comp

Direction

comp

Direction

comp

Current

comp

Current

comp

Current

comp

CTL amp

Logic

TSD

BIAS

Frequency

generator

VM1

Regulator

Reg

5V power supply

Pin Description

Pin No.

Symbol Description

Pin No.

Symbol Description

1 SL1IN Slide control voltage input 1 2 SL2IN Slide control voltage input 2 3 VM2 Motor Power Supply 3 (for Slide) 4 RSL2 Slide current sense 2 5 SL2+ Slide non-inverted output 2 6 SL2- Slide inverted output 2 7 GND GND 8 RSL1 Slide current sense 1

9 SL1+ Slide non-inverted output 1 10 SL1- Slide inverted output 1 11 GND GND 12 W Motor drive output W 13 V Motor drive output V 14 U Motor drive output U 15 RSP Spindle current sensie 16 HW- HW- sensor amp. input 17 HW+ HW+ sensor amp. input 18 HV- HV- sensor amp. input 19 HV+ HV+ sensor amp. input 20 HU- HU- sensor amp. input 21 HU+ HU+ sensor amp. input

22 VM1 Motor Power Supply 1 (for Spindle) 23 HB Bias for Hall Sensor 24 FG Frequency generator output 25 REF Refernce voltage input 26 SPIN Spindle control voltage input 27 FOIN Focus control voltage input 28 TOIN Tracking control voltage input 29 GND GND 30 5VCC 5V Power Supply (for FS, TS, LO) 31 TO- Tracking inverted output 32 TO+ Tracking non-inverted output 33 GND GND 34 FO+ Focus non-inverted output 35 FO- Focus inverted output 36 LO+ Loading non-inverted output 37 LO- Loading inverted output 38 BRS Brake select control terminal 39 LOIN+ Loading control input(+) 40 LOIN- Loading control input( - ) 41 MU1 Mute 1 42 OSC PWM carrier oscilation set

Page 18

1Mbits DRAM

CLOCK

GEN

DATA

processor

DMA SEQUENCER

ADDRESS GEN

(Serial I/F)

CLOCK

GEN

PRIORITY RESOLVER

Subcode

Deinterleave & ECC

MAIN DATA

ERROR CORRECTION

ATAPI REGISTERS

12byte PACKET FIFO

HOST

I/F

DESCRAMBLER

SYNC CONTROL

Sub CPU I/F

DRVSS

DRVDD

HDB0~F

110~113

115~118

120~123

125~128

HCS0,1

97~99

95,96

HA0~2

XHRD

XHWR

XHAC

HDRQ

HINT

XS16

REDY

0~7D

0~6A

DASP

XPDI

XHRS

107

103

100

101

106

102

105

104

DMA FIFO

Digital OUT

8fs

1bit DAC

Error

Correction

block

Subcode P~W

Processor

32K RAM

EFM

Timing Generator

Subcode Q

Processor

84~91

XRD

77~83

XWR

XCS

XTL1

XINT

XWAT

XTL2

PWM2N

PWM2P

SENS

FOK

PWM1N

143 135 134 130 131

PWM1P

MIRR

DFCT

COUT

142

OP Amp

DACSERVO DSP

Auto Sequencer

8 bit

A/D

OP Amp

Analog SW

SAO

TAO

FAO

BSSD

DOUT

DAC

I/F

CD-DSP

I/F

CPU Interface

FOK

MIRR

DFCT

XTLO XTLI

138 130

Digital PLL

ASY

Sync protector

PCO

VDD

Vss

FILI

FILO

CLTV

ASYI

ASYO

WFCK

SCOR

RFDC

TESEFE

SQCK

SQSO

MDP

PWMI

ADIO

RFAC

CLV/CAV

Processor

SERVO BLOCK

DAC BLOCK

DATA BLOCK

33343536373839

5 4 3 2 58 14 57 56 63 10

• IC401 (M37903F8CHP) : Shrink µ-com [MODEL : CRD-8402B(s)]

Controls all Drive systems by input and output the Data from the peripheral IC.

• IC501 (CXD3030R) : DSP+ATAPI DECODER+DRAM

Block Diagram

Page 19

• IC501 CXD3030R

Pin Description

Pin No. Symbol I/O Description

1 AVS6 Analog GND

2 SAO O Analog DAC Analog Output of Slide Filter

3 TAO O Analog DAC Analog Output of Tracking Filter

4 FAO O Analog DAC Analog Output of Focus Filter

5 BSSD I Constant Current Input for DAC Analog of Servo Filter

6 AVD6 Analog Power Supply (2.5V)

7 VSIO0 Digital GND

8 RMUT O 1,0 Audio DAC, Rch Zero Detection Play

9 LMUT O 1,0 Audio DAC, Lch Zero Detection Play

10 DOUT O 1,0 Digital-Out Output

11 SSTP I Disc Inner Track Detection Signal Input

12 MDP O 1,Z,0 Control Output of Spindle Motor

13 PWMI I External Terminal Input of Spindle Motor

14 DFCT I/O 1,0 Defect Signal In/Output

15 ATSK I Pin for Anti-Shock. It set to “L” When is not used.

16 MNT0/XRAOF O 1,0 MNT0/XRAOF* Signal Output

17 MNT1/C2PO O 1,0 MNT1/C2PO* Signal Output

18 MNT2/XUGF O 1,0 MNT2/XUGF* Signal Output

19 MNT3/GTOP O 1,0 MNT3/GTOP* Signal Output

20 VDCO Digital Power Supply (2.5V)

21 XRST I System Reset “L” is reset

22 VSCO Digital GND

23 MTST1 I Test Pin Normally “L”

24 MTST0 I Test Pin Normally “L”

25 XPLCK/WDCK O 1,0 XPLCK/WDCK*/C2PO*/PWM4* Signal Output

26 VDIO0 Digital Power Supply (3.3V)

27 WFCK/LRCK O 1,0 WFCK/LRCK*/PWM2* Signal Output

28 RFCK/PCMD O 1,0 RFCK/PCMD*/PWM3* Signal Output

29 LOCK/BCK O 1,0 LOCK/BCK* Signal Output

30 AVD2 Analog Power Supply (2.5V)

31 IGEN I Resistor Connection Pin of Current Source Reference for OP Amp

32 AVS2 Analog GND

33 ADIO O Analog OP Amp Output

34 RFDC I RF Signal Input

35 CE I Center Servo Analog Input

36 TE I Tracking Error Signal Input

37 SE I Slide Error Input

Page 20

Pin No. Symbol I/O Description

38 FE I Focus Error Input

39 VC I Center voltage Input

40 VPCO1 O 1,Z,0 Output of VCO2 for wide-Band EFM PLL

41 VCTL I Input of VCO2 Control voltage for Wide-Band EFM PLL

42 FILO O Analog Filter Output for Master PLL (Slave = Digital PLL)

43 FILI I Filter Input for Master PLL

44 PCO O 1,Z,0 Change Pump Output for Master PLL

45 CLTV I Multiplier VCO Control Voltage Input

46 AVS1 Analog GND

47 RFAC I EFM Signal Input

48 BIAS I Asymmetry Circuit Constant Current Input

49 ASYI I Asymmetry Comparator Voltage Input

50 ASYO O 1,0 EFM Full-Swing Output (L=V

SS, H=VDD)

51 AVD1 Analog Power Supply (2.5V)

52 ADC1 Digital Power Supply (2.5V)

53 ADC2 Digital Power Supply (2.5V)

54 VSC1 Digital GND

55 VSC2 Digital GND

56 FOK I/O 1,0 Focus OK Signal IN/OUT

57 MIRR I/O 1,0 Mirror Signal IN/OUT

58 COUT I/O 1,0 Track Number Count Signal IN/OUT

59 GFS O 1,0 GFS Output

60 SCOR O 1,0 Outputs a high signal when either subcode S0 or S1 is detected

61 SQSO O 1,0 SubQ 80bit PCM Peck and Level Data 16bit Output

62 SQCK I SQSO Readout clock Input

63 SENS O 1,Z,0 SENS Output to Sub CPU

64 SCLK I Sens Serial Data Readout Clock Input

Set to high when not used.

65 MUTE I DSP Mute (High:ON, Low:OFF)

66 DRV

DD Internal DRAM Exclusive Power Supply

67 DRV

SS Internal DRAM Exclusive GND

68 F16M O 1,0 1/2 Division of XTLI

Not changes with variable pitch.

69 XWAT O 1,0 Wait Signal for Sub CPU Buffer Memory Access, Negative Logic

70 XINT O 1,Z,0 Interrupt Signal to Sub CPU, Negative Logic

71 VDIO1 Digital Power Supply (3.3V)

72 VSIO1 Digital Power Supply GND

73 VSIO2 Digital Power Supply GND

74 XCS I Chip Select Signal from Sub CPU, Negative Logic

Page 21

Pin No. Symbol I/O Description

75 XWR I Data Write Strobe Signal from Sub CPU, Negative Logic

76 XRD I Data Read Strobe Signal from Sub CPU, Negative Logic

77 A6 I Sub CPU Address (MSB)

78 A5 I Sub CPU Address

79 A4 I Sub CPU Address

80 A3 I Sub CPU Address

81 A2 I Sub CPU Address

82 A1 I Sub CPU Address

83 A0 I Sub CPU Address (LSB)

84 D7 I/O 1,Z,0 Sub CPU Data Bus

85 D6 I/O 1,Z,0 Sub CPU Data Bus

86 D5 I/O 1,Z,0 Sub CPU Data Bus

87 D4 I/O 1,Z,0 Sub CPU Data Bus

88 D3 I/O 1,Z,0 Sub CPU Data Bus

89 D2 I/O 1,Z,0 Sub CPU Data Bus

90 D1 I/O 1,Z,0 Sub CPU Data Bus

91 D0 I/O 1,Z,0 Sub CPU Data Bus (LSB)

92 VDIO2 Digital Power Supply (3.3V)

93 XPDI I/O Z,0 Passed Diagnostics Signal, Open Drain Output, Negative Logic

94 DASP I/O Z,0 Drive Active/Slave Present Signal, Open Drain Output, Negative Logic

95 HCS1 I Chip Select Negative Signal from Host

96 HCS0 I Chip Select Negative Signal from Host

97 HA2 I Host Address (MSB)

98 HA0 I Host Address (LSB)

99 HA1 I Host Addresas

100 XS16 O Z,0 Host 16-bit I/O Port Select Signal, Open Drain Output, Negative Logic

101 HINT I/O 1,Z,0 Host Interrupt Demand Signal, Positive Logic

102 XHAC I DMA Acknowledge Signal from Host, Negative Logic

103 REDY O Z, 0 Host I/O Channel Ready Signal, Open Drain Output, Negative Logic

104 XHRD I Data Read Strobe Signal from Host

105 XHWR I Data Write Strobe Signal from Host

106 HDRQ O 1, Z, 0 DMA Request Signal to Host, Positive Logic

107 XHRS I Chip Reset Signal from Host, Negative Logic

108 VSIO3 Digital Power Supply GND

109 VDIO4 Digital Power Supply (3.3V)

110 HDBF I/O 1,Z,0 Host Data Bus (MSB)

111 HDB0 I/O 1,Z,0 Host Data Bus (LSB)

112 HDBE I/O 1,Z,0 Host Data Bus

113 HDB1 I/O 1,Z,0 Host Data Bus

Page 22

Notes :

• LRCK, BCK and PCMD are changed to 32-bit slot and 48-bit slot by command. 32-bit slot is output in 2's complements on an LSB-first basis and 48-bit slot is output in 2's complements on an MSB-first basis.

• *'s signal is able to convert to output by a command. (Refer to sub CPU Register 08h (W) of decoder part)

• The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.

• XRAOF is a signal issued when a jitter margin of +28F is exceeded by the 32K RAM.

• C2PO is a signal to indicate data error.

• XUGF is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is

effected.

Pin No. Symbol I/O Description

114 VSIO5 Digital Power Supply GND

115 HDBD I/O 1,Z,0 Host Data Bus

116 HDB2 I/O 1,Z,0 Host Data Bus

117 HDBC I/O 1,Z,0 Host Data Bus

118 HDB3 I/O 1,Z,0 Host Data Bus

119 VDIO3 Digital Power Supply (3.3V)

120 HDBB I/O 1,Z,0 Host Data Bus

121 HDB4 I/O 1,Z,0 Host Data Bus

122 HDBA I/O 1,Z,0 Host Data Bus

123 HDB5 I/O 1,Z,0 Host Data Bus

124 VSIO4 Digital Power Supply GND

125 HDB9 I/O 1,Z,0 Host Data Bus

126 HDB6 I/O 1,Z,0 Host Data Bus

127 HDB8 I/O 1,Z,0 Host Data Bus

128 HDB7 I/O 1,Z,0 Host Data Bus

129 VDC3 Digital Power Supply (2.5V)

130 XTL2 O 1, 0 Crystal Oscillating Circuit Output of the Clock for Decoder

131 XTL1 I Crystal Oscillating Circuit Input of the Clock for Decoder

132 VSC3 Digital GND

133 AVS3 Analog GND

134 PWM2N O 1, 0 PWM Output of Audio DAC. Default R Ch, Reverse Phase

135 PWM2P O 1, 0 PWM Output of Audio DAC. Default R Ch, Forward Phase

136 AVD3 Analog Power Supply (2.5V)

137 AVD4 Power Supply for Master Clock (2.5V)

138 XTLO O 1,0 Crystal Oscillating Circuit Output for the Master Clock

139 XTLI I Crystal Oscillating Circuit Input for the Master Clock

140 AVS4 GND for the Master Clock

141 AVS5 Analog GND

142 PWM1P O 1, 0 PWM Output of Audio DAC. L Ch, Forward Phase

143 PWM1N O 1, 0 PWM Output of Audio DAC. L Ch, Reverse Phase

144 AVD5 Analog Power Supply (2.5V)

Page 23

• GTOP monitors the state of Frame Sync protection. ("H" : Sync protection window released)

• XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK

coincides with a change point of the EFM signal.

• RFCK is a signal generated at 136-µs periods using a crystal oscillator.

• LOCK is sampling the GFS at 460Hz and outputs "H" when GFS is "H".

("L" outputs when "L" is output eight times in succession or inputs when LKIN is "H".)

Page 24

3.3V Reg

2.7V Reg

+3.3V

+5V

+12V

+2.7V

GND

+5V

+12V

GND

SPINDLE

MOTOR

SLED

MOTOR

FOCUS

COIL

TRACKING

COIL

M63020FP

MOTOR DRIVE

Disc Motor unit

Optical Pick-up

CXA2581N RF Amp.

CXD3030R

DSP + DRAM + I/F

CLOCK 33.86MHz

16.93MHz

I/F Cable

H O S T

M37903F8CHP

System

Controller

AUDIO

Circuitry

R-ch

L-ch

Line-out

Headphone Jack

A B CD

BLOCK DIAGRAM

Page 25

PBM00 (MAIN C.B.A)

007

002

003

030

020

A02

A01

020

051

032

050

029

434

021

434

413

001

413

430

028

027

026

025

033

435

013

010

009

008

011

012

005

034

014

420

434

031

016

015

004

006

431431

A B C D E F GH

EXPLODED VIEW

LG CRD-8402B Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual