LG CRD-8245B Service Manual

GENERAL FEATURE

• Enhanced IDE interface	•	Closed enclosure
• Ultra Slim type CD-ROM drive	•	Software Volume Control
(Height: 12.7mm)	• 8 Times Digital Filter for CD Audio
• Fast 110ms Average Access Time	•	Built-in MODE-1 ECC/EDC
• MAX 3,600KB/sec (24X) Sustained Transfer	• MTBF 60,000h POH (at 10% Utilization)
rate	• PIO Mode 4 & Multi-word DMA Mode 2
• Photo-CD Multisession Disc Spec compliant		support & Ultra DMA Mode2 support
• MPC level 3 Spec compliant	• Digital audio through ATAPI Interface
• Drawer Type Manual load/Electrical Release	• Spin-down Mode for energy saving
• 3-Way eject support (Software, Open button,	• Support Standby & Sleep mode
Emergency eject)
• Built-in ATAPI Interface Controller

SPECIFICATIONS

1.SUPPORTED SYSTEM

•IBM Compatible 486SX or Above

2.SUPPORTED OS

•	MS-DOS Version 3.1 or Windows 3.1	•	Windows 2000
•	OS/2 Warp (Ver 3.0 & 4.0) or higher	•	Windows NT (Version 3.51 or 4.0) or higher

•Windows '95 or ‘98 higher

3.GENERAL PERFORMANCE

•	Data Transfer Rate ..........................................................................................	Sustained Data Transfer Rate
	.............................................................................................	10 Times Speed (Inner side) : 1,500 kbytes/sec
	.............................................................................................	24 Times Speed (Outer side): 3,600 kbytes/sec
•	Data Buffer Capacity..........................................................................................	1 Mbit DRAM (Internal DSP)
•	Access Time ............................................................................................	Random Access : Average 110 ms

4. POWER REQUIREMENTS

•	Voltage	........................................................................................................................................+5V DC+5%
•	Ripple....................................................................................................................................	+5V : 100mVp-p
•	Current .........................................................................................	Peak in executing access : 1,000mA MAX
	................................................................................................................................	Random access : 800mA
	..............................................................................................................................	Normal operation : 700mA
	..............................................................................................................................................	Standby : 30mA
	..................................................................................................................................................	Sleep : 30mA

5. AUDIO PERFORMANCE

•	Frequency Response......................................................................................................	20Hz~20KHz( +1-3 dB)
•	S/N Ratio (IHF-A)..................................................................................................	70 dB (Typical, 1KHz 0dB)
•	Distortion (20K-LPF) ............................................................................................	0.05% (Typical, 1KHz 0dB)
•	Channel Separation ................................................................................................................	65 dB (Typical)
•	Dynamic Range (IHF-A)..........................................................................................................	70 dB (Typical)
• Output Level (47kΩ Load).................................................................................................		0.75Vrms (Typical)

3

DISASSEMBLY

1. CABINET

A.Release 3 screws (A).

B.Lift up the Cabinet in the direction of arrow (1). (See Fig. 1)

	(A)
CABINET
(A)	(A)
(1)
	HOOKS
	Fig. 1

2. MAIN CIRCUIT BOARD

A.Insert and press a rod in the Emergency Eject Hole and then the CD Tray will open in the direction of arrow (2).

B.Release 2 screws (B).

C.Remove the Main Circuit Board.

(B)

(B)

MAIN CIRCUIT BOARD

EMERGENCY

EJECT HOLE

Fig. 2

4

3. FRONT PANEL

A.Release 5 screws (C) and remove the Cover Bottom.

B.Remove the Front Panel.

C.At this time, be careful not to damage the 5 hooks

(a) of the it.

	FRONT PANEL
	ASSY
	HOOK (a)
		(C)
	(C)	COVER
		BOTTOM
	Fig. 3

4. BASE PICK-UP

A. Remove the Base Pick-Up.

BASE PICK-UP

Fig. 4

IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

IC101 (LA9239) : RF Amplifier IC

I-V converts and amplifies the signal received from the pick-up and then applies to DSP part of onechip IC (IC501).

Block Diagram
							PH
	BHC						BH		PH
REF		1		BH				36
	PHC	2						35	BH
REF							PH-CONTROL
					PH	EQ-CONTROL		7_MODE
									VCC1
	RFAO
		3						34
								VCC
	GND1								RFSM
		4		REF		REF	REF	33
	RFA-								RHLD
						7_MODE		32
		5
	RFIN	6						31	GND2
100K	FIN1	7	REF					30	REFL
			REF
100K	FIN2	8					REF	29	FE-
	E	9						28	FE
56K
	F	10					REF	27	TE-
56K			REF			REF
VCC	REFI	11						26	TE
									TSS
	VREF	12					REF	25
	LDD	13						24	TS
	LDS	14	APC	VCC		REF	REF	23	VCC2	+
	LDON	15						22	TSH
								VCC
	GHS	16		REF				21	FBAL
	BHH	17						20	TBAL
	EQS	18						19	SGC
10

5V

52 33K 39K

5V

Pin Description

Pin No.	Pin Name	Descriptions
1	BHC	Bottom hold external condensor pin for checking RFAGC.
2	PHC	Peak hold external condensor pin for checking RFAGC.
3	RFAO	RF Pre AMP output
4	GND	RF GND
5	RFA-	RF Pre AMP (-) input
6	RFIN	RF Sum input
7	FIN1	Pickup output (B+D),
8	Fin2	Pickup output (A+C),
9	E	Pickup output (E)
10	F	Pickup output (F)
11	REFI	Eeternal Condensor Pin of Reference Voltage.
12	VREF	Reference output
13	LDD	APC circuit output
14	LDS	APC circuit input
15	LDON	Laser on/off.
16	GHS	RF signal gain control.
17	BHH	BH response control.
18	EQS	RF equalizer. PH detection control
19	SGC	Servo gain control
20	TBAL	TE balance adjust
21	FBAL	FE balance adjust
22	TSH	TS wide band control
23	VCC2	Servo VCC
24	TS	TS output
25	TSS	TS wide band control
26	TE	TE signal output (To DSP)
27	TE-	TE gain control
28	FE	FE signal output (To DSP)
29	FE-	FE gain control
30	REFL	Reflection output (To DSP)
31	GND2	Servo GND
32	RHLD	RF hold control
33	RFSM	EFM signal output (To DSP)
34	VCC1	RF VCC
35	BH	RF bottom hold output (To DSP)
36	PH	RF peak hold output (To DSP)

11

IC201 (AN8498SH) : Servo Actuator Drive IC

Generates the signal to drive Focus Actuator Coil, Tracking Actuator Coil, Sled Motor, and Stepping Motor by Control Signal input from DSP and u-COM.

Block Diagram

15kΩ

0.012µF

15kΩ

0.012µF

15kΩ

0.012µF

100pF

1.65V

22µF

H:active

L:standby

100Ω

5V

47µF

FG Signal Output

H:3FG

L:1FG

H:S-BRK

L:R-BRK

Spindle Speed

Control Input

					VMAC
					36
IN1	20kΩ	A				35	FO1
	41
		B	Logic		DMOS
Ω		S		Drive
1k					H/B	32	RO1
FB1 43
			FB
IN2	20kΩ	A				30	FO2
	47				DMOS
Ω		B	Logic	Drive
		S			H/B
1k						29	RO2
FB2 46
			FB			31	PGAC
						22	VMSL
IN3	20kΩ	A				28	FO3	M
	23	B	Logic		DMOS
		S		Drive
	Ω				H/B
							RO3
FB3	1.1k					26
	24		FB				PGSL
						27
CT							VPUMP
	34	Delta wave				39
VREF 45		Oscillator					BC1	0.1µF
						38
					Charge
								0.1µF
							BC2
	VREF Reset				Pump	37
STBY	25	Stand-by
			Heat		OSC
							VMSP1
			Protection
VDD 44		VDD Reset				49
H1H 16						8	VMSP2
							A1
H1L 14						52
				Upper
H2H 13		Hall		Drive	DMOS	56	A21
					3-Phase
H2L 12		Comp	Divide				A22
		Matrix	Circuit		Bridge	1

H3H 11				Low		A3
				Drive	5
H3L 10
					55	RCS1
VH					54	RCS2
	9	Hall				RCS3
					53
100Ω		Bias
				FF		RCS4
					4
						RCS5
FG	7		SRESET	SSET	3
						RCS6
		FG
SFG					2
	6	Generator				CS
				X5	51
SBR		S-BRK
	50						Rcs=
		Conversion		VCL		GND	0.33Ω
EC					40
	18	Absolute	VT
					+
ECR	17	value

19	20	21
VP	VN	VO

5V

47µF

5V

100µF

12

Pin Description

Pin No	Symbol	Description
1	A22	SP Drive Output 2
2	RCS6	SP Power Source 6
3	RCS5	SP Power Source 5
4	RCS4	SP Power Source 4
5	A3	SP Drive output 3
6	SFG	SP FG mode conversion
7	FG	SP FG signal output
8	VMSP2	SP Motor power supply 2
9	VH	SP Hall Bias
10	H3L	SP Hall (-) input 3
11	H3H	SP Hall (+) input 3
12	H2L	SP Hall (-) input 2
13	H2H	SP Hall (+) input 2
14	H1L	SP Hall (-) input 1
15	N.C.	N.C.
16	H1H	SP Hall + input 1
17	ECR	SP Torque Reference input
18	EC	SP Torque input
19	VP	Op amp Non-inverted input
20	VN	Op amp inverted input
21	VO	Op amp output
22	VMSL	Ch3 power supply
23	IN3	Ch3 input
24	FB3	Ch3 feedback output
25	STBY	Stand-by
26	RO3	Ch3 inverted output
27	PGSL	Ch3 Power GND
28	FO3	Ch3 Non-inverted output

Pin No	Symbol	Description
29	RO2	CH2 inverted Output
30	FO2	CH2 Non-inverted Output
31	PGAC	CH1, 2 Power GND
32	RO1	CH1 Inverted Output
33	N.C.	N.C.
34	CT	3 Delta-wave Output
35	FO1	Ch1 Non-inverted Output
36	VMAC	Ch1, 2 Power Supply
37	BC2	Charge Pump Volume Connector2
38	BC1	Charge Pump Volume Connector1
39	VPUMP	Charge Pump Boost the Voltage of Output
40	GND	GND
41	IN1	CH1 Input
42	N.C.	N.C.
43	FBI	CH1 Feedback Output
44	VDD	Control Circuit Power Supply
45	VREF	Reference Voltage Input
46	FB2	CH2 Feedback Output
47	IN2	CH2 Input
48	N.C.	N.C.
49	VMSP1	SP Motor Power Supply
50	SBR	SP Break mode conversion
51	CS	SP Voltage Defected Output
52	A1	SP Drive Output1
53	RCS3	SP Power Source 3
54	RCS2	SP Power Source 2
55	RCS1	SP Power Source 1
56	A21	SP Drive Output 2

13

IC501 (HMS985300) : DSP+ATAPI DECODER+ASP+System Controller

Block Diagram

		Driver
	TDO, FDO					LC895300
	SLDO, SPDO		FG
						LC895299
	*11	VCEC		Data bus[0.7]	DRAM
					Data bus[0.15]	Adress bus[0.18]
		PLL
LA9238	*1				Sub-code I/F
					de-interleve
	*12	CD-DSP			Adress generator	Each Block
	*2
						Bus control
	*14
						siganl
Audio		SRAM			Sub-code ECC
	*3
Circuit
						Bus
					Address generator
						Arbiter
		FGCNT				&
					De-scramble &	DRAM
		CD-DSP I/F				controller
					Buffering
		& SYNC
					Address generator
		Detector
ZRESET
					ECC & EDC	Buffer
		Merge			Address generator	DRAM
		EXT10		CMDI
HOST							*13
	*4
	*5				ATAPI I/F	Clock	XTALCK
	*6					generator
				Each Block		Each Block	XTAL
				Register
				decoder	Data output input I/F
					Address generator		*9
							*10
					Microcontroller
					RAM access
				*7	Address generator
FGCNT CMDI
SW1		EXTII		*8
SW2	Interrupt		Micro			ZOE, ZWE, ZCE
							128K
SW3	Controller		controller			D0~D7
							EEPROM
						A0~A16
	Timer					1.5K
IOPORT						RAM
0~14

Gray Block si characteristic of LG895300.

*1	EFMIN,EFMIN2,PH,BH,FE,TE,TES,RREC
*2	RHLD,TSH,EQS,GHS,LDON,FBAL,TBAL,TOFST,SGC
*3	LOUT,ROUT,DOUT
*4	DD~DD15,ZDASP,ZPDIAG
*5	ZCSIFX,ZCS3FX,DA0~2,ZDIOR,ZDIOW,ZDMACK,ZHRST,CSEL
*6	DMARQ,HINTRQ,ZIOCS16,IORDY
*7	ZRD,ZWR,ZCS,MCK,SUA0~7
*8	D0~7
*9	CRCERR/FLOCK,HFLO/WRQ/DIR/TLOCK,FSEQ,FSX/LRCK/FV,EFLG/ CK2/PRF,C2F/PCK,EFMOUT
*10	TEST0~2
*11	PCKISTF,PCKIFTP,PDO,POS1~3,RF
*12	SLCO0~3,JITC,DSLB,PHC,BHC
*13	PLL1
*14	SLCIT1~2,AD1,VREF,CSS

14