LG CRD-8245B Service Manual

3

GENERAL FEATURE

SPECIFICATIONS

1. SUPPORTED SYSTEM

• IBM Compatible 486SX or Above

2. SUPPORTED OS

3. GENERAL PERFORMANCE

• Data Transfer Rate..........................................................................................Sustained Data Transfer Rate

.............................................................................................10 Times Speed (Inner side) : 1,500 kbytes/sec

.............................................................................................24 Times Speed (Outer side): 3,600 kbytes/sec

• Data Buffer Capacity..........................................................................................1 Mbit DRAM (Internal DSP)

• Access Time ............................................................................................Random Access : Average 110 ms

4. POWER REQUIREMENTS

• Voltage........................................................................................................................................+5V DC+5%

• Ripple....................................................................................................................................+5V : 100mVp-p

• Current .........................................................................................Peak in executing access : 1,000mA MAX

................................................................................................................................Random access : 800mA

..............................................................................................................................Normal operation : 700mA

..............................................................................................................................................Standby : 30mA

..................................................................................................................................................Sleep : 30mA

5. AUDIO PERFORMANCE

• Frequency Response......................................................................................................20Hz~20KHz( dB)

• S/N Ratio (IHF-A)..................................................................................................70 dB (Typical, 1KHz 0dB)

• Distortion (20K-LPF) ............................................................................................0.05% (Typical, 1KHz 0dB)

• Channel Separation ................................................................................................................65 dB (Typical)

• Dynamic Range (IHF-A)..........................................................................................................70 dB (Typical)

• Output Level (47kΩ Load).................................................................................................0.75Vrms (Typical)

• Enhanced IDE interface

• Ultra Slim type CD-ROM drive

(Height: 12.7mm)

• Fast 110ms Average Access Time

• MAX 3,600KB/sec (24X) Sustained Transfer

rate

• Photo-CD Multisession Disc Spec compliant

• MPC level 3 Spec compliant

• Drawer Type Manual load/Electrical Release

• 3-Way eject support (Software, Open button,

Emergency eject)

• Built-in ATAPI Interface Controller

• Closed enclosure

• Software Volume Control

• 8 Times Digital Filter for CD Audio

• Built-in MODE-1 ECC/EDC

• MTBF 60,000h POH (at 10% Utilization)

• PIO Mode 4 & Multi-word DMA Mode 2

support & Ultra DMA Mode2 support

• Digital audio through ATAPI Interface

• Spin-down Mode for energy saving

• Support Standby & Sleep mode

• MS-DOS Version 3.1 or Windows 3.1

• OS/2 Warp (Ver 3.0 & 4.0) or higher

• Windows '95 or ‘98 higher

• Windows 2000

• Windows NT (Version 3.51 or 4.0) or higher

+1

-3

4

1. CABINET

A. Release 3 screws (A). B. Lift up the Cabinet in the direction of arrow (1).

(See Fig. 1)

2. MAIN CIRCUIT BOARD

A. Insert and press a rod in the Emergency Eject

Hole and then the CD Tray will open in the

direction of arrow (2). B. Release 2 screws (B). C. Remove the Main Circuit Board.

3. FRONT PANEL

A. Release 5 screws (C) and remove the Cover

Bottom. B. Remove the Front Panel. C. At this time, be careful not to damage the 5 hooks

(a) of the it.

4. BASE PICK-UP

A. Remove the Base Pick-Up.

(1)

(A)

Fig. 3

Fig. 1

Fig. 4

(B)

(2)

Fig. 2

DISASSEMBLY

CABINET

HOOKS

MAIN CIRCUIT BOARD

FRONT PANEL ASSY

HOOK (a)

COVER

BOTTOM

BASE PICK-UP

EMERGENCY EJECT HOLE

(C)

10

REF

REFREF

REF

VCC

APC

PH

EQ-CONTROL

BH

PH-CONTROL

7_MODE

5V

39K

33K

52

5V

+

7_MODE

36

PH

100K

1

2

3

4

5

6

7

BHC

PHC

RFAO

GND1

RFA-

RFIN

FIN1

35

BH

34

VCC1

33

RFSM

32

RHLD

31

GND2

30

REFL

29

FE-

28

FE

27

TE-

26

TE

25

TSS

24

TS

23

VCC2

22

TSH

21

FBAL

20

TBAL

19

SGC

100K

8

FIN2

56K

9

E

F

VCC

56K

10

11

12

REFI

VREF

13

LDD

14

LDS

15

LDON

16

GHS

17

BHH

18

EQS

IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

IC101 (LA9239) : RF Amplifier IC

I-V converts and amplifies the signal received from the pick-up and then applies to DSP part of onechip IC (IC501).

Block Diagram

Pin No. Pin Name Descriptions

1 BHC Bottom hold external condensor pin for checking RFAGC. 2 PHC Peak hold external condensor pin for checking RFAGC. 3 RFAO RF Pre AMP output 4 GND RF GND 5 RFA- RF Pre AMP (-) input 6 RFIN RF Sum input 7 FIN1 Pickup output (B+D), 8 Fin2 Pickup output (A+C),

9 E Pickup output (E) 10 F Pickup output (F) 11 REFI Eeternal Condensor Pin of Reference Voltage. 12 VREF Reference output 13 LDD APC circuit output 14 LDS APC circuit input 15 LDON Laser on/off. 16 GHS RF signal gain control. 17 BHH BH response control. 18 EQS RF equalizer. PH detection control 19 SGC Servo gain control 20 TBAL TE balance adjust 21 FBAL FE balance adjust 22 TSH TS wide band control 23 VCC2 Servo VCC 24 TS TS output 25 TSS TS wide band control 26 TE TE signal output (To DSP) 27 TE- TE gain control 28 FE FE signal output (To DSP) 29 FE- FE gain control 30 REFL Reflection output (To DSP) 31 GND2 Servo GND 32 RHLD RF hold control 33 RFSM EFM signal output (To DSP) 34 VCC1 RF VCC 35 BH RF bottom hold output (To DSP) 36 PH RF peak hold output (To DSP)

Pin Description

11

12

H1H

VDD

15kΩ

IN1

FB1

IN2

FB2

IN3

FB3

CT

VREF

STBY

0.012µF

1kΩ

1.1kΩ

H1L

16

44

25

14

H2H

H2L

13

12

H3H

H3L

VH

FG

FG Signal Output

Spindle Speed

Control Input

SFG

SBR

EC

ECR

VP

V

CL

SRESET

SSET

V

T

VN VO

GND

CS

RCS6

RCS5

RCS4

RCS3

RCS2

RCS1

A3

A22

A21

A1

VMSP2

VMSP1

BC2

BC1

11

10

9

7

6

50

18

17

19 20 21

40

51

3

4

53

54

55

1

52

8

49

37

38

VPUMP

39

PGSL

27

RO3

26

FO3

28

VMSL

22

PGAC

31

RO2

29

FO2

30

RO1

FO1

VMAC

32

35

36

15kΩ

20kΩ

0.012µF

100pF

1.65V 22µF

5V

47µF

100Ω

Rcs=

0.33Ω

5V

100µF

5V 47µF

0.1µF

100Ω

1kΩ

15kΩ

FF

Divide

Circuit

Hall Comp Matrix

5

56

2

H:active L:standby

H:3FG L:1FG

H:S-BRK L:R-BRK

45

34

24

41

43

47

46

23

Absolute

value

S-BRK

Conversion

FG

Generator

Hall

Bias

+

X5

Upper

Drive

Low

Drive

DMOS

3-Phase

Bridge

OSC

Charge

Pump

DMOS

H/B

DMOS

H/B

DMOS

H/B

Drive

Logic

A B S

FB

Logic

Delta wave

Oscillator

VREF Reset

Stand-by

VDD Reset

Heat

Protection

Drive

M

IC201 (AN8498SH) : Servo Actuator Drive IC

Generates the signal to drive Focus Actuator Coil, Tracking Actuator Coil, Sled Motor, and Stepping Motor by Control Signal input from DSP and u-COM.

Block Diagram

13

Pin No

Symbol Description

1 A22 SP Drive Output 2 2 RCS6 SP Power Source 6 3 RCS5 SP Power Source 5 4 RCS4 SP Power Source 4 5 A3 SP Drive output 3 6 SFG SP FG mode conversion 7 FG SP FG signal output 8 VMSP2 SP Motor power supply 2

9 VH SP Hall Bias 10 H3L SP Hall (-) input 3 11 H3H SP Hall (+) input 3 12 H2L SP Hall (-) input 2 13 H2H SP Hall (+) input 2 14 H1L SP Hall (-) input 1 15 N.C. N.C. 16 H1H SP Hall + input 1 17 ECR SP Torque Reference input 18 EC SP Torque input 19 VP Op amp Non-inverted input 20 VN Op amp inverted input 21 VO Op amp output 22 VMSL Ch3 power supply 23 IN3 Ch3 input 24 FB3 Ch3 feedback output 25 STBY Stand-by 26 RO3 Ch3 inverted output 27 PGSL Ch3 Power GND 28 FO3 Ch3 Non-inverted output

Pin Description

Pin No

Symbol Description

29 RO2 CH2 inverted Output 30 FO2 CH2 Non-inverted Output 31 PGAC CH1, 2 Power GND 32 RO1 CH1 Inverted Output 33 N.C. N.C. 34 CT 3 Delta-wave Output 35 FO1 Ch1 Non-inverted Output 36 VMAC Ch1, 2 Power Supply 37 BC2 Charge Pump Volume Connector2 38 BC1 Charge Pump Volume Connector1 39 VPUMP

Charge Pump Boost the Voltage of Output 40 GND GND 41 IN1 CH1 Input 42 N.C. N.C. 43 FBI CH1 Feedback Output 44 VDD Control Circuit Power Supply 45 VREF Reference Voltage Input 46 FB2 CH2 Feedback Output 47 IN2 CH2 Input 48 N.C. N.C. 49 VMSP1 SP Motor Power Supply 50 SBR SP Break mode conversion 51 CS SP Voltage Defected Output 52 A1 SP Drive Output1 53 RCS3 SP Power Source 3 54 RCS2 SP Power Source 2 55 RCS1 SP Power Source 1 56 A21 SP Drive Output 2

14

IC501 (HMS985300) : DSP+ATAPI DECODER+ASP+System Controller

Driver

VCEC PLL

TDO, FDO SLDO, SPDO

*11

*1

*12

*2

*14

*3

*4 *5 *6

LA9238

CD-DSP

Data bus[0.7]

DRAM Data bus[0.15]

LC895300

LC895299

Adress bus[0.18] Sub-code I/F de-interleve

Adress generator

Sub-code ECC

Address generator

ATAPI I/F

Data output input I/F

Microcontroller RAM access

De-scramble & Buffering

ECC & EDC

SRAM

CD-DSP I/F & SYNC Detector

Merge

EXT10

CMDI

Each Block Register

FGCNT

Audio Circuit

ZRESET

HOST

decoder

*7

*8

*10

*9

*13

XTALCK

Each Block

XTAL

Micro controller

1.5K RAM

Clock generator

Buffer DRAM

Bus Arbiter & DRAM controller

Each Block Bus control siganl

128K EEPROM

A0~A16

D0~D7

ZOE, ZWE, ZCE

Gray Block si characteristic of LG895300.

Interrupt Controller

Timer

FGCNT CMDI

EXTII

SW1 SW2 SW3

IOPORT 0~14

FG

Block Diagram

*1 EFMIN,EFMIN2,PH,BH,FE,TE,TES,RREC *2 RHLD,TSH,EQS,GHS,LDON,FBAL,TBAL,TOFST,SGC *3 LOUT,ROUT,DOUT *4 DD~DD15,ZDASP,ZPDIAG *5 ZCSIFX,ZCS3FX,DA0~2,ZDIOR,ZDIOW,ZDMACK,ZHRST,CSEL *6 DMARQ,HINTRQ,ZIOCS16,IORDY *7 ZRD,ZWR,ZCS,MCK,SUA0~7 *8 D0~7 *9 CRCERR/FLOCK,HFLO/WRQ/DIR/TLOCK,FSEQ,FSX/LRCK/FV,EFLG/ CK2/PRF,C2F/PCK,EFMOUT *10 TEST0~2 *11 PCKISTF,PCKIFTP,PDO,POS1~3,RF *12 SLCO0~3,JITC,DSLB,PHC,BHC *13 PLL1 *14 SLCIT1~2,AD1,VREF,CSS