LG C1100 Service Manual
Service Manual
Model : C1100
Service Manual
C1100
P/N : MMBD0034301 Date : June, 2004 / Issue 1.0
- 1 -
1. INTRODUCTION
................................
2
1.1 Purpose
...............................................
2
1.2 Regulatory Information
........................
2
1.3 Abbreviations
.......................................
4
2. PERFORMANCE
.................................
6
2.1 H/W Features
......................................
6
2.2 Technical Specification
........................
7
3. TECHNICAL BRIEF
.........................
11
3.1 Transceiver
.......................................
11
3.2 Power Amplifier Module
....................
16
3.3 13MHz Clock
.....................................
17
3.4 Power Supplies for RF Circuits
.........
17
3.5 Digital Main Processor
......................
18
3.6 Analog Main & Power Management
Processor
...........................................
23
3.7 Memory
.............................................
33
3.8 Display and Interface
.........................
34
3.9 Keypad Switches and Scanning
.........
35
3.10 Microphone
........................................
36
3.11 Main Receiver
..................................
37
3.12 Headset Jack Interface
.....................
38
3.13 Speaker & MIDI IC
...........................
39
3.14 Key Back-light Illumination
...............
40
3.15 LCD Back-light Illumination
..............
41
3.16 MOTOR
............................................
42
4. TROUBLE SHOOTING
...................
43
4.1 RX Trouble
........................................
43
4.2 TX Trouble
.........................................
51
4.3 Power On Trouble
.............................
59
4.4 Charging Trouble
...............................
61
4.5 LCD Trouble.
.....................................
63
4.6 Receiver Trouble
...............................
65
4.7 Speaker Trouble
................................
67
4.8 Mic Trouble
........................................
69
4.9 Vibrator Trouble
.................................
71
4.10 Key Backlight LED Trouble
..............
73
4.11 Folder on/off Trouble
........................
74
4.12 SIM Detect Trouble
..........................
76
4.13 Earphone Trouble
.............................
77
4.14 Indicator LED Trouble
......................
80
4.15 RTC Trouble
.....................................
81
5. DISASSEMBLY INSTRUCTION
...
82
5.1 Disassembly
......................................
82
6. DOWNLOAD AND
CALIBRATION ............................. 90
6.1 Download
..........................................
90
6.2 Calibration
.........................................
97
7. BLOCK DIAGRAM
.........................
100
8. CIRCUIT DIAGRAM
.......................
101
9. PCB LAYOUT
.....................................
95
11.1 TOP
.................................................
95
11.2 BOTTOM
.........................................
96
10. ENGINEERING MODE
................
107
10.1 BB Test
..........................................
107
10.2 RF Test
..........................................
108
10.3 MF Mode
.......................................
108
10.4 Trace optiont
.................................
110
10.5 Call timer
.......................................
110
10.6 Fact. Reset
....................................
110
10.7 S/W version
...................................
110
11. STAND ALONE TEST
..................
111
11.1 Introduction
....................................
111
11.2 Setting Method
..............................
111
11.3 HW Test : Software for Standalone
Test Setup
.....................................
112
12. AUTO CALIBRATION
..................
114
12.1 Overview
.......................................
114
12.2 Requirements
................................
114
12.3 Equipment Setup
............................
114
12.4 AGC
...............................................
116
12.5 APC
...............................................
116
12.6 ADC
...............................................
116
12.7 Setting
...........................................
116
12.8 How to do calibration
.....................
116
13. EXPLODED VIEW &
REPLACEMENT PART LIST
.............................................................
117
13.1 Exploded View
...............................
117
13.2 Replacement Parts
........................
119
13.3 Accessory
......................................
126
Table Of Contents
- 2 -
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download
the features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for
example, persons other than your company’s employees, agents, subcontractors, or person
working on your company’s behalf) can result in substantial additional charges for your
telecommunications services. System users are responsible for the security of own system.
There are may be risks of toll fraud associated with your telecommunications system. System
users are responsible for programming and configuring the equipment to prevent unauthorized
use. The manufacturer does not warrant that this product is immune from the above case but will
prevent unauthorized use of common-carrier telecommunication service of facilities accessed
through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and
possibly causing harm or interruption in service to the telephone network, it should disconnect
telephone service until repair can be done. A telephone company may temporarily disconnect
service as long as repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If
these changes could reasonably be expected to affect the use of the this phone or compatibility
with the network, the telephone company is required to give advanced written notice to the user,
allowing the user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its
authorized agent. The user may not make any changes and/or repairs expect as specifically
noted in this manual. Therefore, note that unauthorized alternations or repair may affect the
regulatory status of the system and may void any remaining warranty.
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by
local regulatory agencies. In accordance with these agencies, you may be required to provide
information such as the following to the end user.
1. INTRODUCTION
- 3 -
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look
slightly different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference
from unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the
sign. Following information is ESD handling:
Service personnel should ground themselves by using a wrist strap when exchange system
boards.
When repairs are made to a system board, they should spread the floor with anti-static mat
which is also grounded.
Use a suitable, grounded soldering iron.
Keep sensitive parts in these protective packages until these are used.
When returning system boards or parts like EEPROM to the factory, use the protective
package as described.
1. INTRODUCTION
1. INTRODUCTION
- 4 -
1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Rate
CC-CV Constant Current – Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
1. INTRODUCTION
- 5 -
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
- 6 -
2. PERFORMANCE
2.1 H/W Features
Item Feature Comment
Li-ion, 760 mAh
Standard Battery Cell Size: 33.8(W) x 49.7(H) x 4.6(T) [mm]
Weight: 30.00g
Under the minimum current consumption environment
Stand by Current (such as paging period 9), the level of standby current
is below 4mA.
Talk time Up to 3 hours (GSM TX Level 7)
Stand by time Up to 200 hours (Paging Period: 9, RSSI: -85 dBm)
Charging time Approx. Under 3 hours
RX Sensitivity GSM, EGSM: –105dBm, DCS: –105dBm
TX output power
GSM, EGSM: 33dBm (Level 5),
DCS: 30dBm (Level 0)
GPRS compatibility Class 10
SIM card type 3V only
Display Main LCD: 128 x 128 pixel 65K Color STN
Hard icons. Key Pad;
Status Indicator
0 ~ 9, #, *, Up/Down/Left/Right Navigation Key,
Menu Key, Clear Key, Send Key, END/PWR Key
Soft Key (Left/Right)
ANT External
EAR Phone Jack Yes
PC Synchronization Yes
Speech coding EFR/FR/HR
Data and Fax Yes
Vibrator Yes
Loud Speaker Yes
Voice Recording No
C-Mike Yes
Receiver Yes
Travel Adapter Yes
MIDI 16 Poly
Options Hands-free kit, CLA, Data Kit
2. PERFORMANCE
- 7 -
2. PERFORMANCE
2.2 Technical Specification
Item Description Specification
GSM
TX: 890 + n x 0.2 MHz
RX: 935 + n x 0.2 MHz (n=1~124)
EGSM
1 Frequency Band TX: 890 + (n-1024) x 0.2 MHz
RX: 935 + (n-1024) x 0.2 MHz (n=975~1024)
DCS
TX: 1710 + (n-512) x 0.2 MHz
RX: 1805 + (n-512) x 0.2 MHz (n=512~885)
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM, EGSM
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
12 19 dBm 3dB
4 Power Level DCS
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
- 8 -
Item Description Specification
GSM, EGSM
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 –30
250 –33
400 –60
600~ <1,200 –60
1,200~ <1,800 –60
1,800~ <3,000 –63
3,000~ <6,000 –65
5 Output RF Spectrum 6,000 –71
(due to modulation)
DCS
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 –30
250 –33
400 –60
600~ <1,200 –60
1,200~ <1,800 –60
1,800~ <3,000 –65
3,000~ <6,000 –65
6,000 –73
GSM, EGSM
Offset from Carrier (kHz). Max. dBm
400 –19
600 –21
1,200 –21
6 Output RF Spectrum 1,800 –24
(due to switching
DCS
transient)
Offset from Carrier (kHz). Max. dBm
400 –22
600 –24
1,200 –24
1,800 –27
7 Spurious Emissions Conduction,Emission Status
2. PERFORMANCE
- 9 -
2. PERFORMANCE
Item Description Specification
GSM, EGSM
8 Bit Error Rate
BER (Class II) < 2.439% @–102 dBm
DCS
BER (Class II) < 2.439% @–100 dBm
9
RX Level Report Accuracy
3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 –12 –
200 0 –
300 0 –12
11 Sending Response 1,000 0 –6
2,000 4 –6
3,000 4 –6
3,400 4 –9
4,000 0 –
12 RLR 2 3 dB
Frequency (Hz) Max. (dB) Min. (dB)
100 –12 –
200 0 –
300 2 –7
500
❈
–5
13 Receiving Response 1,000 0 –5
3,000 2 –5
3,400 2 –10
4,000 2
* Mean that Adopt a straight line in between 300 Hz
and 1,000 Hz to be Max. level in the range.
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
–35 17.5
–30 22.5
16 Distortion
–20 30.7
–10 33.3
0 33.7
7 31.7
10 25.5
17 Side tone Distortion Three stage distortion < 10%
18
System frequency
≤ 2.5 ppm
(13 MHz) tolerance
19 32.768KHz tolerance ≤ 30 ppm
- 10 -
Item Description Specification
At least 80 dB under below conditions:
20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm.
21 Charge Current
CC Charge : < 500 mA
Trickle Charge : < 60 mA
Antenna Bar Number Power
5 –85 dBm ~
4 –90 dBm ~ –86 dBm
22 Antenna Display 3 –95 dBm ~ –91 dBm
2 –100 dBm ~ –96 dBm
1 –105 dBm ~ –101 dBm
0 ~ –105 dBm
Battery Bar Number Voltage
0 ~ 3.62V
23 Battery Indicator
1 3.62 ~ 3.73V
2 3.73 ~ 3.82V
3 3.82V ~
24 Low Voltage Warning
3.5 0.03V (Standby)
3.62 0.03V (Call)
25 Forced shut down
3.35 0.03V
Voltage
1 Li-ion Battery
26 Battery Type
Standard Voltage = 3.7V
Battery full charge voltage = 4.2V
Capacity : 950mAh
Switching-mode charger
27 Travel Charger Input : 100 ~ 240V, 50/60 Hz
Output : 5.2V, 600 mA
2. PERFORMANCE
- 11 -
3. TECHNICAL BRIEF
3.1 Transceiver (SI4205-BM, U301)
The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part,
a voltage supply part, and a VCTCXO part.
The Aero I transceiver is the integrated RF front end for multi-band GSM/GPRS digital cellular
handsets and wireless data modems. The integrated solution eliminates the IF SAW filter,
external low noise amplifier (LNAs) for three bands, transmit and RF voltage controlled oscillator
(VCO modules, and other discrete components found in conventional designs.
Figure 3-1. RECEIVER FUNCTIONAL BLOCK DIAGRAM
ANTENNA SWITSH
TCXO
3. TECHNICAL BRIEF
(1) Receiver Part
The Aero I transceiver uses a low-IF receiver architecture which allows for the on chip
integration of the channel selection filters, eliminating the external RF image reject filters and the
IF SAW filter required in conventional superheterodyne architectures.
A. RF front end
RF front end consists of Antenna Switch(FL400), two SAW Filters(FL401, FL402) and dual
band LNAs integrated in transceiver (U401).
The Received RF signals(GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz) are fed into
the antenna or Mobile switch.
The Antenna Switch(FL400) is used to control the Rx and Tx paths. And, the input signals
VC1 and VC2 of a FL400 are directly connected to baseband controller to switch either Tx or
Rx path on.
The logic and current is given below Table 3-1.
Table 3-1. The Logic and current
Three differential-input LNAs are integrated in SI4205. The GSM input supports the GSM 850
(869-849 MHz) or E-GSM 900 (925-960MHz) bands. The DCS input supports the DCS 1800
(1805-1880 MHz) band. The PCS input supports the PCS 1900 (1930-1990 MHz) band.
The LNA inputs are matched to the 150Ω balanced output SAW filters through external LC
matching networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in
register 05h (Figure 3-2).
VC1 VC2 Current
DCS TX 0V 2.5 ~ 3.0V 10.0 mA max
GSM TX 2.5 ~ 3.0V 0V 10.0 mA max
GSM/DCS RX 0V 0V < 0.1 mA
- 12 -
3. TECHNICAL BRIEF
- 13 -
3. TECHNICAL BRIEF
Figure 3-2. SI4205 RECEIVER PART
B. Intermediate frequency (IF) and Demodulation
A quadrature image-reject mixer downconverts the RF signal to a 100KHz intermediate
frequency (IF) with the RFLO from the frequency synthesizer. The RFLO frequency is
between 1737.8 to 1989.9 MHz, and is internally divided by 2 for GSM 850 and E-GSM 900
modes. The mixer output is amplified with an analog programmable gain amplifier (PGA),
which is controlled with the AGAIN[2:0] bits in register 05h (Figure3-2). The quadrature IF
signal is digitized with high resolution A/D converters (ADCs).
The ADC output is downconverted to baseband with a digital 100KHz quadrature LO signal.
Digital decimation and IIR filters perform channel selection to remove blocking and reference
interference signals. The selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1).
The low selectivity filter has a flatter group channelization filter is in the baseband chip. After
channel selection, the digital output is scaled with a digital PGA, which is controlled with the
DGAIN [5:0] bits in register 05h.
The amplified digital output signal go through with DACs that drive a differential analog signal
onto the RXIP,RXIN,RXQP and RXQN pins to interface to standard analog ADC input
baseband ICs. No special processing is required in the baseband for offset compensation or
extended dynamic range.
Compared to a direct-conversion architecture, the low-IF architecture has a much greater
degree of immunity to dc offsets that can arise from RF local oscillator(RFLO) self-mixing,
2nd order distortion of blockers, and device 1/f noise.
- 14 -
(2) Transmitter Part
The transmit (Tx) section consists of an I/Q baseband upconverter, and offset phase-locked
loop (OPLL) and two output buffers that can drive external power amplifiers (PA), one for the
GSM 850 (824-849 MHz) and E-GSM 900 (880-915 MHz) bands and one for the DCS 1800
(1710-1785 MHz) and PCS 1900 (1850-1910MHz) bands.
Figure 3-3. SI4205 TRANSMITTER PART
A. IF Modulator
The baseband converter(BBC) within the GSM chipset generates I and Q baseband signals
for the Transmit vector modulator. The modulator provides more than 40dBc of carrier and
unwanted sideband rejection and produces a GMSK modulated signal. The baseband
software is able to cancel out differential DC offsets in the I/Q baseband signals caused by
imperfections in the D/A converters.
The Tx-Modulator implements a quadrature modulator. A quadrature mixer upconverts the
differential in-phase (TXIP, TXIN) and quadrature (TXQP, TXQN) signals with the IFLO to
generate a SSB IF signal that is filtered and used as the reference input to the OPLL.
The IFLO frequency is generated between 766 and 896 MHz and internally divided by 2 to
generate the quadrature LO signals for the quadrature modulator, resulting in an IF between
383 and 448 MHz. For the E-GSM 900 band, two different IFLO frequencies are required for
spur management. Therefore, the IF PLL must be programmed per channel in the E-GSM
900 band.
B. OPLL
The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated
TXVCO. The TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its
output is divided by 2 for the GSM 850 and E-GSM 900 bands. The RFLO frequency is
generated between 1272 and 1483 MHz. To allow a single VCO to be used for the RFLO,
high-side injection is used for the GSM 850 and E-GSM 900 bands, and low-side injection is
used for the DCS 1800 and PCS 1900 bands. The I and Q signals are automatically swapped
when switching bands. Additionally, the SWAP bit in register 03h can be used to manually
exchange the I and Q signals. Low-pass filters before the OPLL phase detector reduce the
harmonic content of the quadrature modulator and feedback mixer outputs. The cutoff
frequency of the filters is programmable with the FIF[3:0] bits in register 04h (Figure 3-3), and
should be set to the recommended settings detailed in the register description.
3. TECHNICAL BRIEF
÷ 2
BBG[1:0]
FIF[3:0]
TXBAND[1:0]
PDIB
PDRB
SWAP
TXIP
TXIN
I
Q
TXQP
TXQN
÷ 1,2
REG
RFOG
RFOD
REG
- 15 -
3. TECHNICAL BRIEF
(3) Frequency Synthesizer
Figure 3-4. SI4205 FREQUENCY SYNTHESIZER PART
The Aero I transceiver integrates two complete PLLs including VCOs, varactors, resonators,
loop filters, reference and VCO dividers, and phase detectors. The RF PLL uses two
multiplexed VCOs. The RF1 VCO is used for receive mode, and the RF2 VCO is used for
transmit mode. The IF PLL is used only during transmit mode. All VCO tuning inductors are
also integrated. The IF and RF output frequencies are set by programming the N-Divider
registers, N RF1, N RF2 and NIF. Programming the N-Divider register for either RF1 or RF2
automatically selects the proper VCO. The output frequency of each PLL is as follows:
The DIV2 bit in register 31h controls a programmable divider at the XIN pin to allow either a
13 or 26 MHz reference frequency. For receive mode, the RF1 PLL phase detector update
rate ( ) should be programmed = 100 kHz for DCS 1800 or PCS 1900 bands, and = 200
kHz for GSM 850 and E-GSM 900 bands. For transmit mode, the RF2 and IF PLL phase
detector update rates are always =200 kHz.
3.2 Power Amplifier Module (RF3133, U302)
The RF3133 is a high-power, high-efficiency power amplifier module with integrated power
control. The device is self-contained with 50Ω input and output terminals. The power control
function is also incorporated, eliminating the need for directional couplers, detector diodes,
power control ASICs and other power control circuitry; this allows the module to be driven
directly from the DAC output.
The device is designed for use as the final RF amplifier in GSM 850, E-GSM 900, DCS and PCS
handheld digital cellular equipment and other applications in the 824-849 MHz, 880-915 MHz,
1710-1785 MHz, and 1850-1910 MHz bands.
On-board power control provides over 37 dB of control range with an analog voltage input
(TX_RAMP); and, power down with a logic “low” for standby operation (TX_ENABLE).
External control (BAND_SELECT) is used to select the GSM or DCS band with a logic high or
low. A logic low enables the GSM band whereas a logic high enables the DCS band.
Figure 3-5. FUNCTIONAL BLOCK DIAGRAM OF RF3133
- 16 -
1DSC/PCS IN
2
3
4
5
6
7
BAND SELECT
TX ENABLE
VBATT
VREG
VRAMP
GSM IN
DSC/PCS OUT
VCC2VCC2
VCC OUT
GSM OUT
11
8
12
10
9
3. TECHNICAL BRIEF
- 17 -
3. TECHNICAL BRIEF
3.3 13MHz Clock (VCTCXO, X301)
The 13 MHz clock(X301) consists of a TCXO(Temperature Compensated Crystal Oscillator)
which oscillates at a frequency of 13 MHz. It is used within the Si4205, analog base band
chipset (U102, AD6537B), digital base band chipset (U101, AD6525), and MIDI (U401) chipset.
Figure 3-6. VCTCXO CIRCUIT DIAGRAM
3.4 Power Supplies for RF Circuits (RF LDO, U303)
Two regulators are used for RF circuits. One is MIC5255 (U303), and the other is one port of
AD6537B (U102).
MIC5255 (U303) supplies power to transceiver (SI4205, U301).
One port of AD6537B supplies power to VCTCXO (X301).
Main power (VBAT) from battery is used for PAM (RF3133, U302) because PAM requires high
power.
Table 3-2. RF POWER SUPPLIERS
Figure 3-7. RF LDO CIRCUIT DIAGRAM
AD6535_AFCDAC
1608
VVCXO
2.2u
C371
4
VCC
15K
R317
X301
13MHz
GND
2
OUT
3
C372
1000p
AFC
Supplier Voltage Powers Enabled signal
U303 (VRF) 2.85V U301, U302 CLKON
U102 (VVCX0) 2.75V X301
Battery (VBAT) 3.4~4.2V U302,U303
VBAT
1
2
3
10uC361
R317 0
CLKON
C362
10u
VRF
C363
0.01u
5
OUT
4
BYP EN
U303MIC5255-2.85BM5
IN
GND
- 18 -
3.5 Digital Main Processor (AD6525, U101)
3. TECHNICAL BRIEF
AD6525 GSM-PROCESSOR
KEYPADCOL[4:0]
KEYPADROW[4:0]
KEYPAD
Matrix
JTAG
Universal
System
Connector
(USC)
Power
Sub-system
32kHz
AD6537B
DRV-OUT AGC
13MHz
VCO
Synthesizer
LAN-IN
RADIO
(AD6523/AD6524)
Control
Serial
Port
RX/TX
I/Q
Serial
Port
VOICE
DATA
Serial
Port
Backlight
Service light
FLASH
16 bit
SRAM
8 or 16 bit
(optional)
Accessory
Devices
e.g.BATTERY
SIM
PA Supply
Enable
VDDIO
VDDCORE
GNDIO
GNDCORE
ASDO
ASFS
ASDI
VSDO
VSDI
VSFS
BSDO
BSOFS
BSDI
BSIFS
CLKOUT_GATE
CLKOUT
VBCRESET
Generic Serial Port E
OSCIN
OSCOUT
JTAGEN
TCK, TMS
TDI, TDO
PWRON
VDDRTC
RESET
JTAGE, HSL, GPIO
USCTX/RX/CLK
Generic Serial port A
Generic Serial port B
Generic Serial port D
BACKLIGHT0
BACKLIGHT1
ROMCS
ADD[23:0]
DATA[15:0]
RD
WR
HWR/UBS
LWR/LBS
ASDI
ASDFS
ASDO
VSDI
VSDO
VSFS
MCLK oe
MCLK
RESET
RAMP
RF Timing
I/Q Interince
VOICE 1/F &
Buzzer
AFC
MODE
JTAG
BSDI
BSIFS
BSDO
BSOFS
DISPLAYCS
LCDCTL
ROMCS
Generic Serial Port C
GPCS0
GPCS1
Generic Serial Port D-A
Generic Serial Port D-B
CLKIN
CLKON
Micro SM™
RF Interface
SIM Serial Interface
GPIO[ ] / IR Q
DISPLAY
(parallel or
serial)
U
S
C
Figure 3-8. SYSTEM INTERCONECTION OF AD6525 EXTERNAL INTERFACE
- 19 -
3. TECHNICAL BRIEF
• AD6525 is an ADI designed processor.
• AD6525 consists of
1. BUS arbitration Subsystem
• EBUS, RBUS, PBUS, SBUS, DMABUS, IOBUS
2. DSP Subsystem
• ADI DSP, Viterbi coprocessor, Ciphering unit, Cache memory/controller system
3. MCU Subsystem
• ARM7TDMI, boot ROM, Clock generation and access control module
4. Peripheral Subsystem
• MMI group
➮ Keyboard, Display, Backlight, RTC, GPIO interface
• House Keeping group
➮ Watchdog Timer, Interrupt controller, General Timer
• GSM system group
• Direct Memory Access group
➮ Between PBUS,RBUS, and EBUS
- 20 -
3. TECHNICAL BRIEF
3.5.1 Interconnection with external devices
A. RTC Block Interface
Countered by external X-TAL
The X-TAL oscillates 32.768KHz
B. LCD module interface
The LCD module is controlled by DBB chipset, AD6525.
When LCD operate, the AD6525 controls the LCD module through LCD_CS, LCD_RESET,
ADD01, WR, DATA[00-15]. LCD_ID, LCD_RESET
Table 3-3. LCD module interface
C. RF Interface
The AD6525 control RF parts through PA_BAND, ANT_SW1, ANT_SW2, CLKON , PA_EN,
S_EN, S_DATA, S_CLK, RF_PWR_DWN
Table 3-4. RF CONTROL SIGNALS DISCRIPTION
Signals Description
LCD_CS MAIN LCD driver chip enable. MAIN LCD driver IC has own CS pin
LCD_RESET This pin resets LCD module.
This pin determines whether the data to LCD module are display data
ADD1(RS) or control data. ADD1 can select 16 bit parallel bus. ADD1 is also
used to address flash memory.
WR Write control. The phone do not read data from LCD chip.
DATA
Parallel data lines. Color LCD driver chip uses the 16-bit data
interface.
2V8_VMEM 3V voltage is supplied to white colored LED driver for backlighting.
LCD_BACKLIGHT Control signal of white LED driver IC.
DATA[00-15] Parallel data lines, Sub LCD driver chip uses the 8-bit data in reface.
GPO Signal Name Description
17 PA_BAND PAM Band Select
9 ANT_SW1 Antenna Switch Band Select
11 ANT_SW2 Antenna Switch Band Select
- CLKON RF LDO Enable/Disable
16 PA_EN PAM Enable/Disable
19 S_EN PLL Enable/Disable
20 S_DATA Serial Data to PLL
21 S_CLK Clock to PLL
4 RF_PWER_DWN Powerdown Input
- 21 -
3. TECHNICAL BRIEF
D. SIM Interface
The AD6525 check status periodically in call mode if SIM card is inserted or not, but the
AD6525 don't check in deep sleep mode.
Interface by SIM_DATA, SIMCLK, SIM_RST(GPIO_23)
Table 3-5. SIM CONTROL SIGNALS DISCRIPTION
Figure 3-9. SIM CIRCUIT
E. Key Interface
Include 5 column and 5 row. The AD6525 detect key press by interrupt.
F. ADP3537B Interrupt
There are two interrupts, EOC and CHRDET
EOC: End of Charge. AD6525 makes charging operation stop when high signal is inputted.
CHRDET: This pin is activated when the charger is inserted.
Description
SIM_DATA
This pin receives and sends data to SIM card. This model support
only 3.0 volt interface SIM card.
SIMCLK Clock 3.25MHz frequency.
SIM_RST(GPIO_23) Reset SIM block
VSIM
SIM_DATA
VA165
AVL14K02200
J101
4
GND1
5
VPP
6
IO
10
GND5
9
GND4
VCC
RST
CLK
GND2
GND3
GCA261-6S
VSIM
1
2
3
7
8
AD6525
C117
0.1u
C115
220n
C116
1000p
- 22 -
3.5.2 AD6525 Architecture
Figure 3-10. AD6525 INTERNAL ARCHITECTURE
The internal architecture of AD6525 is shown in Figure 3-10. AD6525 regroups three main
subsystems connected together through a dynamic and flexible communication bys network.
It also includes onboard system RAM (SRAM) and interfaces with external Flash Memory,
Baseband converter functions, and terminal functions like MMI, SIM and Universal System
Connector (USC).
The Digital Signal Processing (DSP) subsystem primarily hosts all the speech processing,
channel equalization and channel codec functions. The code used to implement such
functions can be stored in external Flash Memory and dynamically downloaded on demand
into the DSP’s program RAM and Instruction Cache.
The microcontroller subsystem supports all the GSM terminal software, including the layer 1,
2 and 3 of the GSM protocol stack, the MMI, and applications software such as data
services, test and maintenance. It is tightly associated with on-chip system SRAM and also
includes boot ROM memory with a small dedicated routine to facilitate the initialization of the
external Flash Memory via code download using the on-chip serial interface to the external
Flash Memory interface.
The peripheral subsystem is composed of system peripherals such as interrupt controller,
real time clock, watch dog timer, power management and a timing and control module. It
also includes peripheral interfaces to the terminal functions: keyboard, battery supervision,
radio and display. Both the DSP and the MCU can access the peripheral subsystem via the
peripheral bus (PBUS).
For program and data storage, both the MCU subsystem and the DSP subsystem can
access the on chip system SRAM and external memory such Flash Memory. The access to
the SRAM module is made through the RAM Bus (RBUS) under the control of the bus
arbitration logic. Similarly, access to the Flash Memory is through the parallel External Bus
(EBUS).
3. TECHNICAL BRIEF
AD6525
AD6537B
DSP
SRAM
FLASH
MMI
USC
MUC
Peripheral
RF-Control
Subsystem
Subsystem
Subsystem
(ARM7TDMI
®
)
DMA and BUS
ARBITRARION
Serial Link
DSP BUS
RBUS
EBUS
PBUS
SBUS
- 23 -
3. TECHNICAL BRIEF
3.6 Analog Main & Power Management Processor (AD6537B, U102)
Figure 3-11. AD6537B FUNCTIONAL BLOCK DIAGRAM
AD6525
or
AD6526
- 24 -
• AD6537B is an ADI designed processor.
• AD6537B consists of
1. BB Transmit section
• This section generates in-phase and quadrature BB modulated GMSK signals.
• Digital GMSK modulator, 10-bit DACs, Reconstruction Filter
2. BB Receive section
• 2 identical ADC channels that process BB in-phase and quadrature input signals.
3. Auxiliary section
• 2 auxiliary DASs •AFC DAC, IDAC, AUX ADC
• AUX ADC : 6 channels 10 bits
AFC DAC : 13 bits
IDAC : 10 bits
4. Voiceband section
• Receive audio signal from MIC.
Send audio signal to Speaker
• It interconnect with external device like main microphone, main receiver, earmicrophone and Hands-free kit.
5. Power Management section
• 8 LDOs Block in the AD6537B. VCORE, VMEM, VEXT, VSIM, VRTC, VABB, VMIC,
VVCXO
• Battery Charging Block
3. TECHNICAL BRIEF
- 25 -
3. TECHNICAL BRIEF
3.6.1 Baseband transmit section
1. The AD6537B Baseband Transmit Section is designed to support GMSK for both singleslot and multi-slot application.
2. The transmit channel consists of a digital GMSK modulator, a matched pair of 10-bit
DACs and a matched pair of reconstruction filter
Figure 3-12. AD6537B BASEBAND TRANSMIT SECTION
3.6.2 Baseband receive section
1. This section consists of two identical ADC channels that process baseband in-phase(I)
and quadrature(Q) input signals.
2. Each channel consists of a coarse switched capacitor Anti-Alias filter, followed by a lowpass digital filter
Figure 3-13. AD6537B BASEBAND RECEIVE SECTION
3. TECHNICAL BRIEF
- 26 -
3.6.3 Auxiliary Section
1. This section includes an Automatic Frequency Control (AFC) DAC, voltage reference
buffers, an Auxiliary ADC, and light controllers.
2. This section also contains AUX ADC and Voltage Reference
• AFC DAC: 13 bits
• IDAC: 10 bits
• The Auxiliary ADC provides :
Two differential inputs for temperature sensing.
- A differential input for the battery charger current sensor
- A single-ended input for battery voltage measurement
- A single-ended input for battery type identification
- Two single-ended inputs for microphone and hookswitch detection, one for each of two
analog
Audio input channels
- Two general purpose external inputs
- REF, REFOUT, REFCHG
- REFADC and REFADC/2, and AGND1 inputs for offset and gain measurement
Figure 3-14. AD6537B AUXILIARY SECTION
CSFS
CSDI
CSDO
AD6537B
Control
Serial
Por t
AFC
DAC
Voltage
Reference
REFTXCM
Aux
ADC
AFCDAC
REFBB
REFOUT
REF
REFCHG
TEMP1
TEMP2
AUXADC1
AUXADC2
AIN1P
AIN2P
BATTYPE
ISENSE
VBATSENSE
LIGHT1
LIGHT2
LIGHT3
Light
Controllers
3. TECHNICAL BRIEF
- 27 -
3.6.4 Audio Section
1. Receive audio signal from microphone. C1100 use differential configuration.
2. Send audio signal to speaker. C1100 use differential configuration.
3. This section provides an audio codec with a digital-to-analog converter and an analog-todigital converter, a ring tone volume controller, a microphone interface, and multiple
analog input and output channels.
4. It interconnect with external device like main microphone, main receiver, and headset jack
through the AIN1N, AIN1P, AIN2N, AIN2P, AIN3N, AIN3P, AOUT1P, AOUT1N, AOUT2P,
AOUT2N, AOUT3P, and AOUT3N port.
• AIN1P, AIN1N : Main microphone positive/negative terminal
• AOUT2P, AOUT2N : Main Speaker positive/negative terminal
• AIN2P, AIN2N : Ear-Mic microphone positive/negative terminal
• AOUT1P, AOUT1N : Ear-Mic speaker positive/negative terminal
Figure 3-15. AD6537B AUDIO SECTION
GPI
CSFS
CSDI
CSDO
ASFS
ASDI
ASDO
AD6537B
Control
Serial
Por t
Ring Tone
Volume Controller
Audio
Serial
Por t
Filter/
SRC
Filter/
SRC
DAC
ADC
PGA
PGA
PGA
AIN3P
AIN3N
8Ω
32Ω
32Ω
SPWR
AOUT2P
AOUT2N
AOUT1N
AOUT3N
AOUT3P
AOUT1P
SGND
AIN1P
AIN1N
AIN2P
AIN2N
Analog
Switch
Analog
Switch
Analog Adder
Microphone Interface
Gain Pre-Amp
3. TECHNICAL BRIEF
- 28 -
3.6.5 Power Management
Figure 3-16. AD6537B POWER MANAGEMENT SECTION
1. Power up sequence logic
1. The AD6537B controls power on sequence
2. Power on sequencez
- If a battery is inserted, the battery powers the 8 LDOs.
- Then if PWRONKEY is detected, the LDOs output turn on.
- REFOUT is also enabled
- Reset is generated and send to the AD6525
3. TECHNICAL BRIEF
- 29 -
Figure 3-17. AD6537B POWER MODE LOGIC
2. LDO Block
1. There are 8LDOs in the AD6537B.
- VCORE : supplies Digital Baseband Processor core and AD6537 digital core
(1.8V, 80mA)
- VMEM : supplies external memory and the interface to the external memory on
the digital baseband processor (1.8V or 2.8V, 150mA)
- VEXT : supplies Radio digital interface and high voltage interface (2.8V,
170mA)
- VSIM : supplies the SIM interface circuitry on the digital processor and SIM
card (1.8V or 2.85V, 20mA)
- VRTC : supplies the Real-Time Clock module (1.8 V, 200 µA)
- VABB : supplies the analog portions of the AD6537
- VMIC : supplies the microphone interface circuitry (2.5 V, 1 mA)
- VVCXO : supplies the voltage controlled crystal oscillator ( 2.75 V, 10 mA)
AD6537B
THERM
Thermal
Shutdown
DDLO
UVLO
CHGDET
VBAT
KEYON
DBBON
VRTC
VEXT
VCXDEN
POWERMODE
Enable
Mode
Enable
Mode
Enable
Mode
Enable
Mode
Enable
Digital core
LDO Regulator
Memory Interface
LDO Regulator
External Interface
LDO Regulator
SIM Interface
LDO Regulator
VCXO
LDO Regulator
VCORE Comparator
VMEM Comparator
VEXT Comparator
VCORE
VMEM
VEXT
VCORECP
VMEMCP
VEXTCP
low: VCORE < 1.5V
high: VCORE > 1.5V
high: VMEM > 2.5V or 1.5V
low: VMEM < 2.5V or 1.5V
high: VEXT > 2.5V
low: VEXT < 2.5V
VCORE
VMEM
VEXT
VSM
VVCXO
VSMEn
Control Bit
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