LG 79UB980T-TA, 79UB980T, 79UB989Y, 79UB989Y-TA Service Manual

Printed in KoreaP/NO : MFL68084507 (1405-REV00)

CHASSIS : LB41U

MODEL : 79UB980T 79UB980T-TA

79UB989Y 79UB989Y-TA

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

LED TV

SERVICE MANUAL

North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com

Internal Use Only

- 2 -

Only for training and service purposes

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SERVICING PRECAUTIONS .................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 14

BLOCK DIAGRAM .................................................................................. 23

EXPLODED VIEW .................................................................................. 25

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

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Only for training and service purposes

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental sh orts of the cir cui try that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the

measured resistance should be between 1 MΩ and 5.2 MΩ.

When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

IMPORTANT SAFETY NOTICE

SAFETY PRECAUTIONS

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Only for training and service purposes

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power source before;

a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug

or other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard.

2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture. Unless specied otherwise in this service manual, lubrication

of contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed.

7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.

4. Use only an anti-static type solder removal device. Some sol-

der removal devices not classied as “anti-static” can generate electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material).

7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand

against the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there only until the solder ows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

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Only for training and service purposes

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts.

2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and solder it.

3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection.

Power Output, Transistor Device Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit board.

3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder.

Fuse and Conventional Resistor Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow stake.

2. Securely crimp the leads of replacement component around notch at stake top.

3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections).

1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board.

1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.

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Only for training and service purposes

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This specification is applied to the LED TV used LB41U chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing an d s pe cificat io n b y part number in accordance with BOM.

5) The receiver must be operated for about 5 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

4. Model General Specification

No. Item Specication Remarks

1 Market

Asia, Oceania, Africa, Middle East(PAL/DVB Market)

DTV & Analog * DTV Region: Australia/ NewZealand(AU),

Singapore(SG), Malaysia(MY), Vietnam (VN), South Africa(ZA), Iran(IR), Israel(IL)

2 Broadcasting system

Digital : DVB-T Analog : PAL-BG, DK, I/I’, SECAM-DK/BG/I

▪ Australia/India : only PAL-BG(B)

3 Receiving system

Digital : COFDM, QAM Analog : Upper Heterodyne

▪ DVB-T

- Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32

- Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

5 Video Input (1EA) PAL, SECAM, NTSC

4 System : PAL, SECAM, NTSC, PAL60 Rear (gender)

6 Component Input (1EA) Y/Cb/Cr, Y/Pb/Pr Rear (gender)

7 HDMI Input (4EA)

PC / DTV format,Support HDCP HDMI1-HDCP2.2, HDMI2-ARC, HDMI3, HDMI4-MHL

Side

8 Audio Input (1EA) Component, AV, DVI

Rear (AV Gender) Component, AV and DVI use same jack.

9 SPDIF out(1EA) Optical Audio out Rear (1EA)

10 Analog audio out(1EA) Headphone and External speaker out Rear (1EA)

11 USB Input(3EA) EMF, DivX HD, For SVC (download)

Side JPEG, MP3, DivX HD (USB 3.0 : 1EA, USB 2.0 : 2EA)

12 Speaker Output

70W (Front 10Wx10W, Height 10Wx10W, Woofer 15Wx15W)

3Way 10 Speaker

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Only for training and service purposes

5. External Input Support Format

5.1. Component (Y, CB/PB, CR/PR)

No Resolution H-freq.(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed

1 720*480i 15.73 59.94 13.500 SDTV, DVD 480I(525I)

2 720*480i 15.73 60.00 13.514 SDTV, DVD 480I(525I)

3 720*576i 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz

4 720*480p 31.47 59.94 27.000 SDTV 480P

5 720*480p 31.50 60.00 27.027 SDTV 480P

6 720*576p 31.25 50.00 27.000 SDTV 576P 50Hz

7 1280*720 44.96 59.94 74.176 HDTV 720P

8 1280*720 45.00 60.00 74.250 HDTV 720P

9 1280*720 45.00 50.00 74.250 HDTV 720P 50Hz

10 1920*1080 28.125 50.00 74.250 HDTV 1080I 50Hz,

11 1920*1080 33.72 59.94 74.176 HDTV 1080I

12 1920*1080 33.75 60.00 74.25 HDTV 1080I

13 1920*1080 56.25 50 148.5 HDTV 1080P

14 1920*1080 67.5 60.00 148.5 HDTV 1080P

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Only for training and service purposes

5.2. HDMI : EDID DATA : Refer to adjust specification.

(1) DTV Mode

No Resolution H-freq.(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks

1 640*480 31.469 59.94 25.125 SDTV 480P

2 640*480 31.5 60.00 25.125 SDTV 480P

3 720*480 15.73 59.94 13.500 SDTV, DVD 480I(525I)

Spec. out but display4 720*480 15.75 60.00 13.514 SDTV, DVD 480I(525I)

5 720*576 15.625 50.00 13.500 SDTV, DVD 576I(625I) 50Hz

6 720*480 31.47 59.94 27 SDTV 480P

7 720*480 31.5 60.00 27.027 SDTV 480P

8 720*576 31.25 50.00 27 SDTV 576P

9 1280*720 44.96 59.94 74.176 HDTV 720P

10 1280*720 45 60.00 74.25 HDTV 720P

11 1280*720 37.5 50.00 74.25 HDTV 720P

12 1920*1080 28.125 50.00 74.25 HDTV 1080I

13 1920*1080 33.72 59.94 74.176 HDTV 1080I

14 1920*1080 33.75 60.00 74.25 HDTV 1080I

15 1920*1080 26.97 23.976 63.296 HDTV 1080P

16 1920*1080 27.00 24.000 63.36 HDTV 1080P

17 1920*1080 33.71 29.97 79.120 HDTV 1080P

18 1920*1080 33.75 30.00 79.20 HDTV 1080P

19 1920*1080 56.25 50.00 148.5 HDTV 1080P

20 1920*1080 67.432 59.94 148.350 HDTV 1080P

21 1920*1080 67.5 60.00 148.50 HDTV 1080P

22 3840*2160 53.95 23.98 296.703 UDTV 2160P Only UD Model

23 3840*2160 54 24.00 297.00 UDTV 2160P Only UD Model

24 3840*2160 56.25 25.00 297.00 UDTV 2160P Only UD Model

25 3840*2160 61.43 29.97 296.703 UDTV 2160P Only UD Model

26 3840*2160 67.5 30.00 297.00 UDTV 2160P Only UD Model

27 3840*2160 112.5 50.00 594 UDTV 2160P Only UD Model, Port3

28 3840*2160 135 59.94 593.407 UDTV 2160P Only UD Model, Port3

29 3840*2160 135 60.00 594 UDTV 2160P Only UD Model, Port3

30 4096*2160 53.95 23.98 296.703 UDTV 2160P Only UD Model

31 4096*2160 54 24.00 297 UDTV 2160P Only UD Model

32 4096*2160 56.25 25.00 297 UDTV 2160P Only UD Model

33 4096*2160 61.43 29.97 296.703 UDTV 2160P Only UD Model

34 4096*2160 67.5 30.00 297 UDTV 2160P Only UD Model

35 4096*2160 112.5 50.00 594 UDTV 2160P Only UD Model, Port3

36 4096*2160 135 59.94 593.407 UDTV 2160P Only UD Model, Port3

37 4096*2160 135 60.00 594 UDTV 2160P Only UD Model, Port3

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Only for training and service purposes

(2) PC Mode

No Resolution H-freq.(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks

1 640*350 31.468 70.09 25.17 EGA

2 720*400 31.469 70.08 28.32 DOS

3 640*480 31.469 59.94 25.17 VESA(VGA)

4 800*600 37.879 60.31 40 VESA(SVGA)

5 1024*768 48.363 60.00 65 VESA(XGA)

6 1360*768 47.712 60.015 84.75 VESA(WXGA)

7 1152*864 54.348 60.053 80 VESA

8 1280*1024 63.981 60.020 109.00 SXGA Support to HDMI-PC

9 1920*1080 67.5 60 158.40 WUXGA(Reduced Blanking)

10 3840*2160 54 24.00 297.00 UDTV 2160P Only UD Model

11 3840*2160 56.25 25.00 297.00 UDTV 2160P Only UD Model

12 3840*2160 67.5 30.00 297.00 UDTV 2160P Only UD Model

13 4096*2160 53.95 23.97 296.703 UDTV 2160P Only UD Model

14 4096*2160 54 24 297 UDTV 2160P Only UD Model

- 10 -

Only for training and service purposes

6.2. HDMI Input

(1) HDMI 1.4/2.0 (3D Supported mode manually)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 720*480 31.5 60 27.03 SDTV 480P

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Frame Sequential, Row Interleaving, Column Interleaving

2 720*576 31.25 50 27 SDTV 576P

3 1280*720

45.00 60.00 74.25 HDTV 720P

37.500 50 74.25 HDTV 720P

4 1920*1080

33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half), Top & Bottom

28.125 50.00 74.25 HDTV 1080I

5 1920*1080

27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,

Checker Board, Row Interleaving, Column Interleaving

28.12 25 74.25 HDTV 1080P

33.75 30.00 74.25 HDTV 1080P

67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

56.250 50 148.5 HDTV 1080P

6

3840*2160 4096*2160

53.95 23.976 297.00

HDTV 2160P

2D to 3D, Top & Bottom(half), Side by Side(half),

54 24.00 296.703

56.25 25.00 297.00

61.43 29.970 297.00

67.5 30.00 296.703

7

3840*2160 4096*2160

112.5 50

594

HDTV 2160P HDTV 2160P

2D to 3D, Top & Bottom(half), Side by Side(half), Port3 Only

135 60

6. 3D Mode - DTV/HDMI/USB

6.1. RF Input

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remarks

1 1280*720 37.500 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom

2 1920*1080 28.125 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom

- 11 -

Only for training and service purposes

(2) HDMI 1.4b (3D Supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed

1 640*480

31.469 / 31.5 59.94/ 60 25.125/25.2 1

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 480P) Secondary(SDTV 480P)

31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

62.938/63 59.94/ 60 50.35/50.4 1

Frame packing Line alternative

Secondary(SDTV 480P) (SDTV 480P)

2 720*480

31.469 / 31.5 59.94 / 60 27.00/27.03 2,3

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 480P) Secondary(SDTV 480P)

31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

62.938/63 59.94 / 60 54/54.06 2,3

Frame packing Line alternative

Secondary(SDTV 480P) (SDTV 480P)

3 720*576

31.25 50 27 17,18

Top-and-Bottom Side-by-side(half)

Secondary(SDTV 576P) Secondary(SDTV 576P)

31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

62.5 50 54 17,18

Frame packing Line alternative

Secondary(SDTV 576P) (SDTV 576P)

4 720*576 15.625 50 27 21

Frame packing Field alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half)

Secondary(SDTV 576I) (SDTV 576I (SDTV 576I Secondary(SDTV 576I) Secondary(SDTV 576I)

5 1280*720

37.500 50 74.25 19

Top-and-Bottom Side-by-side(half)

Primary(HDTV 720P) Primary(HDTV 720P)

37.500 50 148.5 19 Side-by-side(Full) (HDTV 720P)

44.96 / 45 59.94 / 60 74.17/74.25 4

Top-and-Bottom Side-by-side(half)

Primary(HDTV 720P) Primary(HDTV 720P)

44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

75 50 148.5 19

Frame packing Line alternative

Primary(HDTV 720P) (HDTV 720P)

89.91/90 59.94 / 60 148.35/148.5 4

Frame packing Line alternative

Primary(HDTV 720P) (HDTV 720P)

6 1920*1080

28.125 50.00 74.25 20

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)

33.72 / 33.75 59.94 / 60 74.17/74.25 5

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

56.25 50.00 148.5 20

Frame packing Field alternative

Primary(HDTV 1080I) (HDTV 1080I)

67.432/67.50 59.94 / 60 148.35/148.5 5

Frame packing Field alternative

Primary(HDTV 1080I) (HDTV 1080I)

7 1920*1080

26.97 / 27 23.97 / 24 74.17/74.25 32

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Primary(HDTV 1080P)

26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

28.12 25 74.25 33

Top-and-Bottom Side-by-side(half)

Secondary(HDTV 1080P) Secondary(HDTV 1080P)

28.12 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

33.716 / 33.75 29.976 / 30.00 74.18/74.25 34

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

43.94/54 23.97 / 24 148.35/148.5 32

Frame packing Line alternative

Primary(HDTV 1080P) (HDTV 1080P)

56.25 25 148.5 33

Frame packing Line alternative

Secondary(HDTV 1080P) (HDTV 1080P)

67.432 / 67.5 29.976 / 30.00 148.35/148.5 34

Frame packing Line alternative

Primary(HDTV 1080P) (HDTV 1080P)

56.250 50 148.5 31

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

67.43 / 67.5 59.94 / 60 148.35/148.50 16

Top-and-Bottom Side-by-side(half)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

- 12 -

Only for training and service purposes

(3) HDMI-PC Input (3D) (3D Supported mode manually)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1024*768 48.36 60 65 HDTV 768P

2D to 3D, Side by Side(half), Top & Bottom

2 1360*768 47.71 60 85.5 HDTV 768P

2D to 3D, Side by Side(half), 7Top & Bottom

3 1920*1080 67.500 60 148.50 HDTV 1080P

2D to 3D, Side by Side(half), Top & Bottom, Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

4

3840*2160 4096*2160

54 24.00 296.703

HDTV 2160P

2D to 3D, Top & Bottom(half), Side by Side(half),

56.25 25.00 297

67.5 30.00 296.703

5 4096*2160 54 24 297.00 HDTV 2160P

2D to 3D, Top & Bottom(half), Side by Side(half), Port3 Only

6 Others - - -

640*350 720*400 640*480 800*600 1152*864

2D to 3D, Side by Side(half), Top & Bottom

(4) Component Input (3D) (3D Supported mode manually)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1280*720 37.5 50 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom

2 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom

3 1280*720 44.96 59.94 74.176 HDTV 720P 2D to 3D, Side by Side(half), Top & Bottom

4 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom

5 1920*1080 33.72 59.94 74.176 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom

6 1920*1080 28.12 50 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom

7 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

8 1920*1080 67.432 59.94 148.352 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

9 1920*1080 27.000 24.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

10 1920*1080 28.12 25 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

11 1920*1080 56.25 50 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

12 1920*1080 26.97 23.976 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

13 1920*1080 33.75 30.000 74.25 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

14 1920*1080 33.71 29.97 74.176 HDTV 1080P 2D to 3D, Side by Side(half), Top & Bottom

- 13 -

Only for training and service purposes

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

2

Over 704x480 Under 1080P interlaced

- - - 2D to 3D, Side by Side(Half), Top & Bottom

3

Over 704x480 Under 1080P progressive

- 50 / 60 -

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving, Frame Sequential

- others -

2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving

4 Over 2160P - 24/25/30/50/60

2D to 3D, Side by Side(Half), Top & Bottom USB Only

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024*768p - 30/60 -

2D to 3D, Side by Side(Half), Top & Bottom2 1280*720p - 30/60 -

3 1920*1080p - 30/60 -

4 Others - - - 2D to 3D

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 320x240 - - - 2D to 3D

2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom

(5) USB, DLNA - Movie (3D) (3D supported mode manually)

(8) Miracast, Widi (3D supported mode manually)

(7) USB, DLNA (3D) (3D supported mode automatically)

(6) USB, DLNA -Photo (3D) (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080p 33.75 30 74.25

Side by Side(Half), Top & Bottom, Checker Board, MPO(Photo), JPS(Photo)

2 2160p 67.5 30 297 MPO(Photo), JPS(Photo)

■ Remark: 3D Input mode

No. Side by Side Top & Bottom Checker board

Single Frame

Sequential

Frame Packing

Line

Interleaving

Column

Interleaving

1

R

L

R

L

- 14 -

Only for training and service purposes

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied to all of the LED TV with LB41U chassis.

2. Designation

(1) Because this is not a hot chassis, it is not necessary to

use an isolation transformer. However, the use of isolation

transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of

25 °C ± 5 °C of temperature and 65 % ± 10 % of relative

humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240

V~, 50/60 Hz. (5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15.

In case of keeping module is in the circumstance of 0 °C, it should be placed in the circumstance of above 15 °C for 2 hours.

In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15 °C for 3 hours.

[Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area.

3. Automatic Adjustment

3.1. ADC Adjustment

ADC adjustment is needed to find the optimum black level and gain in Analog-to-Digital device and to compensate RGB deviation.

3.1.1. Equipment & Condition

(1) USB to RS-232C Jig (2) MSPG-92 5 Series Pattern Generator( MSPG-925 FA,

pattern - 65)

- Resolution : 480i Comp1 1080P Comp1

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7 ± 0.1 Vp-p

- Image

3.1.2. Adjustment method

- Using RS-232, adjust items in the other shown in "3.1.3"

3.1.3. Adj. protocol

Ref.) ADC Adj. RS232C Protocol_Ver1.0

3.1.4. Adj. order

- aa 00 00 [Enter ADC adj. mode]

- xb 00 04 [Change input source to Component1(480i& 1080p)]

- ad 00 10 [Adjust 480i&1080p Comp1]

- xb 00 06 [Change input source to RGB(1024*768)]

- ad 00 10 [Adjust 1920*1080 RGB]

- ad 00 90 End adj.

3.2. MAC address, ESN, Widevine, HDCP

2.0 key download

(1) Equipment & Condition

1) Play file: keydownload.exe

(2) Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

(3) Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process: DETECT → MAC_WRITE →

WIDEVINE_WRITE

4) Play: START

5) Check of result: Ready, Test, OK or NG

(4) Communication Port connection

1) Connect

: PCBA Jig → RS-232C Port == PC → RS-232C Port

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change

xb 00 04 b 00 OK04x (Adjust 480i, 1080p Comp1 )

xb 00 06 b 00 OK06x (Adjust 1920*1080 RGB)

Begin adj. ad 00 10

Return adj. result

OKx (Case of Success) NGx (Case of Fail)

Read adj. data

(main) ad 00 20

(main) 000000000000000000000000007c007b006dx

(sub ) ad 00 21

(Sub) 000000070000000000000000007c00830077x

Conrm adj. ad 00 99

NG 03 00x (Fail) NG 03 01x (Fail) NG 03 02x (Fail) OK 03 03x (Success)

End adj. aa 00 90 a 00 OK90x

- 15 -

Only for training and service purposes

(5) Download

1) AJ/JA Models (14Y LCD TV + MAC + Widevine + ESN + HDCP2.0)

3.3. LAN Inspection

3.3.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

3.3.2. LAN inspection solution

▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC Address.

3.3.3. LAN PORT INSPECTION(PING TEST)

Connect SET -> LAN port == PC -> LAN Port

(1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

3.3.4. LAN PORT inspection (PING TEST)

(1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable.

3.4. Model name & Serial number Download

3.4.1. Model name & Serial number D/L

- Press "Power on" key of service remote control.

(Baud rate : 115200 bps)

- Connect RS232 Signal to USB Cable to USB.

- Write Serial number by use USB port.

- Must check the serial number at Instart menu.

3.4.2. Method & notice

(1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory by D-book 4.0

SET PC

- 16 -

Only for training and service purposes

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded by OTA or service man, sometimes model name or serial number is initialized.(Not always) It is impossible to download by bar code scan, so It need Manual download.

1) Press the "Instart" key of Adjustment remote control.

2) Go to the menu "7.Model Number D/L" like below photo.

3) Input the Factory model name or Serial number like photo.

4) Check the model name Instart menu. → Factory name

displayed.

5) Check the Diagnostics.(DTV country only) → Buyer

model displayed.

3.5. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command

(2) Check the menu on in-start.

4. Manual Adjustment

* ADC adjustment is not needed because of OTP(Auto ADC

adjustment)

4.1. EDID(The Extended Display Identification Data)/DDC(Display Data Channel) download

4.1.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal resolution through information sharing without any necessity of user input. It is a realization of "Plug and Play".

4.1.2. Equipment

- Since embedded EDID data is used, EDID download JIG, HDMI cable and D-sub cable are not need.

- Adjustment remote control

4.1.3. Download method

(1) Press "ADJ" key on the Adjustment remote control, then

select "12.EDID D/L", By pressing "Enter" key, enter EDID D/L menu.

(2) Select "Start" button by pressing "Enter" key, HDMI1/

HDMI2/ HDMI3/ HDMI4 are writing and display OK or NG.

4.1.4. EDID DATA

▪ Reference

- HDMI1 ~ HDMI4

- In the data of EDID, bellows may be different by Input mode.

ⓐ Product ID ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ → ‘01’, Year : ‘2013’ → ‘17’

ⓓ Model Name(Hex): LGTV ⓔ Checksum(LG TV): Changeable by total EDID data. ⓕ Vendor Specific(HDMI)

Command Set ACK

Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]

For HDMI EDID

DVI-D to HDMI or HDMI to HDMI

0 1 2 3 4 5 6 7 8 9 A B C D E F

0x00 00 FF FF FF FF FF FF 00 1E 6D

ⓐ ⓑ

0x01

ⓒ

01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20

ⓓ

0x07

ⓓ

01 ⓔ1

0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21 0x01 22 15 01 29 3D 06 C0 15 07 50

ⓕ

0x02

ⓕ

0x03

ⓕ

10 28 10 E3 05 03 01 02 3A 80 18 71 38 0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2

- 17 -

Only for training and service purposes

(1) EDID

# HDMI1 (C/S: 0xE7, 0x04) EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# HDMI2 (C/S: 0xE7, 0xF4) EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# HDMI3 (C/S: 0xA1, 0x3A) EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# HDMI4 (C/S: 0xE7, 0xD4) EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

* Checksum(HDMI 1/2/3/4)

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 1E 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30

50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E7

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01

10 01 18 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26

20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80

30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58

40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40

50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A

60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC

70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A1

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 02 03 55 F1 54 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50

20 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02

30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C

50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72

60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04

Input FFh (Checksum)

HDMI1 E7 04

HDMI2 E7 F4

HDMI3 A1 3A

HDMI4 E7 D4

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50

20 09 57 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02

30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C

50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72

60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F4

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 02 03 55 F1 58 10 1F 04 13 05 14 03 02 12 20 21

10 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06

20 C0 15 07 50 09 57 07 7C 03 0C 00 30 00 B8 3C 20

30 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10

40 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 03 01

50 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36

60 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E

70 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 3A

0 1 2 3 4 5 6 7 8 9 A B C D E F

0 02 03 4A F1 54 10 9F 04 13 05 14 03 02 12 20 21

10 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50

20 09 57 07 7C 03 0C 00 40 00 B8 3C 20 C0 8E 01 02

30 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10

40 E3 05 03 01 E5 0E 60 61 65 66 01 1D 80 18 71 1C

50 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D 00 72

60 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E 00 00

70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4

- 18 -

Only for training and service purposes

4.2. Camera Function Inspection

(1) Objective : To check how it connects between Camera and

PCBA normally, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.

1) Push Camera Up.

2) Camera’s Preview picture apeears on TV Set.

3) Push Camera Down.

(3) RS-232C Command

4.3. White Balance Adjustment

4.3.1. Overview

▪ W/B adj. Objective & How-it-works

(1) Objective: To reduce each Panel's W/B deviation (2) How-it-works : When R/G/B gain in the OSD is at 192, it

means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value.

(3) Adjustment condition : normal temperature

1) Surrounding Temperature : 25 °C ± 5 °C

2) Warm-up time: About 5 Min

3) Surrounding Humidity : 20 % ~ 80 %

4.3.2. Equipment

(1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol

is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/216-Gray

(Model: 217, Pattern: 78)

→ Only when internal pattern is not available

• Color Analyzer Matrix should be calibrated using CS-100.

4.3.3. Equipment connection MAP

4.3.4. Adj. Command (Protocol)

- LEN: Number of Data Byte to be sent

- CMD: Command

- VAL: FOS Data value

- CS: Checksum of sent data

- A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

▪ RS-232C Command used during auto-adjustment.

Ex) wb 00 00 -> Begin white balance auto-adj.

wb 00 10 -> Gain adj. ja 00 ff -> Adj. data jb 00 c0 ... ... wb 00 1f -> Gain adj. completed *(wb 00 20(Start), wb 00 2f(end)) -> Off-set adj. wb 00 ff -> End white balance auto-adj.

▪ Adj. Map

RS-232C COMMAND

Explanation

CMD DATA ID

ai 00 23 Camera Function Start.

ai 00 24 Camera Function End.

Co lor Anal yze r

Co mp ute r

Pattern Gen era to r

RS -232 C

RS- 232 C

Pro be

Sig nal Sou rce

* If TV internal pattern is used, not needed

START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP

RS-232C COMMAND

[CMD ID DATA]

Explantion

wb 00 00 Begin White Balance adjustment

wb 00 10 Gain adjustment(internal white pattern)

wb 00 1f Gain adjustment completed

wb 00 20 Offset adjustment(internal white pattern)

wb 00 2f Offset adjustment completed

wb 00 ff

End White Balance adjustment (internal pattern disappears )

Adj. item

Command

(lower case ASCII)

Data Range

(Hex.)

Default

(Decimal)

CMD1 CMD2 MIN MAX

Cool

R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

R Cut

G Cut

B Cut

Medium

R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

R Cut

G Cut

B Cut

Warm

R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

R Cut

G Cut

- 19 -

Only for training and service purposes

4.3.5. Adj. method

(1) Auto adj. method

1) Set TV in adj. mode using POWER ON key.

2) Zero calibrate probe then place it on the center of the Display.

3) Connect Cable.(RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre mode. (Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need.

(2) Manual adjustment. method

1) Set TV in Adj. mode using POWER ON.

2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10 cm of the surface.

3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►).

(When right key(►) is pressed 216 Gray internal pattern

will be displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value.

5) Adjustment is performed in COOL, MEDIUM, WARM 3

modes of color temperature.

** G-fix adjustment Adjust modes (Cool), Fix the G gain to 172 (default data) and change the others (G/B Gain). Adjust two modes(Medium / Warm), Fix the one of R/G/B gain to 192 (default data) and decrease the others.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Testpattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 216 Gray pattern.

▪ Adjustment condition and cautionary items

1) Lighting condition in surrounding area Surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding.

2) Probe location : Color Analyzer(CA-210) probe should be within 10 cm

and perpendicular of the module surface (80° ~ 100°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked

using no signal or Full-white pattern.

4.3.6. Reference(White balance adjusmtment coordinate and color temperature)

▪ Luminance : 206 Gray ▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

▪

Standard color coordinate and temperature using CA-210(CH 14)

4.3.7. EDGE & IOL LED White balance table

▪ EDGE LED module change color coordinate because of

aging time.

▪ Apply under the color coordinate table, for compensated

aging time.

▪ (Normal line) Edge & ALEF LED White balance table

- gumi(Mar. ~ Dec.) & Global Model : (normal line) LGD

- gumi Winter table(Jan., Fab.)- Gumi producing model use only Model : (normal line) LGD

▪ AUO, INX, Sharp, CSOT, BOE (Cool =13000 K)

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271 0.270 13000 K 0.0000

Medium 0.286 0.289 9300 K -3

Warm 0.313 0.329 6500 K 0.0000

Mode

Coordinate

Temp ∆uv

x y

Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000

Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K -3

Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000

NC

4.0

Aging

time

(Min)

Cool Medium Warm

x y x y x y

271 270 286 289 313 329 1 0-2 282 289 297 308 324 348 2 3-5 281 287 296 306 323 346 3 6-9 279 284 294 303 321 343 4 10-19 277 280 292 299 319 339 5 20-35 275 277 290 296 317 336 6 36-49 274 274 289 293 316 333 7 50-79 273 272 288 291 315 331 8 80-119 272 271 287 290 314 330 9 Over 120 271 270 286 289 313 329

NC

4.0

Aging

time

(Min)

Cool Medium Warm

x y x y x y

271 270 286 289 313 329 1 0-2 286 295 301 314 328 354 2 3-5 284 290 299 309 326 349 3 6-9 282 287 297 306 324 346 4 10-19 279 283 294 302 321 342 5 20-35 276 278 291 297 318 337 6 36-49 274 275 289 294 316 334 7 50-79 273 272 288 291 315 331 8 80-119 272 271 287 290 314 330 9 Over 120 271 270 286 289 313 329

webOS

Cool Medium Warm

X y x y x y

spec 271 270 285 293 313 329

target 278 280 293 299 320 339

- 20 -

Only for training and service purposes

4.4. Local Dimming Function Check

Step 1) Turn on TV. Step 2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving. Step 3) Confirm the Local Dimming mode. Step 4) Press "exit" key.

4.5. Magic Motion Remote control test

- Eq uipment : RF Remote cont rol for test, IR-KEY-Code

Remote control for test

- You must confirm the battery power of RF-Remote control

before test(recommend that change the battery per every lot)

- Sequence (test)

1) If you select the ‘start key(OK)’ on the Adjustment remote control, you can pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select the "OK" key on the Adjustment remote control.

3) You must remove the pairing with the TV Set by select ‘Mute + OK Key’ on the Adjustment remote control.

4.6. 3D function test

(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) * HDMI mode NO. 872 , pattern No.83 (1) Please input 3D test pattern like below.

(2) When 3D OSD appear automatically, then select green key.

(3) Don't wear a 3D Glasses, Check the picture like below.

4.7. Option selection per country

4.8.1. Overview

- Option selection is only done for models in AJ/JA/IL

4.8.2.Method

(1) Press "ADJ" key on the Adjustment remote control, then

select Country Group Menu.

(2) Depending on destination, select Country Group Code or

Country Group then on the lower Country option, select

US, CA, MX. Selection is done using +, - or ►◄ KEY.

4.8. Color Sensor Function Inspection

4.8.1. Overview

▪ Option selection is only done for models in AJ/JA/IL

4.8.2. Method

(1) Press ADJ key on the Adj. R/C, then select a Area option

Meun.

(2) Depending on destination, select a Area option , using +, -

or ►◄ KEY

4.9. Color Sensor Function Inspection

This Inspection is available only Power-Only Status. (1) Turn on TV (2) Press EYE key of Adj. R/C (3) Confirm color sensor raw data for each channel (4) Cover the Color sensor on the front of the using your hand

and wait for 6 seconds.

(5) Confirm that value is lower than 10 of the “Raw Data

(Sensor data, Backlight )” and “OK” message.

If after 6 seconds, value is not lower than 10 and not

showing the “OK” message, replace color sensor.

(6) Remove your hand from the color sensor and wait for 6

seconds. (7) Compare step 3) raw data. If the variation is higher than 30 for each channel, replace

color sensor

Step 2) Step 3) Step 4)

Step 5) Step 6) Step 7)

- 21 -

Only for training and service purposes

4.8. HDMI ARC Function Inspection

(1) Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

(2) Test method

1) Insert the HDMI Cable to the HDMI ARC port from the master equipment (HDMI2)

2) Check the sound from the TV Set

3) Check the Sound from the Speaker or using AV & Optic TEST program (It’s connected to MSHG-600)

4.9. MHL Test

(1) Turn on TV (2) Select HDMI4 mode using input Menu. (3) Set MHL Zig(M1S0D3617) using MHL input, output and

power cord. (4) Connect HDMI cable between MHL Zig and HDMI4 port. (5) Check LED light of Zig and Module of Set

4.10. UHD 4K Test

(1) Video Inspection(UDG-4004NS)

1) Insert the HDMI Cable to TV Set.

2) Convert to HDMI Mode using TV/AV key on ADJ remote control

3) Inspect the sound and picture operation well.

(Color condition, Picture noise, Sound distortion etc.)

4)Inspection 2D → 3D conversion

(2) Pattern Inspection (MSPG-7100)

1) Insert the HDMI Jack to HDMI 3 Port.

2) Convert to UHD Inspection Pattern. (Use remote control)

3) Check Video and Sound.

4) Convert to 64 Gray Inspection Pattern.

5) Check Video and Sound.

6)Inspect HDMI-CEC function. (Push Play & Pause button)

(3) 4K Inspection.(HEVC Inspection model only)

1) Insert USB that 4K video file is saved.

2) Check that the video plays normally.

4.11. Tool Option selection

- Method : Press "ADJ" key on the Adjustment remote control, then select Tool option.

4.12. Ship-out mode check (In-stop)

- After final inspection, press In-Stop key of the Adjustment remote control and check that the unit goes to Stand-by mode.

- 22 -

Only for training and service purposes

5. GND and Internal Pressure check

5.1. Method

(1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET. (If loose, re-insert)

(2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process.

5.2. Checkpoint

▪ TEST voltage

- GND: 1.5 KV / min at 100 mA

- SIGNAL: 3 KV / min at 100 mA

▪ TEST time: 1 second ▪ TEST POINT

- GND TEST = POWER CORD GND & SIGNAL CABLE

METAL GND

- Internal Pressure TEST = POWER CORD GND & LIVE &

NEUTRAL

▪ LEAKAGE CURRENT: At 0.5 mArms

6. Audio

Measurement condition: (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms

7. USB S/W download(Service only)

(1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick.

- If your downloaded program version in USB Stick is Low, it didn't work. But your downloaded version is High, USB data is automatically detecting.(Download Version High & Power only mode, Set is automatically Download)

(3) Show the message "Copying files from memory".

(4) Updating is starting. (5) Updating Completed, The TV will restart automatically.

(6) If your TV is turned on, check your updated version and

Tool option. (explain the Tool option, next stage)

* If downloading version is more high than your TV have,

TV can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn't have a DTV/ATV test on production line.

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote control.

2) Select "Tool Option 1" and push "OK" key.

3) Punch in the number. (Each model has their number.)

No. Item Min Typ Max Unit

1

Audio practical max Output, L/R (Distor-

tion=10% max Output)

9 10 12 W

EQ Off

AVL Off

Clear Voice Off

8.5 8.9 9.9 Vrms

2

Speaker

(8 Ω Impedance)

9 10 12 W

EQ On

AVL On

Clear Voice On

- 23 -

Only for training and service purposes

AUDA/D

BB_TP_DATA

DAC_DATA

AAD_DATA

HSR_P/M

CVBS

DIF(P/N)

SIF

Tuner

COMP1/AV1/DVI_ L/R

AV1

COMP1

AV1_CVBS

Comp1 Y,Pb,Pr

H13

LG1154AN

Audi o AMP

(4.2ch~ 7.2ch)

OPTIC

SPK

H/P

H/P Audio L/R

SPDIF

I2S

16x2

DDR3

4GbÝ 6 ( 1600)

Vx1

CVBS

SCART

SC_CVBS, RGB, Audio L/R

DTV/MNT_LR/V_OUT

LNB

H/P

AMP

H13

LG1154D

CI

eMMC

CI

HDMI

2.0 Switch

HDMI1(HDC P2.2)

TS output

From H13D

D14

1Gb x 4 (1600)

DDR3

HDMI output

Motion-R &

USB1(USB3.0)

USB2(USB2.0)

USB3(USB2.0)

USB

HUB

HDMI_CEC

USB 3.0

USB 2.0

USB_CAM

USB 2.0 (WIFI11ac & BT)

USB_WI-Fi

PHY

RMII

LAN

WOL / WOW

Logo Light

IR/Joy key

RS-232C

8x4

8

16x4

U14

1Gb x 2(1600)

DDR3

FHD HS-LVDS

16x2

2:1 Mux

1:2 Splitter

OSD HS-LVDS

URSA9

1Gb x 4 (1866)

DDR3

16x4

Vx1 8Lane

Vx1 2Lane

OSD

USB redr iver

Jitter

cleaner

HDMI2(ARC)

HDMI3

HDMI4(MHL)

HDCP2.2

MHL

BLOCK DIAGRAM

1. External

- 24 -

Only for training and service purposes

Tuner

DIF

TS (P)

System

Demux

Audio DSP

Multi-STD

Audi o Decoder

LX4 Hi Fi EP

SIF

Global Baseband

V/Q, D VB-T/ C ISDB-T

CVBS(3c h)

Component(2ch)

HDMI-Rx 1. 4

(1-port PHY)

3D, AR C, 4kx2k

AAD

(THAT)

Mux

H13A H13D

Audio L/R(4-ch)

SCART out

SW

I2S(Ext ern al)

Audio DAC (48KHz)

Video Decoder

Multi-STD

HD D ecoder

(Boda950)

CVBS AFE(2-ch)

12b@54MHz

CVBS-Out

Mux

10x3c h

DE

CVBS

Encoder

DDR3 PHY

DDR3 Controller

Audio

Line Out

LVDS

Tx

Audio PLL

w/ D CO

Source Mux

TNR

De-interlacer

Main/Sub Sc aler

H3D

VCR

2D GFX

JPG/PNG Decoder

TrustZone

CPU

ARMCA9 Core

Dual 1.2GHz

32KBI$

32KBD$

1MB L2 $

SWSW

3ch Video

AFE

10b@148.5MH z

w/ LLPLL

LVDS

Rx

Sound DSP

Clear Voice II

Perceptual

Volume Control

Slim SPK

DivX

Bluetooth

Digita l AMP

I2S

I2S(HPD)

SPDIF

JPG Encoder

CVD

Y/C

CVBS

CPU

64KB SRAM

48KB ROM

UART

OTP

Timer

UARTx 3

EMAC

SCI

SPIx2

I2Cx10

eMMC

DMAC(8ch)

Timer

WDT

PHY

SRAM 16KB

I2Cx1

BE

H3D

DDR3 PHY

DDR3 Controller

SPLL

DDR

PLL

DPLL

DDR

PLL

Digital

Audio

Output

16

TS(P) TS(P)

FRC

SRE

PE1

OSD

LED

Output f ormatter

TCON

MCU

Capture

Block

(3CH)

GBB AFE

1ch@30MH z

w/ PLL

BTSC AFE

10b@18.432MH z

w/ PLL

1ch L/R

Audi o- ADC

24b@48KHz

CVBS DAC

5x1c h (1ch)

I2Cx1

HDMI

(1-Link)

HDMI

Mux

DVB-CI/CI+

8

Video Encoder

1080p@30fps

Analog Chip Total Pin : 183w/o Power

Digital Chip Total Pin : 491w/o Power

AtoDPin : 79

TS(S)

Vx1/EPI/LVDS Com bo

(120Hz)

GPU Rogue Han

USB3.0 x 1

USB2.0x3

GPIOx136

Secure Engine

TS(S)

Audio DAC

(48KHz )

I2S

SW

CPLL

DCO

x2

MCU

SDRAM

(MCP)

GPIOIx16

2. Internal

- 25 -

Only for training and service purposes

CAM1

200

301

540

521

303

304

307

123

400

710

305

900

306

120

560

570

122

522

500

501

310

302

530

303

800

121

LV1

LV2

A10

A22

A2

AG1

Set + Stand

AT1

(Option)

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essenti al that these sp ecial safet y parts shoul d be replac ed with the same compon ents as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

EB_ADDR[3]

EB_ADDR[14]

EMMC_DATA[1]

EB_DATA[1]

EB_ADDR[0]

EB_ADDR[6]

EMMC_DATA[7]

EB_ADDR[9]

EB_DATA[6]

EMMC_DATA[3]

EB_ADDR[10]

EB_ADDR[2]

EB_ADDR[13]

EB_ADDR[4]

EB_DATA[0]

EB_DATA[2]

EB_ADDR[11]

EMMC_DATA[4]

EB_DATA[3]

EB_DATA[5]

EB_ADDR[8]

EB_ADDR[12]

EB_ADDR[5]

EMMC_DATA[6]

EB_DATA[7]

EB_ADDR[7]

EB_DATA[4]

EMMC_DATA[2]

EB_ADDR[1]

EMMC_DATA[0]

EMMC_DATA[5]

R164331/16W

5%

PLLSET0

R113 10K

UHD

XO_MAIN

M_REMOTE_RX

BIT6

OPM1

EPHY_REFCLK

+3.3V_TUNER

H13A_SDA

I2C_SCL6

R111

10K

BIT1_0

M_REMOTE_RTS

AUD_LRCH2

R148

1.8K

I2C_SDA_MICOM_SOC

USB3_TX0P

C103

0.1uF

SOC_RESET

H13_CONNECT

R146

1.8K

AR100

33

R166 10K

OPT

TDI0

/RST_PHY

I2C_SCL_MICOM_SOC

CAM_TRIGGER_DET

R122 10K

URSA9

SOC_TX

R100 33

OPT

BIT1

R130 10K

OPT

/USB_OCD2

HDMI_HPD_2

CAMERA_DM

AV1_CVBS_DET

HDMI_HPD_3

R168 10K

OPT

+3.3V_NORMAL

CAM_CD2_N

EPHY_MDC

CAM_WAIT_N

U14_RESET

TMS0

CAM_REG_N

TRST_N0

SOC_SPI1_CS

R135

1.8K

KR_PIP_NOT

USB3_TX0M

I2C_SCL1

R136

1.8K

KR_PIP_NOT

R142

1.8K

D14_HWRESET

I2C_SDA_MICOM

EPHY_RXD0

I2C_SCL5

+3.3V_NORMAL

C101

8pF

R110 10K

BIT0_1

EB_ADDR[0-14]

R141

1.8K

+3.3V_NORMAL

R162

200

1%

SMARTCARD_DET/SD_EMMC_DATA[3]

I2C_SCL2_SOC

AMP_RESET_N_1

C105 0.1uF

CAM_CD1_N

+3.3V_NORMAL

SOC_RESET

R116 10K

U14

R131 10K

R175

3.3K

SMARTCARD_RST/SD_EMMC_DATA[2]

SIL9617_INT

R160 10K

OPT

I2C_SDA6

PLLSET0

OPM1

PCM_5V_CTL

HUB_DP

SOC_SPI1_MISO

R104

0

HDMI_CLK-

R138

1.8K

TDO0

HUB_DM

TDI0 TDO0

+3.3V_NORMAL

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

I2C_SDA4

EPHY_EN

AR101

3.3K

I2C_SDA6

/RST_HUB

AUD_LRCH2

M_REMOTE_RX

R126 10K

BIT7_1

I2C_SCL4

IC100

LG1154D_H13D

XIN

A26

XOUT

B26

XTAL_BYPASS

B27

H13DA_XTAL

AT37

PORES_N

AU16

OPM1

AD34

OPM0

AD33

H13DA_SCL

AT26

H13DA_SDA

AU26

TRST_N0

AP9

TMS0

AN9

TCK0

AP11

TDI0

AN11

TDO0

AN10

TRST_N1

AM10

TMS1

AM9

TCK1

AM11

TDI1

AM12

TDO1

AL11

PLLSET1

AL9

PLLSET0

AL10

BOOT_MODE

AE34

EXT_INTR3/GPIO70

Y33

EXT_INTR2/GPIO69

W32

EXT_INTR1/GPIO68

W33

EXT_INTR0/GPIO67

W34

UART0_RXD

AU12

UART0_TXD

AT12

UART1_RXD

AU13

UART1_TXD

AT13

UART1_RTS

AP12

UART1_CTS

AR12

SPI_CS0/GPIO36

AE35

SPI_DO0/GPIO38

AE36

SPI_DI0/GPIO39

AF36

SPI_SCLK0/GPIO37

AF35

SPI_CS1

AG34

SPI_DO1

AF33

SPI_DI1

AG33

SPI_SCLK1

AG32

SCL0/GPIO66

AR15

SDA0/GPIO65

AP15

SCL1/GPIO64

AR16

SDA1/GPIO79

AP16

SCL2/GPIO78

AP17

SDA2/GPIO77

AR17

SCL3

AP6

SDA3

AR6

SCL4

AH32

SDA4

AJ33

SCL5

AH34

SDA5

AH33

CAM_CE1_N

F33

CAM_CE2_N

F34

CAM_CD1_N/GPIO76

D32

CAM_CD2_N/GPIO75

E32

CAM_VS1_N/GPIO86

G32

CAM_VS2_N/GPIO85

G33

CAM_IREQ_N/GPIO73

F32

CAM_RESET

G34

CAM_INPACK/GPIO74

D33

CAM_VCCEN_N/GPIO87

H32

CAM_WAIT_N/GPIO84

E33

CAM_REG_N/GPIO72

D34

CAM_IOIS16_N/GPIO83

H33

SC_CLK/GPIO130

T33

SC_DETECT/GPIO133

U33

SC_VCCEN/GPIO129

T32

SC_VCC_SEL/GPIO128

V32

SC_RST/GPIO131

V33

SC_DATA/GPIO132

V34

SD_CLK/GPIO125

A25

SD_CMD/GPIO124

C25

SD_CD_N/GPIO123

B25

SD_WP_N/GPIO122

E25

SD_DATA3/GPIO121

D25

SD_DATA2/GPIO120

E24

SD_DATA1/GPIO135

D24

SD_DATA0/GPIO134

C24

USB2_2_DP0

L37

USB2_2_DM0

L36

USB2_2_TXRTUNE

K34

USB2_1_DP0

M37

USB2_1_DM0

M36

USB2_1_TXRTUNE

K33

USB2_0_DP

AU7

USB2_0_DM

AT7

USB2_0_TXRTUNE

AP7

USB3_DP0

P37

USB3_DM0

P36

USB3_RX0P

N36

USB3_RX0M

N37

USB3_TX0P

R36

USB3_TX0M

R37

USB3_RESREF

N34

USB3_REFPADCLKM

P33

USB3_REFPADCLKP

P32

NC_1

L32

NC_2

L33

NC_3

M31

NC_4

AJ31

GPIO136

J32

GPIO137

J33

GPIO138

K32

GPIO139

J34

GPIO31

AL34

GPIO30

AM33

GPIO29

AM32

GPIO28

AF30

GPIO27

AN34

GPIO26

AK34

GPIO25

AL33

GPIO24

AL32

GPIO23/UART2_TX

AR9

GPIO22/UART2_RX

AM5

GPIO21

AM6

GPIO20

AM7

GPIO19

AL6

GPIO18

AK7

GPIO17

AK6

GPIO16

AK5

GPIO15

AJ5

GPIO14

AJ6

GPIO13

AJ7

GPIO12

AH6

GPIO11

AG7

GPIO10

AG6

GPIO9

AG5

GPIO8

AF5

GPIO7

AH30

GPIO6

AG30

GPIO5

AN33

GPIO4

AK33

GPIO3

AE30

GPIO2

AD30

GPIO1

AN32

GPIO0

AK32

DDCD0_CK

AC32

DDCD0_DA

AC33

HPD0

AB33

PHY0_ARC_OUT_0

AE37

PHY0_RX0N_0

AC36

PHY0_RX0P_0

AC37

PHY0_RX1N_0

AB36

PHY0_RX1P_0

AB37

PHY0_RX2N_0

AA36

PHY0_RX2P_0

AA37

PHY0_RXCN_0

AD36

PHY0_RXCP_0

AD37

HUB_PORT_OVER0

R32

HUB_VBUS_CTRL0

R33

EB_CS3/GPIO93

K35

EB_CS2/GPIO92

K36

EB_CS1/GPIO91

K37

EB_CS0/GPIO90

L35

EB_WE_N/GPIO95

H35

EB_BE_N1/GPIO81

H36

EB_WAIT/GPIO94

J35

EB_OE_N/GPIO82

J36

EB_BE_N0/GPIO80

H37

EB_ADDR15/GPIO89

G37

EB_ADDR14/GPIO88

G36

EB_ADDR13/GPIO103

G35

EB_ADDR12/GPIO102

F36

EB_ADDR11/GPIO101

F35

EB_ADDR10/GPIO100

E36

EB_ADDR9/GPIO99

E37

EB_ADDR8/GPIO98

E35

EB_ADDR7/GPIO97

D37

EB_ADDR6/GPIO96

D36

EB_ADDR5/GPIO111

D35

EB_ADDR4/GPIO110

C36

EB_ADDR3/GPIO109

C35

EB_ADDR2/GPIO108

B37

EB_ADDR1/GPIO107

B36

EB_ADDR0/GPIO106

B35

EB_DATA7/GPIO105

C32

EB_DATA6/GPIO104

B33

EB_DATA5/GPIO119

A33

EB_DATA4/GPIO118

C33

EB_DATA3/GPIO117

A34

EB_DATA2/GPIO116

B34

EB_DATA1/GPIO115

C34

EB_DATA0/GPIO114

A36

EMMC_CLK

Y37

EMMC_CMD

Y36

EMMC_RESETN

W35

EMMC_DATA7

T36

EMMC_DATA6

W36

EMMC_DATA5

V35

EMMC_DATA4

V37

EMMC_DATA3

V36

EMMC_DATA2

U35

EMMC_DATA1

U36

EMMC_DATA0

U37

RMII_REF_CLK

AU11

RMII_CRS_DV

AU8

RMII_MDIO

AT8

RMII_MDC

AR8

RMII_TXEN

AR10

RMII_TXD1

AT10

RMII_TXD0

AU10

RMII_RXD1

AT11

RMII_RXD0

AR11

/RST_HUB

R109 10K

BIT0_0

HDMI_MUX_SEL

SOC_RX

TRST_N0

+3.3V_LNA_TU

R118

3.3K

RF_SWITCH_CTL

R149

10K

R135-*1

1.5K

KR_PIP

/PCM_CE1

R150

3.3K

OPT

D13_INT

USB3_RX0P

R124 10K

BIT6_1

HDMI_RX0-

USB_CTL1

XIN_MAIN

H13_CONNECT

R9531_FLASH_WP

R152

560

H13D_XTAL_560ohm

OPM0

P100

12505WS-10A00

T32

1

2

3

4

5

6

7

8

9

10

11

SOC_SPI1_MOSI

I2C_SCL_MICOM_SOC

SOC_SPI1_SCLK

IC102-*1

M24256-BRMN6TP

EEPROM_ST

3

E2

2

E1

4

VSS

1

E0

5

SDA

6

SCL

7

WC

8

VCC

TCK0

CAM_IREQ_N

EPHY_INT

I2C_SCL4

/PCM_CE2

R151

10K

USB3_RX0M

HDMI_RX1-

R107 100

I2C_SDA1

R133 33

OPT

BIT0

PLLSET1

TMS0

R155

10K

CI

HDMI_CLK+

EB_BE_N1

R129 10K

BIT7

SOC_SPI1_SCLK

AMP_RESET_N_1

EMMC_CLK

BIT8

R134 33

OPT

M_REMOTE_TX

I2C_SCL2

I2C_SDA_MICOM_SOC

EPHY_MDIO

M_RFModule_RESET

EMMC_RST

SC_DET

SPDIF_OUT_ARC

R128 10K

OLED

HDMI_RX1+

+3.3V_NORMAL

SMARTCARD_VCC/SD_EMMC_CMD

USB3_DM

M_REMOTE_RTS

/TU_RESET2

I2C_SDA_MICOM_SOC

TCK0

R157

200

1%

PCM_RESET

BOOT_MODE

HDMI_RX2+

EB_OE_N

R167 33

OPT

BIT4

+3.3V_NORMAL

R147

1.8K

R108

1M

I2C_SCL6

C100

8pF

I2C_SCL2_SOC

SOC_SPI0_MOSI

BIT10

EB_BE_N0

/USB_OCD1

R127 10K

LCD

EPHY_TXD1

R123 10K

BIT6_0

MN864778_RESET

M_REMOTE_CTS

M_REMOTE_TX

R114 10K

FHD

R112

10K

BIT1_1

I2C_SCL_MICOM_SOC

R154

10K

CI

WIFI_DM

R163 10K

OPT

R137

1.8K

CAMERA_DP

+3.3V_NORMAL

PLLSET1

SMARTCARD_DATA/SD_EMMC_CLK

INSTANT_BOOT

X100

24MHz

4

GND_2

1

X-TAL_12GND_1

3

X-TAL_2

R136-*1

1.5K

KR_PIP

+3.3V_NORMAL

EB_WE_N

R9531_RESET

XIN_MAIN

I2C_SDA5

SMARTCARD_CLK/SD_EMMC_DATA[0]

R101 33

OPT

R132 10K

OPT

R143

1.8K

I2C_SCL5

I2C_SDA4

H13A_SCL

0.1uF

T32

I2C_SDA2

SOC_SPI1_CS SOC_SPI1_MOSI

FRC_FLASH_WP

BIT2

I2C_SCL2_SOC

I2C_SCL5

R125 10K

BIT7_0

+3.3V_NORMAL

CAM_TRIGGER_DET

I2C_SDA2_SOC

AMP_RESET_N_1

HP_DET

Compensation_Done

/USB_OCD3

R120 10K

D9

AMP_RESET_N

IC102

R1EX24256BSAS0A

EEPROM_RENESAS

3

A2

2

A1

4

VSS

1

A0

5

SDA

6

SCL

7

WP

8

VCC

C104 0.1uF

I2C_SDA2_SOC

R121 10K

URSA7/URSA9P

CAM_SLIDE_DET

SOC_SPI1_MISO

I2C_SCL1

I2C_SDA1

EB_DATA[0-7]

XO_MAIN

BIT5

CAM_SLIDE_DET

C108

0.1uF

R115 10K

NON_U14

HDMI_RX2-

R103

3.3K

BOOT_MODE

SOC_SPI0_SCLK

I2C_SDA5

EPHY_TXD0

EPHY_CRS_DV

USB_CTL2

R161 200 1%

BIT3

M_REMOTE_CTS

R117

3.3K

OPT

I2C_SCL_MICOM

INSTANT_BOOTOPM0

SOC_SPI0_MISO

/TU_RESET1

R159

200

1%

USB3_DP

HDMI_RX0+

USB_CTL3

R145

1.8K

I2C_SDA2_SOC

IC102-*2

AT24C256C-SSHL-T

EEPROM_ATMEL

3

A2

2

A1

4

GND

1

A0

5

SDA

6

SCL

7

WP

8

VCC

R1020

EPHY_RXD1

EMMC_CMD

R153

10K

CI

COMP1_DET

BIT9

WIFI_DP

AR102

33

R144

1.8K

+3.3V_NORMAL

R119 10K

NOT_D9

I2C_SDA5

SIL9617_RESET

SOC_SPI0_CS0

EMMC_DATA[0-7]

DPC_CTL

R152-*1

100

H13D_XTAL_100ohm

2013-12-17

H13 D CHIP

BSD-14Y-UD-001-HD

Only SMART CARD

BIT(0/1)

BIT(6/7)

BIT9

BIT8

DVB

00

PLL SET[1:0] : internal pull up "00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz) "01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz) "10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz) "11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)

Resolution

TW/COL

EU

UHD

01

BIT10 Reserved

BOOT_MODE0

EU/CIS

10

High

Default

BIT2

T2/C

KR

ATV_SOC

Display

Support U14

ATV_EXT

OLED

FHD

ATSC_PIP

Write Protection

- Low : Normal Operation

- High : Write Protection

I2C for tuner

ATV_EXT

D9 Model

System Configuration

11

ISDB_PIP

TW/COL

For ISP

BR

A0’h

AJJA

T/C

Place near by LG1154D

WebOS UHD HW Option

JP

ATSC_PIP

U14 SPI

T2/C_PIP

URSA9

North.AM.

CN/HK

MAIN Clock(24Mhz)

CN/HK

BOOT MODE "0 : EMMC "1 : TEST MODE



T2/C

North.AM

T2/C/S2

ISDB

Jtag I/F For Main

T2/C/S2/AT

10

I2C for tuner

11

To surround amp

For connecting SIC debug tool

BIT3

URSA7/URSA9PBIT5

Default

JP

BIT4

local dimming

ATSC

INSTANT_MODE0

NVRAM

T2/C

D9

T/C

URSA7/URSA9

OP MODE[1:0] "00" : Normal Mode "01/10/11" : Internal Test mode

Non_U14

interface

T2/C_PIP

JP

Reserved

KR

T/C

ATV_SOC

LCD

AJJA

I2C PULL UP

T2/C/S2/ATV_EXT

01

Low

Non_D9

Low

System Clock for Analog block(24Mhz)

Clock for LG1154D

Not Used Net (UB85/95/UC89)

U14

20131016 version

D13 SPI

00

High

BR

I2C port

INSTANT boot MODE "1 : Instant boot "0 : normal

(internal pull down)

AC-coupling CAP

Not Used Net (Only OLED)

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

C311

0.1uF

OPT

L228

BLM18PG121SN1D

C218 0.1uF

22uFC299

MDS62110209

M200

GASKET_8.0X6.0X8.5H

SMD_GASKET_8.5T

+3.3V_NORMAL

+1.2V_VDD

VDD25_LTX

4.7uFC214

L207

BLM18PG121SN1D

4.7uFC241

VDDC15_M0

C314

0.1uF

OPT

+1.2V_VDD

C300 0.1uF

C381 0.1uF

C304

0.1uF

OPT

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

VDD33_1

E11

VDD33_2

F5

VDD33_3

F6

VDD33_4

F11

VDD33_5

G5

VDD33_6

H13

VDD33_7

J13

VDD33_8

P12

VDD33_9

P13

VDD33_10

R5

VDD33_11

R6

VDD33_XTAL

N16

AVDD33_CVBS_1

T13

AVDD33_CVBS_2

T14

VDD25_CVBS_1

N10

VDD25_CVBS_2

N11

VDD25_VSB_1

N12

VDD25_VSB_2

N13

VDD25_REF

U5

VDD25_COMP_1

N7

VDD25_COMP_2

N8

VDD25_COMP_3

N9

VDD25_APLL

F14

VDD25_AUD_1

M6

VDD25_AUD_2

N6

VDD25_AAD

M13

LTX_LVDD_1

F15

LTX_LVDD_2

F16

SDRAM_VDDQ_1

H15

SDRAM_VDDQ_2

J15

SDRAM_VDDQ_3

J16

SDRAM_VDDQ_4

K15

SDRAM_VDDQ_5

K16

VDD10_XTAL

R18

VDDC10_1

G7

VDDC10_2

G8

VDDC10_3

G9

VDDC10_4

H7

VDDC10_5

H12

VDDC10_6

J7

VDDC10_7

J12

VDDC10_8

K7

VDDC10_9

K12

VDDC10_10

L7

VDDC10_11

L12

VDDC10_12

M7

VDDC10_13

M12

AVDD10_CVBS

T17

AVDD10_VSB

T18

AVDD10_LLPLL

M8

DVDD10_APLL_1

G10

DVDD10_APLL_2

G11

LTX_VDD

G12

VSS25_REF

V5

GND_1

C3

GND_2

D3

GND_3

D4

GND_4

D17

GND_5

E4

GND_6

F4

GND_7

F7

GND_8

F8

GND_9

F9

GND_10

F10

GND_11

F12

GND_12

F13

GND_13

F17

GND_14

F18

GND_15

G4

GND_16

G6

GND_17

G13

GND_18

G14

GND_19

G15

GND_20

G16

GND_21

G17

GND_22

G18

GND_23

H4

GND_24

H5

GND_25

H6

GND_26

H8

GND_27

H9

GND_28

H10

GND_29

H11

GND_30

H14

GND_31

J4

GND_32

J5

GND_33

J6

GND_34

J8

GND_35

J9

GND_36

J10

GND_37

J11

GND_38

J14

GND_39

K4

GND_40

K5

GND_41

K6

GND_42

K8

GND_43

K9

GND_44

K10

GND_45

K11

GND_46

K13

GND_47

K14

GND_48

L1

GND_49

L2

GND_50

L3

GND_51

L4

GND_52

L5

GND_53

L6

GND_54

L8

GND_55

L9

GND_56

L10

GND_57

L11

GND_58

L13

GND_59

L14

GND_60

L15

GND_61

L16

GND_62

L17

GND_63

L18

GND_64

M1

GND_65

M2

GND_66

M3

GND_67

M4

GND_68

M5

GND_69

M9

GND_70

M10

GND_71

M11

GND_72

M14

GND_73

M15

GND_74

M16

GND_75

N4

GND_76

N5

GND_77

N14

GND_78

N15

GND_79

N17

GND_80

P4

GND_81

P5

GND_82

P6

GND_83

P7

GND_84

P8

GND_85

P9

GND_86

P10

GND_87

P11

GND_88

P14

GND_89

P15

GND_90

P16

GND_91

R4

GND_92

R7

GND_93

R8

GND_94

R9

GND_95

R10

GND_96

R11

GND_97

R12

GND_98

R13

GND_99

R14

GND_100

R15

GND_101

R16

GND_102

R17

GND_103

T4

GND_104

T7

GND_105

T8

GND_106

T9

GND_107

T10

GND_108

T11

GND_109

T12

GND_110

T15

GND_111

T16

GND_112

U4

GND_113

U6

GND_114

U18

GND_115

V4

GND_116

V16

C350

0.1uF

C302

0.1uF

VDD25_XTAL

+2.5V_Normal

C307

0.1uF

JP203

C354

0.1uF

AVDD33_CVBS

C357

0.1uF

L222 BLM18PG121SN1D

4.7uFC211

R201

1K 1%

VDD12_VTXPHY

VDD10_XTAL

+2.5V_Normal

VDDC10

C359

0.1uF

L211 BLM18PG121SN1D

L200 BLM18PG121SN1D

VDD33

AVDD33_XTAL

4.7uF

C200

C363

0.1uF

C251 0.1uF

VREF_M1_0

VREF_M0_1

R303

1K 1%

C366

0.1uF

C274 0.1uF

4.7uFC297

VDD25_REF

L230

BLM18PG121SN1D

R300

1K 1%

4.7uFC378

C305

0.1uF

OPT

VSS25_REF

VDDC12_XTAL

+1.0V_VDD

4.7uFC255

4.7uF

C202

L227 BLM18PG121SN1D

VDDC15_M1VDDC15_M0

L206 BLM18PG121SN1D

C312

0.1uF

OPT

AVDD33

C308

0.1uF

MDS62110217

M200-*1

GASKET_8.0X6.0X12.5H

SMD_GASKET_12.5T

C288

0.1uF

VSS25_REF

C352

0.1uF

IC101-*1

LG1154AN_H13A_ISDB-T (LG1154AN-IT)

H13A_BRAZIL

XIN_SUB

P17

XO_SUB

P18

VSB_AUX_XIN

J17

XTAL_BYPASS

N18

CLK_24M

D18

XTAL_SEL0

M18

XTAL_SEL1

M17

PORES_N

E3

OPM0

K3

OPM1

K2

H13A_SCL

A8

H13A_SDA

B8

CVBS_IN3

U13

CVBS_IN2

V14

CVBS_IN1

V15

CVBS_VCM

V13

BUF_OUT1

U15

BUF_OUT2

U14

REFT

U7

REFB

V6

ADC1_COM

V7

ADC2_COM

U10

ADC3_COM

V12

SC1_SID

T5

SC1_FB

T6

PB1_IN

U8

Y1_IN

V8

SOY1_IN

V9

PR1_IN

U9

PB2_IN

V10

Y2_IN

U11

SOY2_IN

V11

PR2_IN

U12

AAD_ADC_SIF

H18

AAD_ADC_SIFM

H17

AUDA_VBG_EXT

P2

AUDA_OUTL

N1

AUDA_OUTR

N2

AUD_SCART_OUTL

N3

AUD_SCART_OUTR

P1

AUAD_L_CH4_IN

P3

AUAD_R_CH4_IN

R1

AUAD_L_CH3_IN

R2

AUAD_R_CH3_IN

T1

AUAD_L_CH2_IN

U2

AUAD_R_CH2_IN

U3

AUAD_L_CH1_IN

V2

AUAD_R_CH1_IN

V3

AUAD_R_REF

U1

AUAD_M_REF

T3

AUAD_L_REF

T2

AUAD_REF_PO

R3

ANTCON

K17

RFAGC

K18

IFAGC

J18

ADC_I_INCOM

U16

ADC_I_INP

U17

ADC_I_INN

V17

GPIO0

F3

GPIO1

F2

GPIO2

F1

GPIO3

G3

GPIO4

G2

GPIO5

G1

GPIO6

H3

GPIO7

H2

GPIO8

H1

GPIO9

J3

GPIO10

E18

GPIO11

E17

GPIO12

H16

GPIO13

J2

GPIO14

J1

GPIO15

K1

VDDC12_XTAL

VREF_M1_1

IC100

LG1154D_H13D

GND_1

A27

GND_2

B5

GND_3

C5

GND_4

C26

GND_5

C27

GND_6

D5

GND_7

D26

GND_8

E5

GND_9

E6

GND_10

E7

GND_11

E8

GND_12

E22

GND_13

E23

GND_14

E26

GND_15

F7

GND_16

F8

GND_17

F22

GND_18

F23

GND_19

F24

GND_20

F25

GND_21

F26

GND_22

F27

GND_23

F31

GND_24

G7

GND_25

G8

GND_26

G9

GND_27

G10

GND_28

G11

GND_29

G12

GND_30

G13

GND_31

G14

GND_32

G15

GND_33

G16

GND_34

G17

GND_35

G18

GND_36

G19

GND_37

G20

GND_38

G21

GND_39

G22

GND_40

G23

GND_41

G24

GND_42

G25

GND_43

G26

GND_44

G27

GND_45

G28

GND_46

G29

GND_47

G30

GND_48

G31

GND_49

H9

GND_50

H26

GND_51

H27

GND_52

H28

GND_53

H29

GND_54

H30

GND_55

H31

GND_56

J7

GND_57

J30

GND_58

J31

GND_59

K7

GND_60

K30

GND_61

K31

GND_62

L30

GND_63

L31

GND_64

M7

GND_65

M12

GND_66

M13

GND_67

M14

GND_68

M15

GND_69

M16

GND_70

M17

GND_71

M18

GND_72

M19

GND_73

M20

GND_74

M24

GND_75

M25

GND_76

M26

GND_77

M30

GND_78

M32

GND_79

M33

GND_80

M34

GND_81

N12

GND_82

N13

GND_83

N14

GND_84

N15

GND_85

N16

GND_86

N17

GND_87

N18

GND_88

N19

GND_89

N20

GND_90

N24

GND_91

N30

GND_92

N31

GND_93

N32

GND_94

N33

GND_95

P7

GND_96

P12

GND_97

P13

GND_98

P14

GND_99

P19

GND_100

P20

GND_101

P21

GND_102

P22

GND_103

P23

GND_104

P24

GND_105

P30

GND_106

P31

GND_107

R12

GND_108

R13

GND_109

R14

GND_110

R16

GND_111

R17

GND_112

R18

GND_113

R19

GND_114

R20

GND_115

R21

GND_116

R22

GND_117

R23

GND_118

R24

GND_119

R25

GND_120

R26

GND_121

R30

GND_122

R34

GND_123

T7

GND_124

T12

GND_125

T13

GND_126

T14

GND_127

T16

GND_128

T17

GND_129

T18

GND_130

T19

GND_131

T20

GND_132

T21

GND_133

T25

GND_134

T26

GND_135

T30

GND_136

T31

GND_137

T34

GND_138

U7

GND_139

U12

GND_140

U13

GND_141

U14

GND_142

U16

GND_143

U17

GND_144

U18

GND_145

U19

GND_146

U20

GND_147

U21

GND_148

U25

GND_149

U26

GND_150

U30

GND_151

U31

GND_152

V7

GND_153

V12

GND_154

V13

GND_155

V14

GND_156

V16

GND_157

V17

GND_158

V18

GND_159

V19

GND_160

V20

GND_161

V21

GND_162

V25

GND_163

V26

GND_164

V30

GND_165

V31

GND_166

W5

GND_167

W6

GND_168

W7

GND_169

W12

GND_170

W13

GND_171

W14

GND_172

W15

GND_173

W16

GND_174

W17

GND_175

W18

GND_176

W19

GND_177

W20

GND_178

W21

GND_179

W25

GND_180

W26

GND_181

W30

GND_182

W31

GND_183

Y3

GND_184

Y4

GND_185

Y5

GND_186

Y8

GND_187

Y12

GND_188

Y13

GND_189

Y14

GND_190

Y15

GND_191

Y16

GND_192

Y17

GND_193

Y18

GND_194

Y19

GND_195

Y20

GND_196

Y21

GND_197

Y22

GND_198

Y23

GND_199

Y24

GND_200

Y25

GND_201

Y26

GND_202

Y31

GND_203

Y35

GND_204

AA8

GND_205

AA12

GND_206

AA13

GND_207

AA14

GND_208

AA16

GND_209

AA17

GND_210

AA18

GND_211

AA19

GND_212

AA20

GND_213

AA21

GND_214

AA22

GND_215

AA23

GND_216

AA24

GND_217

AA25

GND_218

AA26

GND_219

AA31

GND_220

AB6

GND_221

AB8

GND_222

AB12

GND_223

AB13

GND_224

AB16

GND_225

AB17

GND_226

AB18

GND_227

AB19

GND_228

AB20

GND_229

AB21

GND_230

AB22

GND_231

AB23

GND_232

AB25

GND_233

AB26

GND_234

AB30

GND_235

AB31

GND_236

AC8

GND_237

AC12

GND_238

AC13

GND_239

AC16

GND_240

AC17

GND_241

AC18

GND_242

AC19

GND_243

AC20

GND_244

AC21

GND_245

AC22

GND_246

AC23

GND_247

AC25

GND_248

AC30

GND_249

AC31

GND_250

AD8

GND_251

AD12

GND_252

AD13

GND_253

AD19

GND_254

AD20

GND_255

AD25

GND_256

AD31

GND_257

AE12

GND_258

AE13

GND_259

AE15

GND_260

AE16

GND_261

AE17

GND_262

AE18

GND_263

AE19

GND_264

AE20

GND_265

AE21

GND_266

AE22

GND_267

AE24

GND_268

AE25

GND_269

AE26

GND_270

AE31

GND_271

AF12

GND_272

AF13

GND_273

AF15

GND_274

AF16

GND_275

AF17

GND_276

AF18

GND_277

AF19

GND_278

AF20

GND_279

AF21

GND_280

AF22

GND_281

AF24

GND_282

AF31

GND_283

AG8

GND_284

AG31

GND_285

AH8

GND_286

AH31

GND_287

AJ8

GND_288

AJ30

GND_289

AK8

GND_290

AK9

GND_291

AK10

GND_292

AK14

GND_293

AK15

GND_294

AK16

GND_295

AK17

GND_296

AK18

GND_297

AK19

GND_298

AK20

GND_299

AK21

GND_300

AK22

GND_301

AK23

GND_302

AK26

GND_303

AK27

GND_304

AK28

GND_305

AK29

GND_306

AK30

GND_307

AK31

GND_308

AL8

GND_309

AL12

GND_310

AL13

GND_311

AL14

GND_312

AL15

GND_313

AL16

GND_314

AL17

GND_315

AL18

GND_316

AL19

GND_317

AL20

GND_318

AL21

GND_319

AL22

GND_320

AL23

GND_321

AL24

GND_322

AL25

GND_323

AL26

GND_324

AL27

GND_325

AL28

GND_326

AL29

GND_327

AL30

GND_328

AL31

GND_329

AM8

GND_330

AM13

GND_331

AM14

GND_332

AM15

GND_333

AM16

GND_334

AM17

GND_335

AM18

GND_336

AM19

GND_337

AM20

GND_338

AM21

GND_339

AM22

GND_340

AM23

GND_341

AM24

GND_342

AM25

GND_343

AM26

GND_344

AM27

GND_345

AM28

GND_346

AM29

GND_347

AM30

GND_348

AM31

GND_349

AN6

GND_350

AN12

GND_351

AN13

GND_352

AN15

GND_353

AN16

GND_354

AN17

GND_355

AN18

GND_356

AN19

GND_357

AN20

GND_358

AN21

GND_359

AN22

GND_360

AN23

GND_361

AN24

GND_362

AN25

GND_363

AN26

GND_364

AN27

GND_365

AN28

GND_366

AN29

GND_367

AN30

GND_368

AN31

VDD25_AUD

AVDD33_XTAL

C203 0.1uF

C355

0.1uF

VREF_M1_1

C223 0.1uF

JP202

L220

BLM18PG121SN1D

C296

0.1uF

OPT

VDD25_REF

C362

0.1uF

4.7uFC351

22uF

C303

L234 BLM18PG121SN1D

AVDD33

C361

0.1uF

+1.0V_VDD

L216 BLM18PG121SN1D

C370

0.1uF R203

1K 1%

4.7uFC364

C368 0.1uF

VDDC10

+3.3V_NORMAL

AVDD25

C369

0.1uF

L209

BLM18PG121SN1D

4.7uFC216

4.7uFC270 L226

BLM15BD121SN1

+3.3V_NORMAL

C372

0.1uF

+3.3V_NORMAL

C283 0.1uF

VDD25_LTX

VDD25_LVDS

VDDC12_XTAL

VDDC15_M1

R202

1K 1%

C309

0.1uF

OPT

C207 0.1uF

OPT

R301

1K 1%

+2.5V_Normal

VDDC15_M0

VDD25_LTX

+1.2V_VDD

C313

0.1uF

OPT

VDD10_XTAL

JP204

VDD25_AUD

C206 0.1uF

L201 BLM18PG121SN1D

4.7uFC205

C353

0.1uF

+1.5V_DDR

VREF_M0_0

4.7uFC275

L238 BLM18PG121SN1D

+2.5V_Normal

VDDC15_M0

AVDD25

C356

0.1uF

R302

1K 1%

VDD10_XTAL

VREF_M0_1

C259 0.1uF

C360

0.1uF

L203 BLM18PG121SN1D

C204 0.1uF

+1.2V_VDD

VREF_M0_0

C344

0.1uF

OPT

VDD12_VTXPHY

VDD25_XTAL

C358

0.1uF

+1.5V_DDR

4.7uFC242

+2.5V_Normal

4.7uFC279

+1.2V_VDD

C246 0.1uF

VDD25_LVDS

C367

0.1uF

VDD33

L225

BLM15BD121SN1

VDDC15_M1

C310

0.1uF

OPT

4.7uFC298

JP205

VREF_M1_0

AVDD33_CVBS

C306

0.1uF

C365

0.1uF

VDDC15_M1

4.7uFC201

IC100

LG1154D_H13D

M0_DDR_VREF1

A24

M0_DDR_VREF2

A4

M1_DDR_VREF1

A2

M1_DDR_VREF2

Y1

XTAL_VDD

P26

XTAL_VDDP

N26

VDD33_1

M21

VDD33_2

Y30

VDD33_3

AA30

VDD33_4

AE8

VDD33_5

AF8

VDD33_6

AK13

VDD33_7

AK24

VDD33_8

AK25

AVDD33_USB_1

M22

AVDD33_USB_2

M23

AVDD33_BT_USB_1

AK11

AVDD33_BT_USB_2

AK12

AVDD33_HDMI_1

AF25

AVDD33_HDMI_2

AF26

SP_VQPS

R31

VDD25_LVRX_1

AE23

VDD25_LVRX_2

AF23

VTXPHY_VDD25_1

AE14

VTXPHY_VDD25_2

AF14

VDD25_DR3PLL

N25

GPLL_AVDD25

AD26

VDD15_M0_1

H10

VDD15_M0_2

H11

VDD15_M0_3

H12

VDD15_M0_4

H13

VDD15_M0_5

H14

VDD15_M0_6

H15

VDD15_M0_7

H16

VDD15_M0_8

H17

VDD15_M0_9

H18

VDD15_M0_10

H19

VDD15_M0_11

H20

VDD15_M0_12

H21

VDD15_M0_13

H22

VDD15_M0_14

H23

VDD15_M0_15

H24

VDD15_M0_16

H25

VDD15_M1_1

H7

VDD15_M1_2

H8

VDD15_M1_3

J8

VDD15_M1_4

K8

VDD15_M1_5

L7

VDD15_M1_6

L8

VDD15_M1_7

M8

VDD15_M1_8

N7

VDD15_M1_9

N8

VDD15_M1_10

P8

VDD15_M1_11

R7

VDD15_M1_12

R8

VDD15_M1_13

T8

VDD15_M1_14

U8

VDD15_M1_15

V8

VDD15_M1_16

W8

VDDC11_1

N21

VDDC11_2

N22

VDDC11_3

N23

VDDC11_4

P15

VDDC11_5

P16

VDDC11_6

P17

VDDC11_7

P18

VDDC11_8

R15

VDDC11_9

T15

VDDC11_10

T22

VDDC11_11

T23

VDDC11_12

T24

VDDC11_13

U15

VDDC11_14

U22

VDDC11_15

U23

VDDC11_16

U24

VDDC11_17

V15

VDDC11_18

V22

VDDC11_19

V23

VDDC11_20

V24

VDDC11_21

W22

VDDC11_22

W23

VDDC11_23

W24

VDDC11_24

AB15

VDDC11_25

AB24

VDDC11_26

AC15

VDDC11_27

AC24

VDDC11_28

AD15

VDDC11_29

AD16

VDDC11_30

AD17

VDDC11_31

AD18

VDDC11_32

AD21

VDDC11_33

AD22

VDDC11_34

AD23

VDDC11_35

AD24

VTXPHY_VDD11_1

AB14

VTXPHY_VDD11_2

AC14

VTXPHY_VDD11_3

AD14

AVDD11_DR3PLL

P25

AVDD11_DCO

AA15

GPLL_VDD11

AC26

C371

0.1uF

4.7uFC239

R200

1K 1%

VDD25_XTAL

C301 0.1uF

C208 0.1uF

C209 0.1uF

C213 0.1uF

C210 0.1uF

C212 0.1uF

C215 0.1uF

C217 0.1uF

C219 0.1uF

4.7uFC222

1uFC224

MAIN POWER

BSD-14Y-UD-003-HD

2013-12-17

+1.5V_Bypass Cap

(1)

(4)

LG1154A

+1.24V_Bypass Cap

+1.0V_Bypass Cap

(2)

1005 size bead Bottom side of chip

+0.75V

+3.3V

+2.5V_Bypass Cap

+1.5V

+1.1V

LG1154D

GND JIG POINT

SMD TOP for EMI

+2.5V_Bypass Cap

LG1154A

(1)

(2)

AFE 3CH Power

+2.5V

+3.3V_Bypass Cap

Place at the bottom side

Bottom side of chip

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

FE_DEMOD1_TS_DATA[5]

TPI_DATA[2]

TPO_DATA[2]

TPO_DATA[7]

TPO_DATA[5]

FE_DEMOD1_TS_DATA[6]

FE_DEMOD1_TS_DATA[1]

TPI_DATA[5]

FE_DEMOD1_TS_DATA[4]

TPO_DATA[0]

TPI_DATA[4]

FE_DEMOD1_TS_DATA[3]

TPI_DATA[1]

FE_DEMOD1_TS_DATA[2]

TPO_DATA[1]

TPI_DATA[3]

TPO_DATA[4]

TPI_DATA[7]

TPO_DATA[6]

TPI_DATA[6]

FE_DEMOD1_TS_DATA[7]

TPO_DATA[3]

TPI_DATA[0]

R436

2.7K

EU

L/DIM0_VS

R433

100

R435

10K

EU

OPM[1]

C404

0.01uF 50V

D401

5.5V

+3.3V_NORMAL

COMP2_PR_IN_SOC

C441 0.047uF

BIT1

PWM1

ADC_I_INN

C457 1000pF

OPT

R4061K

1/16W

1%

SCART_FB_BUFFER

TXA2P/TX9P

SC_ID

BPL_IN

R458

47K

1%

SC_CVBS_IN_SOC

AUD_LRCH1

10uFC452

DTV/MNT_V_OUT_SOC

FE_DEMOD2_TS_CLK

R437 10K 1%

TXD2N/TX15N

FE_DEMOD2_TS_DATA

R465

390

1/16W

1%

R449 68

R487-*1

10K

TU_W_BR/TW/CO

TXD4P/TX12P

R497 100

C437

0.01uF

C460 0.01uF

EU

C405 150pF 50V

COMP1/AV1/DVI_L_IN

C415

0.1uF

COMP2_PR_IN_SOC

SCART_AMP_R_FB

PWM1

TXD1N/TX16N

PWM2

AUAD_L_REF

L409

EU

1uH

C4494.7uF

SCART_Rout_SOC

TXC2N/TX21N

R413

75

1%

R482

10K

OPT

C427

12pF

R6450

100

TXA0N/TX11N

C411 10pF 50V OPT

C428 1000pF

XOUT_SUB

D404

5.5V

R442

22K

EU

TXD0P/TX17P

C433 4.7uF

FE_DEMOD1_TS_DATA[1-7]

OPM[1]

R480100

EU

IF_N

BIT8

TXC0N/TX23N

SC_R_IN

R451 330

R426

22K

EU

AUAD_REF_PO

D13_STPO_ERR

TXC4N/TX18N

C451 0.1uF

XTAL_SEL[0]

SCART_AMP_L_FB

+3.3V_NORMAL

R412

75 1%

EU

FE_DEMOD2_TS_VAL

SC_ID_SOC

TXA3P/TX7P

REFB

R481

10K

OPT

TPO_CLK

IC100

LG1154D_H13D

INTR_GBB

AT16

INTR_AFE3CH

AU17

INTR_AGPIO

AT17

AUD_FS20CLK

AT24

AUD_FS21CLK

AU24

AUD_FS23CLK

AT23

AUD_FS24CLK

AU23

AUD_FS25CLK

AT22

AUD_HDMI_MCLK

AU36

AUD_DAC1_LRCK

AT20

AUD_DAC1_SCK

AU20

AUD_DAC1_LRCH

AT19

AUD_DAC0_LRCK

AU19

AUD_DAC0_SCK

AT18

AUD_DAC0_LRCH

AU18

AUD_ADC_LRCK

AU22

AUD_ADC_SCK

AT21

AUD_ADC_LRCH

AU21

BB_SCL

AT25

BB_SDA

AU25

BB_TPI_CLK

AP23

BB_TPI_ERR

AR23

BB_TPI_SOP

AP22

BB_TPI_VAL

AR22

BB_TPI_DATA7

AP21

BB_TPI_DATA6

AR21

BB_TPI_DATA5

AP20

BB_TPI_DATA4

AR20

BB_TPI_DATA3

AP19

BB_TPI_DATA2

AR19

BB_TPI_DATA1

AP18

BB_TPI_DATA0

AR18

CLK_54M

AU28

CVBS_GC2

AR24

CVBS_GC1

AU27

CVBS_GC0

AT27

CVBS_UP

AP24

CVBS_DN

AR25

FS00CLK

AU29

H13A_AUDCLK_OUT

AT29

DAC_START

AP27

DAC_DATA4

AR27

DAC_DATA3

AP26

DAC_DATA2

AR26

DAC_DATA1

AP25

DAC_DATA0

AT28

AAD_GC4

AR30

AAD_GC3

AP29

AAD_GC2

AR29

AAD_GC1

AP28

AAD_GC0

AR28

AAD_DATA9

AP35

AAD_DATA8

AR35

AAD_DATA7

AP34

AAD_DATA6

AR34

AAD_DATA5

AP33

AAD_DATA4

AR33

AAD_DATA3

AP32

AAD_DATA2

AR32

AAD_DATA1

AP31

AAD_DATA0

AR31

AAD_DATAEN

AP30

ADCO_OUT_CLK

AT36

HSR_AP

AT30

HSR_AM

AU30

HSR_BP

AT31

HSR_BM

AU31

HSR_CP

AT32

HSR_CM

AU32

HSR_CLKP

AT33

HSR_CLKM

AU33

HSR_DP

AT34

HSR_DM

AU34

HSR_EP

AT35

HSR_EM

AU35

AUD_HPDRV_LRCH

AT14

AUD_HPDRV_LRCK

AT15

AUD_HPDRV_SCK

AU15

FRC_LR_O_SYNC_FLAG

AC7

L_VSOUT_LD

AN5

DIM0_SCLK

AR14

DIM0_MOSI

AP14

DIM1_SCLK

AN14

DIM1_MOSI

AP13

PWM0

AF6

PWM1

AF7

PWM2

AD7

PWM_IN

AE6

EPI_EO

AP5

EPI_VST

AN8

EPI_DPM

AP8

EPI_MCLK

AR7

EPI_GCLK

AN7

STPI0_CLK/GPIO47

AK35

STPI0_SOP/GPIO46

AK36

STPI0_VAL/GPIO45

AK37

STPI0_ERR/GPIO44

AJ35

STPI0_DATA/GPIO43

AJ36

STPI1_CLK/GPIO42

AH35

STPI1_SOP/GPIO41

AH37

STPI1_VAL/GPIO40

AH36

STPI1_ERR/GPIO55

AG35

STPI1_DATA/GPIO54

AG36

TP_DVB_CLK

AM36

TP_DVB_SOP

AL36

TP_DVB_VAL

AL35

TP_DVB_ERR

AL37

TP_DVB_DATA0

AM35

TP_DVB_DATA1

AN36

TP_DVB_DATA2

AN37

TP_DVB_DATA3

AN35

TP_DVB_DATA4

AP37

TP_DVB_DATA5

AP36

TP_DVB_DATA6

AR37

TP_DVB_DATA7

AR36

TPI_CLK

A28

TPI_SOP

B29

TPI_VAL

B28

TPI_ERR

C28

TPI_DATA0

B32

TPI_DATA1

C31

TPI_DATA2

B31

TPI_DATA3

A31

TPI_DATA4

C30

TPI_DATA5

A30

TPI_DATA6

B30

TPI_DATA7

C29

TPIO_CLK/GPIO53

D30

TPIO_SOP/GPIO52

D31

TPIO_VAL/GPIO51

F30

TPIO_ERR/GPIO50

E31

TPIO_DATA0/GPIO58

E30

TPIO_DATA1/GPIO59

F29

TPIO_DATA2/GPIO60

E29

TPIO_DATA3/GPIO61

F28

TPIO_DATA4/GPIO62

E28

TPIO_DATA5/GPIO63

D28

TPIO_DATA6/GPIO48

E27

TPIO_DATA7/GPIO49

D27

AUDCLK_OUT

AD5

DACLRCH

AD6

DACSLRCH/GPIO127

Y6

PCMI3SCK/GPIO112

Y7

DACSCK

AC6

DACLRCK

AC5

PCMI3LRCK/GPIO113

AA6

PCMI3LRCH

AB7

DACCLFCH/GPIO126

AB5

IEC958OUT

AU14

DACSUBMCLK

AA32

DACSUBLRCH

AA34

DACSUBSCK

AA33

DACSUBLRCK

AB34

TEST1

AE32

TEST2

AE33

TX0N

AT6

TX0P

AU6

TX1N

AT5

TX1P

AU5

TX2N

AT4

TX2P

AU4

TX3N

AU3

TX3P

AU2

TX4N

AT2

TX4P

AT1

TX5N

AR4

TX5P

AR3

TX6N

AP1

TX6P

AP2

TX7N

AP4

TX7P

AP3

TX8N

AN4

TX8P

AN3

TX9N

AM4

TX9P

AM3

TX10N

AL4

TX10P

AL3

TX11N

AK1

TX11P

AK2

TX12N

AK4

TX12P

AK3

TX13N

AJ4

TX13P

AJ3

TX14N

AH4

TX14P

AH3

TX15N

AG4

TX15P

AG3

TX16N

AF1

TX16P

AF2

TX17N

AF4

TX17P

AF3

TX18N

AE4

TX18P

AE3

TX19N

AD4

TX19P

AD3

TX20N

AC4

TX20P

AC3

TX21N

AB1

TX21P

AB2

TX22N

AB4

TX22P

AB3

TX23N

AA4

TX23P

AA3

TX_LOCKN

AR5

R402 33

R45647K 1%

BIT3

R439 10K 1%

TXA3N/TX7N

TXB3P/TX1P

XTAL_SEL[1]

AUAD_R_CH2_IN

C459

0.1uF

TU_W_BR/TW/CO

R409

100K

EU

ADC_I_INP

L/DIM0_SCLK

R404

100K

EU

R495 100

R444

51

NON_TU_W_BR/TW

R448 68

R492 330

HP_ROUT_MAIN

TXB1P/TX4P

R423 100

SCART_FB_DIRECT

SC_G

AUD_MASTER_CLK

R4641K1/16W

1%

R440 10K 1%

TXB3N/TX1N

COMP2_Y_IN_SOC

R436-*1

0

NON_EU

R462

100

TPI_VAL

URSA_RESET_SoC

TXB2N/TX3N

FE_DEMOD1_TS_SYNC

R441

1M

+3.3V_NORMAL

C444

0.1uF

HP_ROUT

R484

10K

OPT

SCART_Lout

L407

DAC_START_PULLDOWN

C426

12pF D13_STPO_SOP

IF_P

AUAD_R_CH3_IN

C453 2.2uF

DAC_START_PULLDOWN

C420 0.047uF

R452 100

R498 100

AV1_CVBS_IN

TXC1P/TX22P

SC_FB

C414

0.1uF

EU

C409

0.22uF 10V

HP_OUT

FE_DEMOD1_TS_DATA[0]

PWM_DIM

SCART_Rout_SOC

SC_CVBS_IN_SOY

COMP2_Y_IN_SOC

SC_FB_BUF

TPI_DATA[0-7]

SC_FB_SOC

COMP1_Pr

R401 470

1/16W 5%

SCART_FB_BUFFER

C430

10pF

50V

AUAD_R_REF

TXC1N/TX22N

XIN_SUB

Q400

MMBT3904(NXP)

SCART_FB_BUFFER

E

B

C

R455

51K

1%

C450 0.1uF

BIT5 BIT6

AUDA_OUTL

AUDA_OUTR

R496 100

TPI_SOP

COMP1_Y

TXD0N/TX17N

BIT2

R420 27K

1%

R419 27K

1%

COMP1/AV1/DVI_R_IN

+2.5V_Normal

TXC3N/TX19N

R427

33

L408

1uH

PWM_DIM2

TP400

COMP2_PB_IN_SOC

L/DIM0_SCLK

COMP2_Y_IN_SOC_SOY

FE_DEMOD1_TS_ERROR

TU_CVBS_SOC

C474

10pF

50V

OPT

REFT

TXD2P/TX15P

R453 330

L406

OPT

C400

0.01uF OPT

OPM[0]

C473

10pF

50V

OPT

R438 10K 1%

R447 68

HP_LOUT_MAIN

TXA0P/TX11P

REFB

TXC0P/TX23P

C424 0.047uF

SOC_RESET

R418 27K

1%

TXA4P/TX6P

C438

0.01uF

SC_L_IN

X400

24MHz

4

GND_2

1

X-TAL_12GND_1

3

X-TAL_2

AUD_LRCH

C6006

1uF25V

EU

TXACLKN/TX8N

FE_DEMOD2_TS_SYNC

C470

10pF

50V

R446

4.7K

SCART_FB_BUFFER

R407 330

TXB0N/TX5N

TXA1P/TX10P

R421 27K

1%

AUDA_OUTR

SCART_Lout_SOC

BIT7

C419 0.047uF

TXC2P/TX21P

R444-*1

220

TU_W_BR/TW

TPO_DATA[0-7]

R6005

10K

EU

AR403 33 1/16W

AUAD_REF_PO

R45421/10W

5%

OPT

D406

5.5V

C458 0.01uF

EU

TXB2P/TX3P

TXD3N/TX13N

C407

0.22uF 10V

HP_OUT

AUD_LRCK

C462 150pF

EU

COMP2_Y_IN_SOC_SOY

R417

75

1%

BIT4

AUAD_L_CH3_IN

R6451

100

10uF

C455

+12V

L401

BLM18PG121SN1D

HP_OUT

R487

0

NON_TU_W_BR/TW/CO

R483

10K

OPT

XIN_SUB

TXBCLKP/TX2P

COMP1_Pb

AUAD_M_REF

D13_STPO_DATA

SC_CVBS_IN_SOY

C429 1000pF

AUAD_L_CH3_IN

C443 0.047uF

AUAD_R_REF

L400

BLM18PG121SN1D

HP_OUT

L/DIM0_MOSI

AUD_LRCH1

TPO_ERR

COMP1_Y_IN_SOC

R431

33

TXB1N/TX4N

SC_FB_BUF

BIT0

TPI_ERR

PWM2

HP_LOUT

TXA2N/TX9N

BPL_IN

C423 0.047uF

COMP1_Y_IN_SOC_SOY

R459

100

COMP1_PB_IN_SOC

AR402 33 1/16W

NON_OLED

SC_ID_SOC

H13A_SCL

SPDIF_OUT

C431

10pF

50V

TPI_ERR

C402 150pF 50V

OPT

R415

75 1%

COMP2_PB_IN_SOC

AR404

33

R450

68

FE_DEMOD2_TS_ERROR

TXDCLKN/TX14N

R6006

10K

EU

AV1_CVBS_IN_SOC

TPO_ERR

C456

4.7uF 10V

TXD1P/TX16P

R411 75 1% 3216

HP_LOUT_AMP

AUAD_R_CH2_IN

C406

2.2uF 10V

EU

AUDA_OUTL

TXCCLKP/TX20P

+3.3V_NORMAL

C436-*1 100pF

TU_W_BR/TW

C436 22pF

NON_TU_W_BR/TW

C448

4.7uF 10V

OPT

COMP1_PB_IN_SOC

C412

0.1uF

EU

SCART_Lout_SOC

D13_STPO_VAL

TXA1N/TX10N

TPI_CLK

TU_CVBS

R414

75 1%

EU

C445

0.1uF

R408

100K

EU

SC_FB_SOC

BIT9

C434 4.7uF

XTAL_SEL[0]

TXD3P/TX13P

R460

100

AUAD_R_CH3_IN

SC_B

C435 4.7uF

COMP1_PR_IN_SOC

R422

75

SCART_FB_DIRECT

AUAD_L_CH2_IN

TXC3P/TX19P

C440 0.047uF

IF_AGC

C401

0.01uF OPT

R443

51

NON_TU_W_BR/TW

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

XIN_SUB

P17

XO_SUB

P18

VSB_AUX_XIN

J17

XTAL_BYPASS

N18

CLK_24M

D18

XTAL_SEL0

M18

XTAL_SEL1

M17

PORES_N

E3

OPM0

K3

OPM1

K2

H13A_SCL

A8

H13A_SDA

B8

CVBS_IN3

U13

CVBS_IN2

V14

CVBS_IN1

V15

CVBS_VCM

V13

BUF_OUT1

U15

BUF_OUT2

U14

REFT

U7

REFB

V6

ADC1_COM

V7

ADC2_COM

U10

ADC3_COM

V12

SC1_SID

T5

SC1_FB

T6

PB1_IN

U8

Y1_IN

V8

SOY1_IN

V9

PR1_IN

U9

PB2_IN

V10

Y2_IN

U11

SOY2_IN

V11

PR2_IN

U12

AAD_ADC_SIF

H18

AAD_ADC_SIFM

H17

AUDA_VBG_EXT

P2

AUDA_OUTL

N1

AUDA_OUTR

N2

AUD_SCART_OUTL

N3

AUD_SCART_OUTR

P1

AUAD_L_CH4_IN

P3

AUAD_R_CH4_IN

R1

AUAD_L_CH3_IN

R2

AUAD_R_CH3_IN

T1

AUAD_L_CH2_IN

U2

AUAD_R_CH2_IN

U3

AUAD_L_CH1_IN

V2

AUAD_R_CH1_IN

V3

AUAD_R_REF

U1

AUAD_M_REF

T3

AUAD_L_REF

T2

AUAD_REF_PO

R3

ANTCON

K17

RFAGC

K18

IFAGC

J18

ADC_I_INCOM

U16

ADC_I_INP

U17

ADC_I_INN

V17

GPIO0

F3

GPIO1

F2

GPIO2

F1

GPIO3

G3

GPIO4

G2

GPIO5

G1

GPIO6

H3

GPIO7

H2

GPIO8

H1

GPIO9

J3

GPIO10

E18

GPIO11

E17

GPIO12

H16

GPIO13

J2

GPIO14

J1

GPIO15

K1

C6001

1uF25V

EU

AUD_SCK

TPO_VAL

ADC_I_INN

C454 0.1uF

SC_FB

TXA4N/TX6N

C439 100pF 50V

OPT

R410 75 1% 3216

COMP1_Y_IN_SOC

FE_DEMOD1_TS_VAL

IC400

NJM2561BF1

EU

3

VSAG

2

VOUT

4

VIN

1

POWER_SAVE

6

V+

5

GND

C432 4.7uF

C472

10pF

50V

OPT

HP_ROUT_AMP

R479100

EU

TXCCLKN/TX20N

R430

22K

OPT

C408 150pF 50V

EU

TXD4N/TX12N

AUAD_L_CH2_IN

R403

100K

EU

R467 82

1/16W1%

D403

5.5V

TXDCLKP/TX14P

SC_CVBS_IN_SOC

C403

2.2uF 10V

EU

TXB4N/TX0N

C421 0.047uF

L/DIM0_VS

XTAL_SEL[1]

R445

22K

OPT

TXACLKP/TX8P

R461

100

R443-*1

220

TU_W_BR/TW

XOUT_SUB

D13_STPO_CLK

R422-*1

0

NON_EU

TP402

TXB0P/TX5P

AUAD_L_REF

BIT10

C410 150pF

H13A_SDA

IC101

LG1154AN_H13A

H13A_NON_BRAZIL

INTR_GBB

E1

INTR_AFE3CH

E2

INTR_AGPIO

D1

AUD_FS20CLK

A6

AUD_FS21CLK

B6

AUD_FS23CLK

A5

AUD_FS24CLK

B5

AUD_FS25CLK

A4

AUDCLK_OUT_SUB

C4

AUD_HDMI_MCLK

C18

AUD_DAC1_LRCK

A2

AUD_DAC1_SCK

B2

AUD_DAC1_LRCH

B1

AUD_DAC0_LRCK

C2

AUD_DAC0_SCK

C1

AUD_DAC0_LRCH

D2

AUD_ADC_LRCK

B4

AUD_ADC_SCK

A3

AUD_ADC_LRCH

B3

BB_SCL

A7

BB_SDA

B7

BB_TP_CLK

E8

BB_TP_ERR

D8

BB_TP_SOP

C8

BB_TP_VAL

E7

BB_TP_DATA7

D7

BB_TP_DATA6

C7

BB_TP_DATA5

E6

BB_TP_DATA4

D6

BB_TP_DATA3

C6

BB_TP_DATA2

E5

BB_TP_DATA1

D5

BB_TP_DATA0

C5

CLK_F54M

B10

CVBS_GC2

C9

CVBS_GC1

B9

CVBS_GC0

A9

CVBS_UP

D9

CVBS_DN

E9

FS00CLK

B11

AUDCLK_OUT

A11

DAC_START

D11

DAC_DATA4

C11

DAC_DATA3

E10

DAC_DATA2

D10

DAC_DATA1

C10

DAC_DATA0

A10

AAD_GC4

D13

AAD_GC3

C13

AAD_GC2

E12

AAD_GC1

D12

AAD_GC0

C12

AAD_DATA9

C17

AAD_DATA8

E16

AAD_DATA7

D16

AAD_DATA6

C16

AAD_DATA5

E15

AAD_DATA4

D15

AAD_DATA3

C15

AAD_DATA2

E14

AAD_DATA1

D14

AAD_DATA0

C14

AAD_DATAEN

E13

ADCO_OUT_CLK

B18

HSR_AP0

A12

HSR_AM0

B12

HSR_BP0

A13

HSR_BM0

B13

HSR_CP0

A14

HSR_CM0

B14

HSR_CLKP0

A15

HSR_CLKM0

B15

HSR_DP0

A16

HSR_DM0

B16

HSR_EP0

A17

HSR_EM0

B17

OPM[0]

C417 0.047uF

DTV/MNT_V_OUT_SOC

TXBCLKN/TX2N

REFT

COMP1_Y_IN_SOC_SOY

R466821/16W

1%

L/DIM0_MOSI

CLK_54M_VTT

SC_CVBS_IN

C442 0.047uF

ADC_I_INP

C418 0.047uF

R432

100

R457

51K

1%

C446

0.1uF

DTV/MNT_V_OUT

TXB4P/TX0P

C422 0.047uF

SC_R

TPO_SOP

SCART_Rout

C425 0.047uF

AV1_CVBS_IN_SOC

COMP1_PR_IN_SOC

CLK_54M_VTT

TU_CVBS_SOC

FE_DEMOD1_TS_CLK

+3.3V_NORMAL

R434

100

AUAD_M_REF

TU_SIF

TXC4P/TX18P

C447

1uF 25V

OPT

R416

75 1%

EU

R424

33

R405

33

R400

33

R425

33

MAIN AUDIO/VIDEO

2013-12-17

BSD-14Y-UD-004-HD

OP MODE[0:1] : SW[2:1] 00 => Normal Operaiton Mode /T32 Debug Mode 01 => Internal Test Purpose 10 => Internal Test Purpose 11 => Internal Test Purpose

XTAL SEL[1:0] : SW[4:3] 00 => Xtal Input 01 => CLK 24M from H13D 10 => XTAL Bypass from H13D

AUDIO IN

OP MODE Setting & Select XTAL Input

Near Place Scart AMP

LG1154D

Placed as close as possible to SOC

AFE 3CH REF Setting

LG1154A

Place JACK Side

FOR EMI

Placed as close as possible to IC4300

MAIN Clock(24Mhz)

Placed as close as possible to IC100

Placed as close as possible to IC4300

To ADC

Clock for H13A

Tuner IF Filter

NC

Place at JACK SIDE

DIMMING

I2S_I/F

Place SOC Side

To front, woofer, center amp FOR UB98/UB9

To height amp FOR UB98/UB9

Not Used Net (UB85/95/UC89)

Must be used

Close to LG1154A

Close to IC4300

LGE Internal Use Only

THERMAL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

M1_DDR_DQ16

M0_DDR_A14

M1_DDR_A2

C511 22uF

10V

M0_U_CLKN

M1_DDR_BA1

M1_DDR_DM1

R559

240 1%

M0_DDR_A1

M1_DDR_DM3

M0_DDR_A8

VDDC15_M0

M0_U_CLKN

M0_DDR_DQ1

M0_DDR_ODT

M1_DDR_DQ10

M0_U_CLK

M1_DDR_DQ5

M0_DDR_A11

M1_DDR_DQ27

M1_DDR_DQ17

M0_DDR_RASN

M0_DDR_WEN

M0_DDR_CASN

AR10 56

M0_DDR_DQ12

M0_DDR_CKE

M1_DDR_DQS2

M0_DDR_A12

M0_DDR_A15

M0_DDR_DQ17

M1_DDR_DM0

M0_DDR_DQ26

M0_U_CLK

C521

0.1uF 16V

M0_DDR_DQ3

M0_DDR_A1

VDDC15_M1

M1_DDR_DQ13

M0_DDR_DQ23

R532

1K 1%

R538

1K 1%

M1_DDR_A5

M1_DDR_A6

M1_DDR_DQ19

M0_DDR_A13

C550

0.1uF

C513

0.1uF

M1_DDR_A13

AR12 56

M1_DDR_DQ26

R552

1K 1%

M0_D_CLK

M0_DDR_A13

M0_DDR_DQ19

M0_DDR_DQ5

+3.3V_NORMAL

M1_DDR_BA2

M1_DDR_DM1

M0_DDR_DQ27

H5TQ4G83AFR-PBC

IC500

A0

K3

A1

L7

A2

L3

A3

K2

A4

L8

A5

L2

A6

M8

A7

M2

A8

N8

A9

M3

A10/AP

H7

A11

M7

A12/BC

K7

A13

N3

BA0

J2

BA1

K8

BA2

J3

CK

F7

CK

G7

CKE

G9

CS

H2

ODT

G1

RAS

F3

CAS

G3

WE

H3

RESET

N2

DQS

C3

DQS

D3

DM/TDQS

B7

NF/TDQS

A7

DQ0

B3

DQ1

C7

DQ2

C2

DQ3

C8

DQ4

E3

DQ5

E8

DQ6

D2

DQ7

E7

NC_1

A3

NC_2

F1

NC_3

F9

NC_4

H1

NC_5

H9

A15

J7

VREFCA

J8

VREFDQ

E1

ZQ

H8

VDD_1

A2

VDD_2

A9

VDD_3

D7

VDD_4

G2

VDD_5

G8

VDD_6

K1

VDD_7

K9

VDD_8

M1

VDD_9

M9

VDDQ_1

B9

VDDQ_2

C1

VDDQ_3

E2

VDDQ_4

E9

VSS_1

A1

VSS_2

A8

VSS_3

B1

VSS_4

D8

VSS_5

F2

VSS_6

F8

VSS_7

J1

VSS_8

J9

VSS_9

L1

VSS_10

L9

VSS_11

N1

VSS_12

N9

VSSQ_1

B2

VSSQ_2

B8

VSSQ_3

C9

VSSQ_4

D1

VSSQ_5

D9

A14

N7

M0_DDR_DQS_N1

M1_DDR_A8

M0_D_CLK

VDDC15_M0

C568

0.1uF

C559

0.1uF

M1_DDR_BA2

M0_DDR_A11

M1_DDR_DQ11

M1_DDR_A12

VDDC15_M1

M0_1_DDR_VREFCA

M1_DDR_DQ12

M0_DDR_DM3

M0_DDR_A14

M0_DDR_DQ13

M0_D_CLKN

C501

0.1uF

M0_DDR_DQ6

IC100

LG1154D_H13D

M0_DDR_A[0]

F15

M0_DDR_A[1]

F13

M0_DDR_A[2]

F17

M0_DDR_A[3]

F19

M0_DDR_A[4]

E10

M0_DDR_A[5]

E18

M0_DDR_A[6]

E11

M0_DDR_A[7]

F18

M0_DDR_A[8]

F11

M0_DDR_A[9]

F16

M0_DDR_A[10]

E9

M0_DDR_A[11]

E12

M0_DDR_A[12]

E13

M0_DDR_A[13]

E16

M0_DDR_A[14]

F12

M0_DDR_A[15]

F14

M0_DDR_BA[0]

E19

M0_DDR_BA[1]

F10

M0_DDR_BA[2]

E15

M0_DDR_U_CLK

B10

M0_DDR_U_CLKN

A10

M0_DDR_D_CLK

A19

M0_DDR_D_CLKN

B19

M0_DDR_CKE

E14

M0_DDR_ODT

F21

M0_DDR_RASN

E21

M0_DDR_CASN

E20

M0_DDR_WEN

F20

M0_DDR_RESET_N

E17

M0_DDR_ZQCAL

F9

M0_DDR_DQS[0]

B20

M0_DDR_DQS_N[0]

A20

M0_DDR_DQS[1]

C19

M0_DDR_DQS_N[1]

D19

M0_DDR_DQS[2]

A11

M0_DDR_DQS_N[2]

B11

M0_DDR_DQS[3]

C10

M0_DDR_DQS_N[3]

D10

M0_DDR_DM[0]

D18

M0_DDR_DM[1]

C20

M0_DDR_DM[2]

D9

M0_DDR_DM[3]

C11

M0_DDR_DQ[0]

D22

M0_DDR_DQ[1]

C15

M0_DDR_DQ[2]

C23

M0_DDR_DQ[3]

D16

M0_DDR_DQ[4]

B24

M0_DDR_DQ[5]

B15

M0_DDR_DQ[6]

D23

M0_DDR_DQ[7]

A15

M0_DDR_DQ[8]

C16

M0_DDR_DQ[9]

D21

M0_DDR_DQ[10]

D17

M0_DDR_DQ[11]

C22

M0_DDR_DQ[12]

C18

M0_DDR_DQ[13]

C21

M0_DDR_DQ[14]

C17

M0_DDR_DQ[15]

D20

M0_DDR_DQ[16]

C13

M0_DDR_DQ[17]

D7

M0_DDR_DQ[18]

D13

M0_DDR_DQ[19]

C6

M0_DDR_DQ[20]

D14

M0_DDR_DQ[21]

D6

M0_DDR_DQ[22]

C14

M0_DDR_DQ[23]

A5

M0_DDR_DQ[24]

C7

M0_DDR_DQ[25]

D12

M0_DDR_DQ[26]

D8

M0_DDR_DQ[27]

B13

M0_DDR_DQ[28]

C9

M0_DDR_DQ[29]

C12

M0_DDR_DQ[30]

C8

M0_DDR_DQ[31]

D11

M0_DDR_WEN

C506 10uF

M0_DDR_DQ10

M0_DDR_A2

M1_DDR_A6

M1_DDR_A13

M1_DDR_A4

M0_DDR_DQ5

M1_DDR_DQ1

H5TQ4G63AFR-PBC

IC503-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_DDR_DQ14

M1_DDR_CKE

M0_DDR_BA0

M0_DDR_DQS2

M0_DDR_RESET_N

M1_DDR_RESET_N

R512

1K 1%

M1_DDR_DQ28

M0_DDR_DQ0

M1_DDR_A3

M0_DDR_A10

C510

1000pF

M1_DDR_A5

M0_DDR_VREFCA_T

M1_DDR_VREFDQ

M1_DDR_WEN

M1_DDR_DQ8

M1_DDR_DQ10

M0_D_CLK

M0_U_CLK

M0_DDR_A6

R537

1K 1%

M1_DDR_DQ25

M0_DDR_A11

R519

200

M1_1_DDR_VREFCA

M1_DDR_BA0

M0_DDR_DQ9

M0_DDR_VREFCA

M0_DDR_BA2

M0_DDR_DQ22

M0_DDR_BA1

M1_DDR_A8

M1_DDR_DQ24

R511

1K 1%

M0_DDR_CASN

VDDC15_M1

M0_DDR_A13

C561

0.1uF

M0_DDR_A0

M0_DDR_A5

M1_DDR_A5

M0_DDR_BA0

M1_DDR_A14

M1_U_CLKN

M1_DDR_WEN

M0_DDR_DQS1

M0_DDR_CASN

R546 10K

1%

M1_DDR_BA1

M0_DDR_DQS_N1

M0_DDR_A11

R500

240

1%

M0_DDR_DQ31

M1_DDR_A0

M1_DDR_DQS_N1

M1_DDR_DQ30

M1_DDR_DQS1

M0_DDR_RASN

VDDC15_M0

M0_DDR_A4

M0_DDR_CKE

M0_DDR_A12

M0_DDR_DQ2

M0_DDR_DQ8

M1_DDR_CASN

M1_DDR_BA2

VDDC15_M1

M0_DDR_DQS_N3

R545

240

R555

1K 1%

M1_DDR_DQ20

M1_DDR_A1

M0_DDR_A7

R516

1K 1%

M0_DDR_A0

M1_DDR_DQ6

M1_DDR_BA1

M0_DDR_A12

M0_U_CLKN

M1_DDR_A3

C500

0.1uF

M0_DDR_DQS_N0

R556

1K 1%

R543

240

M0_DDR_CKE

M1_DDR_A3

M0_DDR_DQ26

M0_DDR_A15

M1_DDR_A12

M1_DDR_RASN

VDDC15_M0

M1_DDR_RESET_N

M1_DDR_DM2

M1_DDR_A0

C505

0.1uF

M1_DDR_RESET_N

R561

240 1%

M1_DDR_DQ7

M1_DDR_DQ29

M0_DDR_BA2

M0_DDR_A4

M1_DDR_A7

R3104 56

VDDC15_M0

R557

1K 1%

M1_DDR_DQS1

K4B4G1646B-HCK0

IC503

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_DDR_DQ17

AR11 56

M1_DDR_A15

M1_DDR_DQ6

M1_U_CLK

M0_DDR_BA0

R520 10K

M1_DDR_DQ29

M1_D_CLK

M1_DDR_A11

M1_DDR_A4

C572

0.1uF

R558

240 1%

M1_DDR_A7

M0_DDR_DM1

C514

0.1uF

L500

UBW2012-121F

M0_DDR_DQ18

R518

100

C515 4700pF

M0_DDR_BA2

M0_D_CLK

M0_DDR_DQ7

M0_DDR_A7

AR7 56

C583

0.1uF

M0_DDR_A14

R521 10K

M0_D_CLKN

M0_DDR_BA2

M0_DDR_BA0

C530

0.1uF

C569

0.1uF

M0_DDR_A12

C504

0.1uF

M0_DDR_A3

M0_DDR_A15

H5TQ4G63AFR-PBC

IC501-*1

DDR_HYNIX

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M1_D_CLK

M1_DDR_DQ12

R560

240 1%

M1_DDR_DQS2

M0_DDR_DM0

M1_DDR_DQS3

M1_DDR_DQS0

M1_DDR_A6

M1_DDR_DQ30

M0_DDR_A0

M1_DDR_A11

M1_DDR_DQ3

M0_DDR_WEN

M0_D_CLKN

M1_DDR_BA0

M1_DDR_A8

M1_DDR_DQ18

R535

200

M0_DDR_DM2

M0_DDR_DQ16

M0_DDR_A1

VDDC15_M0

M1_U_CLK

M0_DDR_A6

VDDC15_M0

IC506

TPS51200DRCR

3

VO

2

VLDOIN

4

PGND

1

REFIN

5

VOSNS6REFOUT

7

EN

8

GND

9

PGOOD

10

VIN

11

[EP]

M0_DDR_A2

M0_DDR_DQS0

M0_DDR_BA1

M0_DDR_DQS2

M0_DDR_ODT

M1_DDR_DQS_N3

M0_DDR_ODT

R539

1K 1%

C522

0.1uF 16V

M1_DDR_DQ22

M0_DDR_A15

M0_1_DDR_VREFDQ_T

M0_DDR_A11

M1_DDR_DQS_N2

M0_DDR_A3

M0_DDR_DQ1

M1_DDR_A14

M0_DDR_DQS0

M0_DDR_DQ29

M1_DDR_DQ15

M0_DDR_DQS_N2

M0_DDR_DQ17

M1_DDR_DQ8

M1_DDR_DQ14

M0_DDR_DQ14

M1_DDR_DQ4

M0_DDR_A3

M1_DDR_A10

M1_DDR_A9

R513

1K 1%

M1_DDR_DM0

M0_DDR_A9

M0_DDR_CKE

M1_D_CLK

M1_DDR_DQ21

C503 10uF

M0_DDR_DQ30

K4B4G1646B-HCK0

IC501

DDR_SAMSUNG

A0

N3

A1

P7

A2

P3

A3

N2

A4

P8

A5

P2

A6

R8

A7

R2

A8

T8

A9

R3

A10/AP

L7

A11

R7

A12/BC

N7

A13

T3

A15

M7

BA0

M2

BA1

N8

BA2

M3

CK

J7

CK

K7

CKE

K9

CS

L2

ODT

K1

RAS

J3

CAS

K3

WE

L3

RESET

T2

DQSL

F3

DQSL

G3

DQSU

C7

DQSU

B7

DML

E7

DMU

D3

DQL0

E3

DQL1

F7

DQL2

F2

DQL3

F8

DQL4

H3

DQL5

H8

DQL6

G2

DQL7

H7

DQU0

D7

DQU1

C3

DQU2

C8

DQU3

C2

DQU4

A7

DQU5

A2

DQU6

B8

DQU7

A3

VREFCA

M8

VREFDQ

H1

ZQ

L8

VDD_1

B2

VDD_2

D9

VDD_3

G7

VDD_4

K2

VDD_5

K8

VDD_6

N1

VDD_7

N9

VDD_8

R1

VDD_9

R9

VDDQ_1

A1

VDDQ_2

A8

VDDQ_3

C1

VDDQ_4

C9

VDDQ_5

D2

VDDQ_6

E9

VDDQ_7

F1

VDDQ_8

H2

VDDQ_9

H9

NC_1

J1

NC_2

J9

NC_3

L1

NC_4

L9

A14

T7

VSS_1

A9

VSS_2

B3

VSS_3

E1

VSS_4

G8

VSS_5

J2

VSS_6

J8

VSS_7

M1

VSS_8

M9

VSS_9

P1

VSS_10

P9

VSS_11

T1

VSS_12

T9

VSSQ_1

B1

VSSQ_2

B9

VSSQ_3

D1

VSSQ_4

D8

VSSQ_5

E2

VSSQ_6

E8

VSSQ_7

F9

VSSQ_8

G1

VSSQ_9

G9

M0_DDR_DQ28

M1_DDR_A14

M1_DDR_VREFDQ

M1_DDR_CASN

M0_DDR_A5

M1_DDR_DQ9

M1_DDR_ODT

VDDC15_M0

M1_DDR_DQ15

M0_DDR_DQS3

M0_1_DDR_VREFDQ_T

M0_DDR_RESET_N

M1_DDR_DQ5

M0_DDR_DM0

M1_DDR_DQ1

M1_D_CLKN

M1_DDR_DM2

M1_DDR_CKE

R581

200

M0_DDR_A2

M0_DDR_DQ6

M0_D_CLKN

H5TQ4G83AFR-PBC

IC502

A0

K3

A1

L7

A2

L3

A3

K2

A4

L8

A5

L2

A6

M8

A7

M2

A8

N8

A9

M3

A10/AP

H7

A11

M7

A12/BC

K7

A13

N3

BA0

J2

BA1

K8

BA2

J3

CK

F7

CK

G7

CKE

G9

CS

H2

ODT

G1

RAS

F3

CAS

G3

WE

H3

RESET

N2

DQS

C3

DQS

D3

DM/TDQS

B7

NF/TDQS

A7

DQ0

B3

DQ1

C7

DQ2

C2

DQ3

C8

DQ4

E3

DQ5

E8

DQ6

D2

DQ7

E7

NC_1

A3

NC_2

F1

NC_3

F9

NC_4

H1

NC_5

H9

A15

J7

VREFCA

J8

VREFDQ

E1

ZQ

H8

VDD_1

A2

VDD_2

A9

VDD_3

D7

VDD_4

G2

VDD_5

G8

VDD_6

K1

VDD_7

K9

VDD_8

M1

VDD_9

M9

VDDQ_1

B9

VDDQ_2

C1

VDDQ_3

E2

VDDQ_4

E9

VSS_1

A1

VSS_2

A8

VSS_3

B1

VSS_4

D8

VSS_5

F2

VSS_6

F8

VSS_7

J1

VSS_8

J9

VSS_9

L1

VSS_10

L9

VSS_11

N1

VSS_12

N9

VSSQ_1

B2

VSSQ_2

B8

VSSQ_3

C9

VSSQ_4

D1

VSSQ_5

D9

A14

N7

R550

1K 1%

M1_DDR_DQS_N0

M1_U_CLKN

M0_DDR_A13

IC100

LG1154D_H13D

M1_DDR_A[0]

N6

M1_DDR_A[1]

R6

M1_DDR_A[2]

L6

M1_DDR_A[3]

J6

M1_DDR_A[4]

U5

M1_DDR_A[5]

J5

M1_DDR_A[6]

T5

M1_DDR_A[7]

K6

M1_DDR_A[8]

U6

M1_DDR_A[9]

M6

M1_DDR_A[10]

V5

M1_DDR_A[11]

R5

M1_DDR_A[12]

P5

M1_DDR_A[13]

L5

M1_DDR_A[14]

T6

M1_DDR_A[15]

P6

M1_DDR_BA[0]

H5

M1_DDR_BA[1]

V6

M1_DDR_BA[2]

M5

M1_DDR_U_CLK

R2

M1_DDR_U_CLKN

R1

M1_DDR_D_CLK

F1

M1_DDR_D_CLKN

F2

M1_DDR_CKE

N5

M1_DDR_ODT

G6

M1_DDR_RASN

F5

M1_DDR_CASN

G5

M1_DDR_WEN

H6

M1_DDR_RESET_N

K5

M1_DDR_ZQCAL

F6

M1_DDR_DQS[0]

E2

M1_DDR_DQS_N[0]

E1

M1_DDR_DQS[1]

F3

M1_DDR_DQS_N[1]

F4

M1_DDR_DQS[2]

P1

M1_DDR_DQS_N[2]

P2

M1_DDR_DQS[3]

R3

M1_DDR_DQS_N[3]

R4

M1_DDR_DM[0]

G4

M1_DDR_DM[1]

E3

M1_DDR_DM[2]

T4

M1_DDR_DM[3]

P3

M1_DDR_DQ[0]

C4

M1_DDR_DQ[1]

K3

M1_DDR_DQ[2]

B3

M1_DDR_DQ[3]

J4

M1_DDR_DQ[4]

A3

M1_DDR_DQ[5]

K2

M1_DDR_DQ[6]

B4

M1_DDR_DQ[7]

K1

M1_DDR_DQ[8]

J3

M1_DDR_DQ[9]

D4

M1_DDR_DQ[10]

H4

M1_DDR_DQ[11]

C3

M1_DDR_DQ[12]

G3

M1_DDR_DQ[13]

D3

M1_DDR_DQ[14]

H3

M1_DDR_DQ[15]

E4

M1_DDR_DQ[16]

M3

M1_DDR_DQ[17]

V4

M1_DDR_DQ[18]

M4

M1_DDR_DQ[19]

W3

M1_DDR_DQ[20]

L4

M1_DDR_DQ[21]

W4

M1_DDR_DQ[22]

L3

M1_DDR_DQ[23]

Y2

M1_DDR_DQ[24]

V3

M1_DDR_DQ[25]

N4

M1_DDR_DQ[26]

U4

M1_DDR_DQ[27]

M2

M1_DDR_DQ[28]

T3

M1_DDR_DQ[29]

N3

M1_DDR_DQ[30]

U3

M1_DDR_DQ[31]

P4

M0_DDR_DQ4

M0_DDR_DQ11

M0_DDR_CASN

M1_DDR_CKE

M1_DDR_A13

M0_DDR_DQ21

M1_DDR_BA0

M0_DDR_A2

M1_DDR_RASN

M0_DDR_VREFCA

M0_DDR_A10

C553

0.1uF

M0_DDR_DQ13

M1_U_CLK

M0_U_CLK

M0_DDR_DQS_N3

M0_DDR_BA2

C529

0.1uF

M0_DDR_WEN

M1_DDR_DQ25 M1_DDR_DQ26

M1_DDR_A4

M0_DDR_A1

R549 10K

1%

M0_DDR_BA1

VDDC15_M0

M1_DDR_DQ0

M0_DDR_A9

M0_DDR_DQ24

M1_DDR_DQ2

M0_DDR_WEN

M0_DDR_VREFCA_T

M0_DDR_A8

C509

0.1uF

M1_U_CLKN

M0_DDR_DM2

M0_DDR_DQ21

VDDC15_M0

M0_DDR_VREFDQ

M0_DDR_A10

M1_DDR_A15

M0_DDR_CASN

M1_DDR_DQ13

M0_DDR_CKE

M1_DDR_A9

VDDC15_M0

M1_DDR_DQ23

M1_DDR_DQS_N1

R534

1K 1%

M0_DDR_VREFDQ_T

M0_DDR_A8

M0_DDR_DQ31

M1_DDR_DQ28

M0_DDR_DQ4

AR8 56

M1_DDR_DQ4

M1_DDR_DQ9

M0_DDR_A10

M1_DDR_DQ24

M0_DDR_DQ14

M0_DDR_A5

R540 10K

M0_1_DDR_VREFCA

C519

0.1uF 16V

M0_DDR_DQ12

M1_DDR_CASN

M0_DDR_RESET_N

M1_DDR_DQ31

M1_DDR_A15

M1_DDR_A0

M1_DDR_DM3

M1_DDR_DQ16

M0_DDR_A4

M0_DDR_DQ20

C507 10uF

R510

1K 1%

M0_DDR_DQ8

M0_DDR_A3

C577

0.1uF

R553

1K 1%

M1_DDR_A9

M0_DDR_RESET_N

R541 10K

M1_DDR_DQ11

M0_DDR_RESET_N

AR9 56

M1_DDR_DQ19

M0_DDR_A6

M0_DDR_ODT

DDR_VTT

M1_DDR_WEN

M0_DDR_DQ0

VDDC15_M1

M0_DDR_DQ27

M1_DDR_DQ18

M1_D_CLKN

M1_DDR_VREFCA

M0_DDR_A0

R536

1K 1%

M0_1_DDR_VREFDQ

M0_DDR_DQ30

M1_D_CLKN

M0_DDR_A4

M0_DDR_A7

M0_DDR_DQ9

M0_DDR_A6

M0_DDR_DQ22

M0_DDR_RASN

M1_DDR_RASN

M1_DDR_A11

M0_DDR_DQ19

M0_DDR_DQ2

C520

0.1uF 16V

M1_DDR_DQS_N3

R531

1K 1%

M1_DDR_A7

M0_DDR_DQ10

M0_DDR_RASN

M1_DDR_DQ20

M0_DDR_A0

M0_DDR_DQ25

R515

1K 1%

M0_DDR_DQ20

M0_1_DDR_VREFCA_T

M1_1_DDR_VREFDQ

M1_DDR_A1

VDDC15_M0

M1_DDR_DQ2

M0_DDR_A15

M0_DDR_DQ7

R533

1K 1%

M0_DDR_VREFDQ_T

M0_DDR_DQ23

M0_D_CLK

M0_DDR_A14

M0_DDR_DQ15

M0_DDR_A14

M0_DDR_DQ11

VDDC15_M1

M0_DDR_BA1

C551

0.1uF

R580

200

M0_DDR_DQ3

M1_DDR_ODT

C508

0.1uF

M1_DDR_DQ23

M1_DDR_ODT

M1_DDR_DQS_N2

VDDC15_M0

M0_DDR_A6

H5TQ4G83AFR-PBC

IC504

A0

K3

A1

L7

A2

L3

A3

K2

A4

L8

A5

L2

A6

M8

A7

M2

A8

N8

A9

M3

A10/AP

H7

A11

M7

A12/BC

K7

A13

N3

BA0

J2

BA1

K8

BA2

J3

CK

F7

CK

G7

CKE

G9

CS

H2

ODT

G1

RAS

F3

CAS

G3

WE

H3

RESET

N2

DQS

C3

DQS

D3

DM/TDQS

B7

NF/TDQS

A7

DQ0

B3

DQ1

C7

DQ2

C2

DQ3

C8

DQ4

E3

DQ5

E8

DQ6

D2

DQ7

E7

NC_1

A3

NC_2

F1

NC_3

F9

NC_4

H1

NC_5

H9

A15

J7

VREFCA

J8

VREFDQ

E1

ZQ

H8

VDD_1

A2

VDD_2

A9

VDD_3

D7

VDD_4

G2

VDD_5

G8

VDD_6

K1

VDD_7

K9

VDD_8

M1

VDD_9

M9

VDDQ_1

B9

VDDQ_2

C1

VDDQ_3

E2

VDDQ_4

E9

VSS_1

A1

VSS_2

A8

VSS_3

B1

VSS_4

D8

VSS_5

F2

VSS_6

F8

VSS_7

J1

VSS_8

J9

VSS_9

L1

VSS_10

L9

VSS_11

N1

VSS_12

N9

VSSQ_1

B2

VSSQ_2

B8

VSSQ_3

C9

VSSQ_4

D1

VSSQ_5

D9

A14

N7

M1_DDR_DQS_N0

M0_DDR_BA1

M0_DDR_DQS_N2

M1_DDR_A2

M0_DDR_DQS1

M0_DDR_A13

M0_DDR_ODT

R530

100

M0_DDR_DQ29

M0_DDR_A4

C560

0.1uF

M0_DDR_A7

M0_DDR_VREFDQ

M1_DDR_CKE

M1_DDR_DQ21

M0_DDR_A10

M1_DDR_A12

M0_DDR_DQ24

R514

1K 1%

M0_U_CLKN

M0_DDR_A5

C562

0.1uF

M1_DDR_DQS3

M1_DDR_A1

M0_1_DDR_VREFCA_T

M0_D_CLKN

VDDC15_M0

C512

0.1uF

R517

1K 1%

M0_DDR_A8

M1_1_DDR_VREFDQ

M0_DDR_A9

VDDC15_M1

R554

1K 1%

M1_DDR_DQ7

M1_DDR_DQ27

M0_DDR_RASN

M0_DDR_DQS_N0

M0_DDR_A9

M1_DDR_VREFCA

M1_DDR_A10

M0_DDR_A1

L501

UBW2012-121F

M0_DDR_A5

M0_DDR_A12

M0_DDR_A7

M0_DDR_DQ28

M0_U_CLKN

M1_DDR_DQS0

C574

0.1uF

R551

1K 1%

M0_DDR_A2

M0_DDR_DM3

M1_1_DDR_VREFCA

M0_DDR_A9

M1_DDR_DQ0

M0_1_DDR_VREFDQ

DDR_VTT

M1_DDR_DQ31

M1_DDR_DQ22

M0_DDR_A3

M1_DDR_A10

M1_DDR_DQ3

M0_DDR_DQ18

M0_DDR_RESET_N

R501

240

1%

M0_DDR_DQ15

M1_DDR_RESET_N

M0_DDR_CKE

H5TQ4G83AFR-PBC

IC505

A0

K3

A1

L7

A2

L3

A3

K2

A4

L8

A5

L2

A6

M8

A7

M2

A8

N8

A9

M3

A10/AP

H7

A11

M7

A12/BC

K7

A13

N3

BA0

J2

BA1

K8

BA2

J3

CK

F7

CK

G7

CKE

G9

CS

H2

ODT

G1

RAS

F3

CAS

G3

WE

H3

RESET

N2

DQS

C3

DQS

D3

DM/TDQS

B7

NF/TDQS

A7

DQ0

B3

DQ1

C7

DQ2

C2

DQ3

C8

DQ4

E3

DQ5

E8

DQ6

D2

DQ7

E7

NC_1

A3

NC_2

F1

NC_3

F9

NC_4

H1

NC_5

H9

A15

J7

VREFCA

J8

VREFDQ

E1

ZQ

H8

VDD_1

A2

VDD_2

A9

VDD_3

D7

VDD_4

G2

VDD_5

G8

VDD_6

K1

VDD_7

K9

VDD_8

M1

VDD_9

M9

VDDQ_1

B9

VDDQ_2

C1

VDDQ_3

E2

VDDQ_4

E9

VSS_1

A1

VSS_2

A8

VSS_3

B1

VSS_4

D8

VSS_5

F2

VSS_6

F8

VSS_7

J1

VSS_8

J9

VSS_9

L1

VSS_10

L9

VSS_11

N1

VSS_12

N9

VSSQ_1

B2

VSSQ_2

B8

VSSQ_3

C9

VSSQ_4

D1

VSSQ_5

D9

A14

N7

M0_DDR_DM1

C552

0.1uF

M0_DDR_DQ16

M0_DDR_DQ25

DDR_VTT

M0_U_CLK

M0_DDR_DQS3

M1_DDR_A2

M0_DDR_A8

VDDC15_M1

C516

1uF

C502

1uF

MAIN DDR

2013-12-17

BSD-14Y-UD-005-HD

DDR3 1.5V bypass Cap - Place these caps near Memory

DDR3 4Gbit (x16)

4Gbit : T7(A14)

DDR3 1.5V bypass Cap - Place these caps near Memory

1Gbit : T7(NC_6)

DDR3 4Gbit

Real USE : 1Gbit

DDR3 4Gbit

* DDR_VTT

Close to REFOUT pin

H5TQ1G63DFR-PBC(x16)

Place at the bottom side

LGE Internal Use Only

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CI_DATA[1]

CI_DATA[7]

CI_IN_TS_DATA[4]

CI_ADDR[6]

CI_IN_TS_DATA[7]

CI_DATA[0-7]

CI_DATA[4]

CI_ADDR[7]

EB_DATA[7]

CI_IN_TS_DATA[1]

EB_DATA[6]

CI_DATA[0]

EB_DATA[5]

EB_DATA[4]

CI_ADDR[4]

EB_DATA[3]

CI_ADDR[3]

CI_ADDR[0]

EB_DATA[2]

@netLa

CI_ADDR[10]

EB_DATA[1]

CI_DATA[2]

EB_DATA[0]

CI_DATA[3]

CI_DATA[0]

CI_ADDR[9]

TPO_DATA[2]

CI_ADDR[2]

CI_ADDR[14]

TPO_DATA[6]

CI_ADDR[8]

CI_DATA[5]

CI_IN_TS_DATA[2]

TPO_DATA[5]

CI_IN_TS_DATA[0]

CI_ADDR[13]

TPO_DATA[1]

CI_ADDR[11]

CI_DATA[6]

TPO_DATA[7]

TPO_DATA[0]

CI_ADDR[5]

CI_DATA[2]

TPO_DATA[4]

CI_IN_TS_DATA[3]

CI_DATA[3]

CI_ADDR[12]

CI_DATA[6]

CI_DATA[5]

CI_ADDR[1]

TPO_DATA[3]

CI_IN_TS_DATA[5] CI_IN_TS_DATA[6]

CI_DATA[4]

CI_DATA[1]

CI_DATA[7]

CI_ADDR[11]

+5V_CI_ON

R721 33

CI

/PCM_WAIT

CAM_IREQ_N

EB_ADDR[4]

CI_IN_TS_CLK

CI_TS_CLK

AR703

100

CI

CAM_CD2_N

C700

0.1uF 16V

CI

TPI_DATA[5]

CI_ADDR[8]

CI_TS_DATA[6]

EB_ADDR[6]

/PCM_IRQA

CI_ADDR[3]

TPO_SOP

R705

10K

CI_IN_TS_DATA[5]

/PCM_WAIT

/CI_CD1

CI_ADDR[6]

CAM_REG_N

EB_ADDR[0]

EB_WE_N

C706 0.1uF

CI

CI_ADDR[2]

EB_ADDR[10]

AR713

33

CI

+5V_NORMAL

EB_ADDR[13]

CI_IN_TS_SYNC

CI_ADDR[14]

CI_TS_DATA[3]

AR701

33

CI

CI_TS_CLK

C702

0.1uF CI

EB_BE_N0

CI_ADDR[1]

CI_ADDR[5]

CI_TS_DATA[1]

/PCM_IRQA

+5V_CI_ON

EB_ADDR[5]

IC700

AP2151WG-7

CI

3

FLG

2

GND

4

EN

1

OUT

5

IN

CI_TS_DATA[7]

CI_TS_DATA[0]

/CI_CD2

CI_TS_DATA[3]

TPO_DATA[0-7]

C707

0.1uF 16V

CI

R717 100

CI

C701

0.1uF 16V

CI

TPI_VAL

CI_IN_TS_DATA[1]

/PCM_IOWR

CI_DATA[0-7]

AR710

33

CI

CAM_CD1_N

R706

10K

CI

CI_DATA[0-7]

EB_ADDR[11]

TPI_DATA[4]

AR704

100

CI

EB_ADDR[2]

TPI_CLK

CI_IN_TS_DATA[3]

CAM_WAIT_N

EB_ADDR[12]

AR705

33

CI

CI_ADDR[8]

C704 12pF 50V OPT

R702

33

CI

CI_TS_DATA[7]

/CI_CD2

CI_ADDR[10]

TPI_SOP

CI_ADDR[0]

CI_ADDR[3]

/PCM_REG

AR700

100

CI

EB_ADDR[14]

CI_ADDR[5]

C708 1uF 25V

CI

R709

10K

CI

CI_ADDR[11]

CI_TS_SYNC

CI_ADDR[7]

PCM_RESET

CI_TS_VAL

/PCM_WE

R703

10K

TPO_VAL

EB_DATA[0-7]

CI_TS_DATA[0]

CI_ADDR[6]

CI_TS_DATA[4]

CI_TS_DATA[1]

CI_IN_TS_DATA[0]

EB_BE_N1

AR707

33

CI

CI_TS_SYNC

/PCM_CE1

AR706

33

CI

AR708

33

CI

/PCM_OE

C703

4.7uF 10V CI

CI_IN_TS_DATA[4]

R723

10K

CI

CI_TS_DATA[6]

TPI_DATA[1]

/PCM_IORD

CI_IN_TS_CLK

CI_IN_TS_DATA[0-7]

AR709

33

CI

CI_ADDR[10]

CI_ADDR[13]

C709

0.1uF 50V CI

/PCM_OE

CI_ADDR[9]

CI_IN_TS_SYNC

CI_IN_TS_VAL

C705 12pF 50V

OPT

R701

33

CI

AR712

33

CI

TPI_DATA[6]

CI_ADDR[7]

TPI_DATA[2]

TPO_CLK

TPI_DATA[0]

CI_ADDR[12]

CI_ADDR[4]

CI_ADDR[2]

TPI_DATA[7]

CI_TS_DATA[4]

CI_IN_TS_DATA[6]

CI_TS_DATA[5]

R704 100

CI

CI_ADDR[14]

EB_ADDR[1]

EB_ADDR[8]

CI_TS_VAL

/PCM_IORD

CI_ADDR[4]

CI_TS_DATA[2]

CI_ADDR[12]

EB_OE_N

R716

100

CI

TPI_DATA[3]

/PCM_CE2

CI_IN_TS_DATA[2]

/PCM_WE

CI_ADDR[1]

EB_ADDR[3]

EB_ADDR[9]

+5V_NORMAL

R700 10K

CI

AR711

33

CI

CI_IN_TS_VAL

/PCM_CE2

CI_ADDR[9]

AR702

100

CI_ADDR[0]

CI_ADDR[13]

CI_TS_DATA[2]

/PCM_REG

/PCM_IOWR

CI_TS_DATA[5]

EB_ADDR[7]

PCM_5V_CTL

CI_IN_TS_DATA[7]

/CI_CD1

+5V_CI_ON

JK700

10125901-115LF

CI

G1G2

57

21

52

16

10

47

41

5

36

59

23

45

54

18

49

43

13

7

38

2

25

56

20

51

15

9

46

40

4

35

58

22

53

17

11

48

42

12

6

37

1

24

55

19

50

44

14

8

39

3

2660 2761 2862 2963 3064 31 32 33 34

65 66 67 68

69

BSD-14Y-UD-007-HD

2013-12-17

PCMCIA

CI POWER ENABLE CONTROL

LGE Internal Use Only

LG 79UB980T-TA, 79UB980T, 79UB989Y, 79UB989Y-TA Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual