LG 60PA6500-TF Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

PLASMA TV

SERVICE MANUAL

CHASSIS : PA21A

MODEL : 60PA6500 60PA6500-TF

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67444303 (1112-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION ................................................................ 6

BLOCK DIAGRAM .................................................................................. 13

EXPLODED VIEW .................................................................................. 14

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

1.5 Kohm/10W

To Instrument's
exposed
METALLIC PARTS

Good Earth Ground
such as WATER PIPE,
CONDUIT etc.

AC Volt-meter

0.15u

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental sh orts of the cir cui try that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 M
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Ω and 5.2 MΩ.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied all of the PDP TV with PA21A chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.

(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with

BOM.

(5) The receiver must be operated for about 5 minutes prior to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed
(2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

.

4. Module General Specification

- 60" 2D FHD

No Item Specication Remark

1 Display Screen Device 152 cm (60 inch) wide Color Display Module PDP

2 Aspect Ratio 16:9

3 PDP Module PDP60R4####,

RGB Closed (Well) Type, Glass Filter (38%)
Pixel Format: 1920 horiz. By 1080 ver.

4 Operating Environment 5) Temp. : 0 ~ 40 deg

6) Humidity : 20 ~ 80%

5 Storage Environment 7) Temp. : -20 ~ 60 deg

8) Humidity : 10 ~ 90 %

6 Input Voltage AC100 ~ 240V, 50/60Hz Maker LG

LGE SPEC

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model General Specification

No Item Specication Remark

1 Market Australia, New Zealand, Indonesia, Malaysia, Singa-

pore, South Africa, Israel, Iran, Vietnam, Myanmar,
Non-EU analog

2 Broadcasting system 1) PAL/SECAM BG

2) PAL/SECAM DK

3) PAL I / II

4) SECAM L/L’

5) DVB T

6) DVB C

3 Receiving system Analog : Upper Heterodyne

Digital : COFDM

4 Scart Jack (1EA) PAL, SECAM

5 Component Input

(1EA)

6 RGB Input (1EA) RGB-PC Analog (D-Sub 15Pin)

7 RS232C (1EA) SVC

8 HDMI Input (2 or 3EA) HDMI-PC

9 Audio Input (2EA) RGB/DVI Audio, Component L/R Input

10 SPDIF Out (1 EA) SPDIF Out

11 USB (1EA) for SVC, S/W Download, DivX

12 LAN only DVB-T2 models

13 PCMCI (1EA) DVB-T/C Decryption Interface, CI+

Y/Cb/Cr, Y/ Pb/Pr

HDMI-DTV

EU (PAL Market)

HDMI1/DVI, HDMI2,
HDMI3

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to PA21A chassis applied PDP TV all
models manufactured in TV factory.

2. Designation

(1) Th e ad justm ent is accord ing to the order whic h is

designated and which must be followed, according to the

plan which can be changed only on agreeing.
(2) Power adjustment : Free Voltage.
(3) Magnetic Field Condition: Nil.
(4) Input signal Unit: Product Specification Standard.
(5) Reserve after operation: Above 5 Minutes (Heat Run)

Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz

(6) Adjustment equipment s : Color Ana lyzer (CA -210 or

CA-110), DDC Adjustment Jig equipment, SVC remote

controller.
(7) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15

- In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours.

- In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

3. Main PCB check process

* APC - After Manual-Insult, executing APC

* Boot file Download

(1) Execute ISP program “Mstar ISP Utility” and then click

“Config” tab.

(2) Set as below, and then click “Auto Detect” and check “OK”

message

If “Error” is displayed, Check connection between computer,

jig, and set.

(3) Click “Read” tab, and then load download file (XXXX.bin)

by clicking “Read”

(4) Click “Connect” tab. If “Can’t ” is displayed, Check

connection between computer, jig, and set.

■ After RGB Full White in HEAT-RUN Mode, the receiver must

be operated prior to the adjustment.

■ Enter into HEAT-RUN MODE

1) Press the POWER ON KEY on R/C for adjustment.

2) OSD display and screen display PATTERN MODE.

● Set is activated HEAT run without signal generator in this

mode.

● Single color pattern ( WHITE ) of HEAT RUN MODE uses to

check panel.

● Caution : If you turn on a still screen more than 20 minutes

(Especially digital pattern, cross hatch pattern), an
after image may be occur in the black level part of
the screen.

(8) Push The “IN STOP KEY” – For memory initialization.

Case1 : Software version up

1) After downloading S/W by USB , Multi-vision set will reboot

automatically

2) Push “In-stop” key

3) Push “Power on” key

4) Function inspection

5) After function inspection, Push “In-stop” key.

Case2 : Function check at the assembly line

1) When TV set is entering on the assembly line, Push “In-

stop” ke y at rst.

2) Push “Power on” key for turning it on.

-> If you push “Power on” key, TV set will recover channel
information by itself.

3) After function inspection, Push “In-stop” key.

(5) Click “Auto” tab and set as below.
(6) Click "Run".
(7) After downloading, check "OK" message.

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* USB DOWNLOAD(*.epk file download)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is Low,

it didn’t work.

- But your downloade d version is High, USB data is

automatically detecting

(3) Show the message “Copying files from memory”

(4) Updating is staring.

(5) Updating C om pl et ed, T he Mu lt i- vi si on will restart

automatically.

(6) If your Multi-vision is turned on, check your updated

version and Tool option. (explain the Tool option, next
stage)

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote controller.

2) Select "Tool Option 1" and Push “OK” button.

3) Punch in the number. (Each of mode ls has th eir
number.)

4) Completed selecting Tool option.

50PA6500-T* 60PA6500-T*

Tool option 1 37056 49344

Tool option 2 39306 39306

Tool option 3 3697 3697

Tool option 4 54342 54342

Tool option 5 10 10

* Caution : Using ‘power on’ button of the Adjustment R/C ,

power on Multi-vision.

* ADC Calibration Protocol (RS232)

NO Enter

Adjust MODE

Item Adjust ‘Mode In’ ADC Adjust

CMD 1 A A

CMD 2 A D

Data 0 0 0

1 0

When transfer the
‘Mode In’,
Carry the command.

- Adjust Sequence

▪aa 00 00 [Enter Adjust Mode]
▪xb 00 40 [Component1 Input (480i)]
▪ad 00 10 [Adjust 480i Comp1]
▪xb 00 60 [RGB Input (1024*768)]
▪ad 00 10 [Adjust 1024*768 RGB]
▪aa 00 90 End Adjust mode

* Required equipment : Adjustment R/C.

ADC adjust

Automatically adjustment
(The use of a internal
pattern)

3.2. Function Check

3.2.1. Check display and sound

■ Check Input and Signal items. (cf. work instructions)

1) COMPONENT (480i)

2) RGB (PC : 1024 x 768 @ 60hz)

3) HDMI

4) DVI

5) PC Audio In
* Display and Sound check is executed by Remote control-

ler.

3.1. ADC Process

3.1.1. ADC

■ Enter Service Mode by pushing “ADJ” key,

■ Enter Internal ADC mode by pushing “►” key at “5. ADC

Calibration”

Only for training and service purposes

* Caution : Not to push the INSTOP KEY after completion if

the function inspection.

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Total Assembly line process

4.1. POWER PCB Assy voltage adjustment

(Vs voltage adjustment)

● Required Equipment for adjustment

- D.M.M

● Condition for adjustment

- No signal with the snow noise in RF mode

4.2. Adjustment Preparation

● Required Equipment

- Remote controller for adjustment

- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same

product : CH 11 (PDP)

* Please adjust CA-210, CA-100+ by CS-1000 before measur-

ing

- Auto W/B adjustment instrument(only for Auto adjust-

ment)

- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO

W/B EQUIPMENT.

Before Adjust of White Balance, Please press
POWER ONLY key

- Adjust Process will start by execute RS232C Command.

● Color temperature standards according to CSM and Module

CSM PLASMA

Cool 11000K

Medium 9300K

Warm 6500K

* Auto-control interface and directions

1) Adjust in the place where the inux of light like oodlight

around is blocked. (Illumination is less than 100Lux).

2) Adhere closely the Color Analyzer ( CA210 ) to the
module less than 10cm distance, keep it with the surface
of the Module and Color Analyzer’s Prove vertically.
(80~100°).

3) Aging time

- After aging start, keep the power on (no suspension of
power supply) and heat-run over 5 minutes.

- Using ‘no signal’ or ‘full white pattern’ or the others,
check the back light on.

■ Auto adjustment Map(RS-232C)

RS-232C COMMAND

[ CMD ID DATA ]

Wb 00 00 White Balance Start
Wb 00 ff White Balance End

RS-232C

COMMAND

[CMD ID DATA]

Cool Mid Warm Cool Mid Warm

R Gain jg Ja jd 00 172 192 192 192

G Gain jh Jb je 00 172 192 192 192

B Gain ji Jc jf 00 192 192 172 192

R Cut 64 64 64 128

G Cut 64 64 64 128

B Cut 64 64 64 128

M

I

N

CENTER

(DEFAULT)

M

A
X

● CS-1000/CA-100+/CA-210(CH 10) White balance adjust-

ment coordinates and color temperature.

CSM Color Coordination Temp ± Color

x y

COOL 0.276 0.283 11000K 0.002

MEDIUM 0.285 0.293 9300K 0.002

WARM 0.313 0.329 6500K 0.002

* Connecting picture of the measuring instrument (On Auto-

matic control)

- Inside PATTERN is used when W/B is controlled. Con­nect to auto controller or push Adjustment R/C POWER­ON -> Enter the mode of White-Balance, the pattern will
come out.

Coordination

* Caution

- Color Temperature : COOL, Medium, Warm.

- One of R Gain/G Gain/ B Gain should be kept on 0xC0,
and adjust other two lower than C0. (when R/G/B Gain
are all C0, it is the FULL Dynamic Range of Module)

* Manual W/B process using adjusts Remote control.

■ After enter Service Mode by pushing “ADJ” key,

■ Enter White Balance by pushing “►” key at “6. White

Balance”.

■ Stick the sensor to the center of the screen and select

each items(Red/Green/Blue Gain) using ▲/▼(CH +/-)

key on R/C.

■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.

■ Adjust three modes all(Cool/Medium/Warm) : Fix the one

of R/G/B Gain and Change the others.

■ When the adjustment is completed, Enter “COPY ALL”.

■ Exit adjustment mode using EXIT key on R/C.

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* After You nish all adjustments, Press “In-start” button and

compare Tool option and Area option value with its BOM, if it
is correctly same then unplug the AC cable.

If it is not same, then correct it same with BOM and unplug

AC cable.
For correct it to the model’s module from factory JIG model.
* Push The “IN STOP KEY” after completing the function

inspection. And Mechanical Power Switch must be set “ON”
* To check the coordinates of White Balance, you have to

measure at the below conditions.

- Picture mode : Vivid, Energy Saving : Off, Below the Ad-

vanced control, Dynamic Contrast : Off, Dynamic Colour : Off
Colour Temp.

Cool 30

Medium 0

Warm 30

-> Picture Mode change : Vivid -> Vivid(User)

4.3. DDC EDID Write (RGB 128Byte)

-> Not used any more, Use Auto D/L

■ Connect D-sub Signal Cable to D-Sub Jack.

■ Write EDID DATA to EEPROM (24C02) by using DDC2B

protocol.

■ Check whether written EDID data is correct or not.

* For SVC main Ass’y, EDID have to be downloaded to Insert

Process in advance.

4.4. DDC EDID Write (HDMI 256Byte)

-> Not used any more, Use Auto D/L

■ Connect HDMI Signal Cable to HDMI Jack.

■ Write EDID DATA to EEPROM(24C02) by using DDC2B

protocol.

■ Check whether written EDID data is correct or not.

* For SVC main Ass’y, EDID have to be downloaded to Insert

Process in advance.

4.5. EDID DATA

(1) All Data : HEXA Value
(2) Changeable Data :
* : Serial No : Controlled / Data:01
** : Month : Controlled / Data:00
*** : Year : Controlled
**** : Check sum

* Caution : Never connect HDMI & D-sub Cable when EDID

downloaded.

■ Edid data and Model option download (RS232)

- Manual Download

NO Enter

download MODE

Item download ‘Mode In’ download

CMD 1 A A

CMD 2 A E

Data 0 0 00

0 10

When transfer the

‘Mode In’,

Carry the command.

* Caution

● Use the proper signal cable for EDID Download

- Analog EDID : Pin3 exists

- Digital EDID : Pin3 exists

* Caution

- Never connect HDMI & D-sub Cable at the same time.

- Use the proper cables below for EDID Writing.

- Download HDMI1, HDMI2 separately because HDMI1 is dif­ferent from HDMI2.

For Analog EDID For HDMI EDID

D-sub to D-sub DVI-D to HDMI or HDMI to HDMI

EDID data Model

option download

Automatically download

(The use of a internal

pattern)

4.6. EDID DATA Auto Download

(1) Press Adj. key on the Adj. R/C,
(2) Select EDID D/L menu.
(3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is

failure, NG is displayed.

(5) If Download is failure, Re-try downloads.

Only for training and service purposes

No. Item Condition Hex Data

1 Manufacturer ID GSM 1E6D

2 Version Digital : 1 01

3 Revision Digital : 3 03

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* 2D HD EDID data

- 2D FHD RGB EDID data [C/S : 7C]

- 2D FHD HDMI1 EDID data [C/S : 63, 76]

- 2D FHD HDMI2 EDID data [C/S : 63, 66]

- 2D FHD HDMI3 EDID data [C/S : 63, 56]

* Vender ID

Input HEX

HDMI1 10

HDMI2 20

HDMI3 30

* Checksum: Changeable by total EDID data.

EDID C/S data 2D-FHD

HDMI RGB

check sum

(Hex)

Block 0 0x63 0x7C

Block 1 0x76(HDMI1)

0x66(HDMI2)

0x56(HDMI3)

Only for training and service purposes

EDID C/S data 2D-HD

HDMI RGB

check sum

(Hex)

Block 0 0x3F 0x58

Block 1 0xFC(HDMI1)

0xEC(HDMI2)

0xDC(HDMI3)

4.7. Checking the EYE-Q Operation.

(1) Press the EYE Key on the adjustment remote controller.
(2) Check the Sensor DATA ( It must be under 10) and keep

the data longer than 1.5s

(3) Check ‘OK’

Green Eye-Check(Factory Mode)

Sensor Data 9

Power saving mode 1

OK

(Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)
* IF you press IN-STAP Button, change Green Eye-check

OSD.

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model name & Serial number Download

5.1. Model name & Serial number D/L

■ Press “Power on” key of service remocon.(Baud rate :

115200 bps)

■ Connect RS232 Signal Cable to RS-232 Jack.

■ Write Serial number by use RS-232.

■ Must check the serial number at signal test of customer sup-

port. (Refer to below).

5.2. Signal TABLE

CMD LENGTH ADH ADL DATA_1 ... Data_n

CMD: A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
Delay : 20ms

CS DELAY

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘5.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like
photo.

4) Check the model name Instart menu -> Factory name
displayed.

5) Check the Diagnostics (DTV country only) -> Buyer
model displayed

5.3. Command Set

* Description

No. 1

Adjust mode EEPROM WRITE

CMD(hex) A0h

LENGTH(hex) 84h+n

Description n-bytes Write (n = 1~16)

FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart,
0, Phase
Data write : Model Name and Serial Number write in EEP­ROM,.

5.4. Method & Notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory
by D-book 4.0

* Manual Download (Model Name and Serial Number)
If the TV set is downloaded By OTA or Service man,

Sometimes model name or serial number is initialized.( Not
always)

6. Download CI+ Key (EU model only)

* Connect TV SET and PC which download keys Writing pro-

gram by RS232C-Cable

(1) Start “CIKeyl.exe”Program and Click (3) Button to connect

TV and PC.
(2) Click (5) to download CI+ Key.
43 When download succeed, you can see “OK” on (6)

There is impossible to download by bar code scan, so It need
Manual download.

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(3) result value

- normally status for download : OKx

- abnormally status for download : NGx

(2) ch eck the key downlo ad for transmi tted command

(RS232 : ci 00 10)

CMD1 CMD2 Data 0

C 1 1 0

(3) result value

- normally status for download : OKx

- abnormally status for download : NGx

■ Check the method of CI+ Key value (RS232)

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(2) check the mothed of CI+ key by command
(RS232 : ci 00 20)

CMD1 CMD2 Data 0

C 1 1 0

(3) result value

i 01 OK 1d1852d21c1ed5dcx

└──> CI+ Key Value

7. Download MAC Address, CI+ Key
and widevine Key.

- Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

-> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA).

8. SW Download Guide.

* Put a *.bin to USB Stick and Turn on TV

(1) Put the USB Stick to the USB socket

(2) Automatically detecting update le in USB Stick

* If your downloaded program version in USB Stick is Low,

it didn’t work.

But your downloaded version is High, USB data is auto-

matically detecting.

(3) Show the message “Copying les from memory”

(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ

Remote-control.

* IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OP-

TION MENU.

(6) When TV turn on, check the Updated version on Diagnos-

tics MENU.

* Connect TV SET and PC which download keys Writing

program by RS232C-Cable

1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
connect TV and PC.

2) Click (4) to download MAC Address.

3) Click (5) to download CI+ Key.

4) When download succeed, you can see “OK” on (6)

* Each Chassis has it’s own MAC Address. Please be careful

of download.

■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(2) ch eck the key downlo ad for transmi tted command

(RS232 : ci 00 10)

CMD1 CMD2 Data 0

C 1 1 0

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

BLOCK DIAGRAM

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

400

910

900

120

590

501

240

201

202

203

204

205

206

200

207

580

208

209

301

302

303

304

305

300

520

601

A2

LV1

A10

A9

A12

310

540

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essenti al that these sp ecial safet y parts shoul d be replac ed with the same compon ents as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Full SCART

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

EU

JK100

PSC008-02

SHIELD

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

AV_DET

COM_GND

SYNC_IN

SYNC_OUT

SYNC_GND2

SYNC_GND1

RGB_IO

R_OUT

RGB_GND

R_GND

D2B_OUT

G_OUT

D2B_IN

G_GND

ID

B_OUT

AUDIO_L_IN

B_GND

AUDIO_GND

AUDIO_L_OUT

AUDIO_R_IN

AUDIO_R_OUT

+3.3V

R106
75

R108
75

R107
75

R104
10K
EU

R105
1K
EU

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

AV/SC1_DET

R115

470K

R116

470K

EU

R113

R114
10K

EU

+5V

MULTI

B

R135

0

EU

REC_8

R136

330

R139

EU

2K

EU

Q103-*1

E

Q103

C

ISA1530AC1
EU

D112-*1
MMBD6100

C

R138

2K
EU

R137

2K
EU

C112
10uF
16V

EU

R140

2K
EU

E

C

MULTI

B

R141

220

EU

R142

390

READY

D112

C

A2

A1

C113
10uF
16V

EU

+3.3V_ST

B

MMBT3904(NXP)

EU

KDS184

A2

A1

R144

470

EU

C

B

Q104

E

EU

R143
180

EU

EU

MMBT3904(NXP)

Q107

C114
27pF

50V

EU

R145

6.8K
EU

C115
27pF

50V

EU

EU
R189
10K

E

C

SCART1_Lout

SCART1_MUTE

R146
18K

EU

R147
10K

EU

MMBT3904(NXP)

B

R149
15K
EU

R148
15K

EU

Q106

10uF

12K

R160

C116

16V

EU

EU

EU

E

C

R154

5.6K

R152

6.8K
EU

C117

0.1uF
16V

READY

DTV/MNT_VOUT

B

EU

MMBT3904(NXP)

Q105

EU

12K

R159

OUT1

IN1-

IN1+

VEE

EU

MMBT3906(NXP)

R129
0

EU

C106
100uF

16V
EU

R123

33
EU

R121
10K

EU

R124

10K

EU

C109
27pF

50V

EU

C110

1000pF

50V

READY

R126
12K

EU

R127
12K

EU

C107

5600pF

50V

EU

C108

5600pF

50V

EU

C111
220pF

50V

EU

R117

75
EU

R118

5%

75

470K

EU

EU

1/1 6W

R119

75
EU

R120

2.7K
EU

EU

C102

1000pF

50V

READY

C103

1000pF

50V

READY

SC1_SOG_IN

AV/SC1_CVBS_IN

SC1_VOUT

SC1_FB

SC1_ID

AV/SC1_L_IN

AV/SC1_R_IN

Q100

MMBT3904(NXP)

EU

MMBT3904(NXP)

R134
100
1/4W

Q101

C

E

EU

EU

DTV_R_OUT

Q102

MMBT3904(NXP)

EU

L103

120-ohm

EU

EU
1K

R158

EU

E

1K

R157

B

C

IC101

AZ4580MTR-E1

1

2

3

4

R155

P_17V

PDP GP4 LM1
EAX64280504

SC_RE1

SC_RE2

EU

7.5K
R156

EU
3K

P_17V

VCC

8

OUT2

7

IN2-

6

IN2+

5

5.6K
R153

EU

SCART1_Rout

CI SLOT

BUF2_FE_TS_DATA[0-7]

/CI_CD1

CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

CI_IORD
CI_IOWR

BUF2_FE_TS_SYN

BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]

BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]

BUF2_FE_TS_DATA[0-7]

BUF2_FE_TS_DATA[7]

PCM_RST

/PCM_WAIT

REG
CI_TS_CLK
CI_TS_VAL

CI_TS_SYNC

CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]

R150
10K
EU

+5V

/CI_CD2

+5V

R151
10K

R102

EU

100
EU

AR100 33

R100
R101

AR101 33

AR102 33

R103
100
EU

EU

33

+3.3V_CI

EU

R165

TC74LCX244FT

10K

AR105

EU

AR106 33

EU

AR107 33

IC100

1OE

1

20

EU

1A1

19

2

2Y4

18

3

1A2

17

4

2Y3

16

5

1A3

15

6

2Y2

14

7

1A4

13

8

2Y1

12

9

GND

10

11

+3.3V_CI

VCC

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

/PCM_OE
/PCM_WE
/PCM_IORD
/PCM_IOWR

PCM_A[12]
PCM_A[13]
PCM_A[14]
/PCM_REG

PCM_A[8]
PCM_A[9]CI_ADDR[9]
PCM_A[10]
PCM_A[11]

EU

C105

0.1uF
16V

CI_ADDR[0]
PCM_A[7]
CI_ADDR[1]
PCM_A[6]
CI_ADDR[2]

PCM_A[5]

CI_ADDR[3]
PCM_A[4]

BUF2_FE_TS_DATA[0-7]

AR108

33 EU

BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]

BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]
BUF2_FE_TS_DATA[7]

BUF1_FE_TS_SYN

BUF1_FE_TS_VAL_ERR

BUF1_FE_TS_CLK

CI POWER ENABLE CONTROL

PCM_5V_CTL

BUF1_FE_TS_DATA[0]

BUF1_FE_TS_DATA[1]

BUF1_FE_TS_DATA[2]

BUF1_FE_TS_DATA[3]

AR109

33 EU

BUF1_FE_TS_DATA[4]

BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

AR110

33

EU

+5V

R184
10K
READY

BUF2_FE_TS_SYN
BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

5%

1/1 6W

B

R181
10K
EU

BUF1_FE_TS_DATA[0-7]

Q114
RSR025P03
EU

S

R187
10K
EU

R188
2K
EU

C

Q113
MMBT3904(NXP)
EU

E

BUF1_FE_TS_DATA[0-7]

L100

120-ohm

EU

D

C131

0.1uF

G

16V
READY

AO3407A

D

S

G

MULTI

Q114-*1

+5V_CI_ON

C104

0.1uF
16V
EU

R198
10K
READY

3.3V_CI

+3.3V

C136

0.1uF
16V
READY

L101

120-ohm

EU

+3.3V_CI

C137

0.1uF
16V
EU

CI_OE

+5V_CI_ON

C100

C101

22uF

0.1uF

10V

16V

EU

EU

JK102

10067972-000LF

EU

35
36

R111
10K
EU

R112
0

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

2

EU

READY

R109
10K

EU

33

EU

33

EU

EU

EU

R110
0
READY

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

R128 0

18

READY

19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

1

69

AR103

33

EU

R130 33 EU

1/16W

R131 33 EU

5%

R132 100

AR104

33

EU

PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]

EU

PCM_D[0]
PCM_D[1]
PCM_D[2]

CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]

CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

PCM_D[0-7]

R133
10K
EU

/PCM_CE

CI_OE

CI_WE
/PCM_IRQA

BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

CI_ADDR[0-14]

PCM_D[0-7]

CI_WE
CI_IORD
CI_IOWR

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[8]

CI_ADDR[10]
CI_ADDR[11]

CI_DET

PCM_A[0]

CI_ADDR[7]

PCM_A[1]

CI_ADDR[6]

PCM_A[2]

CI_ADDR[5]

PCM_A[3]

CI_ADDR[4]

REG

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

SCART,CI Slot

2011-10-20

1

6

HDMI_1

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

SHIELD

20

JK200

HDMI_1

19

18

17

16

15

14

13

12

11

CK+

10

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

5V_HDMI_1

R200
1K
HDMI_1

R201

1.8K HDMI_1

HDMI_1

JK211

PPJ239-01

NON_EU

+5V

5V_DET_HDMI_1

MMBT3904(NXP)

R204

3.3K
JP201

R281

HDMI_1

R282

10K

10K
HDMI_1

JP2 02

[RD1]E-LUG

6H

[RD1]O-SPRING_2

5H

[RD1]CONTACT_2

4H

[WH1]O-SPRING

5G

[RD1]CONTACT_1

4F

[RD1]O-SPRING_1

5F

[RD1]E-LUG-S

7F

[BL1]O-SPRING

5E

[BL1]E-LUG-S

7E

Q200

HDMI_1

R207
33
HDMI_1

R208
33

C

E

HDMI_1

B

R217
10K
HDMI_1

R202
10K
HDMI_1

DDC_SDA_1

DDC_SCL_1

HDMI_ARC

CEC_REMOTE

CK-_HDMI1

CK+_HDMI1

D0-_HDMI1

D0+_HDMI1

D1-_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

HPD1

DATA2_SHIELD

DATA1_SHIELD

DATA0_SHIELD

DDC/CEC_GND

HDMI1_NON Screw

CLK_SHIELD

+5V_POWER

DATA2+

DATA2-

DATA1+

DATA1-

DATA0+

DATA0-

JK200-*1

YKF45-7058V

1

2

3

4

5

6

7

8

9

CLK+

10

11

CLK-

12

CEC

13

NC

14

SCL

15

SDA

16

17

18

HPD

19

20

SHIELD

SIDE_HDMI_1

20

JK201

BODY_SHIELD

19

18

17

16

15

14

13

12

11

CK+

10

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

5V_HDMI_2

+5V

R226
1K
SIDE_HDMI_1

R227

1.8K SIDE_HDMI_1

R286

10K

SIDE_HDMI_1

5V_DET_HDMI_2

MMBT3904(NXP)

SIDE_HDMI_1

R230

3.3K
SIDE_HDMI_1

R287
10K
SIDE_HDMI_1

SIDE_HDMI_2SIDE_HDMI_1

C

Q201

E

JP204

R231
33
SIDE_HDMI_1

R232
33
SIDE_HDMI_1

JP2 05

COMPONENT2

B

R237
10K
SIDE_HDMI_1

JK208

PPJ234-02

EU

R203
10K
SIDE_HDMI_1

DDC_SDA_2

DDC_SCL_2

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

SIDE_HDMI_2

[GN]E-LUG

6A

[GN]O-SPRING

5A

[GN]CONTACT

4A

[BL]E-LUG-S

7B

[BL]O-SPRING

5B

[RD]E-LUG-S

7C

[RD]O-SPRING_1

5C

[RD]CONTACT_1

4C

5D

[WH]O-SPRING

4E

[RD]CONTACT_2

5E

[RD]O-SPRING_2

6E

[RD]E-LUG

HPD2

JK202

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

9

8

7

6

5

4

3

2

1

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

5V_HDMI_3

SIDE_HDMI_2

R251
75

R252
75

R253
75

+5V

5V_DET_HDMI_3

R240
1K
SIDE_HDMI_2

R241

1.8K SIDE_HDMI_2

R288

R289

10K

10K
SIDE_HDMI_2

+3.3V

COMP2_Y+

COMP2_Pb+

COMP2_Pr+

R256 10K

R254

470K

R25710K

R255

470K

Q202

MMBT3904(NXP)

SIDE_HDMI_2

R244

3.3K
JP207

SIDE_HDMI_2

R245
33 SIDE_HDMI_2

R246
33

JP2 08

R259

10K

R266
1K

R265
10K

R267

R262

12K

R263

12K

C R209

B

E

SIDE_HDMI_2

COMP2_DET

AV2_DET

1K

COMP2_L_IN

COMP2_R_IN

10K
SIDE_HDMI_2

R250
10K
SIDE_HDMI_2

DDC_SDA_3

DDC_SCL_3

CEC_REMOTECEC_REMOTE

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

For CEC

HPD3

CEC_REMOTE

RS232C

JK203

SPG09-DB-009

1

6

2

7

3

8

4

9

5

10

Q204

MMBT3904(NXP)

USA

NON_RGB

R274 0

NON_RGB

R275 0

R260
56K
READY

R261
0
READY

D222
READY

+5V_ST

C

E

PC_SER_DATA

PC_SER_CLK

+3.3V_ST

R276

R228
10K

USA

D224
MMBD301LT1G
30V
READY

S

G

+3.3V_ST

R278

10K

100

R277

100

R229
100K

USA

B

R233
100K

USA

R268
100

B D

R279

10K

TX

Q203
BSS83

READY

R283 0
R284 0

R269
27K
READY

MAX3232CDR

VCC

GND

DOU T1

RIN 1

ROU T1

DIN 1

DIN2

ROUT2

CEC_REMOTE_S7

S7_TXD
S7_RXD
PM_TXD
PM_RXD

IC206

16

15

14

13

12

11

10

9

SIDE USB

3AU04S-305-ZC-(LG)

C1+

1

0.1uF

V+

2

0.1uF

C1-

3

C2+

4

C2-

5

V-

6

DOUT2

7

RIN2

8

SPDIF

+3.3V_ST

C228

16V

C225

16V

C226

0.1uF
16V

C227

0.1uF
16V

FIX_POLE

10mm

R296

10K

READY

JK204

JST1223-001

Fiber Optic

4

JK209

USB DOWN STR EAM

C229

0.1uF
16V

5%

1/16W

GND

1

2

3

5

VCC

VINPUT

1234

+5V

C219

R285

0.1uF
100

16V

C220
10pF
50V

PEN_TOUCH

+5V_ST

Capacitors on VBUSA should be
placed as closd to connector as possible.

C212

0.1uF
16V

D225

AP2337SA-7

B140A

PEN_TOUCH

VIN

3

40V

C213
10uF
10V

USB1_OCD

SIDE_USB_DM

SIDE_USB_DP

1A SPEC

IC207

1

GND

ETHERNET

JK210

XRJV-01V-0-D12-080

1

1

2

2

3

3

4

4

5

ET_NET

5

6

6

7

7

8

8

9

9

VOUT

2

SPDIF_OUT



+2.5V

C200

0.1uF
16V
ET_NET

 



R264

10K

R258
33

2F01TC1-CLM97-4F

+3.3V

D200

5.6V
ET_NET

MULTI

JK204-*1

GND

1

Fiber Optic

VCC

2

VIN

3

4

SHIELD

SWITCH ADDED

IC204

AP2191SG-13

NC

8

1

OUT_2

7

2

$0.11

OUT_1

6

3

FLG

5

4

D205

D204

5.6V

5.6V
ET_NET

ET_NET

GND

IN_1

IN_2

EN

R273
0
ET_NET

R280
0
ET_NET

D206

5.6V
ET_NET

+3.3V

R270
10K

R271
33

+5V

+5V_ST

R243

R247

0

0
READY

USB1_CTL

JK210-*1

BS-R430051

TP

ET_NET_UDE

1

1

2

2

3

3

TN

4

4

5

RP

5

6

6

7

7

8

8

RN

9

9

R291
0
ET_NET

R290
0
ET_NET

[GN1]CONTACT

4D

[GN1]O-SPRING

5D

[GN1]E-LUG

6D

[RD2]E-LUG

6N

[RD2]O-SPRING_2

5N

[RD2]CONTACT

4N

[WH2]O-SPRING

5M

[RD2]O-SPRING_1

5L

[RD2]E-LUG-S

7L

[BL2]O-SPRING

5K

[BL2]E-LUG-S

7K

[GN2]CONTACT

4J

[GN2]O-SPRING

5J

[GN2]E-LUG

6J

R235
470K

NON_EU

R238
470K

NON_EU

NON_EU

R234
10K

NON_EU

R239
10K

R236

R242

12K

12K

NON_EU

R248
10K

NON_EU

NON_EU

+3.3V

NON_EU
R249
1K

COMP1_R_IN

COMP1_L_IN

SC1_R+/COMP1_Pr+

SC1_B+/COMP1_Pb+

COMP1_DET

SC1_G+/COMP1_Y+

RGB PC

JK205

SPG09-DB-010

6

1

7

2

8

3

9

4

10

5

16

GND

11

12

13

14

15

SHILED

RED_GND
GND_2
RED
GREEN_GND
DDC_DATA
GREEN
BLUE_GND
H_SYNC
BLUE
NC
V_SYNC
GND_1
SYNC_GND
DDC_CLOCK
DDC_GND

R297

R205
33

R206
33

+5V_ST

10K

C202
10pF
50V

R298
10K

R214
75

R215
75

R216
75

R212
10

R211
10

C203
10pF
50V

DSUB_R+

RGB_DDC_SDA
DSUB_G+

DSUB_HSYNC
DSUB_B+

DSUB_VSYNC

RGB_DDC_SCL
PC_SER_DATA

PC_SER_CLK

+3.3V

R224

10K

R225

PC AUDIO

JK206

PEJ027-04

1K

DSUB_DET

E_SPRING

3

T_TERMINAL1

6A

B_TERMINAL1

7A

R_SPRING

4

T_SPRING

5

B_TERMINAL2

7B

T_TERMINAL2

6B

R218
470K

R219
470K

R220
10K

1/16W

5%

R221
10K

R222
12K

R223
12K

PC_R_IN

PC_L_IN

JK207

PEJ027-04

USA

E_SPRING

3

T_TERMINAL1

6A

B_TERMINAL1

7A

R_SPRING

4

T_SPRING

5

B_TERMINAL2

7B

T_TERMINAL2

6B

R21 0
10
USA

R213
0
NON_USA

IR

TX

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

JACK INTERFACE

2011-10-20

2

6

TUNER

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

TUNER
TDSS-G101D
TDSS-H101F
TDSH-T101F

OPT1
DVB-T/C
ATSC

DVB-T_SCA

OPT2
HNIM

HNIM
HNIM

OPT3

X
X

RF_SW

FE_TS_DATA[0-7]

FNIM

AR300

FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]

FE_TS_DATA[4]
FE_TS_DATA[5]

FE_TS_DATA[6]

FE_TS_DATA[7]

FE_TS_SYN

FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR

FE_TS_CLK

33

BUF1_FE_TS_DATA[0]

BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]

FNIM

AR301

33

BUF1_FE_TS_DATA[4]

BUF1_FE_TS_DATA[5]

BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

AR302

FNIM

33

BUF1_FE_TS_SYN

BUF1_FE_TS_CLK

BUF1_FE_TS_DATA[0-7]

+1.25V_TU

TDSN_B001F

TDSN_G201D

C300

C301

10uF

0.1uF

6.3V

16V

FNIM

FNIM

DVB_T2

28

SHIELD

TU304
TDSN-G301D

NC_1

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

+B3[2.5V]

9

NC_2

10

NC_3

11

+B4[3.3V]

12

+B5[1.23V]

13

NC_4

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

SBTVD
DVB_T2

FNIM
FNIM

SBTVD

28

SHIELD

RF_SW

TU303
TDSN_B001F

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

+B3[3.3V]

12

+B4[1.23V]

13

NC_4

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

X

Close to Tuner Pin

TU302
TDSS-G101D

DVB_T/C

1

2

3

4

5

6

7

8

9

10

11

12

SHIELD

FE_TS_SYN

FE_TS_VAL_ERR

FE_TS_CLK

FE_TS_DATA[0]

FE_TS_DATA[1]

FE_TS_DATA[2]

FE_TS_DATA[3]

FE_TS_DATA[4]

FE_TS_DATA[5]

FE_TS_DATA[6]

FE_TS_DATA[7]

NC

RESET

SCL

SDA

+3.3V

SIF

+1.8V

CVBS

IF_AGC

DIF[P]

DIF[N]

TU301
TDSS-H101F

ATSC

10

11

12

SHIELD

FE_TS_DATA[0-7]

NC

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

IF_AGC

9

DIF[P]

DIF[N]

DVB_T_SCA

12

SHIELD

TU300
TDSH-T101F

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

READY

16V

0.1uF
C306

Close to Tuner Pin

C302

0.1uF
16V

DVB_T2

HNIM
HNIM

HNIM

C303
10uF

16V

0

0

0

+3.3V_TU

0.1uF
C310

R302

R3030
R304

R305

16V

C304
68pF

50V

IF_AGC_MAIN

IF_P_MSTAR

IF_N_MSTAR

C305
68pF
50V

RF_SWITCH

16V
RF_SWITCH

R301

100

R307

R306

16V

TU_CVBS

R310
1K

C307

0.1uF

RF_SWITCH_CTL

+3.3V_TU

R311

R309

22

22

R308

2.2K

2.2K

10K

TU_SCL

TU_SDA

Close to Tuner Pin

+5V

R316

R312

4.7K

470

MMBT3906(NXP)

B

C308

0.1uF

TUNER_RESET

R317
82

E

Q301

C

C311

0.1uF
16V

+1.8V_TU

TU_SIF

+2.5V_TU

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TUNER

Tuner block

3

6

VIDEO/AUDIO

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

IC400-*1

LGE2111A-TE

C7

GPIO36

E6

GPIO37

F5

GPIO38

B6

GPIO39

E5

GPIO40

D5

GPIO41

B7

GPIO42

E7

GPIO45

F7

GPIO46

AB5

GPIO49

AB3

GPIO50

A9

GPIO51

Dvix only

F4

GPIO52

AB1

I2C_SCKM0/GPIO53

N6

I2C_SDAM0/GPIO54

AB2

GPIO73

AC2

GPIO74

GPIO196
GPIO193
GPIO194
GPIO195

DSUB_HSYNC
DSUB_VSYNC

DSUB_R+

DSUB_G+

DSUB_B+

R400

R403

10K

2.4K

SC1_ID
SC1_FB

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

SC1_SOG_IN

COMP2_Pr+

COMP2_Y+

COMP2_Pb+

TU_CVBS

AV/SC1_CVBS_IN

COMP2_Y+

DTV/MNT_VOUT

1000pF

READY

IC400-*2

LGE2111A-TE SPIL

C7

GPIO36

E6

GPIO37

F5

GPIO38

B6

GPIO39

E5

GPIO40

D5

GPIO41

B7

GPIO42

E7

GPIO45

F7

GPIO46

AB5

GPIO49

AB3

GPIO50

A9

GPIO51

USA_SPIL_MAIN IC

F4

GPIO52

AB1

I2C_SCKM0/GPIO53

N6

I2C_SDAM0/GPIO54

AB2

GPIO73

AC2

GPIO74

C400

GPIO196
GPIO193
GPIO194
GPIO195

LVA0P
LVA0N
LVA1P
LVA1N
LVA2P
LVA2N
LVA3P
LVA3N
LVA4P
LVA4N

LVB0P
LVB0N
LVB1P
LVB1N
LVB2P
LVB2N
LVB3P
LVB3N
LVB4P
LVB4N

LVACKP
LVACKN
LVBCKP
LVBCKN

LVA0P
LVA0N
LVA1P
LVA1N
LVA2P
LVA2N
LVA3P
LVA3N
LVA4P
LVA4N

LVB0P
LVB0N
LVB1P
LVB1N
LVB2P
LVB2N
LVB3P
LVB3N
LVB4P
LVB4N

LVACKP
LVACKN
LVBCKP
LVBCKN

50V

AB25
AB23
AC25
AB24
AD25
AC24
AE23
AC23
AC22
AD23

V23
U24
V25
V24
W25
W23
AA23
Y24
AA25
AA24

AE24
AD24
Y23
W24

T25
U23
T24
T23

AB25
AB23
AC25
AB24
AD25
AC24
AE23
AC23
AC22
AD23

V23
U24
V25
V24
W25
W23
AA23
Y24
AA25
AA24

AE24
AD24
Y23
W24

T25
U23
T24
T23

R404 22

R405 22
R406 33
R407 68
R408 33
R409 68
R410 33
R411 68
R412 0

R413 33
R414 68
R415
R416
R417 33
R418 68

R498 0

NON_EU

R420 33
R421 68
R422
R423
R424 33
R425 68
R426 0

R427 33
R428 33

EU

R429 33

R433 68

CK+_HDMI2
CK-_HDMI2

D0+_HDMI2

D0-_HDMI2
D1+_HDMI2
D1-_HDMI2
D2+_HDMI2
D2-_HDMI2
DDC_SDA_2
DDC_SCL_2

HPD2

SC_RE1

CK+_HDMI3
CK-_HDMI3

D0+_HDMI3
D0-_HDMI3
D1+_HDMI3
D1-_HDMI3

D2+_HDMI3

D2-_HDMI3

DDC_SDA_3
DDC_SCL_3

HPD3

CK+_HDMI1
CK-_HDMI1
D0+_HDMI1

D0-_HDMI1
D1+_HDMI1
D1-_HDMI1

D2+_HDMI1
D2-_HDMI1
DDC_SDA_1
DDC_SCL_1

HPD1

CEC_REMOTE_S7

C401 0.047uF

C402 0.047uF

C403 0.047uF

C404 0.047uF

C405 0.047uF

C406 0.047uF

C407 1000pF

C408 0.047uF

C409 0.047uF

C410

33

C411

68

C412

C413

C414 1000pF

C415 0.047uF

C416 0.047uF

C417 0.047uF

33

C418 0.047uF

68

C419 0.047uF

C420 0.047uF

C421 1000pF

C422 0.047uF

C423 0.047uF

EU

C424 0.047uF

C428 0.047uF

IC400-*3

LGE2111A-T8 SPIL

C7

GPIO36

E6

GPIO37

F5

GPIO38

B6

GPIO39

E5

GPIO40

D5

GPIO41

B7

GPIO42

E7

GPIO45

F7

GPIO46

AB5

GPIO49

AB3

GPIO50

A9

GPIO51

EU_SPIL_MAIN IC

F4

GPIO52

AB1

I2C_SCKM0/GPIO53

N6

I2C_SDAM0/GPIO54

AB2

GPIO73

AC2

GPIO74

0.047uF

0.047uF

0.047uF

0.047uF

GPIO196
GPIO193
GPIO194
GPIO195

IC400

LGE2111A-T8

J2

RXACKP

J3

RXACKN

K3

RXA0P

J1

RXA0N

K2

RXA1P

K1

RXA1N

L2

RXA2P

L3

RXA2N

T5

DDCDA_DA/GPIO24

T4

DDCDA_CK/GPIO23

V5

HOTPLUGA/GPIO19

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

R5

HOTPLUGB/GPIO20

AE9

RXCCKP

AC9

RXCCKN

AC10

RXC0P

AD9

RXC0N

AC11

RXC1P

AD10

RXC1N

AE11

RXC2P

AD11

RXC2N

AE8

DDCDC_DA/GPIO28

AD8

DDCDC_CK/GPIO27

AC8

HOTPLUGC/GPIO21

F2

RXDCKP

F3

RXDCKN

G3

RXD0P

F1

RXD0N

G2

RXD1P

G1

RXD1N

H2

RXD2P

H3

RXD2N

R6

DDCDD_DA/GPIO30

U6

DDCDD_CK/GPIO29

P5

HOTPLUGD/GPIO22

R4

CEC/GPIO5

P2

HSYNC0

R3

VSYNC0

N2

RIN0P

P3

RIN0M

N3

GIN0P

N1

GIN0M

M3

BIN0P

M2

BIN0M

M1

SOGIN0

V2

HSYNC1

V3

VSYNC1

U3

RIN1P

U2

RIN1M

T1

GIN1P

T2

GIN1M

R2

BIN1P

R1

BIN1M

T3

SOGIN1

AA2

HSYNC2

Y2

RIN2P

AA3

RIN2M

W2

GIN2P

Y3

GIN2M

V1

BIN2P

W3

BIN2M

W1

SOGIN2

AA8

CVBS0

Y4

CVBS1

W4

CVBS2

AA5

CVBS3

Y5

CVBS4

AA4

CVBS5

Y6

CVBSOUT0

AA1

CVBSOUT1

AB4

VCOM

AB25

LVA0P

AB23

LVA0N

AC25

LVA1P

AB24

LVA1N

AD25

LVA2P

AC24

LVA2N

AE23

LVA3P

AC23

LVA3N

AC22

LVA4P

AD23

LVA4N

V23

LVB0P

U24

LVB0N

V25

LVB1P

V24

LVB1N

W25

LVB2P

W23

LVB2N

AA23

LVB3P

Y24

LVB3N

AA25

LVB4P

AA24

LVB4N

AE24

LVACKP

AD24

LVACKN

Y23

LVBCKP

W24

LVBCKN

T25
U23
T24
T23

SPDIF_IN/GPIO152

SPDIF_OUT/GPIO153

I2S_IN_BCK/GPIO150

I2S_IN_SD/GPIO151
I2S_IN_WS/GPIO149

I2S_OUT_BCK/GPIO156
I2S_OUT_MCK/GPIO154

I2S_OUT_SD/GPIO157

I2S_OUT_WS/GPIO155

ET_RXD[0]/RP/GPIO60
ET_TXD[0]/TP/GPIO57

ET_RXD[1]/RN/GPIO63

ET_TXD[1]/LED1/GPIO56

ET_TX_CLK/TN/GPIO59

ET_TX_EN/GPIO58

ET_MDIO/GPIO62

ET_COL/LED0/GPIO55

IF_AGC
RF_AGC

USB0_DM
USB0_DP

USB1_DM
USB1_DP

AUOUTL0
AUOUTL2
AUOUTL3
AUOUTR0
AUOUTR2
AUOUTR3

AUVRM

AUVAG
AUVRP

EARPHONE_OUTL
EARPHONE_OUTR

ET_MDC/GPIO61

IRIN/GPIO4

HWRESET

AC4

VIFP

AD3

VIFM

AC3

IP

AE3

IM

AD4

SIFP

AC5

SIFM

R452

AD2
AE2

AE6
AD6

AD1

XIN

AC1

XOUT

D7
D6

R488 100

E3
E2

AC12
AE12

C8
D8
D9

R462 22

B10
C9
B9

C10

AB9

AUL0

AA11

AUR0

Y9

AUL1

AA9

AUR1

AA7

AUL2

AB8

AUR2

Y8

AUL3

Y10

AUR3

AC7

AUL4

AD7

AUR4

W6
V6
V4
Y7
W5
U5

AD5

AE5
AC6

AA6
AB6

C6
C5

A6
C4

B5
C3
A3
B3
B4

N4
T6

ARC0

N5

R446 10K

0

HNIM

TU_SCL
TU_SDA

R466

R461 22

C431

4.7uF

ETH_LED1

R402 22

DSUB_DET

AV2_DET

ETH_LED0

R450

100

HNIM

R451 100

HNIM

C432 0.1uF
C433

HNIM

C435

0.1uF
HNIM

+3.3V

3.3K

NON_EU
NON_EU

EU

R442
100

EU

R444

100

C434

1uF

EU

C451 0.1uF

C452 0.1uF

R464 47
R465 47

0.1uF
L400

120-ohm

Main

HNIM

C450
100pF
50V

HNIM

R468

3.3K
P_SDA

SPDIF_OUT

EU

C437 2.2uF
C438

2.2uF

EU

C472

2.2uF

C478

2.2uF

C443

2.2uF
C444 2.2uF
C445 2.2uF
C446 2.2uF

C449

C454

0.1uF

10uF

R431

49.9
1%
ET_NET

C426

0.1uF
ET_NET

ARC

C1419

16V

0.1uF

READY

HNIM

HNIM

+3.3V

R441

1M

BLM18SG121TN1D

R443

49.9
1%
ET_NET

R14 06
150
READY

R14 07

63. 4
READY

GND

HNIM

READY
C456

C459

100pF

100pF

50V

50V

C460
100pF
50V

C1612

0.047uF
25V

HNIM

GND_2

X-TAL_12GND_1

AUD_SCK
AUD_MASTER_CLK
AUD_LRCH

AUD_LRCK

AV/SC1_L_IN
AV/SC1_R_IN

COMP1_L_IN
COMP1_R_IN
COMP2_L_IN
COMP2_R_IN
PC_L_IN
PC_R_IN

L401

R445

R460

49.9

49.9

1%

1%

ET_NET

ET_NET

C458

0.1uF
ET_NET

HDMI_ARC

HNIM

C457

1000pF
50V

READY

R497 100

HNIM

X-TAL_2

4

3

X400
24MHz

1

SIDE_USB_DM
SIDE_USB_DP

SUB_SDA
SUB_SCL

P_SCL

SCART1_Lout

SCART1_Rout

RP
TP

RN

TN
CI_DET

TX

SOC_RESET

IF_P_MSTAR

IF_N_MSTAR

TU_SIF

C1613

0.1uF
HNIM

C447 5pF
C448 5pF

IF_AGC_MAIN

/PCM_IRQA

/PCM_WAIT

PCM_D[0-7]

PCM_D[0]
PCM_D[1]
PCM_D[2]
PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]

PCM_A[0]
PCM_A[1]
PCM_A[2]
PCM_A[3]
PCM_A[4]
PCM_A[5]
PCM_A[6]
PCM_A[7]
PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]
PCM_A[12]
PCM_A[13]
PCM_A[14]

EU

R45822
R45922

EU

22
R481 22
R482 22

R477 22
R478 22

R469 22
R470 22

R471

2.2K

+3.3V

+5V

EU

R472

2.2K

PCM_A[0-14]

R473
10K

C461

0.1uF
READY

16V

I2C_SCL
I2C_SDA

R476
10K

EU

C462

0.1uF
EU

16V

RGB_DDC_SDA
RGB_DDC_SCL

/PCM_REG

/PCM_OE

/PCM_WE

/PCM_IORD

/PCM_IOWR

/PCM_CE

PCM_RST
/CI_CD1

/CI_CD2

UART_TXD
UART_RXD

S7_TXD

S7_RXD

PWM0
PWM1

COMP2_DET

SC_RE2

LED_RED

KEY1
KEY2

TOUCH_VER_CHK

AMP_MUTE

MODEL OPTION

PIN NAME

MODEL_OPT_1

MODEL_OPT_2

+3.3V_ST

<LM1 CHIP Config>
(AUD_SCK,AUD_MASTER_CLK,PWM1,PWM0)

B51_NO_EJ : 4’b0000 Boot from 8051 with SPI flash
SB51_WOS : 4’b0001 Secure B51 without scramble
SB51_WS : 4’b0010 Secure B51 with scramble
MIPS_SPI_NO_EJ : 4’b0100 Boot from MIPS with SPI flash
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash
MIPS_WOS : 4’b1001 Secure MIPS without scramble
MIPS_WO : 4’b1010 Secure MIPS with scramble

C429
22uF
16V

D400
KDS181

+3.3V

R1401
1K
READY

R1400
1K
READY

C487
10uF
16V
READY

PIN NO.

A9

R434
100K

R401
1K
FHD

R419
1K
HD

R436
10

R430
1K
3D

R467
1K
2D

C430

0.1uF
16V

HIGH

3D

FHD HDF4

R47922
R480

SOC_RESET

W21

PCMDATA[0]/GPIO126

AA18

PCMDATA[1]/GPIO127

AB22

PCMDATA[2]/GPIO128

AE20

PCMDATA[3]/GPIO120

AA15

PCMDATA[4]/GPIO119

AE21

PCMDATA[5]/GPIO118

AB21

PCMDATA[6]/GPIO117

Y15

PCMDATA[7]/GPIO116

W20

PCMADR[0]/GPIO125

V20

PCMADR[1]/GPIO124

W22

PCMADR[2]/GPIO122

AB18

PCMADR[3]/GPIO121

AA20

PCMADR[4]/GPIO99

AA21

PCMADR[5]/GPIO101

Y19

PCMADR[6]/GPIO102

AB17

PCMADR[7]/GPIO103

Y16

PCMADR[8]/GPIO108

AB19

PCMADR[9]/GPIO110

AB20

PCMADR[10]/GPIO114

AA16

PCMADR[11]/GPIO112

AA19

PCMADR[12]/GPIO104

AC21

PCMADR[13]/GPIO107

AA17

PCMADR[14]/GPIO106

Y20

PCMREG_N/GPIO123

AB15

PCMOE_N/GPIO113

AA22

PCMWE_N/GPIO197

AD22

PCMIORD_N/GPIO111

AD20

PCMIOWR_N/GPIO109

AD21

PCMCE_N/GPIO115

AC20

PCMIRQA_N/GPIO105

Y18

PCMCD_N/GPIO130

Y21

PCMWAIT_N/GPIO100

Y22

PCM_RESET/GPIO129

U21

PCM2_CE_N/GPIO131

V21

PCM2_IRQA_N/GPIO132

R20

PCM2_CD_N/GPIO135

T20

PCM2_WAIT_N/GPIO133

U22

PCM2_RESET/GPIO134

D4

UART1_TX/GPIO43

E4

UART1_RX/GPIO44

N25

UART2_TX/GPIO65

N24

UART2_RX/GPIO64

B8

UART3_TX/GPIO47

A8

UART3_RX/GPIO48

P23

I2C_SCKM2/DDCR_CK/GPIO72

P24

I2C_SDAM2/DDCR_DA/GPIO71

D2

DDCA_DA/UART0_TX

D1

DDCA_CK/UART0_RX

P21

PWM0/GPIO66

N23

PWM1/GPIO67

P22

PWM2/GPIO68

R21

PWM3/GPIO69

P20

PWM4/GPIO70

F6

PWM_PM/GPIO199

H6

SAR0/GPIO31

G5

SAR1/GPIO32

G4

SAR2/GPIO33

J5

SAR3/GPIO34

J4

SAR4/GPIO35

R23

VSYNC_LIKE/GPIO145

R24

SPI1_CK/GPIO201

R25

SPI1_DI/GPIO202

T21

SPI2_CK/GPIO203

T22

SPI2_DI/GPIO204

LOW

2D

MODEL_OPT_1
RF_SWITCH_CTL
MODEL_OPT_3

SOC_RESET

+3.3V

R453

1K

R456

1K READY

R439

1K READY

R447

1K READY

R455

R463

1K READY

1K

R440

R457

1K

R454

1KREADY

R448

1K

1K

AUD_SCK
AUD_MASTER_CLK
PWM1
PWM0
LED_RED

IC400

LGE2111A-T8

NF_CE1Z/GPIO138

NF_WPZ/GPIO198
NF_CEZ/GPIO137
NF_CLE/GPIO136
NF_REZ/GPIO139
NF_WEZ/GPIO140
NF_ALE/GPIO141
NF_RBZ/GPIO142

GPIO_PM[0]/GPIO6

PM_UART_TX/GPIO_PM[1]/GPIO7

GPIO_PM[2]/GPIO8
GPIO_PM[3]/GPIO9

GPIO_PM[4]/GPIO10

PM_UART_RX/GPIO_PM[5]/GPIO11

PM_SPI_SCZ1/GPIO_PM[6]/GPIO12

GPIO_PM[7]/GPIO13
GPIO_PM[8]/GPIO14
GPIO_PM[9]/GPIO15

PM_SPI_SCZ2/GPIO_PM[10]/GPIO16

GPIO_PM[11]/GPIO17

PM_SPI_SCK/GPIO1

PM_SPI_CZ0/GPIO_PM[12]/GPIO0

PM_SPI_SDI/GPIO2
PM_SPI_SDO/GPIO3

TS0CLK/GPIO87

TS0VALID/GPIO85

TS0SYNC/GPIO86

TS0DATA_[0]/GPIO77
TS0DATA_[1]/GPIO78
TS0DATA_[2]/GPIO79
TS0DATA_[3]/GPIO80
TS0DATA_[4]/GPIO81
TS0DATA_[5]/GPIO82
TS0DATA_[6]/GPIO83
TS0DATA_[7]/GPIO84

TS1CLK/GPIO98
TS1VALID/GPI96
TS1SYNC/GPIO97

TS1DATA_[0]/GPIO88
TS1DATA_[1]/GPIO89
TS1DATA_[2]/GPIO90
TS1DATA_[3]/GPIO91
TS1DATA_[4]/GPIO92
TS1DATA_[5]/GPIO93
TS1DATA_[6]/GPIO94
TS1DATA_[7]/GPIO95

DDR

A-TMA0
A-TMA1
A-TMA2
A-TMA3
A-TMA4
A-TMA5
A-TMA6
A-TMA7
A-TMA8

A-TMA9
A-TMA10
A-TMA11
A-TMA12
A-TMA13
A-TMA14

A-TMBA0
A-TMBA1
A-TMBA2

A-TMCK
A-TMCKB
A-TMCKE

A-TMODT

A-TMRASB
A-TMCASB

A-TMWEB

A-TMRESETB

A-TMDQSL

A-TMDQSLB

A-TMDQSU

A-TMDQSUB

A-TMDML
A-TMDMU

A-TMDQL0

A-TMDQL1
A-TMDQL2

A-TMDQL3

A-TMDQL4

A-TMDQL5
A-TMDQL6
A-TMDQL7

A-TMDQU0

A-TMDQU1
A-TMDQU2

A-TMDQU3

A-TMDQU4
A-TMDQU5
A-TMDQU6

A-TMDQU7

CLose to Saturn7M IC

VCC_1.5V_DDR

R483
1K
1%

R484
1K
1%

A11
C14
B11
F12
C15
E12
A14
D11
B14
D12
C16
C13
A15
E11
B13

F13
B15
E13

C17
A17
B16

E14
B12
A12
C12

F11

B19
C18

B18
A18

E15
A21

D17
G15
B21
F15
B22
F14
A22
D15

G16
B20
F16
C21
E16
A20
D16
C20

C463

0.1uF

AE18
AC17
AD18
AC18
AC19
AD17
AE17
AD19

H5
K6
K5
J6
K4
L6
C2
L5
M6
M5
C1
M4

A2
D3
B2

R432 22

B1

Y14
AA10
Y12

Y13
Y11
AA12
AB12
AA14
AB14
AA13
AB11

AC15
AD15
AC16

AD16
AE15
AE14
AC13
AC14
AD12
AD13
AD14

A_DDR3_A[0]
A_DDR3_A[1]
A_DDR3_A[2]
A_DDR3_A[3]
A_DDR3_A[4]
A_DDR3_A[5]
A_DDR3_A[6]
A_DDR3_A[7]
A_DDR3_A[8]
A_DDR3_A[9]
A_DDR3_A[10]
A_DDR3_A[11]
A_DDR3_A[12]
A_DDR3_A[13]
A_DDR3_A[14]

A_DDR3_BA[0]
A_DDR3_BA[1]
A_DDR3_BA[2]

A_DDR3_MCLK
A_DDR3_MCLKZ
A_DDR3_MCLKE

A_DDR3_ODT
A_DDR3_RASZ
A_DDR3_CASZ
A_DDR3_WEZ

A_DDR3_RESET

A_DDR3_DQSL
A_DDR3_DQSLB

A_DDR3_DQSU
A_DDR3_DQSUB

A_DDR3_DQML
A_DDR3_DQMU

A_DDR3_DQL[0]
A_DDR3_DQL[1]
A_DDR3_DQL[2]
A_DDR3_DQL[3]
A_DDR3_DQL[4]
A_DDR3_DQL[5]
A_DDR3_DQL[6]
A_DDR3_DQL[7]

A_DDR3_DQU[0]
A_DDR3_DQU[1]
A_DDR3_DQU[2]
A_DDR3_DQU[3]
A_DDR3_DQU[4]
A_DDR3_DQU[5]
A_DDR3_DQU[6]
A_DDR3_DQU[7]

C464
1000pF

1/16W

AR401 22

1/16W

AR400 22

R438

1K

R486 100

R449100

ERROR_DET

R489 33

READY

R487 33

R490 33

CI_TS_CLK
CI_TS_VAL
CI_TS_SYNC

CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]
CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

BUF1_FE_TS_CLK
BUF1_FE_TS_VAL_ERR
BUF1_FE_TS_SYN

BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

IC400

LGE2111A-T8

A-MVREFCA

/PF_WP

/PF_CE0
/PF_CE1
/PF_OE
/PF_WE
PF_ALE
/F_RB

AC_DET
PM_TXD

DISP_EN
5V_ON
RL_ON
PM_RXD

/FLASH_WP

USB1_CTL

MODEL_OPT_3

SPI_SCK
/SPI_CS

SPI_SDI
SPI_SDO

CI_TS_DATA[0-7]

BUF1_FE_TS_DATA[0-7]

B23

B_DDR3_A[0]

D25

B_DDR3_A[1]

F22

B_DDR3_A[2]

G22

B_DDR3_A[3]

E24

B_DDR3_A[4]

F21

B_DDR3_A[5]

E23

B_DDR3_A[6]

D22

B_DDR3_A[7]

D24

B_DDR3_A[8]

D21

B_DDR3_A[9]

C24

B_DDR3_A[10]

C25

B_DDR3_A[11]

F23

B_DDR3_A[12]

E21

B_DDR3_A[13]

D23

B_DDR3_A[14]

G20

B_DDR3_BA[0]

F24

B_DDR3_BA[1]

F20

B_DDR3_BA[2]

G25

B_DDR3_MCLK

G23

B_DDR3_MCLKZ

F25

B_DDR3_MCLKE

D20

B_DDR3_ODT

B25

B_DDR3_RASZ

B24

B_DDR3_CASZ

A24

B_DDR3_WEZ

E20

B_DDR3_RESET

K24

B_DDR3_DQSL

K25

B_DDR3_DQSLB

J21

B_DDR3_DQSU

J20

B_DDR3_DQSUB

H24

B_DDR3_DQML

L20

B_DDR3_DQMU

L23

B_DDR3_DQL[0]

J24

B_DDR3_DQL[1]

L24

B_DDR3_DQL[2]

J23

B_DDR3_DQL[3]

M24

B_DDR3_DQL[4]

H23

B_DDR3_DQL[5]

M23

B_DDR3_DQL[6]

K23

B_DDR3_DQL[7]

G21

B_DDR3_DQU[0]

L22

B_DDR3_DQU[1]

H22

B_DDR3_DQU[2]

K20

B_DDR3_DQU[3]

H20

B_DDR3_DQU[4]

L21

B_DDR3_DQU[5]

H21

B_DDR3_DQU[6]

K21

B_DDR3_DQU[7]

CLose to Saturn7M IC

VCC_1.5V_DDR

R491
1K
1%

C465

R492

0.1uF

1K
1%

C466
1000pF

B-TMA0
B-TMA1
B-TMA2
B-TMA3
B-TMA4
B-TMA5
B-TMA6
B-TMA7
B-TMA8
B-TMA9
B-TMA10
B-TMA11
B-TMA12
B-TMA13
B-TMA14

B-TMBA0
B-TMBA1
B-TMBA2

B-TMCK
B-TMCKB
B-TMCKE

B-TMODT
B-TMRASB
B-TMCASB
B-TMWEB

B-TMRESETB

B-TMDQSL
B-TMDQSLB

B-TMDQSU
B-TMDQSUB

B-TMDML
B-TMDMU

B-TMDQL0
B-TMDQL1
B-TMDQL2
B-TMDQL3
B-TMDQL4
B-TMDQL5
B-TMDQL6
B-TMDQL7

B-TMDQU0
B-TMDQU1
B-TMDQU2
B-TMDQU3
B-TMDQU4
B-TMDQU5
B-TMDQU6
B-TMDQU7

B-MVREFCA

LVDS

MODEL_OPT_1

RF_SWITCH_CTL

POWER

+1.10V_VDDC

+2.5V

+3.3V_ST

+3.3V

+1.5V_DDR_IN

C467
1000pF

5V_DET_HDMI_1
5V_DET_HDMI_2
5V_DET_HDMI_3

COMP1_DET

AV/SC1_DET

AMP_RESET_N

TUNER_RESET

PCM_5V_CTL

AMP_SCL
AMP_SDA

USB1_OCD

SCART1_MUTE

VDDC : 2026mA

MIUVDDC

L405

120-ohm

Main

Close to the Main IC

L402

120-ohm

Main

AVDD2P5:172mA

L414

AVDD25_PGA:13mA

Main

L403
Main

L406

120-ohm

Main

C439

0.1uF

Close to the Main IC

AVDD_NODIE:7.362mA

120-ohm

120-ohm

AVDD33

Close to the Main IC

L408

120-ohm

Main

AU33:31mA

Close to the Main IC

L409

120-ohm

Main

VDD33_T/VDDP/U3_VD33_2:47mA

VDD33_NAND

Close to the Main IC

AVDD_DDR0:55mA

AVDD_DDR1:55mA
L412
Main

C488
10uF

Close to the Main IC

120-ohm

C440

0.1uF

0.1uF

1uF

C453

C468

C436

0.1uF

L413

120-ohm

Main

C441

0.1uF

C442

0.1uF

C455

0.1uF

C470

0.1uF

C7
E6
F5
B6
E5
D5
B7
E7

F7
AB5
AB3

A9

F4
AB1

N6
AB2
AC2

IC400

LGE2111A-T8

GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO45
GPIO46
GPIO49
GPIO50
GPIO51
GPIO52
I2C_SCKM0/GPIO53
I2C_SDAM0/GPIO54
GPIO73
GPIO74

C1406 0.1uF
C1407 0.1uF

C1408 0.1uF
C1409 10uF
C1410 10uF

10uFC1411

C1412 0.1uF

10uFC1413

FB_CORE

C1415 0.1uF
C1416 0.1uF
C1417 10uF

C425 0.1uF

C1418 0.1uF

C469 0.1uF

C471 0.1uF

C427 10uF

1uF

C473

10uFC474

C475 0.1uF

C476 0.1uF

C477 0.1uF

1uFC479
10uFC482

C483 10uF

10uFC484

C485 0.1uF

C486 0.1uF
C492 10uF

C493 0.1uF
C494 0.1uF
C497 10uF
C498 10uF

LVA0P
LVA0N
LVA1P
LVA1N
LVA2P
LVA2N
LVA3P
LVA3N
LVA4P
LVA4N

LVB0P
LVB0N
LVB1P
LVB1N
LVB2P
LVB2N
LVB3P
LVB3N
LVB4P
LVB4N

LVACKP
LVACKN
LVBCKP
LVBCKN

GPIO196
GPIO193
GPIO194
GPIO195

K12

G9

H9
K10
K11
L10
M12
M13
N12
P14
P15
R10
R14
R15
T10

P10
P19
R16
L11
M14

W9
W10
W11
W12

Y17

V18
U19

W14
W15

U7

L7

M7

P7

R7

M19

V7

W7

R19
T19

W18
W19

V19

J17
K15
K16
L15

K17
L17
M17
L16

E9

A23
B17
C23

A5
C11
C19
C22
D14
D18
D19
E17
E18
E19
E22

F8
F17
F18
F19

G8

H8
N22
N21
N20
M22
M21
M20
F10
V15
W16

V8
T18

AB25
AB23
AC25
AB24
AD25
AC24
AE23
AC23
AC22
AD23

V23
U24
V25
V24
W25
W23
AA23
Y24
AA25
AA24

AE24
AD24
Y23
W24

T25
U23
T24
T23

IC400

LGE2111A-T8

AVDDLV_USB

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14

AVDD1P0
FB_CORE
AVDDL_MOD
AVDD10_LAN
DVDD_DDR

AVDD2P5_ADC_1
AVDD2P5_ADC_2
AVDD2P5_ADC_3
AVDD25_REF

AVDD25_LAN

AVDD_MOD_1
AVDD_MOD_2

AVDD25_PGA
AVSS_PGA

AVDD_NODIE

AVDD_DVI_USB_1
AVDD_DVI_USB_2
AVDD3P3_MPLL
AVDD_DMPLL

DVDD_NODIE

AVDD_AU33
AVDD_EAR33

VDDP_1
VDDP_2

AVDD_LPLL_1
AVDD_LPLL_2

VDDP_NAND

AVDD_DDR0_D_1
AVDD_DDR0_D_2
AVDD_DDR0_D_3
AVDD_DDR0_C

AVDD_DDR1_D_1
AVDD_DDR1_D_2
AVDD_DDR1_D_3
AVDD_DDR1_C

GND_EFUSE

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31

GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136

RXA4­RXA4+
RXA3­RXA3+
RXACK­RXACK+
RXA1­RXA1+
RXA0­RXA0+

RXB4­RXB4+
RXB3­RXB3+
RXBCK­RXBCK+
RXB1­RXB1+
RXB0­RXB0+

RXA2­RXA2+
RXB2­RXB2+

G10
G11
G12
G13
G14
G17
G18
G19
G24
H11
H12
H13
H14
H15
H16
H17
H18
H19
J9
J10
J11
J12
J13
J14
J15
J16
J18
J19
J25
K9
K13
K14
H10
K18
K19
K22
L8
L9
J8
L12
L13
L18
L19
M8
K8
M10
M11
L14
M15
M16
M18
M25
N10
N11
N13
N14
N15
N16
N17
N19
K7
P8
P9
M9
P11
P13
P16
P17
P18
P12
R8
R9
R11
R12
R13
R17
T8
T9
N7
T11
T12
T13
T14
T15
T16
T17
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
R18
V9
V10
V11
V12
V14
V17
T7
E8

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

MAIN

2011-10-20

4

6

VCC_1.5V_DDR

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

R502

1K
1%

R503

1K
1%

Hynix_1G_1600

H5TQ1G63DFR-PBC

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3

M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

SS_1G_1600

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3

M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

VCC_1.5V_DDR

R500

1K
1%

R501

1K
1%

Hynix_1G_1600

IC500-*1

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

SS_1G_1600

IC500-*2

K4B1G1646G-BCK0

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_DDR_IN

L500

500
Main

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13

A15

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

K4B1G1646G-BCK0

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13

NC_5

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

IC501-*1

IC501-*2

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VREFCA

VREFDQ

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

C501

0.1uF

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

C500

0.1uF

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VCC_1.5V_DDR

C544
10uF
10V

A-MVREFCA

A-MVREFDQ

C503

1000pF

C524 10uF
C525 0.1uF
C526 0.1uF
C527 0.1uF
C528 0.1uF
C529 0.1uF
C530 0.1uF
C531 0.1uF
C532 0.1uF
C533 0.1uF

A-TMA14

B-MVREFCA

B-MVREFDQ

C502

1000pF

C506 10uF
C507

0.1uF
C508 0.1uF
C509 0.1uF
C510 0.1uF
C511 0.1uF
C512 0.1uF
C513 0.1uF
C514 0.1uF
C515 0.1uF

B-TMA14

C545

0.1uF
16V

IC501

H5TQ1G63DFR-H9C

A10/AP

A12/BC

RESET

A10/AP

A12/BC

NC_5

RESET

DQSL
DQSL

DQSU
DQSU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

NC_5

DQSL
DQSL

DQSU
DQSU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

A11

A13

BA0
BA1
BA2

CKE

ODT
RAS
CAS

DML
DMU

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7
R7

A11

N7
T3

A13

M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

F3
G3

C7
B7

E7

DML

D3

DMU

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7
R7
N7
T3

M7

M2
N8
M3

J7

CK

K7

CK

K9

L2

CS

K1
J3
K3
L3

WE

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

M8

VREFCA

H1

VREFDQ

R505

L8

ZQ

240

1%

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

IC500

H5TQ1G63DFR-H9C

M8

VREFCA

H1

VREFDQ

R504

L8

ZQ

240

1%

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

DDR3 Memory
1GBit x 2

A-TMA0
A-TMA1
A-TMA2
A-TMA3
A-TMA4
A-TMA5
A-TMA6
A-TMA7
A-TMA8
A-TMA9
A-TMA10
A-TMA11
A-TMA12
A-TMA13

A-TMBA0
A-TMBA1
A-TMBA2

A-TMCKE

A-TMODT
A-TMRASB

A-TMCASB

A-TMWEB

A-TMRESETB

A-TMDQSL
A-TMDQSLB

A-TMDQSU
A-TMDQSUB

A-TMDML
A-TMDMU

A-TMDQL0
A-TMDQL1

A-TMDQL2
A-TMDQL3
A-TMDQL4
A-TMDQL5
A-TMDQL6

A-TMDQL7

A-TMDQU0
A-TMDQU1
A-TMDQU2
A-TMDQU3

A-TMDQU4

A-TMDQU5
A-TMDQU6
A-TMDQU7

B-TMA0
B-TMA1
B-TMA2
B-TMA3
B-TMA4
B-TMA5
B-TMA6
B-TMA7
B-TMA8
B-TMA9
B-TMA10
B-TMA11
B-TMA12
B-TMA13

B-TMBA0

B-TMBA1

B-TMBA2

B-TMCKE

B-TMODT
B-TMRASB
B-TMCASB
B-TMWEB

B-TMRESETB

B-TMDQSL

B-TMDQSLB

B-TMDQSU

B-TMDQSUB

B-TMDML
B-TMDMU

B-TMDQL0

B-TMDQL1

B-TMDQL2

B-TMDQL3

B-TMDQL4

B-TMDQL5

B-TMDQL6

B-TMDQL7

B-TMDQU0

B-TMDQU1

B-TMDQU2

B-TMDQU3

B-TMDQU4

B-TMDQU5

B-TMDQU6

B-TMDQU7

R509

56
1%

VCC_1.5V_DDR

R506
10K

SS_1G_1333

IC501-*3

K4B1G1646G-BCH9

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

R508

56
1%

VCC_1.5V_DDR

R507
10K

SS_1G_1333

IC500-*3

K4B1G1646G-BCH9

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

0.01uF

M8

H1

L8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R510

C542

0.01uF
50V

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

C543

50V

56
1%

R511

LVDS

R512

+5V

4.7K

R513

4.7K

MULTI

R577

+5V

4.7K

A2CA1

D500

KDS184

P500

P503

A-TMCK

A-TMCKB

56
1%

SS_2G_1333

IC501-*4

K4B2G1646C

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

N7

K2

VDD_4

A12/BC

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

B-TMCK
B-TMCKB

TF05-51S

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

HD

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

104060-8017

RXA0­RXA0+
RXA1­RXA1+

RXA2­RXA2+

RXACK­RXACK+

RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2­RXB2+

RXBCK­RXBCK+

RXB3­RXB3+
RXB4­RXB4+

FHD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

R576
R536
R537 0

2K
R579

47K
R578

READY
0

0

RXA0­RXA0+
RXA1­RXA1+

RXA2-

RXA2+

RXACK­RXACK+
RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2-

RXB2+

RXBCK­RXBCK+
RXB3­RXB3+
RXB4­RXB4+

P_SDA
DISP_EN
P_SCL

PC_SER_DATA
PC_SER_CLK

B

UART_RXD
UART_TXD

C

E

Q500

MMBT3904(NXP)

81

SS_2G_1333

IC500-*4

K4B2G1646C

N3

M8

A0

VREFCA

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

A2CA1

D500*-1

MMBD6100

LD500

Key/IR

+3.3V_ST

USA

IR

+3.3V_ST

R540

10K

KEY1

KEY2

LED_RED

+3.3V_ST

SUB_SCL

SUB_SDA

R542
10K

R516
100

R515

4.7K

R538

4.7K

R518
100

R517
100

C535
220pF
50V

R539

4.7K

C517
10pF

50V

C534
220pF
50V

R514
22

ZD500

5.48VTO5.76V

C520
10pF

50V

R519
100

C522
10pF

R520

50V

100

READY

C523
10pF

50V

READY

+3.3V_ST

ZD502

5.48VTO5.76V

ZD501

5.48VTO5.76V

ZD503

5.48VTO5.76V

ZD506

5.48VTO5.76V

ZD507

5.48VTO5.76V

C547

0.1uF
16V

ZD504

5.48VTO5.76V
ZD505

5.48VTO5.76V

P501

12507WS-08L

1

2

3

4

5

6

7

8

9

NAND Flash
1GBit

/F_RB

/PF_OE

/PF_CE0

/PF_CE1

PF_ALE

/PF_WE

/PF_WP

R556

3.3K

SERIAL FLASH
8MBit

IC505-*1

MX25L8006EM2I-12G

MX

VCC

CS#

8

1

SO/SIO1

HOLD#

2

7

WP#

SCLK

3

6

GND

SI/SIO0

4

5

EEPROM
1MBit

IC503-*1

R1EX24256BSAS0A

Renesas_IC503

VCC

A0

8

1

WP

A1

7

2

SCL

A2

6

3

SDA

VSS

5

4

HDCP EEPROM
8KBit

R558
0

R563

4.7K

NC_1

+3.3V

NC_2

NC_3

NC_4

NC_5

NC_6

R568

R565

4.7K

1K

R566
1K
READY

C550

0.1uF

NC_7

NC_8

VCC_1

VSS_1

NC_9

NC_10

NC_11

NC_12

R567
1K

NC_13

NC_14

NC_15

/SPI_CS

SPI_SDO

/FLASH_WP

AT24C256C-SSHL-T

A0

1

A1

2

A2

3

GND

4

IC502

CAT24C08WI-GT3-H-RECV(TV)

NC_1

1

NC_2

2

READY

A2

3

VSS

4

IC504

H27U1G8F2BTR-BC

1

2

3

4

5

6

R/B

7

RE

8

CE

9

10

11

12

13

14

15

CLE

16

ALE

17

WE

18

WP

19

20

21

22

23

24

+3.3V_ST

+3.3V_ST

R564
10K

R561
0

IC503

VCC

8

WP

7

SCL

6

SDA

5

VCC

8

R570

WP

4.7K

7

SCL

6

SDA

5

R569

4.7K
READY

DO[IO1]

%WP[IO2]

C552

0.1uF

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

W25Q80BVSSIG

CS

1

2

3

GND

4

+3.3V

+3.3V

R571
22

R572
22

IC505

NC_29

NC_28

NC_27

NC_26

I/O7

I/O6

I/O5

I/O4

NC_25

NC_24

NC_23

VCC_2

VSS_2

NC_22

NC_21

NC_20

I/O3

I/O2

I/O1

I/O0

NC_19

NC_18

NC_17

NC_16

R573
22

R574
22

I2C_SCL

I2C_SDA

+3.3V

8

7

6

5

AR518

22

C554
10uF

10V

C555

0.1uF

AR519

22

VCC

HOLD[IO3]

CLK

DI[IO0]

I2C_SCL

I2C_SDA

+3.3V_ST

R575
33

PCM_A[7]

PCM_A[6]

PCM_A[5]

PCM_A[4]

PCM_A[3]

PCM_A[2]

PCM_A[1]

PCM_A[0]

C556

0.1uF

SPI_SCK

SPI_SDI

Addr:10101--

SS

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

R/B

RE

CE

NC_7

NC_8

VCC_1

VSS_1

NC_9

NC_10

CLE

ALE

WE

WP

NC_11

NC_12

NC_13

NC_14

NC_15

PCM_A[0-7]

IC504-*1

K9F1G08U0D-SCB0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0’h

NC_29

48

NC_28

47

NC_27

46

NC_26

45

I/O7

44

I/O6

43

I/O5

42

I/O4

41

NC_25

40

NC_24

39

NC_23

38

VCC_2

37

VSS_2

36

NC_22

35

NC_21

34

NC_20

33

I/O3

32

I/O2

31

I/O1

30

I/O0

29

NC_19

28

NC_18

27

NC_17

26

NC_16

25

* LCI: LVDS Connection Indicator

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

Memory.LVDS,IR

2011-10-20

5

6

Power Wafer

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

+3.3V_ST

RL_ON
5V_ON

+5V_ST

C600
10uF
10V

C601

0.1uF
16V

C602

0.1uF
16V
READY

VIN

AP2121N-3.3TRE1

P_17V

P600

R600
10K

C603

0.1uF
16V
READY

SMAW200-H18S1

1
3
5
7
9

10
12

11

14

13

16

15

18

17

19

2
4
6
8

P_17V

C607

0.1uF
16V

C606

0.1uF
16V

L600

120

AC_DET

R609

C613
10uF

+5V

C608
10uF
10V

C610

0.1uF
16V

ERROR_DET

100

+5V_ST

25V
READY

10uF
25V

0.1uF
50V

R1
R617
59K
1%

C623
22pF
50V

READY

R619

17.4K
1%

TPS54327DDAR

EN

VFB

VREG5

SS

C626
3300pF
50V

IC603

1

9

2

THERMAL

3

4

R661

10K

R2

C624
1uF
10V

C621

C620

Vout=0.765*(1+R1/R2)

1.25V_TU

+3.3V

C605
10uF

6.3V

VIN

TJ3940S-2.5V-3L

3

2

VOUT

C604-*1

1uF
10V

+3.3V_ST

MULTI

C604
1uF

6.3V

IC600

3

1

GND

IC601

+2.5V

VOUT

2

1

GND

R612
1

C612
10uF

6.3V

L613

120-ohm

2A

DVB_T2

+2.5V_TU

C671
10uF
10V
DVB_T2

C682

0.1uF
16V
DVB_T2

+3.3V

C617
10uF

6.3V
FNIM

R618

240

FNIM

+1.25V_TU

R1

IC602

AP1117EG-13

FNIM

ADJ/GND

R2

R6151FNIM

OUTIN

Vout=1.25*(1+R2/R1)

R620
1
FNIM

C625
10uF

6.3V
FNIM

3.3V_TU /1.8V_TU3.3Vst 2.5V Multi/2.5_TU

+3.3V

L604

120-ohm

2A

+3.3V Multi

[EP]GND

VIN

8

VBST

7

C628

4700pF

SW

50V

6

GND

5

+3.3V_TU

AZ1117BH-ADJTRE1

INPUT ADJ/GND

C627
10uF

6.3V

Vout=1.25*(1+R2/R1)

L605
NR5040T2R2N

2.2uH

IC604

OUTPUT

SS2

17

5

RLIM1

R647

100K

R648

120K

RLIM2

16

6

EN1

R649

33K

DCON_EN

EN2

BST1

R662
56K

DCON_EN

R650
33K

R634
56K

15

14

13

12

11

10

7

+5V

L606

CIS21J121

BST2

VIN2

LX2_2

LX2_1

LX1_2

9

LX1_1

8

VIN1

C653
10uF
25V

C652

0.047uF
25V

C642 0.01uF

READY

C641 100pF

C636 3300pF

C634
10uF
16V

R622
0

C632

4.7uF
10V

V3V

GND_1

C650
10uF
16V

C629
10uF
16V

+3.3V

C630

0.1uF
16V

PGOOD

GND_2

GND_3

GND_4

GND_5

[EP]GND

R2

+1.8V_TU

5%

100

R613

5%

220

R614

R1

R621
1

C631
10uF

6.3V

R639
10K

LOW_P

V7V

20

21

22

23

24

25

IC605

TPS65253RHDR

26

29

27

THERMAL

28

1

2

FB1

ROSC3CMP1

R630

3K

R635

10K

1%

R631
390K

1%

C645 3300pF

FB2

19

C648 100pF

CMP2

18

4

SS1

READY

C649 0.01uF

1.5V DDR / 1.24V Core

DCON_EN

R670

4.7
READY

C609
3300pF
READY

C655

0.047uF
25V

C651

C656

22uF

22uF

16V

16V

L607

NR5040T3R3N

L608

NR5040T3R3N

C657

C683

22uF

22uF

16V

C654
10uF
25V

C611
3300pF
50V
READY

R666

4.7
READY

16V

Vout=0.8*(1+R1/R2)

R2

R656
47K
1%

R657
43K
1%

R653

4.3K
1%

R654
51K
1%

R655
100K
1%

C666

0.022uF
16V

C661

0.022uF
16V

R658
0
READY

+1.5V_DDR_IN

+1.10V_VDDC

FB_CORE

R1

R1

R2

+3.3V

AMP_MUTE

AMP_RESET_N

R623 2K

R624 2K

R625

R626

AUD_MASTER_CLK

AMP_SDA

AMP_SCL

2.2

0

AUD_SCK

AUD_LRCK

AUD_LRCH

R627
10K

READY

AC_DET

C633

0.1uF

16V

R628

READY

READY

B

C638

10K

R629

READY

READY

READY

0.1uF
50V

C

Q600

MMBT3904(NXP)

READY

E

C643

0.1uF
50V

2K

C637
4700pF
50V

C635
22pF
50V

C639
22pF
50V

R633

10K

R636
0

READY

C640
22pF
50V

C644
22pF
50V

R637

TWARN/OUT4A

0

R638

22

C647
680pF
50V

R640

22

R641

22

R642

22

R643

22

R644

22

R645
22

R646
22

C646

0.1uF
50V

EAPD/OUT4B

VDD_DIG_1

GND_DIG_1

PWRDN

VDD_PLL

FILTER_PLL

GND_PLL

XTI

BICKI

LRCKI

SDI

RESET

INT_LINE

SDA

SCL

GND_DIG_2

VDD_DIG_2

[EP]GND

19

20

21

22

23

24

25

26

Close-by

27

28

29

30

31

32

33

34

35

Close-by

36

STA368BWG

THERMAL

37

IC606

Close-by

Close-by

18

OUT3A/FFX3A

17

OUT3B/FFX3B

16

CONFIG

15

VDD

14

GND_REG

13

OUT1A

12

GND1

11

VCC1

10

OUT1B

9

OUT2A

8

VCC2

7

GND2

6

OUT2B

5

VCC_REG

4

VSS

3

TEST_MODE

2

SA

1

GND_SUB

C660

0.1uF
50V

C662

C663 0.1uF 50V

C664 1uF 25V

C665 0.1uF 50V

P_17V

C659

0.1uF
50V

1uF 25V

0.1uF
50V

330pF

330pF

C667

C669

C670

Audio AMP

L609

10.0uH

39

39

R685

R686

C672

0.22uF
50V

L610

50V

10.0uH

L611

10.0uH

50V

39

R687

C668

35V

68uF

39

R688

L612

10.0uH

C673

0.22uF
50V

C674

0.22uF
50V

C675

0.22uF
50V

C676

0.22uF
50V

C677

0.22uF
50V

C678
1000pF
50V

C679
1000pF
50V

C680
1000pF
50V

C681
1000pF
50V

4

3

P601

2

1

SMAW250-H04R

EMI GND

GND

R604
0

R602
0

R601
0

R603
0

R607
0

R605
0

R606
0

R608
0

EMI_GND1

EMI_GND2

EMI_GND3

EMI_GND4

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

Power,AMP

2011-04-01

6

GP2R, LM1 Training Manual

Table of contents

1. PCB layout.

2. GP2R vs LM1

3. GP2R. (Block, Power, I2C)

4. LM1. (Block, Power, I2C)

5. LM1 SOC Power sequence.

6. Memory test.

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

7. Pen touch overview.

LGE Internal Use Only

1. PCB Layout.

GP2R (206 x 183)

※ LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP)

LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LM1 (206 x 141.5)

LGE Internal Use Only

2. GP2R vs GP4 LM1.

Difference GP2R 50PZ550 LM1 50PA6500 Changes

PDP Module

Tool

PCB

VSC

Main IC

Jack Layout

Sub Assy

PSU

SW
JIG

-

Power Wafer 18P 18P Stand by 0.3W ↓

Stand by 3.5V O O Stand by 3.5V .

R3(FHD) R4(FHD) New module. 50R4 Initial model.

PZ Tool PA Tool 12’ years New tool.

206x183 206x141.5 change PCB Size. (smaller than GP2R.)

S7R S7LR Internal sub-Micom .(PM block)

Slim Depth Slim Depth Same.

PZ Tool PA Tool GP2R 15pin, LM1 8pin

50R3 XP5 B’d 50R4 UP1 B’d Reduce power on time.

GP2R LM1 PDP only code.
GP2R LM1 Support DFT JI G.

. . Develop new WAFER and CABLE. (12 years)

12V_secondary X X Not use 12V.

IR Wafer 15P 8P LM1 not support 3D.

USB O O SIDE USB.

Memory DDR3 DDR3 DDR3 1Gbit . 2ea

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3. GP2R Power measure Summary

Power Line Voltage Spec [V] Voltage [V] Ripple spec [Vpp] Ripple [mV] Current [A] Remark

+5V_ST 4.845~5.355 5.01 86 0.009

+5V_ST_EN 4.845~5.355 5.00 17 0.710

+3.3V_AVDD 3.14~3.6 3.31 0.5 15 0.285

+2.5V_AVDD 2.38~2.62 2.53 20 0.200

+1.5V_DDR_IN 1.425~1.575 1.57 1.5V +/-5% 20 0.310

+1.26V_VDDC 1.2~1.32 1.27 30 0.770

+3.3V_ST 3.234~3.366 3.30 0.5 19 0.024

+17V 16.15~17.85 17.03 1.09A 1.420

+5V_TU 4.75~5.25 4.99 None 20 0.170

+5V 4.845~5.355 5.03 57 2.600

+3.3V_TU 3.15~3.46 3.26 None 26 0.320

+1.2V_TU 1.20~1.32 1.27 None 21 0.300

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-1. GP2R Power Block Diagram

5Vst

17V

L603
MAX 3A

C619
100u
16V

+5V_ST

C627

0.1u
16V

C654
22u
16V

C655

0.01u
25V

Q600
RTR030P02

+5V_ST_EN

C656
100u
16V

IC601

C636

0.01u
50V

AP2121N
300mA

IC605
TPA54319

C601

0.1u
16V

+17V +5V_TU

C634

C635

4.7u

4.7u

50V

50V

C657

0.1u
16V

+3.3V_ST

C605
100u
16V

C606

0.1u
16V

C641
10u
16V

C600

0.1u
16V

C642
10u
16V

C609
10u
16V

C610
10u
16V

IC600
AZ1085S

3.3V

C611

0.1u
16V

C612

0.1u
16V

C607
22u

6.3V

C608

0.1u
16V

IC602
TPA54319

IC603
TPA54319

L602

C615

2A

0.1u
16V

+1.5V_DDR_IN

C637

C647

10u

10u

10V

10V

+1.26V_VDDC

C651

C652

10u

10u

10V

10V

L610
2A

+3.3V_AVDD

IC604
TJ3964

C650

0.1u
16V

C653

0.1u
16V

2A/3ea

C616
22u

6.3V

C304
22u
10V

C219

0.1u
16V

10u

2ea

+2.5V_AVDD

C623

0.1u
16V

2A/2ea

2A/2ea

C552

0.1u
16V

C307

0.1u
16V

0.1u

13ea

2A 2A/2ea

10u

2ea

10u

4ea

10u

2ea

10u
1ea

IC205
AT24C02BN
RGB EDID

S7_3.3V_AVDD

NAND Flash/HDCP/EEPROM

2.5V_AVDD

10u

0.1u

1ea

4ea

0.1u

32ea

0.1u

10ea

0.1u

2ea

0.1u

8ea

DDR

S7 AVDD_DDR

DVDD

VDDC

IC203
MAX3232CDR

S7_MPLL

IC503(S-FLASH)
MX25L8005M2I-15G

SUB ASSY

5V_TU

C341

C344
68u
35V

68u
35V

C340

0.1u
50V

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

IC303 Audio AMP
STA338BWG13TR

LGE Internal Use Only

3-2. GP2R Power Block Diagram

+5V

L604
3A

L605
3A

C621

100u

16V

+5V

C624

100u

16V

C628

0.1u
16V

C631
22u
16V

C658

0.1u
16V

C750

0.1u
16V

L708
2A

IC606
AZ1085S

C725
10u
16V

C728

0.1u
16V

IC706
AZ1085S

C659
22u

6.3V

IC704
TPS54319

C753
22u
16V

C660

0.1u
16V

L101
2A

C754

0.1u
16V

L601
2A

C746
10u
10V

L708
2A

C661

0.1u
16V

C747
10u
10V

C748

0.1u
16V

+3.3V_3D

C751

0.1u
16V

L300
2A

IC206
AP2191

C126

0.1u
16V

L709
2A

IC707
AZ1117ST

L705
2A

L706
2A

L707
2A

L100
2A

+3.3V_TU

C309
22u
10V

C313

0.1u
16V

C223
100u

C752
22u
16V

C128

0.1u
16V

16V

C789
10u
16V
C753
10u
16V

0.1u
16V

C755

0.1u
16V

C222

0.1u
16V

L710
2A

13ea

C805
100p
50V
C754
100p
50V

IC301
AZ1117H

R834
0Ω1/10W

0.1u
16V

0.1u
16V

0.1u
16V

+1.2V_TU

C325
22u
10V

C103
22u
10V

7ea

7ea

3ea

C322

0.1u
16V

0.1u
16V

C104

0.1u
16V

C235

0.1u
16V

C735

0.1u
16V

C120

0.1u
16V

C332

0.1u
50V

C302

0.1u
16V

33ea

C300

0.1u
16V

+5V_CI_ON

IC205
AT24C02 EDID

USB

SPDIF

1.0V_LTX

1.0V

IC702 MX25L4005

1.8V

3.3V_LTX

3.3V_VDD

3.3V_PLL

+3.3V_CI

IC101 74LCX244

IC303 Audio AMP

+3.3V_TU

+1.2V_TU

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-3. LDO/DC-DC Start up

■ IC600 (+3.3V_AVDD/AZ1085S)

Vout

Vin

■ IC604(+2.5V_AVDD/TJ3964S)

■ IC602 (+1.5V_DDR_IN/TPS54319)

Vin

Ve
n

Vo
Io

■ IC603 (+1.26V_VDDC/TPS54319)

Vout

Vin

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

Vin

Ve
n

Vo
Io

LGE Internal Use Only

3-4. LDO/DC-DC Start up

■ IC606 (+3.3V/AZ1085S)

Vout

Vin

■ IC605 (+5V_TU/TPS54231)

Vin
Ve

n
Vo

Io

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-5. GP2R I2C MAP

+5V_HD
MI

+3.3V_S
T

DDC_SCL/SDA_1~3

1 (R208,209)
2 (R233,234)

10K

3 (R256,257)

HDMI1,2,3

HDMI1,2,3

0xA0 Ch10,12,11

0xA0 Ch10,12,11

SUB_SCL
SUB_SDA

4.7K (R635,R633)

TOUCH

TOUCH

0x52

0x52

Ch7

Ch7

G_EYE

G_EYE

0x20

0x20

Ch7

Ch7

SATURN7R

SATURN7R

I2S_IN_WS/GPIO174

(F15)

I2S_IN_BCK/GPIO175

(F14)

DDCR_CK/GPIO72

DDCR_DA/GPIO71

TGPIO2/I2C_CLK

TGPIO3/I2C_SDA

TGPIO0/UPGAIN
TGPIO1/DNGAIN

I2S_IN_SD/GPIO176

SPDIF_IN/GPIO177

(N22)
(M22)

(R3)
(T3)

(U1)
(U2)

(F13)

(G14)

<I2C-SCL>
<I2C-SDA>

<TU_SCL>
<TU_SDA>

<P_SCL>
<P_SDA>

LG8300

LG8300

0x74

0x74

Ch4

Ch4

2.2K (R480,R482)

EEPROM

EEPROM

0xA0

0xA0

Ch2

Ch2

4.7K (R319,R326)

TUNER

TUNER

TDTJ-S001D 0x10/C2

TDTJ-S001D 0x10/C2

Ch6

Ch6

AMP STA338BWG13TR

AMP STA338BWG13TR

0x38

0x38

Ch5

Ch5

3.3K (R1412,R1411)

2K (R360,R359)

4.7K (R780,R781)

MODULE

MODULE

0x1C

0x1C

Ch4

Ch4

HDCP

HDCP

EEPROM

EEPROM

0xA8

0xA8

Ch2

Ch2

<EEPROM-SCL>
<EEPROM-SDA>

<SCL1>
<SDA1>

<AMP_SCL>
<AMP_SDA>

<MODULE_SCL/3DF_SCL>
<MODULE_SDA/3DF_SDA>

+3.3
V

+3.3V_T

+3.3
V

+3.3
V_A
VDD

DDCA_CK/UART0_RX
DDCA_DA/UART0_TX

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

<RGB_DDC_SCL>

(B5)

<RGB_DDC_SDA>

(A5)

10K (R237,R247)

EEPROM

EEPROM

RGB 0xA0

RGB 0xA0

Ch8

Ch8

ISP

ISP

<DDC_SCL/UART_RX>

<DDC_SDA/UART_TX>

+5.0
V_ST

LGE Internal Use Only

4. LM1 Power Block optimization.

1. GP2R vs LM1 Power Block.

17V

5.1V

St 5V

AOZ1073 3A

FET SW

AP2191

USB

3.3V Multi
LDO (3A)

3.3V 3D

LDO (3A)

1V 3D core

3.3V Standby

LDO(AP2121)

Amp

5V Tuner

TPS54231 2A

1.25V Tuner
LDO

1.8V 3D DDR

LDO

3.3V AVDD
LDO (3A)

1.5V DDR

AOZ1073 3A

1.26V Core

AOZ1073 3A

2.5V

LDO

17V

5.1V

3.5V
St.

Amp

3.3V Multi

TPS54327(3A)

AP2191

USB

1.24V core

1.5V DDR

TPS65253(3A)

3.3V ST
AP2121

1.8V Tuner
LDO (1A)

1.25V _TU
LDO (1A)

2.5V

LDO (1A)

DC/DC : 4
LDO : 7

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

GP2R Power Block

DC/DC : 2
LDO : 4

LM1 Power Block

LGE Internal Use Only

4-1. P_17V

1
7
V

C620
10uF

25V

3216

OP-Amp
for SC

C667

0.1uF
50V

1608

C693
10uF

25V

3225

Spec) 850mV↓

16mVrms
283mVpp

C621

0.1uF
50V

2012

C668
68uF

35V

8PI/6.3H

C694

0.01uF
50V

1005

C711
10uF

16V

3216

17V to 3.3V
TPS54327
(3A, $0.14)

Audio
AMP

17V to 12V
TPS54231D
(2A)

C712

0.1uF
50V

1608

L605

2.2uH

3.5A

4.9x4.9

LNB

C629/50

10uF

16V

→6.3V

3216

→1608

0.00586↓

change

Spec) 165mV ↓

8.66mVrms

37.5mVpp

C630

0.1uF
16V

1005

L604

120 Ohm

2A

1608

Spec) 165mV↓

23.4mVrms

166.6mVpp

C643

0.1uF
50V

1608

C638
C646

0.1uF
50V

1608

+3.3V

C627
10uF

6.3V

1608

Audio
AMP

L101

120 Ohm

2A

1608

Spec) 165mV ↓

13.5mVrms
158mVpp

C137

0.1uF
16V

1005

+3.3V_TU

Spec) 165mV ↓

4.7mVrms

46.6mVpp

3.3V to 1.8V
AP1117E18G
(850mW)

Spec) 165mV↓

8.5mVrms

186.6mVpp

+3.3V_CI

C631

10uF

6.3V

1608

C614

0.1uF
16V

1005

Buffer for
CI_ADDR
[0:7]

Spec) 90mV↓

4.6mVrms

41.6mVpp

C618

0.1uF
16V

1005

C615
10uF

16V

→6.3V

3216

→1608

change

Tuner

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-2. P_17V

1
7
V

+3.3V

C605
10uF

6.3V

1608

L408/9

120 Ohm

2A

1608

x3

0.1uF
16V

1005

3.3V to 2.5V
TJ3940S-2.5V
(714mW)

* W18/9

x5

0.1uF
16V

1005

C427
10uF

10V

→6.3V

2012

→1608

0.00636↓

change

C612
10uF

6.3V

1608

Spec) 165mV↓

9.7mVrms

67.5mVpp

X4

10uF

10V

→6.3V

2012

→1608

change

* L7

Spec) 165mV↓

8.5mVrms
45mVpp

+2.5V

LM1

x3

120 Ohm

2A

1608

* Y17

C1417

10uF

10V

→6.3V

2012

→1608

change

Spec) 165mV↓

7.8mVrms

47.5mVpp

x6

0.1uF
16V

1005

x2

0.1uF
16V

1005

change

HDCP

C552

0.1uF
16V

1005

C554

10uF

10V

→6.3V

2012

→1608

NVR

LM1

DVB_T2

Nand
Flash

NOT_HNIM

L613

120 Ohm

2A

1608

3.3V to 1.25V
AP1117EG-13
(???mW)

C682

0.1uF
16V

1005

C625
10uF

1608

C684

0.1uF
16V

1005

6.3V

C671
10uF

10V

→6.3V

2012

→1608

change

+1.25V_TU

C685
10uF

6.3V

1608

Tuner

Tuner

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-3. P_5V

5
V

L600

120 Ohm

5A

2012

C608
10uF

10V

→16V

2012

→3216

0.0005↓

change

Spec) 250mV↓

7mVrms
70mVpp

C610

0.1uF
16V

1005

+5V

USB OCD

C219

0.1uF
16V

1005

MOFET
Switch

SPDIF

L100

120 Ohm

2A

1608

+5V_CI_ON

C104

0.1uF
16V

1005

C100
22uF

10V

→16V

3216

→3225

0.017↓

change

Spec) 250mV↓

31mVrms

135.4mVpp

C101

0.1uF
16V

1005

PCMCI

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-4. P_5V

5
V

+5V

L606

120 Ohm

5A

2012

C653/4

10uF

25V

3225

5V to 1.1V
TPS65253RH
D
(adjustable)
$0.25

+1.24V_VDDC

C683/57

22uF

16V

3225

C651/56

22uF

16V

3225

* M14

L405

120 Ohm

2A

1608

+1.5V_DDR_IN

1000pF

x2

0.1uF
16V

1005

x3

0.1uF
16V

1005

C467

50V

1005

Spec) 55mV↓

9.4mVrms

48.3mVpp???mVrms

C1413

10uF

10V

→6.3V

2012

→1608

change

x3

10uF

10V

→6.3V

2012

→1608

change

L412

120 Ohm

2A

1608

???mVrms

* R15

Spec) 55mV↓

17.7mVrms
70mVpp

* M17

x4

10uF

10V

→6.3V

2012

→1608

change

LM1

x4

0.1uF
16V

1005

Spec) 55mV↓

15.9mVrms
90mVpp

C468

1uF
10V

1005

LM1
MIU0/1

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

L500

500 Ohm

3A

???

C544

10uF

10V

→6.3V

2012

→1608

change

VCC_1.5V_DDR

C545

0.1uF
16V

1005

* IC501 / G7

x2

1000pF

50V

1005

Spec) 55mV↓

19.69mVrms

120.8mVpp

x2

0.1uF
16V

1005

DDR1/2

LGE Internal Use Only

4-5. STBY

C600
10uF

10V

→16V

2012

→3216

0.0005↓

change

S
T
B
Y

C601

0.1uF
16V

1005

5V to 3.3V
AP2121N-3.3
(0.3A)

Spec) 250mV↓

23mVrms
150mVpp

C604

1uF

6.3V
1005

+3.3V_ST

C228

0.1uF
16V

1005

L406

120 Ohm

2A

1608

C556

0.1uF
16V

1005

RS232C

C469

0.1uF
16V

1005

Serial Flash

LM1

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

C547

0.1uF
16V

1005

SUB Ass’y

LGE Internal Use Only

4-6. GP4 LM1 I2C MAP

EAX64337201_0

+3.3V_TU

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

IC400

I2S_IN_WS/GPIO149

SPDIF_IN/GPIO152

I2S_IN_SD/GPIO151

I2S_IN_BCK/GPIO150

GPIO49
GPIO50

AE6
AD6

AB5
AB3

D9
D7

D8
C8

TU_SCL

TU_SDA

AMP_SCL

AMP_SDA

P_SCL

P_SDA

SUB_SCL

SUB_SDA

R3082.2K

R624 2K

+3.3V_AVDD

R468 3.3K

R539 4.7K

R309 2.2K

+3.3V

R466 3.3K

+3.3V_ST

R538 4.7K

R623 2K

TU300
TDSS-G201D

IC300
STA368BWG

SCL_3.3V_MOD
SDA_3.3V_MOD

P501
KEY/IR PIN8

P500
LVDS

I2C_SCKM2/DDCR_CK/GPIO72
I2C_SDAM2/DDCR_DA/GPIO71

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

P23
P24

I2C_SCL

I2C_SDA

+3.3V_AVDD

R469 2.2K

R468 2.2K

IC503 EEPROM
IC502 HDCP (OTP)

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure

▶Hot Point

SOC_RESET

Multi_PWR

SOC_RESET

+3.3V_AVDD

0ms

288ms / [Spec] before all pwr input raise

+3.3V_AVDD
+1.10V_VDDC
+1.5V_DDR_IN

Threshold

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

+1.10V_VDDC

+1.5V_DDR_IN

◈ SOC_RESET timing and Power sequence are ok.

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure

◈ Solution

█ Value of Capacitor and resister.

① Cap Æ 22uF.

0CK226DC67A 22uF 6.3V $0.0117

② Resister Æ 100㏀.

+3.3V_AVDD

1

SOC_RESET

2

Threshold

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)

STEP1. Setting like below. (Red box) STEP2. Call “direct MIU Auto BIST” function from Menu.

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)

STEP3. Setting like below and push “Start DQS”. (Red box) STEP4. below picture is test result. Red box is timing margin.

※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU.

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-1. Pen touch overview. (Check the installation status.)

Currently installed programs

1

Check the LG Pentouch Multi-touch Driver or Pentouch TV

Check USB Dongle Driver in Device Manager

2

-LG Pentouch Multi-touch Driver(MultiTouch)

-LG Pentouch Multi-touch Driver(BUS)

-LG Pentouch Multi-touch Driver(Dongle)
the Dongle Driver should be displayed when connected USB Dongle

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-4. Pen touch overview. (Using the Pentouch Function)

■ Image shown may differ from your monitor. You need the following items to use the Pentouch f unctions:

1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function.
2 Select the correct computer input connection to enter the Pentouch mode.

3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.

■ Viewing the Screen Settings

I
mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen
settings have been updated successfully.

① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode.
② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-5. Pen touch overview. (PDP Pen Touch Concept)

Principle 2. The position data processed Pentouch TV
Application looks like PC mouse.
Step 1. USB Dongle receive the position data.

Principle 1. The Pen using PDP Cell’s light energy
Step 1. The pen detect the PDP Cell’s light
Step 2. The pen convert detected light to voltage
Step 3. The pen calculate X,Y position
Step 4. The pen transfer the X,Y data through RF

RF Wireless communication

(2.4GHz)

Pen

Step 2. USB Dongle Driver parsing the positon
Step 3. Pentouch TV application drawing and click function.
Step 4. The result was displayed PDP TV through HDMI or
RGB cable.

The photo sensor in the

pen detect the light

Plasma
Display

The HDMI or RGB signal is PC’s output that configuration set by clone mode.

Copyright © 2011 LG Electronics Inc. All rights reserved.
Only for training and service purposes

USB

Dongle

It can use Multi-Touch function by support 2 pens.

Pentouch TV Application

- It was developed by LG.

- It can be using internet for web surfing , Flash Game etc.

LGE Internal Use Only