LG 55UB8300-UG Schematic

Internal Use Only

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Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

LED TV

SERVICE MANUAL

CHASSIS : LA48V

MODEL : 55UB8300 55UB8300-UG

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL68500701 (1407-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 14

EXPLODED VIEW .................................................................................. 26

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of th e cir cuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exp ose d metallic par t. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions.
Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;

a. Removing or reinstalling any component, circuit board mod-

ule or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explo­sion hazard.

2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.
Unless specied otherwise in this service manual, lubrication of

contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas­ily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component dam­age caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alter­natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten­tial shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or expo­sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.

4. Use only an anti-static type solder removal device. Some solder

removal devices not classied as “anti-static” can generate
electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electri­cally shorted together by conductive foam, aluminum foil or
comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace­ment ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf­cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder ows onto and around both the compo­nent lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent at against the cir­cuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close
as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos­sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connec­tions).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly con­nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied to the LED TV used LA48V

2. Test condition

Each part is tested as below without special notice.

1) Temperature : 25 ºC ± 5 ºC(77±9ºF), CST : 40 ºC±5 ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage
Standard input voltage (100~240V@ 50/60Hz)
* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing and s pe cificatio n b y p art number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : UL, CSA, CE, IEC specification

- EMC : FCC, ICES, CE, IEC specification

- Wireless : Wireless HD Specification (Option)

.

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. General Specification

No Item Specication Remark

1 Market 1) North America

2 Receiving System ATSC / NTSC-M / 64 QAM / 256 QAM

3 Input Voltage AC 100 - 240V ~ 60Hz

4 Available Channel 1) VHF : 02~13

2) UHF : 14~69

3) DTV : 02-69

4) CATV : 01~135

5) CADTV : 01~135

5 Input Voltage AC 100-240V ~50/60Hz

6 Screen Size 40 inch Wide(3840 × 2160)

49 inch Wide(3840 × 2160)
55 inch Wide(3840 × 2160)
60 inch Wide(3840 × 2160)
65 inch Wide(3840 × 2160)

5 Aspect Ratio 16:9

6 Tuning System FS

7 LCD Module V400DK1-KS1

LC490EQE-XGF2
LC490EQE-XGM1
LC550EQE-PGF2
LC550EQE-PGM1

LC650EQF-FGM1

8 Operating Environment 1) Temp : 0 ~ 40 deg

2) Humidity : ~ 80 %

9 Storage Environment 1) Temp : -20 ~ 60 deg

2) Humidity : ~ 85 %

INX
LGD
LGD
LGD
LGD
LGD
LGD
LGD

40UB8000-UB
49UB8300-UG, 49UB8200-UH
55UB8300-UG, 55UB8200-UH
60UB8300-UG, 60UB8200-UH
65UB9200-UA

40UB8000-UB,
49UB8300-UG,
49UB8200-UH,
55UB8300-UG,
55UB8200-UH,
60UB8300-UG,
60UB8200-UH,
65UB9200-UA

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. External input format

5.1. 2D Mode

5.1.1. Component input(Y, CB/PB, CR/PR)

No

1 720*480 15.73 60 13.514 SDTV ,DVD 480I

2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I

3 720*480 31.50 60 27.027 SDTV 480P

4 720*480 31.47 59.94 27.0 SDTV 480P

5 1280*720 45.00 60.00 74.25 HDTV 720P

6 1280*720 44.96 59.94 74.176 HDTV 720P

7 1920*1080 33.75 60.00 74.25 HDTV 1080I

8 1920*1080 33.72 59.94 74.176 HDTV 1080I

9 1920*1080 67.500 60 148.50 HDTV 1080P

Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed

5.1.2. HDMI Input (PC/DTV)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed

HDMI-PC EGA

1 640*350 31.468 70.09 25.17 DOS Х

2 720*400 31.469 70.08 28.32 VESA(VGA) O

3 640*480 31.469 59.94 25.17 VESA(SVGA) O

4 800*600 37.879 60.317 40.00 VESA(XGA) O

5 1024*768 48.363 60.00 65.00 VESA O

6 1152*864 54.348 60.053 80.00 VESA (SXGA) O

7 1280*1024 63.981 60.020 108.00 VESA (WXGA) O

8 1360*768 47.712 60.015 85.50 VESA (WXGA) O

9 1920*1080 67.5 60 148.5

10 3840*2160 54 24.00 297.00

11 3840*2160 56.25 25.00 297.00

12 3840*2160 67.5 30.00 297.00

14 4096*2160 53.95 23.98 297.00

15 4096*2160 54.00 24.00 297.00

WUXGA(Reduced Blanking)

UDTV 2160P

UDTV 2160P

UDTV 2160P

UDTV 2160P

UDTV 2160P

O

O

O

O

O

O

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

HDMI-DTV

1 640 * 480 31.469 59.94 SDTV 480P

2 640 * 480 31.5 60 SDTV 480P

3 720*480 31.469 59.94 27.00 SDTV 480P

4 720*480 31.50 60 27.027 SDTV 480P

5 1280*720 45.00 60.00 74.25 HDTV 720P

6 1280*720 44.96 59.94 74.176 HDTV 720P

7 1920*1080 33.75 60.00 74.25 HDTV 1080I

8 1920*1080 33.72 59.94 74.176 HDTV 1080I

9 1920*1080 67.500 60 148.50 HDTV 1080P

10 1920*1080 67.432 59.939 148.352 HDTV 1080P

11 1920*1080 27.000 24.000 74.25 HDTV 1080P

12 1920*1080 26.97 23.976 74.176 HDTV 1080P

13 1920*1080 33.75 30.000 74.25 HDTV 1080P

14 1920*1080 33.71 29.97 74.176 HDTV 1080P

15 3840*2160 67.5 30.00 297.00 UDTV 2160P

16 3840*2160 61.43 29.97 296.703 UDTV 2160P

17 3840*2160 56.25 25.00 297.00 UDTV 2160P

18 3840*2160 54.0 24.00 297.00 UDTV 2160P

19 3840*2160 53.95 23.976 296.703 UDTV 2160P

20 3840*2160 135 59.94 593.41

21 3840*2160 135 60 594.00

22 4096*2160 53.95 23.976 296.703 UDTV 2160P

23 4096*2160 54

24 4096*2160 56.25 25 297 UDTV 2160P

25 4096*2160 61.43 29.97 296.703 UDTV 2160P

26 4096*2160 67.5 30 297 UDTV 2160P

27 4096*2160 135 59.94 593.41

28 4096*2160 135 60 594.00

24 297 UDTV 2160P

UDTV 2160P(8 bit / YCbCr 4:2:0 Only)

UDTV 2160P(8 bit / YCbCr 4:2:0 Only)

UDTV 2160P(8 bit / YCbCr 4:2:0 Only)

UDTV 2160P(8 bit / YCbCr 4:2:0 Only)

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2. 3D Mode

5.2.1. HDMI Input 1.4b (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock

(MHz)

1 640*480 31.469 / 31.5 59.94/ 60 25.175/25.2 1 Top-and-Bottom

62.938 / 63 59.94/ 60 50.35/50.4 1 Frame packing

2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 Top-and-Bottom

62.938 / 63 59.94 / 60 54/54.06 2,3 Frame packing

3 1280*720 44.96 / 45 59.94 / 60 74.18/74.25 4 Top-and-Bottom

89.91 / 90 59.94 / 60 148.35/148.5 4 Frame packing

4 1920*1080 33.72 / 33.75 59.94 / 60 74.18/74.25 5 Top-and-Bottom

67.432 / 67.5 59.94 / 60 148.35/148.5 5 Frame packing

26.97 / 27 23.97 / 24 74.18/74.25 32 Top-and-Bottom

43.94 / 54 23.97 / 24 148.35/148.5 32 TFrame packing

28.125 25 74.25 33 Top-and-Bottom

56.25 25 148.5 33 Frame packing

33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Top-and-Bottom

67.432 / 67.5 29.976 / 30.00 148.35/148.5 34 Frame packing

67.43 / 67.5 59.94 / 60 148.35/148.50 16 Top-and-Bottom

VIC 3D input proposed

mode

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)
Side-by-side(full)

Field alternative

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)
Side-by-side(full)

Line alternative

Side-by-side(half)

Proposed

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)
(SDTV 480P)

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)
(SDTV 480P)

Primary(HDTV 720P)
Primary(HDTV 720P)

Primary(HDTV 720P)
(HDTV 720P)

Secondary(HDTV 1080I)
Primary(HDTV 1080I)

Primary(HDTV 1080I)
(HDTV 1080I)

Primary(HDTV 1080P)
Primary(HDTV 1080P)

Primary(HDTV 1080P)
(HDTV 1080P)

Secondary(HDTV 1080P)
Secondary(HDTV 1080P)

Secondary(HDTV 1080P)
(HDTV 1080P)

Primary(HDTV 1080P)
Secondary(HDTV 1080P)

Primary(HDTV 1080P)
(HDTV 1080P)

Primary(HDTV 1080P)
Secondary(HDTV 1080P)

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.2. HDMI 1.4/2.0(3D Supported mode manaually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock

(MHz)

1. 720*480 31.5 60 27.03 SDTV 480P 2D to 3D, Side by Side(Half), Top & Bottom,

2. 1280*720 45.00 60.00 74.25 HDTV 720P

3. 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half), Top & Bottom

4. 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,

5. 1920*1080 28.12 25 74.25 HDTV 1080P

6. 1920*1080 33.75 30.00 74.25 HDTV 1080P

7. 1920*1080 67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,

8. 3840*2160 53.95 23.976 296.703 HDTV 2160P

9. 3840*2160 54 24.00 297.00 HDTV 2160P

10. 3840*2160 56.25 25.00 297.00 HDTV 2160P

11. 3840*2160 61.43 29.970 296.703 HDTV 2160P

12. 3840*2160 67.5 30.00 297.00 HDTV 2160P

13. 4096*2160 53.95 23.976 296.703 HDTV 2160P

14. 4096*2160 54 24.00 297.00 HDTV 2160P

15. 4096*2160 56.25 25.00 297.00 HDTV 2160P

16. 4096*2160 61.43 29.970 296.703 HDTV 2160P

17. 4096*2160 67.5 30.00 297.00 HDTV 2160P

18. 3840*2160 135 60 594 HDTV 2160P 2D to 3D, Top & Bottom(half),

19. 4096*2160 135 60 594 HDTV 2160P

Proposed 3D input proposed mode

Checker Board, Frame Sequential,
Row Interleaving, Column Interleaving

Checker Board, Row Interleaving,
Column Interleaving

Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving

Side by Side(half), Port3 Only

2D to 3D, Top & Bottom(half),
Side by Side(half), Port3 Only

5.2.3. HDMI-PC Input (3D) (3D Supported Mode Manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock

(MHz)

1. 1024*768 48.36 60 65 HDTV 768P 2D to 3D,

2. 1920*1080 67.500 60 148.50 HDTV 1080P 2D to 3D,

3. 3840*2160 54 24.00 296.703 HDTV 2160P 2D to 3D,

56.25 25.00 297

67.5 30.00 296.703

4. 4096*2160 54 24.00 297.00 HDTV 2160P 2D to 3D,

5. Others - - - 2D to 3D,

Proposed 3D input proposed mode

Side by Side(half), Top & Bottom

Side by Side(half), Top & Bottom,
Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving

Top & Bottom, Side by Side(half),

Side by Side(half), Top & Bottom

Side by Side(half), Top & Bottom

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.4. RF Input(3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 DTV 74.25 HD/SD 2D to 3D, Side by Side, Top & Bottom

2 ATV 74.25 SD 2D to 3D, Side by Side, Top & Bottom

5.2.5. RF Input (3D supported mode automatically)

No. Signal 3D input proposed mode

1 Frame Compatible Side by Side(Half), Top & Bottom

5.2.6. USB, DLNA (Movie) Input (3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

2 Over 704x480

interlaced

3 Over 704x480

progressive

4 Over 704x480

progressive

5 Over 2160P - 24/25/30 - 2D to 3D, Side by Side(Half), Top & Bottom, USB Only

- - - 2D to 3D, Side by Side(Half), Top & Bottom

- 60 - 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving, Column Interleaving,
Frame Sequential

- others - 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving, Column Interleaving

5.2.7. USB, DLNA (Photo) Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 320x240 - - - 2D to 3D

2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom

5.2.8. USB, DNLA Input (3D supported mode automatically) – not used

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080P 33.75 30 - Side by Side(Half), Top & Bottom, Checker Board,

2 2160p 67.5 30 297 MPO(Photo), JPS(Photo)

MPO(Photo)

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.9. Component Input(3D supported mode manually)

No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark

1 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D,

2 1280*720 44.96 59.94 74.176 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

5 1920*1080 33.72 59.94 74.176 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 26.97 23.976 74.176 HDTV 1080P

7 1920*1080 28.12 25 74.25 HDTV 1080P

8 1920*1080 33.75 30.00 74.25 HDTV 1080P

9 1920*1080 33.71 29.97 74.176 HDTV 1080P

10 1920*1080 67.50 60.00 148.5 HDTV 1080P

11 1920*1080 67.432 59.94 148.352 HDTV 1080P

Side by Side(Half),
Top & Bottom

5.2.10. Miracast, Widi (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024X768p - 30 / 60 - 2D to 3D, Side by Side(Half), Top & Bottom

2 1280x720p - 30 / 60 -

3 1920X1080p 30 / 60

4 Others - 2D to 3D

**Remark: 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame

Sequential

1

Frame

Packing

2D to 3D Line Interleav-

ing

Column

Interleaving

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to LA48V Chassis applied LED TV all
models manufactured in TV factory

2. Specification.

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ±5ºC of temperature and 65±10% of relative humidity if

there is no specific designation
(4) The input voltage of the receiver must keep 100~240V,

50/60Hz
(5) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15ºC

▪ In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

▪ In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above 15°C
for 3 hours

* Caution) When still image is displayed for a period of 20

minutes or longer (especially where W/B scale is
strong. Digital pattern 13ch and/or Cross hatch
pattern 09ch), there can some afterimage in the
black level area.

3. Adjustment items

3.1. PCB assembly adjustment items

1) MAC Address, ESN Key and Wide-vine Key D/L

2) LAN Test( Ping-Test )

3) Main S/W program download : Using USB Memory stick

4) Input Tool - Option

5) Download EDID

6) ADC Calibration – RGB & Component

7) Check SW Version

4. PCB assembly adjustment method

4.1. ADC Calibration : component using internal pattern

- An ADC calibration is needed to fine the optimum black level
and gain in Analog-to-Digital device

.

4.1.1. Adj. method

- Using RS-232C, adjust items listed in “4.1.2”

4.1.2. Adj. protocol

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change xb 00 40 b 00 OK04x (Adjust 480i, 1080p Comp1 )

Begin adj. ad 00 10 OKx (Case of Success)

Read adj. data ad 00 20 000000000000000000000000007c007b-

Conrm adj. ad 00 99 NG 01 00x (Fail)

End adj. ad 00 90 a 00 OK90x

4.1.3. Adj. Order (TBD)

▪ aa 00 00 [Enter adj. mode]
▪ xb 00 04 [Change input source to Component1(480i&1080p)]
▪ ad 00 10 [Adjust 480i&1080p Comp1]
▪ aa 00 90 [End adj.]

4.2. 4.2.MAC Address, ESN Key and Wide­vine Key Download

4.2.1. Equipment & Condition

1) Play file: keydownload.exe

2) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

3) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

NGx (Case of Fail)

006dx

OK 01 01x (Success)

3.2. SET assembly adjustment items

1) Input Area option.

2) Adjustment of White Balance : Auto

3) Adjustment of White Balance : Manual

4) Intelligent Sensor Inspection Guide

5) LAN Inspection Guide

6) Widevine Key Inspection Guide

7) Model name & Serial number D/L

8) Wi-Fi MAC Address Check

9) Local Dimming Inspection Guide

10) Preset CH information

11) GND and Internal Pressure check

12) Motion Remote controller Inspection

13) 3D Function test

14) Outgoing Condition Configuration

15) Sound spec

16) Factoring Option Data input.

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2.2. Download process (14Y ULTRA HD TV + MAC
+ WIDEVINE + ESN)

1) Execute “keydownload.exe” on PC

2) Select the download items.

3) Mode check : Online only

4) Check the test process

- DETECT -> MAC_WRITE -> ESN_WRITE (only Colombia/
Panama) ->WIDEVINE_WRITE

5) Play: START

6) Check of result: Ready, Test, OK or NG

4.2.3. Inspection : InINSTART menu, check these keys

4.4. Main S/W program download

4.4.1. Using the Memory Stick

** USB DOWNLOAD : Service Mode

1) Insert the USB memory Stick to the USB port

2) Automatically detect the SW Version.

-> S/W download process is executed automatically.

3) Show the message “Copy the file from the Memory”

4.3. PING Test(LAN Operating Test)

4.3.1. Check PCBA

1) Connect LAN to PCBA& Power On.(Default IP can be set to

automatic setting. When power ON, IP can be Automatically
be achieved from the router)

2) Push ADJ key on Adjust remote-controller.

3) Enter “13. ACAP PING TEST” & check Network.

4.3.2. Check Set(Manufacturer)

1) Co nnect TV-Set & PC with Cross LAN cable.(PC IP :

12.12.2.3)

2) Execute “PINT Test program ”, Ch eck sett ing data of

program. (TV-Set IP : 12.12.2.2)

3) Push Power Only key on Adjust remote-controlle.

4) Click “RUN”, Check “OK” or “NG”

4) After Finished the Download, Automatically DC Off -> On

5) If the TV IS Turn On, Check the updated SW Version and
Tool Option.

Only for training and service purposes

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.5. EDID D/L method

Recommend that don’t connect HDMI and RGB(D-SUB) cable
when downloading the EDID.
If not possible, recommend that connect the MSPG equipment.
There are two methods of downloading the edid data

It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information
Sharing without any necessity of user input. It is a realization

of “Plug and Play”

4.5.1. 1st Method

EDID data’s are automatically downloaded when adjusting the
Tool Options.
Automatically downloaded when pushing the enter key in the
EDID D/L menu.
It takes about 2seconds

4.5.2. 2st Method

=> Caution : Must be checked that the tool option is right or

not. If tool option is wrong, HDMI edid data could
not be downloaded well.

1) Press the ADJ key

2) Move to the 13. EDID D/L and Press the right direction

key(►)

3) Press the right direction key(►) at Start.

4) After about a few seconds, appear “Waiting..” => “OK”, then
complete.

ⓐ Product ID
ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’
Year : ‘2014’ -> ‘18

ⓓ Model Name(Hex): LGTV
ⓔ Checksum(LG TV): Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)

4.5.4.1. EDID
#DTS HDMI1 (C/S: F7 82)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

4.5.3. RS-232C command Method

1) Command : AE 00 10
=> Caution : Do n’t connect HDMI and RGB(D-SUB) cable

when downloading the EDID. If the cables are
connected, Downloading of edid could be failed.

4.5.4. EDID DATA

▪ Reference

- HDMI1 ~ HDMI3

- In the data of EDID, bellows may be different by Input mode

#DTS HDMI2 (C/S: E7 72)
EDID Block 0, Bytes 0-12

EDID Block 1, Bytes 128-255

Only for training and service purposes

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

#DTS HDMI3 (C/S: A1 81)
EDID Block 0, Bytes 0-127

# AC3 HDMI1 (C/S: E7 8B)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# DTS HDMI4 (C/S: E7 52)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

EDID Block 1, Bytes 128-255

# AC3 HDMI2 (C/S: E7 7B)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

Only for training and service purposes

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

# AC3 HDMI3 (C/S: A1 8A)
EDID Block 0, Bytes 0-127

# PCM HDMI1 (C/S: F7 FD)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# AC3 HDMI4 (C/S: E7 5B)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

EDID Block 1, Bytes 128-255

# PCM HDMI1(C/S: E7 ED)

Only for training and service purposes

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

# PCM HDMI3 (C/S: A1 FC)
EDID Block 0, Bytes 0-127

EDID Block 1, Bytes 128-255

# PCM HDMI4 (C/S: E7 CD)

4.6. Camera Port Inspection

(1) Objective : To check how it connects between Camera and

PCBA normally, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.
i) Push Camera Up
ii) Camera’s Preview picture appears on TV Set
iii) Push Camera Down

(3) RS-232C Command

RS-232C COMMAND

CMD DATA ID

Ai 00 23 Camera Function Start.

Ai 00 24 Camera Function End.

Explanation

5. SET assembly adjustment method

5.1. Input Area-Option

(1) Profile : Must be changed the Area option value because

being different of each Country’s Language and

signal Condition.
(2) Equipment : adjustment remote control.
(3) Adjustment method

- The input methods are same as oth er chass is. (Use

IN-START Key on the Adjust Remocon.)

* Checksum (HDMI 1/2/3/4)

Input DTS FFh AC3 FFh PCM FFh

HDMI1 E7 82 E7 8B E7 FD

HDMI2 E7 72 E7 7B E7 ED

HDMI3 A1 81 A1 8A A1 FC

HDMI4 E7 52 E7 5B E7 CD

Only for training and service purposes

Re fe r to Job Expre ss ion of each main ch assis ass’ y
(EBTxxxxxxxx) for Option value.

5.2. Adjustment of White Balance

▪ In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

▪ In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above 15°C
for 3 hours.

- Purpose : A djust the color te mp erature to re du ce the

deviation of the module color temperature.

- Principle : To adjust the white balance without the saturation,

Fix the one of R/G/B gain to 192 (default data) and
decrease the others.

- Adjustment mode : Three modes – Cool / Medium / Warm

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* Required Equipment

▪ Remote controller for adjustment
▪ Color Analyzer : CA100+ or CA-210 or same product (should

be used in the calibrated ch by CS-1000)

- LCD TV : CH-9

- PDP TV : CH-10

- White LED TV : CH-14

- ALEF : CH-18

- RGB LED(MNT) : CH-16

▪ Auto W/B adjustment instrument(only for Auto adjustment)

5.2.1. Adjustment of White Balance :
(For Automatic Adjustment)

Co nnectin g diagra m of eq uipment for meas uring (F or
Automatic Adjustment)

1) Set TV in ADJ mode using P-ONLY key (or POWER ON
key)

2) Place optical probe on the center of the display

- It need to check probe condition of zero calibration before

adjustment.

3) Connect RS-232C Cable

4) Select mode in ADJ Program and begin a adjustment.

5) When WB adjustment is completed with OK message,
check adjustment status of pre-set mode (Cool, Medium,
Warm)

6) Remove probe and RS-232C cable.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

(1) RS-232C Command used during auto-adj.

RS-232C COMMAND

CMD DATA ID

wb 00 00 Begin White Balance adj.

wb 00 10 Gain adj.(internal white pattern)

wb 00 1f Gain adj. completed

wb 00 20 Offset adj.(internal white pattern)

wb 00 2f Offset adj. completed

wb 00 Ff End White Balance adj.

(internal pattern disappears )

Explanation

5.2.2. Adjustment of White Balance
(For Automatic Adjustment)

5.2.2.1. Adj. condition and cautionary items

1) Lighting condition in surrounding area surrounding lighting
should be lower 10 lux. Try to isolate adj. area into dark
surrounding.

2) Probe location: Color Analyzer (CA-210) probe should be
within 10cm and perpendicular of the module surface (90+/-

2.5°)

3) Aging time

A. After Aging Start, Keep the Power ON status during 5

Minutes.

B. In case of LCD, Back-light on should be checked using

no signal or Full-white pattern.

5.2.2.2. Equipment

1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
CH14)

2) Adj. Computer (During auto adj., RS-232C proto col is
needed)

3) Adjust Remocon

4) Vi deo Si gnal G enera tor MS PG-92 5F 720p/216 -Gray
(Model: 217, Pattern: 78)

5.2.2.3. Adjustment

1) Set TV in Adj. mode using POWER ON

2) Zero Calibrate the probe of Color Analyzer, then place it on
the center of LCD module within 10cm of the surface.

3) Press ADJ key -> EZ adjust using adj. R/C > 6. White-

Balance then press the cursor to the right (KEY►). When
KEY(►) is pre sse d 216 Gray internal pattern will be

displayed.

4) One of R Gain / G Gain / B Gain should be fixed at 192, and
the rest will be lowered to meet the desired value.

5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of
color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one of 2 Test-pattern:
ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

** R-fix adjustment
Adjust modes (Cool), Fix the R gain to 210 (default data) and

change the others (G/B Gain ).

- Adjust the R gain more than 210 ( If G gain or B gain is less

than 0 , R gain can adjust more than 210 ) and change the
others ( G/B Gain ). Adjust two modes(Medium / Warm), Fix
the one of R/G/B gain to 192 (default data) and decrease the
others.

Only for training and service purposes

- 20 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.3. LED White balance table

5.2.3.1. Cool Mode

1) Purpose : Esp ec ia ll y G- gain fi x adjust leads to th e
lu minance en ha nc em ent. Ad just t he color
temperature to reduce th e de viati on of the
module color temperature.

2) Principle : To a djust t he whi te balan ce witho ut the

saturation, Adjust the G gain more than 172 ( If R
gain or G gain is more than 255 , G gain can
adjust less than 172 ) and change the others (R/B
Gain).

3) Adjustment mode : mode – Cool

5.2.3.2. Medium / Warm Mode

1) Purpose : A djust the color temp erature to reduc e the
deviation of the module color temperature.

2) Principle : To a djust t he whi te balan ce witho ut the

saturation, Fix the one of R/G/B gain to 192
(default data) and decrease the others.

3) Adjustment mode : Two modes – Medium / Warm

▪ Luminance: 204 Gray
▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.271 0.270 13,000K 0.0000

Medium 0.286 0.289 9,300K 0.0000

Warm 0.313 0.329 6,500K 0.0000

* Change reason : When vivid mode, more detail than other

▪ S ta nda rd col or c oo rdi na te a nd tem perat ure u sin g

CA-210(CH-14) – by aging time

(1) Normal line in Korea (From January to February) : LGD

( UB98xxx, UB95/93xxx, UB85xxx, UB83xxx, UC97 Series

models)

1 0-2 286 295 301 314 328 354

2 3-5 284 290 299 309 326 349

3 6-9 282 287 297 306 324 346

4 10-19 279 283 294 302 321 342

5 20-35 276 278 291 297 318 337

6 36-49 274 275 289 294 316 334

7 50-79 273 272 288 291 315 331

8 80-119 272 271 287 290 314 330

9 Over 120 271 270 286 289 313 329

Coordinate

X Y

Aging time

(Min)

Temp △uv

company set.

Cool Medium Warm

X Y X Y X Y

271 270 286 289 313 329

▪ S ta nda rd col or c oo rdi na te a nd tem perat ure u sin g

CA-210(CH-14) – by aging time

(2) Normal line in Korea (From March to December) : : LGD

(UB98xxx, UB95/93xxx, UB85xxx, UB83xxx, UC97 Series
models)

* Normal line in Mexico : LGD (UB98xxx, UB95/93xxx, UB85xxx,

UB83xxx ,UC97 Series models)

Aging time

(Min)

1 0-2 282 289 297 308 324 348

2 3-5 281 287 296 306 323 346

3 6-9 279 284 294 303 321 343

4 10-19 277 280 292 299 319 339

5 20-35 275 277 290 296 317 336

6 36-49 274 274 289 293 316 333

7 50-79 273 272 288 291 315 331

8 80-119 272 271 287 290 314 330

9 Over 120 271 270 286 289 313 329

Cool Medium Warm

X Y X Y X Y

271 270 286 289 313 329

(3) O/S Module(AUO, INX, Sharp, CSOT, BOE)

Cool Medium Warm

X Y X Y X Y

spec 271 270 286 289 313 329

target 278 280 293 299 320 339

-. To check the Coordinate s of White Balance , you have to
measure at the below conditions.

Picture Mode : select Vivid and change
Dynamic Contrast : Off ,
Dynamic Colour : Off,
Clear White : Off

-> Picture Mode change : Vidid -> Vivid(User)

(If you miss the upper condition, the coordinates of W/B can be
lower than the spec.)

Only for training and service purposes

- 21 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.3. Model name & Serial number D/L

5.3.1. Notice

1) Serial number D/L is using of scan equipment.

2) Se tting of scan equipment operated by Manufacturing
Technology Group.

3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0

4) Check the model name In-start menu -> Factory name
displayed (ex 42LV5500-DD)

5) Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LV5500-DD)

5.3.2. Method : Auto

1) Press “Power on” key of service remocon.(Baud rate :
115200 bps)

2) Connect RS232 Signal Cable to RS-232 Jack

3) Write Serial number by use RS-232.

4) Must check the serial number at Instart menu.

5.4.2. Check the menu on in-start

5.3.3. Method : Manual

* If the TV set is downl oad ed By OTA or Servi ce ma n,

Sometimes model name or serial number is initialized.

(Not always) It is impossible to download by bar code scan,

so It need Manual download.

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘6.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like photo.

5.4. Wi-Fi MAC Address Check

5.4.1. Using RS232 Command

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

5.5. LAN Inspection

5.5.1. LAN Port connection with PCB

1) Network setting at MENU Mode of TV

2) Setting automatic IP

3) Setting state confirmation

4) If automatic setting is finished, you confirm IP and MAC
Address

5.6. WIDEVINE Key Inspection

1) Confirm Key input Data at the “IN START” MENU Mode

Only for training and service purposes

- 22 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.7. Local Dimming Inspection (Optional)

1) Press ‘TILT” key of the Adj. R/C and check moving patterns.
The black bar patterns moves from top left to bottom right. If
local dimming function does not work, a whole screen
shows full white.

5.8. Motion Remote controller Inspection

1) Equipment : Motion remote controller for test, IR-KEY­CODE remote controller for test Check battery before test.
(Recommend : Change battery for every Lot.)

2) Process

- If you select the ‘start key(wheel)’ on the controller, you can

pairing with the TV SET.

- You can check the cursor on the TV Screen, when select the

‘Wheel Key’ on the controller

- You must remove the pairing with the TV Set by select ‘Back

+ Home Key’ on the controller

5.9. 3D function test

1) Equipment : Pattern Generator MSHG-600, MSPG-6100

[SUPPORT HDMI1.4, HDMI mode 872, pattern No. 83

2) Process

(A) Please input 3D test pattern like below (HDMI mode NO.

872 , pattern No.83)

(C) Don’t wear a 3D Glasses, Check the picture like below.

5.10. HDMI ARC Function Inspection

5.10.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

5.10.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

(B) When 3D OSD appear automatically , then select green

button.

Only for training and service purposes

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

* Remark: Inspect in Power Only Mode and check SW version

in master equipment

- 23 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.11. Eye-Q Green Inspection Guide
(Change to Motion EYE care)

1) Turn on the TV set.

2) Press “EYE” button on the Adjustment remote controller.

3) Block the Intelligent Sensor module on the front C/A about 6
seconds. When the “Sensor Data” is lower than 20, you can
see the “OK” message

=> If it doesn’t show “OK” message, the Sensor Module is

defected one. You have to replace that with a good one.

5.13. Camera Function Inspection

(1) Objective : To check how it connects between Camera and

PCBA normally, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.
i) Slide Camera Up
ii) Camera’s Preview picture appears on TV Set
iii) Slide Camera Down

5.14. PIP/ W&R Function Inspection

4) After check the “OK” message come out, take out your hand
from the Sensor module.

=> Check “Sensor Data” value change from “0” to “300” or not.

If it doesn’t change the value, the sensor is also defected
one. You have to replace it.

5.12. AUDIO

No Item Min Typ Max Unit Remark

1 Audio practical

max Output, L/R
(Distortion=10%
max Output)

2

Speaker

(8Ω Impedance)

*Measurement condition:
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)

9.0 10.0 12.0 W Measurement
condition

8.5 8.9 9.8 Vrms

10.0 15.0 W Measurement
condition

(1) Objective : To check the connection between sub tuner and

PCBA, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.

1) Press exit key of the Adj. R/C and Press PIP key.

2) Check that the SUB TUNER pop up window on the TV
Set.

3) Check that the normal operation (picture, sound) of DTV
on the TV Set.

Only for training and service purposes

- 24 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.15. Manual ADC Calibration(Optional)

5.15.1. Adjust method

(1) Enter Service Mode by pushing “ADJ” key

(2) Enter ADC Calibration by pushing “►” key at “9. ADC

Calibration”

(3) Select [Reset] button by pressing Enter key
(4) Change “OTP” to “Internal” by pushing “►” key
(5) Select [Start] button by pressing Enter key, then it will

operate ADC adjustment.

5.16.3. Check point

1) Test voltage

(A) 3 Poles

- GND: 1.5KVac/min at 100mA

- SIGNAL: 3KVac/min at 100mA

2) TEST time: 1 second

3) TEST POINT

(B) 3 Poles

- GND Test = POWER CORD GND and SIGNAL CABLE

GND.

- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.

4) LEAKAGE CURRENT: At 0.5mArms

5.16. GND and Hi-Pot test

5.16.1. GND & HI-POT auto-check preparation

1) Check the POWER CABLE and SIGNAL CABE insertion
condition

5.16.2. GND & HI-POT auto-check

1) Pallet moves in the station. (POWER CORD / AV CORD is
tightly inserted)

2) Connect the AV JACK Tester.

3) Controller (GWS103-4) on.

4) GND Test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, execute next process (Hi-pot test).

(Remove A/V CORD from A/V JACK BOX)

5) HI-POT test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, GOOD Lamp on and move to next

process automatically.

Only for training and service purposes

- 25 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

400

410

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

900

570

LV1

521

540

530

820

522

121

200T

*Option

502

120

503

500

501

504

A10

Set + Stand

200

Only for training and service purposes

- 26 -

A2

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

VCC

Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

WP

SCL

SDA

+3.3V_NORMAL

C103

0.1uF

+3.3V_NORMAL

OPT

R157 4.7K

OPT

R158 4.7K

Write Protection

- Low : Normal Operation

- High : Write Protection

R113 33

R114 33

OPT

R163 4.7K

R161 4.7K

R165 4.7K

OPT

R164 4.7K

R162 4.7K

R166 4.7K

LED1
SPI_DI
LED0
PWM_PM

I2C_SCL1

I2C_SDA1

NVRAM

IC102

AT24C256C-SSHL-T

EAN61133501

A0

1

2

3

4

A0’h

8

7

6

5

A1

A2

GND

CHIP CONFIG

CHIP_CONFIG[3:0]
{LED1, SPI_DI,LED0, PWM_PM}

Value Mode Description
4’b1000 SB51_ExtSPI 51 boot from SPI
4’b1001 HEMCU_ExtSPI ARM boot from SPI
4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC
4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND
4’b1100 DBUS for test only
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication
4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication
4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;

LM14 HW Option

+3.3V_NORMAL

10K

BIT0
BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT0_1

R104 10K

BIT0_0

R103 10K

BIT1_1

R108

10K

BIT1_0

R107

BIT2_1

R110 10K

BIT2_0

R109 10K

BIT3_1

BIT3_0

BIT5_1

BIT4_1

BIT6_1

R116 10K

BIT4_0

R115 10K

R118 10K

BIT5_0

R117 10K

R120 10K

BIT6_0

R119 10K

R112 10K

R111 10K

Mstart Debug

MSTAR_DEBUG_OLD

MSTAR_DEBUG_NEW

P103

12507WS-04L

1

2

3

4

5

DDCA_CK

DDCA_DA

P101

12505WS-04A00

1

2

3

4

5

BIT7_1

BIT8_1

R122 10K

R124 10K

BIT7_0

BIT8_0

R121 10K

R123 10K

RS232C_Debug

UART_4PIN_WAFER

P102

12507WS-04L

BIT(0/1) DVB

01

10

11

BIT(2/3)

00

01

10

11

BIT4

BIT5

1

2

3

4

5

FRC_FLASH_WP

MUX_EN

+3.3V_NORMAL

URSA9_CONNECT

Don’t use! LM14+URSA9: GPIO AH27/AJ27

JP

TW/COL

CN/HK

T2/C/S2/ATV_EXT

T2/C/S2/AT

Vx1 Division

Resolution

+3.5V_ST

ATSC

US

KR

EU

AJJA

EU/CIS AJJA TW/COL CN/HK

T/C

T2/C

2-Division Non-Division

* BIT4: LM14 TX Division OPT

(LM14+URSA9: Non Division)

JP

CI

ATV_INT

T/C Default00ATSC_PIPBRATSC_PIP

T2/C_PIP

FHD UHD

DTV_EXT

T2/C

T2/C/S2

HighLow

SOC_RX

SOC_TX

R189

R188

10K
OPT

10K
OPT

PWM_DIM2

RF_SWITCH_CTL

AMP_RESET_N

I2C for AMP&MODULE

CVBS_OUT_SEL

+3.3V_NORMAL

R181

10K
OPT

DDCA_CK

R182

DDCA_DA

10K

I2C_SCL6
I2C_SDA6

BIT5
BIT6
BIT7
BIT8

/TU_RESET1
/TU_RESET2

BIT0
BIT1
BIT2
BIT3
BIT4

R180 0

I2C_SCL_MICOM_SOC
I2C_SDA_MICOM_SOC

M_RFModule_RESET

ATV_SOC

ATV_EXTJPATV_EXT

BIT6

BIT7

BIT8

+3.3V_TUNER

R147

1.8K

PWM_DIM

PWM_PM

I2C_SCL7

I2C_SDA7

SPI_DI

SOC_TX
SOC_RX

I2C_SCL1
I2C_SDA1

I2C_SCL4
I2C_SDA4

I2C_SCL5
I2C_SDA5

I2C_SCL2
I2C_SDA2

VID0

VID1
LED0
LED1

KR North.AM BR

MODEL

Reserved

Reserved

F10

F9
E11
F12

E9

H6

G5

G4

B3

G6

A5

C5

A4

B5

B6

C6

H4

H5

E6

D6

F7

E7

D7

E8

D9

F8

T6

T5

B4

A3

AG29
AH29
AJ29
AG28
AH28
AJ28
AH27
AJ27

U4

U5
A10
C10

V6

V5

U6

T4

W5

W6

E12
D12
E13
F13
F11

ATV_SOC

LM14+URSA9 LM14 ONLY

I2C PULL UP

+3.3V_LNA_TU

+3.3V_NORMAL

R127

1.8K

R128

1.8K

R129

R148

1.8K

1.8K

IC100

LGE4331

PWM0/GPIO150
PWM1/GPIO151
PWM2/GPIO152
PWM3/GPIO153
PWM_PM/GPIO7

SAR0/GPIO43
SAR1/GPIO44
SAR2/GPIO45
SAR3/GPIO46
SAR5

SPI_CK/GPIO1
SPI_DI/GPIO2
SPI_DO/GPIO3
SPI_CZ0/GPIO0
SPI_CZ1/GPIO_PM6/GPIO16
SPI_CZ2/GPIO_PM10/GPIO20

DDCA_CK/UART0_RX/GPIO8
DDCA_DA/UART0_TX/GPIO9

TX1/GPIO60
RX1/GPIO61
TX2/GPIO62
RX2/GPIO63
TX3/GPIO64
RX3/GPIO65
TX4/GPIO69
RX4/GPIO70
TX5/GPIO87
RX5/GPIO88

GPIO66
GPIO67

TCON0/GPIO155
TCON1/GPIO156
TCON2/GPIO157
TCON3/GPIO158
TCON4/GPIO159
SPI1_CK/GPIO104
VSYNC_LIKE/GPIO103
SPI1_DI/GPIO105

GPIO81/SCK0
GPIO82/SDA0
DDCR_CK/GPIO52
DDCR_DA/GPIO51
GPIO83/SCK4
GPIO84/SDA4
GPIO85/SCK5
GPIO86/SDA5
GPIO89/SCK2
GPIO90/SDA2

VID0/GPIO48
VID1/GPIO49
LED0/GPIO29
LED1/GPIO30
WOL/GPIO50

ATV_INT

Default

DTV_INT

HighLow

R133

1.8K

R134

1.8K

1.8K

R130

EJ_RSTZ/GPIO53

EJ_TRSTZ/GPIO54

EJ_TCK/GPIO55
EJ_TMS/GPIO56
EJ_TDI/GPIO57
EJ_TDO/GPIO58

EJ_DINT/GPIO59

PCM2_CEN/GPIO112
PCM2_IRQA/GPIO113
PCM2_WAIT/GPIO114

PCM2_RESET/GPIO115

GPIO_PM0/GPIO10
GPIO_PM2/GPIO12
GPIO_PM3/GPIO13
GPIO_PM4/GPIO14
GPIO_PM7/GPIO17
GPIO_PM8/GPIO18

GPIO_PM9/GPIO19
GPIO_PM13/GPIO23
GPIO_PM17/GPIO27
GPIO_PM18/GPIO28

GPIO_PM1/GPIO11

GPIO_PM5/GPIO15
GPIO_PM11/GPIO21
GPIO_PM12/GPIO22

R135

1.8K

R136

1.8K

R131

B2M/VBY7N

B2P/VBY7P
BCKM/VBY6P
BCKP/VBY6P

B3M/VBY5P

B3P/VBY5P

B4M/VBY4N

B4P/VBY4P

A0M/VBY3N

A0P/VBY3P

A1M/VBY2N

A1P/VBY2P

A2M/VBY1N

A2P/VBY1P
ACKM/VBY0N
ACKP/VBY0P

A3M/LOCKN
A3P/HTTPDN

AV_LINK

I2C_SCL_MICOM

1.8K

R132

1.8K

R183

TEST

1.8K

IC100

JTAG

R105

JTAG

1K

R106

R153 10K

R152 10K

LGE4331

Jtag I/F
For Main

TRST_N0
TDI0
TDO0
TMS0
TCK0
SOC_RESET

OPT

R169 10K

R159 10K

R154 10K

R170 10K

TS1DATA_[0]/GPIO194
TS1DATA_[1]/GPIO193
TS1DATA_[2]/GPIO192
TS1DATA_[3]/GPIO191
TS1DATA_[4]/GPIO190
TS1DATA_[5]/GPIO189
TS1DATA_[6]/GPIO188
TS1DATA_[7]/GPIO187

TS1CLK/GPIO184

TS1VALID/GPIO186

TS1SYNC/GPIO185

TS0DATA_[0]/GPIO173
TS0DATA_[1]/GPIO174
TS0DATA_[2]/GPIO175
TS0DATA_[3]/GPIO176
TS0DATA_[4]/GPIO177
TS0DATA_[5]/GPIO178
TS0DATA_[6]/GPIO179
TS0DATA_[7]/GPIO180

TS0CLK/GPIO183

TS0VALID/GPIO181

TS0SYNC/GPIO182

TS2DATA_[0]/GPIO207

TS2CLK/GPIO210

TS2SYNC/GPIO209

TS2VALID/GPIO208

VIFP
VIFM

SIFP
SIFM

IF_AGC

TGPIO0/GPIO169
TGPIO1/GPIO170
TGPIO2/GPIO171
TGPIO3/GPIO172

R160 10K

/TU_RESET1
/TU_RESET2

RF_SWITCH_CTL
AMP_RESET_N

TCON_I2C_EN

/USB_OCD2

USB_CTL2

/USB_OCD3

USB_CTL3

M_RFModule_RESET

PCM_5V_CTL

AJ18
AH19
AJ20
AG20
AH21
AH18
AG21
AJ21
AG19
AH20
AG18

AH13
AG17
AJ17
AH14
AG14
AG16
AG15
AH15
AJ15
AH17
AH16

AJ26
AG26
AH26
AG25

AL7
AM7

AL6
AK7

AM5

AM8
AL8
AL5
AK6

TPI_DATA[0]
TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]

TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]

TPI_DATA[7]

TPI_CLK
TPI_VAL

FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]

FE_DEMOD1_TS_DATA[6]
FE_DEMOD1_TS_DATA[7]

TPI_SOP

Close to MSTAR

R140 100

R141 100

/USB_OCD2
USB_CTL2
/USB_OCD3
USB_CTL3

URSA9 VIDEO/OSD LOCKn

TPI_DATA[0-7]

FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_SYNC

C118 0.1uF

C119 0.1uF

C120 0.1uF
C121 0.1uF

ANALOG SIF

Close to MSTAR

LOCKAn_Video

LOCKAn_OSD

FE_DEMOD1_TS_DATA[0-7]

OPT

C122

OPT
C123
33pF

R144 47
R145 47

BLM18PG121SN1D

R142
10K

R143

0

LOCKAn_Video

+3.3V_NORMAL

R191 10K

22

R173

VBY1_LOCK_LED

220

R174

E

VBY1_LOCK_LED

MMBT3906(NXP)

VBY1_LOCK_LED

B

C

LOCKAn_OSD

+3.3V_NORMAL

10K

R192

22

R139

LD1 01

VBY1_LOCK_LED

220

R172

E

VBY1_LOCK_LED

Q101

MMBT3906(NXP)

VBY1_LOCK_LED

B

C

OPT
C126
33pF

C124
1000pF
OPT

+3.3V_NORMAL

L100

C125

0.1uF

C127

0.047uF
25V

LD1 00

SML -512U W

VBY1_LOCK_LED

Q100

SML -512U W

VBY1_LOCK_LED

DTV_IF

R146
300
OPT

IF_P

IF_N

TU_SIF

IF_AGC

AE32

B0M
B0P
B1M
B1P

A4M
A4P

V-BY-ONE

AF30
AF32

MSB/LSB swap

AF31
AG32
AG31
AG30
AH31
AJ31
AJ32
AJ30
AK32

AK31
AK30
AL31
AL30
AM30
AL29
AM29
AK28
AM28
AL28
AK27
AL27

R125

10K

F5
F4
D5
F6
D4
E5
E4

AG22
AH22
AG23
AH23

J5
R6
P4

R190

N6
N5
J6
K4
L5
L6
L4

P5
P6
K6
K5

R5
G7

33

R184

1.8K

R185

1.8K

R186

1.8K

R126

10K

TRST_N0

TCK0
TMS0
TDI0
TDO0

R13733
R138

0

TXVBY1_7N
TXVBY1_7P
TXVBY1_6N
TXVBY1_6P
TXVBY1_5N
TXVBY1_5P
TXVBY1_4N
TXVBY1_4P

TXVBY1_3N
TXVBY1_3P
TXVBY1_2N
TXVBY1_2P

LOCKAn_Video
HTPDAn_Video
LOCKAn_OSD
HTPDAn_OSD

47K

R177

SIL9617_INT
AV1_CVBS_DET
HP_DET
SC_DET

COMP1_DET

L_DIM_EN

PCM_5V_CTL

5V_DET_HDMI_1
5V_DET_HDMI_2

R9531_RESET

5V_DET_HDMI_3

R9531_FLASH_WP

/USB_OCD1
USB_CTL1
URSA_RESET_SoC
SIL9617_RESET

I2C_SDA_MICOM_SOCI2C_SDA_MICOM
I2C_SCL_MICOM_SOC

I2C_SDA8
I2C_SCL8

I2C_SDA7
I2C_SCL7
I2C_SDA6
I2C_SCL6
I2C_SDA1
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC

I2C_SDA4
I2C_SCL4

I2C_SDA5
I2C_SCL5

I2C_SDA2
I2C_SCL2

EB_DATA[0-7]

EB_ADDR[0-14]

Place capacitor
Close to the wafer

HTPDAn_Video
HTPDAn_OSD

CAM_IREQ_N

CAM_CD1_N
PCM_RESET
CAM_REG_N

CAM_WAIT_N

EMMC_DATA[0-7]

R175
22

I2C for SIL9617

I2C for Main Amp & LCD Module

I2C for R9531AN

I2C for NVRAM

I2C for URSA9 (URSA9 Only)

I2C for tuner

I2C for tuner&LNB

R176

TCON_I2C_EN

HDMI_MUX_SEL

10K

EB_OE_N
EB_BE_N1
/PCM_CE1

EB_WE_N

EB_BE_N0

EMMC_RST
EMMC_CMD
EMMC_CLK

C102

0.1uF
JTAG

12505WS-10A00

P100

JTAG

1

2

3

4

5

6

7

8

9

10

11

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]
EB_DATA[4]
EB_DATA[5]

EB_DATA[6]
EB_DATA[7]

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]
EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]
EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]
EB_ADDR[12]

EB_ADDR[13]
EB_ADDR[14]

EMMC_DATA[1]
EMMC_DATA[2]
EMMC_DATA[6]
EMMC_DATA[5]
EMMC_DATA[4]
EMMC_DATA[3]

EMMC_DATA[0]
EMMC_DATA[7]

+3.3V_NORMAL

AL21

PCMDATA[0]/GPIO145

AK22

PCMDATA[1]/GPIO146

AK21

PCMDATA[2]/GPIO147

AH11

PCMDATA[3]/GPIO117

AH10

PCMDATA[4]/GPIO118

AG13

PCMDATA[5]/GPIO119

AJ9

PCMDATA[6]/GPIO120

AJ12

PCMDATA[7]/GPIO121

AM23

PCMADR[0]/GPIO144

AK17

PCMADR[1]/GPIO143

AM20

PCMADR[2]/GPIO141

AL20

PCMADR[3]/GPIO140

AK19

PCMADR[4]/GPIO139

AM19

PCMADR[5]/GPIO137

AL22

PCMADR[6]/GPIO136

AM17

PCMADR[7]/GPIO135

AL15

PCMADR[8]/GPIO129

AK15

PCMADR[9]/GPIO127

AG11

PCMADR[10]/GPIO123

AG12

PCMADR[11]/GPIO125

AM22

PCMADR[12]/GPIO134

AL16

PCMADR[13]/GPIO130

AM16

PCMADR[14]/GPIO131

AL17

PCMIRQA/GPIO133

AG10

PCMOEN/GPIO124

AJ14

PCMIORD/GPIO126

AK18

PCMCEN/GPIO122

AK16

PCMWEN/GPIO132

AH12

PCMCD/GPIO149

AL18

PCMRST/GPIO148

AK20

PCMREG/GPIO142

AJ11

PCMIOWR/GPIO128

AL19

PCMWAIT/GPIO138

AK24

EMMC_RSTN/GPIO204

AK23

EMMC_CMD/GPIO206

AL24

EMMC_CLK/GPIO205

AL26

NAND_ALE/GPIO201

AG24

NAND_WPZ/GPIO200

AK26

NAND_CEZ/GPIO195

AM26

NAND_CLE/GPIO197

AM25

NAND_REZ/GPIO198

AL25

NAND_WEZ/GPIO199

AK25

NAND_RBZ/GPIO202

AH25

NAND_CE1Z/GPIO196

AH24

NAND_DQS/GPIO203

AJ24

PCM2_CD/GPIO116

JTAG

1K

1K

R1001KR102

1K

JTAG

R101

GPIO PULL UP

+3.3V_NORMAL

OPT

R171 10K

R151 10K

R149 10K

R150 10K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

UB83

LM14 SYSTEM

2013-10-28

01

0.22uF

Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

0.22uF

+1.1V_AVDDL_MOD

+1.1V_VDDC_CPU

+3.3V_AVDD_AU33

+3.3V_AVDD_DMPLL

+3.3V_VDDP33

VDDC15_M0

C2000.1uF

C2010.1uF
C2020.22uF

0.22uF

C2030.1uF
C2040.1uF

C205

C206

C2070.22uF

0.22uF

C2080.1uF
C2090.1uF

+1.1V_VDDC

+1.1V_DVDD_DDR

C210
1uF
25V

+1.1V_DVDD_DDR

+3.3V_AVDD33

+3.3V_VDDP33

DVDD18_EMMC

VDDC15_M0

AVDD5V_MHL

C2110.22uF

C2120.22uF

C213

C2140.22uF

C2150.22uF

C2160.22uF

C217

C2180.22uF

C2190.22uF
C2200.22uF

+1.1V_AVDDL_MOD

AB10
AB11
AC10
AC11
AA15
AB15
AC15
AB16

AA20
AA21
AA22
AA23
AA24
AB20
AB21
AB22
AB23
AB24
AC21
AC22
AC23
AC24

AF10

AF15
AF14
AE14
AF12

AF17
AF18

AB31
AB32
AD31
AD32

AE31
AE30

K10
K11
L10
L11
M10
M11
T10
T11
U10
U11
V10
V11

W21
W20

M12
M13

Y20
Y21
Y22
Y23
Y24

L7

Y19

N19
N20
P19
P20

P7
R7
U7
V7

W7
AA7
AB7
AF7
AE7

L19
L20
L21
M19
M20
M21

L22
M22
N21
N22
P21
P22

AF6

D3

A11
B11
A13
B13

M17
M18
L17
L18

R22
T22
R21
T21

IC100

LGE4331

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_14
VDDC_15
VDDC_17
VDDC_18
VDDC_13
VDDC_16
VDDC_19
AVDDV_DVI

AVDDL_MOD_1
AVDDL_MOD_2

AVDDL_SSUSB_1
AVDDL_SSUSB_2

VDDC_CPU_1
VDDC_CPU_2
VDDC_CPU_3
VDDC_CPU_4
VDDC_CPU_5
VDDC_CPU_6
VDDC_CPU_7
VDDC_CPU_8
VDDC_CPU_9
VDDC_CPU_10
VDDC_CPU_11
VDDC_CPU_12
VDDC_CPU_13
VDDC_CPU_14
VDDC_CPU_15
VDDC_CPU_16
VDDC_CPU_17
VDDC_CPU_18
VDDC_CPU_19

DVDD_NODIE

VSENSE

DVDD_DDR_1
DVDD_DDR_2
DVDD_DDR_3
DVDD_DDR_4

AVDD_NODIE
AVDDP3P_ETH
AVDDP3P_USB
AVDDP3P_DVI_1
AVDDP3P_DVI_2
AVDDP3P_DADC
AVDDP3P_ADC
AVDD_AU33
AVDD_EAR33
AVDD_DMPLL

AVDD_MOD
AVDD_PLL
AVDD_LPLL
VDDP_1

VDDP_3318_A
VDDP_2

AVDD_DDR0_1
AVDD_DDR0_2
AVDD_DDR0_3
AVDD_DDR0_4
AVDD_DDR0_5
AVDD_DDR0_6

AVDD_DDR1_1
AVDD_DDR1_2
AVDD_DDR1_3
AVDD_DDR1_4
AVDD_DDR1_5
AVDD_DDR1_6

AVDD_HDMI_5V_PC

GND_EFUSE

AVDD04_DDR_A_1
AVDD04_DDR_A_2
AVDD11_DDR_A_1
AVDD11_DDR_A_2

AVDD04_DDR_B_1
AVDD04_DDR_B_2
AVDD11_DDR_B_1
AVDD11_DDR_B_2

AVDD04_DDR_A_3
AVDD04_DDR_A_4
AVDD11_DDR_A_3
AVDD11_DDR_A_4

AVDD04_DDR_B_3
AVDD04_DDR_B_4
AVDD11_DDR_B_3
AVDD11_DDR_B_4

AVDDL_MOD_3
AVDDL_MOD_4

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140

IC100

LGE4331

N15

A14
A17
A20
A23
A26
A29
B12
B14
B31
C3
C11
C12
C13
C14
C31
C32
D17
D20
D24
D27
D31
D32
E1
E29
E30
E31
F21
F23
F24
F25
F26
F27
F28
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G22
G23
G24
G25
G26
G27
G30
H3
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
K7
K8
K9
K12
K13
K14
K15
K16
K18
K19
K21
K23
K24
K25
K26
L8
L9
L12
L13
L14
L15
L16
L24
L25
L26
L29
L32
M7
M8
M9
M14
M15
M16
M23
M24
M25
M26
N7
N8
N9
N10
N11
N12
N13
N14

N16
N17
N18
N23
N24
N25
N26

P10
P11
P12
P13
P14
P15
P16
P17
P18
P23
P24
P25
P26
P29
P32

R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R23
R24
R25
R26

T12
T13
T14
T15
T16
T17
T18
T19
T20
T23
T24
T25
T26

U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U29
U32

V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26

W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W22
W23
W24
W25
W26

Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y25
Y26
Y29
Y32
AA8
AA9

AA10

GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148

P8

GND_149

P9

GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165

R8

GND_166

R9

GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182

T7

GND_183

T8

GND_184

T9

GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198

U8

GND_199

U9

GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217

V8

GND_218

V9

GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234

W8

GND_235

W9

GND_236
GND_237
GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251

Y7

GND_252

Y8

GND_253

Y9

GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264
GND_265
GND_266
GND_267
GND_268
GND_269
GND_270

GND_271
GND_272
GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293
GND_294
GND_295
GND_296
GND_297
GND_298
GND_299
GND_300
GND_301
GND_302
GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329
GND_330
GND_331
GND_332
GND_333
GND_334
GND_335
GND_336
GND_337
GND_338
GND_339
GND_340
GND_341
GND_342
GND_343
GND_344
GND_345
GND_346
GND_347
GND_348
GND_349
GND_350
GND_351
GND_352
GND_353
GND_354
GND_355
GND_356
GND_357
GND_358
GND_359
GND_360
GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368
GND_369
GND_370
GND_371
GND_372
GND_373
GND_374
GND_375
GND_376
GND_377
GND_378
GND_379
GND_380
GND_381
GND_382
GND_383
GND_384
GND_385
GND_386
GND_387
GND_388
GND_389
GND_390
GND_391
GND_392
GND_393
GND_394
GND_395
GND_396
GND_397
GND_398
GND_399

AA11
AA12
AA14
AA16
AA17
AA18
AA19
AA25
AA26
AB8
AB9
AB12
AB13
AB14
AB17
AB18
AB19
AB25
AB26
AB27
AB28
AB29
AB30
AC7
AC8
AC9
AC12
AC13
AC14
AC16
AC17
AC18
AC19
AC20
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE8
AE9
AE10
AE11
AE12
AE13
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AF1
AF2
AF8
AF9
AF13
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AG1
AG2
AG3
AG7
AG8
AG9
AG27
AH3
AH4
AH5
AH6
AH7
AH8
AH9
AH30
AJ6
AJ7
AJ8
AJ23
AK5
AK8
AK29
AL2
AL3
AL4
AL23
AM14

+1.1V_Bypass Cap

+1.1V_CORE

MLB-201209-0120P-N2

C221
10uF
10V

+1.15V_CPU

C284
10uF
10V

+3.3V_Bypass Cap

+3.3V_NORMAL

C222
10uF
10V

+1.5V_Bypass Cap

+1.5V_DDR

VDDC15_M0

L200

BLM18PG121SN1D

C223 0.1uF

L201

5A

+1.1V_VDDC_CPU

L202

BLM18SG700TN1D

4A

C224 0.1uF

C225 0.1uF

+1.1V_VDDC

C226 0.1uF

C228
10uF
10V

C229
10uF
10V

L206
BLM18PG121SN1D

2A

L203

BLM18PG121SN1D

2A

L204

BLM18PG121SN1D

2A

L205

BLM18PG121SN1D

2A

C227 0.1uF

C230 0.1uF

0.1uF

0.1uF

C242

C232

C235

4.7uF

1uF

C233

C236

C243

+3.3V_AVDD_DMPLL

+3.3V_AVDD33

C238 0.1uFC239 0.1uF

+3.3V_AVDD_AU33

+3.3V_VDDP33

C231 0.1uF

C234 0.1uF

C237
10uF
10V

C240
10uF
10V

0.1uF

0.1uF

C241 0.1uF

C248

C249

C244 0.1uF

C245 0.1uF

0.1uF

0.1uF

C250

0.1uF

0.1uF

C251

0.1uF

C246

C247 0.1uF

C254

C255

0.1uF

0.1uF

C253

0.1uF

0.1uF

C252

0.1uF

C256

C258

C259

0.1uF

0.1uF

0.1uF

C260

0.1uF

C257

C262

C263

0.1uF

0.1uF

0.1uF

C264

0.1uF

C261

C266

C267

C265

0.1uF

0.1uF

0.1uF

C273

C270

0.1uF

0.1uF

0.1uF

C274

C271

0.1uF

0.1uF

C272

C268

0.1uF

0.1uF

C269

GND JIG POINT

5V_HDMI_3

+1.1V_VDDC

JP202

R200

10

JP203

AVDD5V_MHL

L208

BLM18SG700TN1D

4A

L207

BLM18PG121SN1D

2A

JP204

JP205

+1.1V_AVDDL_MOD

C275 0.1uF

C277 0.1uF

+1.1V_DVDD_DDR

C278 0.1uF

C276 0.1uF

C279 0.1uF

C280 0.1uF

C281 0.1uF

C282 0.1uF

C283 0.1uF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

UB83

LM14 POWER

2013-10-28

02

R336

Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

R335
100

100

OPT

C335

0.01uF

C334

0.01uF

HP_LOUT

HP_ROUT

Close to Main soc

HP_LOUT_MAIN

R333

22K

OPT

22K

R334

HP_ROUT_MAIN

OPT

OPT

Clock for MSD808KWD

MAIN Clock(24Mhz)

10pF

C330

10pF

C331

System Clock for Analog block(24Mhz)

GND_1

2

3

X-TAL_2

X-TAL_1

1

4

GND_2

24MHz

X300

R324

1M

XIN_MAIN

XOUT_MAIN

HDMI_RX0-

HDMI_RX0+

HDMI_RX1-

HDMI_RX1+

HDMI_RX2-

HDMI_RX2+
HDMI_CLK­HDMI_CLK+

HDMI_TX_DDC_CLK
HDMI_TX_DDC_SDA

HDMI Input from URSA9

I2C_SCL8
I2C_SDA8

SPDIF_OUT

R300 22
R301

IC100

LGE4331

V2

RXA0N

W3

RXA0P

W2

RXA1N

Y3

RXA1P

Y2

RXA2N

Y1

RXA2P

V3

RXACKN

V1

RXACKP

AC4

22

DDCDA_DA/GPIO36

AD5

HOTPLUGA/GPIO31

R2

RXB0N

T3

RXB0P

T2

RXB1N

U3

RXB1P

U2

RXB2N

U1

RXB2P

R3

RXBCKN

R1

RXBCKP

AC6

DDCDB_CK/GPIO37

AB4

DDCDB_DA/GPIO38

AC5

HOTPLUGB/GPIO32

J2

RXC0N

K3

RXC0P

K2

RXC1N

L3

RXC1P

L2

RXC2N

L1

RXC2P

J3

RXCCKN

J1

RXCCKP

Y4

DDCDC_CK/GPIO39

Y5

DDCDC_DA/GPIO40

AA5

HOTPLUGC/GPIO33

M2

RXD0N

N3

RXD0P

N2

RXD1N

P3

RXD1P

P2

RXD2N

P1

RXD2P

M3

RXDCKN

M1

RXDCKP

AA6

DDCDD_CK/GPIO41

AB6

DDCDD_DA/GPIO42

AB5

HOTPLUGD/GPIO34

W4

CEC/GPIO5

D10

SPDIF_IN/GPIO94

E10

SPDIF_OUT/GPIO95

DDCDA_CK/GPIO35

AE4

LINE_OUT_0L
LINE_OUT_0R

I2S_IN_BCK/GPIO92

I2S_IN_SD/GPIO93
I2S_IN_WS/GPIO91

I2S_OUT_BCK/GPIO98
I2S_OUT_MCK/GPIO97

I2S_OUT_WS/GPIO96

I2S_OUT_SD/GPIO99
I2S_OUT_SD1/GPIO100
I2S_OUT_SD2/GPIO101
I2S_OUT_SD3/GPIO102

GPIO_PM14/GPIO24
GPIO_PM15/GPIO25
GPIO_PM16/GPIO26

LINE_IN_0L
LINE_IN_0R
LINE_IN_2L
LINE_IN_2R

EAR_OUT_L
EAR_OUT_R

ARC0

AUVAG
AUVRM

AJ2
AJ1
AK3
AK1

AH2
AJ3
AJ4
AJ5

Y6

AK2
AK4

B10
C9
B9

A7
C7
A8
B8
C8
B7
C4

N4
M5
M6

2.2uF

2.2uF

2.2uF

2.2uF

R304
22

R305
22

22pF

C307

C308
22pF

C302
C303
C304
C305

R306
22

R307
22

C332
10uF
10V

C309
22pF

C310
22pF

MHL_DET_LM14

/MHL_OCP

COMP1/AV1/DVI_L_IN
COMP1/AV1/DVI_R_IN
SC_L_IN
SC_R_IN

SCART_Lout
SCART_Rout
HP_LOUT
HP_ROUT

HDMI_ARC

1uF

C333

BLM 18PG1 21SN 1D

AUD_SCK
AUD_MASTER_CLK
AUD_LRCK
AUD_LRCH

L30 0

DTV/MNT_V_OUT

TU_CVBS

SC_CVBS_IN

AV1_CVBS_IN

SC_R

SC_G

SC_B

SC_ID
SC_FB

COMP1_Pr

COMP1_Y

COMP1_Pb

C311

1000pF

OPT

R308 68

50V

R312 68
R313 33

68

R314

33

R315
R316 68
R317 33 C321

R318 68
R319 33

68

R320

33

R321
R322 68
R323 33

C312 0.047uF

R309 33
R310 33
R311 33

C316

0.047uF
C317

0.047uF
C318

0.047uF
C319

0.047uF
C320

0.047uF

0.047uF
C322

1000pF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF

0.047uF
1000pF

C313 0.047uF
C314 0.047uF
C315 0.047uF

C323
C324
C325
C326
C327
C328
C329

AC2
AC3
AB2
AB3
AA1
AA3
AA2
AE5
AD6

AF3
AE2
AE3
AD2
AD3
AC1
AD1

AE6

AF4
AF5
AG5

AG6

RIN0M
RIN0P
GIN0M
GIN0P
BIN0M
BIN0P
SOGIN0
HSYNC0
VSYNC0

RIN1M
RIN1P
GIN1M
GIN1P
BIN1M
BIN1P
SOGIN1

VCOM

CVBS0
CVBS1
CVBS2

CVBSOUT1

IC100

LGE4331

ET_TX_CLK/GPIO76

ET_COL/GPIO72
ET_MDC/GPIO78

ET_TX_EN/GPIO75
ET_TXD[0]/GPIO74
ET_TXD[1]/GPIO73
ET_RXD[0]/GPIO77
ET_RXD[1]/GPIO80

ET_MDIO/GPIO79

HWRESET

XOUT

IRIN

USB0_DM
USB0_DP
USB1_DM
USB1_DP
USB2_DM
USB2_DP
USB3_DM
USB3_DP

USB_SSTXP
USB_SSTXN

USB_DM

USB_DP
USB_SSRXP
USB_SSRXN

AM13

TN

AK13

TP

AK12

RN

AL13

RP

AM11
AL9
AK9
AL12
AL11
AK11
AM10
AK10
AL10

H2

AM3

XIN

AM4

H1

R325

2.2

G2

R326

2.2

G3
AL14
AK14
F2
F3
E3
F1

B2
C2
C1
D2
D1
E2

R329

2.2

R332

2.2

R330

2.2

R327

2.2

R331

2.2

R328

2.2

EPHY_TDN
EPHY_TDP
EPHY_RDN
EPHY_RDP

SOC_RESET

XIN_MAIN
XOUT_MAIN

USB_DM3
USB_DP3
WIFI_DM
WIFI_DP
USB_DM2
USB_DP2

USB_DM1
USB_DP1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

UB83

LM14 INPUT

2013-10-28

03

M0_DDR_RESET_N

Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DM0
M0_DDR_DM1

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_D_CLK

M0_D_CLKN
M0_DDR_CKE

M0_DDR_CS1
M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7

M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

IC400

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

M0_DDR_VREFDQ

M8

H1

L8

R400

ZQ

VDDC15_M0

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C410

0.1uF

C411

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_D_CLK

M0_D_CLKN
M0_DDR_CKE

M0_DDR_CS2
M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

IC401

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

ZQ

NC_1
NC_2
NC_3
NC_4

M0_1_DDR_VREFDQ

M8

H1

L8

R403

VDDC15_M0
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C440

0.1uF

C441

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DM0
M1_DDR_DM1

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_CS1
M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7

M1_DDR_DQ8
M1_DDR_DQ9

M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

IC403

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

NC_1
NC_2
NC_3
NC_4

M1_DDR_VREFDQ

M8

H1

L8

R404

ZQ

VDDC15_M0

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C468

0.1uF

C469

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_CS2
M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

M1_DDR_DQS3

M1_DDR_DQS_N3

M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23

M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

IC404

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

NC_1
NC_2
NC_3
NC_4

M1_1_DDR_VREFDQ

M8

H1

L8

R419

ZQ

VDDC15_M0
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C490

0.1uF

C491

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN
M0_DDR_ODT

M0_DDR_RESET_N

M0_DDR_CS1
M0_DDR_CS2

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DM0

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQ8

M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

M0_DDR_DM1
M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DM2
M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

M0_DDR_DM3
M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_DDR_CKE

M0_D_CLK

M0_D_CLKN

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M0

C407 0.1uF

C405 0.1uF

C402 0.1uF

C400 0.1uF

C401 0.1uF

F16
C16
E16
F17
B17
E17
A16
D16
C15
E15
B18
B16
D19
F15
B15
E19
E18
C17
F18
F20
F19
E20
G21
C18
F14
A19
B19
E14
D14

C22
B21
B23
C20
B24
C19
C23
C21
B20
A22
B22

F22
E24
E21
E25
D22
D26
D21
D25
E23
D23
E22

C27
C25
B28
A25
C28
C24
A28
B26
B25
B27
C26

D28
C29
E26
D29
E28
D30
E27
C30
B30
A30
B29

A_DDR3_A0
A_DDR3_A1
A_DDR3_A2
A_DDR3_A3
A_DDR3_A4
A_DDR3_A5
A_DDR3_A6
A_DDR3_A7
A_DDR3_A8
A_DDR3_A9
A_DDR3_A10
A_DDR3_A11
A_DDR3_A12
A_DDR3_A13
A_DDR3_A14
A_DDR3_A15
A_DDR3_BA0
A_DDR3_BA1
A_DDR3_BA2
A_DDR3_RASZ
A_DDR3_CASZ
A_DDR3_WEZ
A_DDR3_ODT
A_DDR3_CKE
A_DDR3_RST
A_DDR3_MCLK
A_DDR3_MCLKZ
A_DDR3_CSB1
A_DDR3_CSB2

A_DDR3_DQ[0]
A_DDR3_DQ[1]
A_DDR3_DQ[2]
A_DDR3_DQ[3]
A_DDR3_DQ[4]
A_DDR3_DQ[5]
A_DDR3_DQ[6]
A_DDR3_DQ[7]
A_DDR3_DQM[0]
A_DDR3_DQS[0]
A_DDR3_DQSB[0]

A_DDR3_DQ[8]
A_DDR3_DQ[9]
A_DDR3_DQ[10]
A_DDR3_DQ[11]
A_DDR3_DQ[12]
A_DDR3_DQ[13]
A_DDR3_DQ[14]
A_DDR3_DQ[15]
A_DDR3_DQM[1]
A_DDR3_DQS[1]
A_DDR3_DQSB[1]

A_DDR3_DQ[16]
A_DDR3_DQ[17]
A_DDR3_DQ[18]
A_DDR3_DQ[19]
A_DDR3_DQ[20]
A_DDR3_DQ[21]
A_DDR3_DQ[22]
A_DDR3_DQ[23]
A_DDR3_DQM[2]
A_DDR3_DQS[2]
A_DDR3_DQSB[2]

A_DDR3_DQ[24]
A_DDR3_DQ[25]
A_DDR3_DQ[26]
A_DDR3_DQ[27]
A_DDR3_DQ[28]
A_DDR3_DQ[29]
A_DDR3_DQ[30]
A_DDR3_DQ[31]
A_DDR3_DQM[3]
A_DDR3_DQS[3]
A_DDR3_DQSB[3]

C403 0.1uF

C404 0.1uF

IC100

LGE4331

C406 0.1uF

B_DDR3_A0
B_DDR3_A1
B_DDR3_A2
B_DDR3_A3
B_DDR3_A4
B_DDR3_A5
B_DDR3_A6
B_DDR3_A7
B_DDR3_A8

B_DDR3_A9
B_DDR3_A10
B_DDR3_A11
B_DDR3_A12
B_DDR3_A13
B_DDR3_A14
B_DDR3_A15
B_DDR3_BA0
B_DDR3_BA1
B_DDR3_BA2

B_DDR3_RASZ
B_DDR3_CASZ

B_DDR3_WEZ
B_DDR3_ODT
B_DDR3_CKE
B_DDR3_RST

B_DDR3_MCLK

B_DDR3_MCLKZ

B_DDR3_CSB1
B_DDR3_CSB2

B_DDR3_DQ[0]
B_DDR3_DQ[1]
B_DDR3_DQ[2]
B_DDR3_DQ[3]
B_DDR3_DQ[4]
B_DDR3_DQ[5]
B_DDR3_DQ[6]

B_DDR3_DQ[7]
B_DDR3_DQM[0]
B_DDR3_DQS[0]

B_DDR3_DQSB[0]

B_DDR3_DQ[8]

B_DDR3_DQ[9]
B_DDR3_DQ[10]
B_DDR3_DQ[11]
B_DDR3_DQ[12]
B_DDR3_DQ[13]
B_DDR3_DQ[14]
B_DDR3_DQ[15]
B_DDR3_DQM[1]
B_DDR3_DQS[1]

B_DDR3_DQSB[1]

B_DDR3_DQ[16]
B_DDR3_DQ[17]
B_DDR3_DQ[18]
B_DDR3_DQ[19]
B_DDR3_DQ[20]
B_DDR3_DQ[21]
B_DDR3_DQ[22]
B_DDR3_DQ[23]
B_DDR3_DQM[2]
B_DDR3_DQS[2]

B_DDR3_DQSB[2]

B_DDR3_DQ[24]
B_DDR3_DQ[25]
B_DDR3_DQ[26]
B_DDR3_DQ[27]
B_DDR3_DQ[28]
B_DDR3_DQ[29]
B_DDR3_DQ[30]
B_DDR3_DQ[31]
B_DDR3_DQM[3]
B_DDR3_DQS[3]

B_DDR3_DQSB[3]

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M0

OPT

C438 0.1uF

REFIN

VLDOIN

VOSNS

PGND

C439 0.1uF

VO

IC402

TPS51200DRCR

1

2

3

4

5

OPT

C4001
10uF
10V

11

THERMAL

[EP]

VIN

10

PGOOD

9

GND

8

EN

7

REFOUT

6

OPT

C4005

C4010

1uF

0.1uF

25V

16V

UBW2012-121F

C442

0.1uF

Close to REFOUT pin

4th layer

+3.3V_NORMAL

L401

C443
4700pF

OPT

OPT

OPT

C4000

C4011

C4004

10uF

0.1uF

1uF

10V

C409 0.1uF

C408 0.1uF

G28

M1_DDR_A0

J31

M1_DDR_A1

H29

M1_DDR_A2

J27

M1_DDR_A3

J30

M1_DDR_A4

H28

M1_DDR_A5

J32

M1_DDR_A6

G31

M1_DDR_A7

H32

M1_DDR_A8

F30

M1_DDR_A9

K30

M1_DDR_A10

H30

M1_DDR_A11

K29

M1_DDR_A12

F31

M1_DDR_A13

H31

M1_DDR_A14

L28

M1_DDR_A15

K28

M1_DDR_BA0

K31

M1_DDR_BA1

J28

M1_DDR_BA2

M27
L27
K27
M28
L31
F32
M32
L30
F29
E32

R31
N30
R30
N31
T30
M31
T31
P31
M30
R32
P30

P28
T28
N28
U28
N27
T27
N29
T29
R28
R27
P27

Y31
V31
Y30
V32
AA30
U31
AA31
V30
U30
W30
W31

V28
Y27
U27
AA28
W28
AA29
V27
AA27
W27
Y28
W29

M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_ODT

M1_DDR_CKE

M1_DDR_RESET_N
M1_D_CLK
M1_D_CLKN

M1_DDR_CS1

M1_DDR_CS2

M1_DDR_DQ0
M1_DDR_DQ1

M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DM0

M1_DDR_DQS0
M1_DDR_DQS_N0

M1_DDR_DQ8

M1_DDR_DQ9

M1_DDR_DQ10

M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14

M1_DDR_DQ15

M1_DDR_DM1

M1_DDR_DQS1
M1_DDR_DQS_N1

M1_DDR_DQ16

M1_DDR_DQ17

M1_DDR_DQ18

M1_DDR_DQ19

M1_DDR_DQ20

M1_DDR_DQ21

M1_DDR_DQ22
M1_DDR_DQ23

M1_DDR_DM2

M1_DDR_DQS2
M1_DDR_DQS_N2

M1_DDR_DQ24

M1_DDR_DQ25

M1_DDR_DQ26

M1_DDR_DQ27

M1_DDR_DQ28
M1_DDR_DQ29

M1_DDR_DQ30

M1_DDR_DQ31

M1_DDR_DM3

M1_DDR_DQS3
M1_DDR_DQS_N3

4th layer

16V

25V

C412 0.1uF

C413 0.1uF

C415 0.1uF

AR400
100
1/16W

M0_DDR_A14

M0_DDR_A8

M0_DDR_A11

M0_DDR_A6

AR401
100

1/16W
M0_DDR_A1
M0_DDR_A4

M0_DDR_A12
M0_DDR_BA1

AR402

100

M0_DDR_A13

M0_DDR_A7
M0_DDR_A9

M0_DDR_A5
M0_DDR_A2
M0_DDR_A3
M0_DDR_A0

M0_DDR_BA0
M0_DDR_BA2
M0_DDR_A15
M0_DDR_A10

M0_DDR_WEN
M0_DDR_CASN
M0_DDR_RASN

M0_DDR_ODT

M0_DDR_CKE

M0_D_CLKN

M0_D_CLK

1/16W

AR403
100
1/16W

AR404
100
1/16W

AR405
100
1/16W

AR406
100
1/16W

M0_DDR_RESET_N M1_DDR_RESET_N

C416 0.1uF

C418 0.1uF

C419 0.1uF

DDR_VTT

C420 0.1uF

C424 0.1uF

C425 0.1uF

C426 0.1uF

C427 0.1uF

C428 0.1uF

C429 0.1uF

C430 0.1uF

C431 0.1uF

C432 0.1uF

C433 0.1uF

C434 0.1uF

C435 0.1uF

C436 0.1uF

C437 0.1uF

C423 0.1uF

* DDR_VTT

VDDC15_M0

R401

1%

10K

C421

R402

10K

1000pF

1%

DDR_VTT

C414

0.1uF

L400

UBW2012-121F

C417
100uF

C422
22uF
10V

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M0

C444 0.1uF

C445 0.1uF

M1_DDR_A14

M1_DDR_A8

M1_DDR_A11

M1_DDR_A6

M1_DDR_A1

M1_DDR_A4
M1_DDR_A12
M1_DDR_BA1

M1_DDR_A13

M1_DDR_A7

M1_DDR_A9

M1_DDR_A5

M1_DDR_A2

M1_DDR_A3

M1_DDR_A0

M1_DDR_BA0
M1_DDR_BA2
M1_DDR_A15
M1_DDR_A10

M1_DDR_WEN

M1_DDR_CASN
M1_DDR_RASN

M1_DDR_ODT

M1_DDR_CKE

M1_D_CLKN

M1_D_CLK

C446 0.1uF

AR407
100
1/16W

AR408
100
1/16W

AR409
100
1/16W

AR410
100
1/16W

AR411
100
1/16W

AR412
100
1/16W

AR413
100
1/16W

C447 0.1uF

C448 0.1uF

C449 0.1uF

DDR_VTT

C450 0.1uF

C451 0.1uF

C453 0.1uF

C454 0.1uF

C455 0.1uF

C456 0.1uF

C457 0.1uF

C458 0.1uF

C459 0.1uF

C460 0.1uF

C461 0.1uF

C462 0.1uF

C463 0.1uF

C464 0.1uF

C465 0.1uF

C466 0.1uF

C452 0.1uF

C467 0.1uF

OPT

OPT

OPT
C4002
10uF
10V

C4006
1uF
25V

C4009

0.1uF
16V

4th layer

VDDC15_M0

VDDC15_M0

R410

R411

R405
10K

1K 1%

1K 1%

M0_DDR_RESET_N

M0_DDR_VREFDQ

C472

0.1uF

+1.5V_Bypass Cap
Close to DDR Power Pin

VDDC15_M0

C476 0.1uF

C480 0.1uF

C475 0.1uF

M0_DDR_CKE

M0_D_CLK

R412

C477

56

0.01uF

1%

50V

R413
56
1%

M0_D_CLKN

VDDC15_M0

R416

1K 1%

C474
1000pF
50V

R417

1K 1%

C481 0.1uF

R418
10K

M0_1_DDR_VREFDQ

C479

0.1uF
C483
1000pF
50V

C484 0.1uF

C485 0.1uF

C486 0.1uF

C487 0.1uF

C488 0.1uF

C489 0.1uF

OPT

C4003
10uF
10V

VDDC15_M0

OPT

VDDC15_M0

R425

R426

C4007
1uF
25V

R422
10K

1K 1%

1K 1%

OPT

C4008

0.1uF
16V

M1_DDR_RESET_N

M1_DDR_VREFDQ

C470

0.1uF
C471
1000pF
50V

4th layer

M1_DDR_CKE

R427
56
1%

R428
56
1%

VDDC15_M0

R431

R432

C497

0.01uF
50V

1K 1%

1K 1%

R433
10K

M1_D_CLK

M1_D_CLKN

M1_1_DDR_VREFDQ

C473

0.1uF
C478

1000pF
50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

UB83

LM14 DDR

2013-10-28

04