LG 55EA970T Schematic

Internal Use Only

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LED TV

SERVICE MANUAL

CHASSIS : ET34D

MODEL : 55EA970T 55EA970T-DA

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67853503 (1401-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 14

EXPLODED VIEW .................................................................................. 24

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental sh orts of the cir cui try that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 M
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Ω and 5.2 MΩ.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions.
Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;

a. Removing or reinstalling any component, circuit board mod-

ule or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explo­sion hazard.

2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture.
Unless specied otherwise in this service manual, lubrication of

contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged eas­ily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component dam­age caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alter­natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten­tial shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or expo­sure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.

4. Use only an anti-static type solder removal device. Some solder

removal devices not classied as “anti-static” can generate
electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electri­cally shorted together by conductive foam, aluminum foil or
comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replace­ment ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity suf­cient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder ows onto and around both the compo­nent lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent at against the cir­cuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close
as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as pos­sible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connec­tions).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly con­nected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

.

1. Application range

This spec sheet is applied all of the 47”, 55”, 60”, 70”, 84” LED
TV with LT34D/ET34D chassis

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC: CE, IEC

2. Test condition

Each part is tested as below without special notice.

1) Temperature : 25 ºC ± 5 ºC(77±9 ºF), CST : 40 ºC±5 ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage
Standard input voltage (100~240V@ 50/60Hz)
* Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

ea ch drawing an d s pe cificat io n b y part number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

4. General Specification

No Item Specication Remark

1. Display Screen Device 47” wide Color Display Module

55” wide color display module

60” wide color display module

65” wide color display module

70” wide color display module

84” wide color display module

2. Aspect Ratio 16:9 All

3. LCD Module 47” TFT WUXGA LCD

55” TFT WUXGA LCD

60” TFT WUXGA LCD

70” TFT WUXGA LCD

84” TFT WUXGA LCD

4. Operating Environment TFT Temp. : 0 ~ 40 deg
Humidity : 0 ~ 85%

ALEF Temp. : 0 ~ 50 deg

Humidity : 20 ~ 90%

5. Storage Environment TFT Temp. : -20 ~ 60 deg
Humidity : 10 ~ 90%

ALEF Temp. : 0 ~ 50 deg

Humidity : 20 ~ 90%

6. Input Voltage AC100 ~ 240V, 50/60Hz

LC470EUH-LEF1(47LA8600-DA/47LA860T-DA)

LC550EUH-LEF1(55LA8600-DA/47LA860T-DA)
(55LA7900-DA/55LA790T-DA)
LC550DUK-SFN1(55LA960T-DA)
LC550EQK-FGK1(55LA970T-DA)
LC550EQD-FGF4(55LA965T-DA)
LC550LUD-MFP2(55EA980T-DA)

LC600EUD-LFF1(60LA8600-DA/60LA860T-DA)

LC650EQK-FGK1(65LA970T-DA)
LC650EQD-FGF4(65LA965T-DA)

JE695D3LB67(70LA860T-DA)

LC840EQD-SEF2(84LA980T-DA)

LGE SPEC

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

7. Power Consumption(Max) =

LCD(Module) + Backlight(LED)

8. LCD Module Size Maker Inch (H) × (V) × (D)

Pixel Pitch Maker Inch (H) × (V) × (D)

Back Light LGD 47” LCM

Display Colors 1.06 B (10-bit) Except FHD 60Hz models

Surface Treatment Hard coating (2H), Anti-glare

T240Hz 47” 70.8 W LC470EUH-LEF1[47LA8600-DA

55” 82 W LC550EUH-LEF1 [55LA8600-DA]

55” 100.8 W LC550EQD-FGF4(55LA965T-DA)

60” 96.8 W LC600EUD-LEF1 [60LA8600-DA

84” 410 W LC840EQD-SEF2(84LA980T-DA)

ALEF
(T240)

LGD 47” 1056.1x605.9x170.7

Sharp 70” 1566 x901.8x29.6

LGD 55” LCM

LGD 55” ALEF

LGD 55:, 84" UD

LGD 55” OLED

Sharp 70” LCM

16.7 M (8-bit) Only FHD 60Hz models

55” 112.2 W LC550EQK-FGK1(55LA970T-DA)

65” 155.1 W LC650EQK-FGK1(65LA970T-DA)

55” 1226 x 702.6 x 10.4

1214.2x685.5x1.5

1226 x 702.6 x 17.9

1223.4x697.2x11.7

60” 1333.8 x 762.5 x 10.6

55” 1226.62x704.63x1.67

84” 1904x1096x15.5

47” 0.5415 x 0.5415

55” 0.630 x 0.630

0.315 x 0.315

60” 0.6861 x 0.2287

65” 0.372 x 0.372

55” 0.6285x0.6285

70” 0.802x0.802

84” 0.4845x0.4845

/47LA860T-DA]

LC550EUH-LEF1 [55LA7900­DA/55LA790T-DA]

/60LA860T-DA]

LC470EUH-LEF1
[47LA8600-DA/47LA860T-DA]

LC550EUH-LEF1 [55LA8600-DA]
LC550EUH-LEF1 [55LA7900-DA /55LA790T-DA]

LC550DUK-SFN1(55LA960T-DA)

LC550EQK-FGK1(55LA970T-DA)

LC550EQD-FGF4(55LA965T-DA)

LC600EUD-LEF1 [60LA8600-DA /60LA860T-DA]

LC550LUD-MFP2[55EM98/880T-DA]

LC840EQD-SEF2(84LA980T-DA)

JE695D3LB67(70LA8600-SA)

LC470EUH-LEF1[47LA8600-DA /47LA860T-DA]

LC550EUH-LEF1 [55LA8600-DA]
LC550EUH-LEF1 [55LA7900-DA/55LA790T-DA]
LC550DUK-SFN1(55LA960T-DA)
LC550EQK-FGK1(55LA970T-DA)

LC550EQD-FGF4(55LA965T-DA)

LC600EUD-LEF1 [60LA8600-DA /60LA860T-DA]

LC650EQK-FGK1(65LA970T-DA)

LC550LUD-MFP2[55EM98/880T-DA]

JE695D3LB67(70LA8600-SA)

LC840EQD-SEF2(84LA980T-DA)

LC470EUH-LEF1(47LA8600-DA /47LA860T-DA)

LC550EUH-LEF1 [55LA8600-DA]
LC550EUH-LEF1 [55LA7900-DA/55LA790T-DA]

LC550DUK-SFN1(55LA960T-DA)

LC550EQK-FGK1(55LA970T-DA)
LC550EQD-FGF4(55LA965T-DA)
LC840EQD-SEF2(84LA980T-DA)

LC550LUD-MFP2[55EM98/880T-DA]

JE695D3LB67(70LA860T-DA)

Only for training and service purposes

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. External Input Support Format

5.1. 2D Model

5.1.1. Component Video Input(Y, CB/PB, CR/PR)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I

2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I

3. 720*480 31.50 60 27.027 SDTV 480P

4 720*480 31.47 59.94 27.0 SDTV 480P

5 1280*720 45.00 60.00 74.25 HDTV 720P

6 1280*720 44.96 59.94 74.176 HDTV 720P

7 1920*1080 33.75 60.00 74.25 HDTV 1080I

8 1920*1080 33.72 59.94 74.176 HDTV 1080I

9 1920*1080 67.500 60 148.50 HDTV 1080P

10 1920*1080 67.432 59.94 148.352 HDTV 1080P

11 1920*1080 27.000 24.000 74.25 HDTV 1080P

12 1920*1080 26.97 23.976 74.176 HDTV 1080P

13 1920*1080 33.75 30.000 74.25 HDTV 1080P

14 1920*1080 33.71 29.97 74.176 HDTV 1080P

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.1. HDMI Input (PC/DTV)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed

HDMI-PC DDC

1 640*350 31.468 70.09 25.17 EGA Х

2 720*400 31.469 70.08 28.32 DOS O

3 640*480 31.469 59.94 25.17 VESA(VGA) O

4 800*600 37.879 60.31 40.00 VESA(SVGA) O

5 1024*768 48.363 60.00 65.00 VESA(XGA) O

6 1152*864 54.348 60.053 80.00 VESA O

7 1280*1024 63.981 60.020 108.00 VESA (SXGA) O

8 1360*768 47.712 60.015 85.50 VESA (WXGA) O

9 1920*1080 67.5 60 148.5 WUXGA

(Reduced Blanking)

10 3840*2160 54 24.00 297.00 UDTV 2160P

11 3840*2160 56.25 25.00 297.00 UDTV 2160P

12 3840*2160 67.5 30.00 297.00 UDTV 2160P

HDMI-DTV

1 720*480 31.47 60 27.027 SDTV 480P

2 720*480 31.47 59.94 27.00 SDTV 480P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 44.96 59.94 74.176 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I

6 1920*1080 33.72 59.94 74.176 HDTV 1080I

7 1920*1080 67.500 60 148.50 HDTV 1080P

8 1920*1080 67.432 59.939 148.352 HDTV 1080P

9 1920*1080 27.000 24.000 74.25 HDTV 1080P

10 1920*1080 26.97 23.976 74.176 HDTV 1080P

11 1920*1080 33.75 30.000 74.25 HDTV 1080P

12 1920*1080 33.71 29.97 74.176 HDTV 1080P

13 3840*2160 53.95 23.976 297.00 UDTV 2160P

14 3840*2160 54 24.00 297.00 UDTV 2160P

15 3840*2160 56.25 25.00 297.00 UDTV 2160P

16 3840*2160 61.43 29.970 297.00 UDTV 2160P

17 3840*2160 67.5 30.00 297.00 UDTV 2160P

O

Only UD Model

Only UD Model

Only UD Model

Only for training and service purposes

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2. 3D mode

5.2.1. HDMI Input 1.4b (3D supported mode automatically)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) VIC 3D input proposed mode

1 640*480 31.469 / 31.5 59.94/ 60 25.175/25.2 1 Top-and-Bottom

Side-by-side(half)

2 62.938 / 63 59.94/ 60 50.35/50.4 1 Frame packing

Line alternative

3 31.469 / 31.5 59.94/ 60 50.35/50.4 1 Side-by-side(Full) (SDTV 480P)

4 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 Top-and-Bottom

Side-by-side(half)

5 62.938 / 63 59.94 / 60 54/54.06 2,3 Frame packing

Line alternative

6 31.469 / 31.5 59.94 / 60 54/54.06 2,3 Side-by-side(Full) (SDTV 480P)

7 720*576 31.25 50 27 17,18 Top-and-Bottom

Side-by-side(half)

8 62.5 50 54 17,18 Frame packing

Line alternative

9 31.25 50 54 17,18 Side-by-side(Full) (SDTV 576P)

10 1280*720 37.5 50 74.25 19 Top-and-Bottom

Side-by-side(half)

11 75 50 148.5 19 Frame packing

Line alternative

12 37.5 50 148.5 19 Side-by-side(Full) (HDTV 720P)

13 44.96 / 45 59.94 / 60 74.18/74.25 4 Top-and-Bottom

Side-by-side(half)

14 89.91 / 90 59.94 / 60 148.35/148.5 4 Frame packing

Line alternative

15 44.96 / 45 59.94 / 60 148.35/148.5 4 Side-by-side(Full) (HDTV 720P)

16 1920*1080 33.72 / 33.75 59.94 / 60 74.18/74.25 5 Top-and-Bottom

Side-by-side(half)

17 67.432 / 67.5 59.94 / 60 148.35/148.5 5 Frame packing

Line alternative

18 33.72 / 33.75 59.94 / 60 148.35/148.5 5 Side-by-side(Full) (HDTV 1080I)

19 28.125 50.00 74.25 20 Top-and-Bottom

Side-by-side(half)

20 56.25 50.00 148.5 20 Frame packing

Line alternative

21 28.125 50.00 148.5 20 Side-by-side(Full) (HDTV 1080I)

22 26.97 / 27 23.97 / 24 74.18/74.25 32 Top-and-Bottom

Side-by-side(half)

23 43.94 / 54 23.97 / 24 148.35/148.5 32 Frame packing

Line alternative

24 26.97 / 27 23.97 / 24 148.35/148.5 32 Side-by-side(Full) (HDTV 1080P)

25 28.125 25 74.25 33 Top-and-Bottom

Side-by-side(half)

26 56.25 25 148.5 33 Frame packing

Line alternative

27 28.125 25 148.5 33 Side-by-side(Full) (HDTV 1080P)

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)
(SDTV 480P)

Secondary(SDTV 480P)
Secondary(SDTV 480P)

Secondary(SDTV 480P)
(SDTV 480P)

Secondary(SDTV 576P)
Secondary(SDTV 576P)

Secondary(SDTV 576P)
(SDTV 576P)

Primary(HDTV 720P)
Primary(HDTV 720P)

Primary(HDTV 720P)
(HDTV 720P)

Primary(HDTV 720P)
Primary(HDTV 720P)

Primary(HDTV 720P)
(HDTV 720P)

Secondary(HDTV 1080I)
Primary(HDTV 1080I)

Primary(HDTV 1080I)
(HDTV 1080I)

Secondary(HDTV 1080I)
Primary(HDTV 1080I)

Primary(HDTV 1080I)
(HDTV 1080I)

Primary(HDTV 1080P)
Primary(HDTV 1080P)

Primary(HDTV 1080P)
(HDTV 1080P)

Secondary(HDTV 1080P)
Secondary(HDTV 1080P)

Secondary(HDTV 1080P)
(HDTV 1080P)

Only for training and service purposes

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) VIC 3D input proposed mode

28 1920*1080 33.716 / 33.75 29.976 / 30.00 74.18/74.25 34 Top-and-Bottom

Side-by-side(half)

29 67.432 / 67.5 29.976 / 30.00 148.35/148.5 34 Frame packing

Line alternative

30 33.716 / 33.75 29.976 / 30.00 148.35/148.5 34 Side-by-side(Full) (HDTV 1080P)

31 56.25 50 148.5 31 Top-and-Bottom

Side-by-side(half)

32 67.43 / 67.5 59.94 / 60 148.35/148.50 16 Frame packing

Line alternative

Primary(HDTV 1080P)
Secondary(HDTV 1080P)

Primary(HDTV 1080P)
(HDTV 1080P)

Primary(HDTV 1080P)
Secondary(HDTV 1080P)

Primary(HDTV 1080P)
Secondary(HDTV 1080P)

5.2.2. HDMI Input(1.3)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 720*480 31.5 60 27.03 SDTV 480P 2D to 3D, Side by Side(Half),

2 720*576 31.25 50 27 SDTV 576P

3 1280*720 45.00 60.00 74.25 HDTV 720P

4 1280*720 37.500 50 74.25 HDTV 720P

5 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half),

6 1920*1080 28.125 50.00 74.25 HDTV 1080I

7 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half),

8 1920*1080 28.12 25 74.25 HDTV 1080P

9 1920*1080 33.75 30.00 74.25 HDTV 1080P

10 1920*1080 67.50 60.00 148.5 HDTV 1080P 2D to 3D, Side by Side(Half),

11 1920*1080 56.250 50 148.5 HDTV 1080P

Top & Bottom, Checker Board,
Frame Sequential,
Row Interleaving,
Column Interleaving

Top & Bottom

Top & Bottom, Checker Board,
Row Interleaving,
Column Interleaving

Top & Bottom,
Checker Board,
Single Frame Sequential,
Row Interleaving,
Column Interleaving

5.2.3. RF Input(3D supported mode manually)

No Resolution Proposed 3D input proposed mode

1 HD (DTV) 1080I

720P

2 SD (DTV) 576P

2D to 3D
Side by Side(Half)
Top & Bottom

576I

3 SD (ATV : CVBS / SCART) -

5.2.4. RF Input(3D supported mode automatically)

No Signal 3D input proposed mode

1 Frame Compatible Side by Side(Half),

Top & Bottom

- 11 -

Only for training and service purposes

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.5. USB, DLNA (Movie) Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

2. Over 704x480 interlaced - - - 2D to 3D, Side by Side(Half),
Top & Bottom

3. Over 704x480 progressive - 50 / 60 - 2D to 3D, Side by Side(Half),
Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving,
Frame Sequential

4. Over 704x480 progressive - others - 2D to 3D, Side by Side(Half),
Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving

5.2.6. USB, DLNA (Photo) Input (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 320x240 - - - 2D to 3D

2. Over 320x240 - - - 2D to 3D, Side by Side(Half),
Top & Bottom

* USB, DNLA Input (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080P 33.75 30 - Side by Side(Half), Top & Bottom,

Checker Board, MPO(Photo)

5.2.7. HDMI-PC Input(3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1024*768 48.36 60 65 2D to 3D,

2. 1360*768 47.71 60 85.5 HDTV 768P

3. 1920*1080 67.500 60 148.50 2D to 3D,

4. Others - - - 2D to 3D,

Side by Side(half),
Top & Bottom

Side by Side(half)
Top & Bottom,
Checker Board,
Single Frame Sequential
Row Interleaving,
Column Interleaving

Side by Side(half)
Top & Bottom

HDTV 768P

HDTV 1080P

640*350
720*400
640*480
800*600
1152*864

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.8. Component Input(3D supported mode manually)

R

L

R

L

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1280*720 45.00 60.00 74.25 HDTV 720P 2D to 3D,

2 1280*720 37.500 50 74.25 HDTV 720P

3 1920*1080 33.75 60.00 74.25 HDTV 1080I

4 1920*1080 28.125 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P

6 1920*1080 28.12 25 74.25 HDTV 1080P

7 1920*1080 33.75 30.00 74.25 HDTV 1080P

8 1920*1080 67.50 60.00 148.5 HDTV 1080P

9 1920*1080 56.250 50 148.5 HDTV 1080P

10 Others - - - SDTV

Side by Side(Half),
Top & Bottom

5.2.9. Miracast, Wifi (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024X768p - 30 / 60 - 2D to 3D,

2. 1280x720p - 30 / 60 -

3 1920X1080p 30 / 60

4 Others - 2D to 3D

Side by Side(Half),
Top & Bottom

5.3. 2D to 3D Mode

- Remark: 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame

Sequential

1

Frame Packing Line

Interleaving

Column

Interleaving

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied all of the LT34D,E/ET34D,E
LED TV models, which produced in manufacture department
or similar LG TV factory

2. Specification

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation
transformer will help protect test instrument.

(2) Adjustment must be done in the correct order. But it is

flexible when its factory local problem occurs.

(3) The adjustment must be performed in the circumstance of

25 ±5ºC of temperature and 65±10% of relative humidity if
there is no specific designation.

(4) The input voltage of the receiver must keep 100~220V,

50/60Hz.

(5) Before adjustment, execute Heat-Run for 5 minutes.

3. Adjustment items

3.1. PCB Assembly Adjustment

1) MAC Address, ESN Key and Wide-vine Key D/L

2) LAN Test( Ping-Test )

3) Main S/W program download : Using USB Memory stick

4) Input Tool - Option

5) Download EDID : EDID data are automatically downloaded
when adjusting the Tool Option.

6) ADC Calibration – RGB & Component

7) Check SW Version

3.2. Set Assembly Adjustment

1) Input Area option.

2) Adjustment of White Balance : Auto

3) Adjustment of White Balance : Manual

4) Intelligent Sensor Inspection Guide

5) LAN Inspection Guide

6) Widevine Key Inspection Guide

7) Model name & Serial number D/L

8) Wi-Fi MAC Address Check

9) Local Dimming Inspection Guide

10) Preset CH information

11) GND and Internal Pressure check

12) Motion Remote controller Inspection

13) 3D Function test

14) Outgoing Condition Configuration

15) Sound spec

16) Factoring Option Data input

4. PCB Assembly Adjustment

4.1. MAC Address, ESN Key and Widevine
Key download

4.1.1. Equipment & Condition

1) Play file: keydownload.exe

2) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

3) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.1.2. Download Process

(13Y LCD TV + MAC + WIDEVINE + ESN)

1) Execute “keydownload.exe” on PC

2) Select the download items.

3) Mode check : Online only

4) Check the test process

- D ET ECT → MAC _W RIT E → E SN_ WR ITE ( onl y
Colombia/Panama)→ WIDEVINE_WRITE

5) Play: START

6) Check of result: Ready, Test, OK or NG

1) 13Y LCD TV+MAC+Widevine+ESN Key+ HDCP1.4 and

HDCP2.0

4.1.3. Inspection

- In INSTART menu, check these keys.

Only for training and service purposes

- 14 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.2. PING Test(LAN Operating Test)

4.2.1. Check PCBA

1) Connect LAN to PCBA& Power On.(Default IP can be set to
automatic setting. When power ON, IP can be Automatically
be achieved from the router)

2) Push ADJ key on Adjust remote-controller.

3) Enter “13. ACAP PING TEST” & check Network

4.2.2. Check Set

1) Co nnect TV-Set & PC with Cross LAN cab le.(PC IP :

12.12.2.3)

2) Execute “P INT Test program”, Check setting data of
program. (TV-Set IP : 12.12.2.2)

3) Push Power Only key on Adjust remote-controlle.

4) Click “RUN”, Check “OK” or “NG”

4.3. Main S/W program download

4.3.1. Using the Memory Stick

** USB DOWNLOAD : Service Mode

1) Insert the USB memory Stick to the USB port

2) Automatically detect the SW Version.

-> S/W download process is executed automatically.

3) Show the message “Copy the file from the Memory”

4) After Finished the Download, Automatically DC Off -> On

5) If the TV IS Turn On, Check the updated SW Version and
Tool Option.

4.4. Input tool option.

Adjust tool option refer to the BOM.

▪ Tool Option Input : PCBA Check Process
▪ Area Option Input : Set Assembly Process

*** Tool Option table

MODEL

47LA8600 32981 53964 30393 41141 47514 1359 47243

47LA860T 32981 53964 30393 46317 47514 1359 47243

55LA960T 32999 54220 30397 46317 47514 1359 48267

55EA880T 32775 54732 5817 46317 39062 1359 47243

55EA980T 32791 54732 5821 46317 39062 1359 47243

55LA965T 33383 53964 30381 46317 47254 1359 48267

55LA970T 33207 54220 30382 46317 47258 1359 48267

65LA965T 34403 53964 30381 46317 47254 1359 48267

65LA970T 34227 54220 30382 46317 47258 1359 48267

55LA7900 32967 53964 30393 41141 47510 1359 47243

55LA8600 32983 53964 30393 41141 47514 1359 47243

60LA8600 32984 53964 30393 41141 47258 1359 48267

60LA860T 32984 53964 30393 46317 47258 1359 48267

70LA860T 39129 53964 5817 46317 47254 1359 47243

84LA980T 33371 53964 30397 46317 47254 1359 48267

After Input Tool Option and AC off
Before PCBA check, you have to change the Tool option and
have to AC off/on (Plug out and in)
(If missing this process, set can operate abnormally)

Tool

Option1

Tool

Option2

Tool

Option3

Tool

Option4

Tool

Option5

Tool

Option6

Tool

Option7

Only for training and service purposes

- 15 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.4.1. Profile

Must be changed the option value because being different with
some setting value depend on module maker, inch and market

4.4.2. Equipment

Adjustment remote control

4.4.3. Adjustment method

The input methods are same as other chassis.(Use ADJ Key
on the Adjust Remocon.)
(If not changed the option, the input menu can differ the model
spec.)
Re fer to Job Expre ss ion of each ma in chassis as s’ y
(EBTxxxxxxxx) for Option value
Caution : Don’t Press “IN-STOP” key after completing the

function inspection.

4.5. EDID D/L method

Recommend that don’t connect HDMI and RGB(D-SUB) cable
when downloading the EDID.
If not possible, recommend that connect the MSPG equipment.
There are two methods of downloading the edid data

It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information
Sharing without any necessity of user input. It is a realization
of “Plug and Play”

4.5.1. 1st Method

EDID datas are automatically downloaded when adjusting the
Tool Options.
Automatically downloaded when pushing the enter key after
adjusting the tool option5.
It takes about 2seconds

4.5.2. 2nd Method

● Caution : Must be checked that the tool option is right or not.

If tool option is wrong, hdmi edid data could not be

downloaded well.

1) Press the ADJ key

2) Move to the 10. EDID D/L and Press the right direction

key(►)

3) Press the right direction key(►) at Start.

4) After about a few seconds, appear “Waiting..” => “OK”, then
compele.

4.5.4. EDID data

4.5.4.1. HDMI(FHD 3D_Deep color support)

1) HDMI 1 Check sum : 0XE8, 0X81 (CEA Block 0x1E :10)

2) HDMI 2 Check sum : 0XE8, 0X71 (CEA Block 0x1E :20)

3) HDMI 3 Check sum : 0x E8, 0X61 (CEA Block 0x1E :30)

3) HDMI 4 Check sum : 0x E8, 0X51 (CEA Block 0x1E :40)

4.6. ADC Calibration : Comp 480i/Comp 1080p/RGB

4.6.1. ADC Calibration : Internal Auto ADC

ADC c alibr ation is not neces sary becaus e MAIN SoC
(LGExxxx) is already calibrated from IC Maker

4.6.2. Manual ADC Calibration

4.6.2.1. Equipment & Condition
(1) Adjustment Remocon
(2) 801GF (802B , 802F, 802R) or MSPG925 FA Pat tern

Generator

- Reso lution: 480i Com p1 (MSPG- 925FA: mod el-20 9,

pattern-65)

- Re solutio n: 1080p Comp1 (MSPG-925FA: model-225,

pattern-65)

- Resolution : 1080p RGB (MS PG-925FA: model-2 25,

pattern-65)

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level: 0.7±0.1 Vp-p

4.5.3. RS-232C command Method

1) Command : AE 00 10

● Caution : Don’t connect HDMI and RGB(D-SUB) cable when

downloading the EDID.

If the cables are connected, Downloading of edid

could be failed

Only for training and service purposes

- 16 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4.6.2.2. Adjust method

4.6.2.2.1.ADC 480i/1080p Comp
(1) Check co nnected c on di tion of Comp cable to th e

equipment

(2) Give a 480i Mode, Horizontal 100% Color Bar Pattern to

Comp1. (MSPG-925FA → Model: 209, Pattern: 65)

(3) Change input mode as Component1 and picture mode as

“Standard”

(4) Press the In-start Key on the ADJ remote after at least 1

min of signal reception. Then, select 7.External ADC. And

Press OK or Right Button for going to sub menu.
(5) Press OK in Comp 480i menu
(6) Give a 1080p Mode, Horizontal 100% Color Bar Pattern to

Comp1. (MSPG-925FA → Model: 225, Pattern: 65)

(7) Press OK in Comp 1080p menu
(8) If ADC Comp is successful, “ADC Component Success” is

displayed.
(9) If ADC calibration is failure, “ADC Component Fail” is

displayed.
(10) If ADC calibration is failure, after rechecking ADC pattern

or condition, retry calibration

(11) If ADC calibration is failure, after recheck ADC pattern or

condition, retry calibration

4.7. Check SW Version

4.7.1. Method

1) Push In-star key on Adjust remote-controller.

2) SW Version check(ex. 47LW9500-DA)

4.8. MHL Test

Step 1) Turn on TV
Step 2) Select HDMI4 mode using input Menu.
Step 3) Set MHL Zig(M1S0D3617) using MHL input, output

and power cord.

Step 4) Connect HDMI cable between MHL Zig and HDMI4

port.

Step 5) Check LED light of Zig and Module of Set

Result) If, The LED light is green and The Module shows
normal stream -> OK
Else -> NG

4.9. Camera Port Inspection

(1) Objective : To check PCBA’s CAMERA Port.
(2) How-it-works
i) Connect the PCBA like below Picture.
ii) Send specific RS-232C Command for displaying Camera

Preview.

* CAMERA need to be status of Slide up.

Only for training and service purposes

(3) RS-232C Command

RS-232C COMMAND

CMD DATA ID

Ai 00 23 Camera Function Start.

Ai 00 24 Camera Function End.

Explanation

5. SET assembly adjustment method

5.1. Input Area-Option

(1) Prole : Must be changed the Area option value because

being different of each Country’s Language and

signal Condition.
(2) Equipment : adjustment remote control.
(3) Adjustment method

- The input methods are same as other chassis.(Use IN-START

Key on the Adjust Remocon.)

Refer to Job Expression of each main chassis ass’y

(EBTxxxxxxxx) for Option value

- 17 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2. Adjustment of White Balance

● In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours

● In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above 15°C
for 3 hours.

▪ Purpose : Adjust the color temperature to reduce the deviation

of the module color temperature.

▪ Principle : To adjust the white balance without the saturation,

Fix the one of R/G/B gain to 192 (default data) and
decrease the others.

▪ Adjustment mode : Three modes – Cool / Medium / Warm

5.2.2. Adjustment of White Balance
(for Manual adjustment)

5.2.2.1. Adj. condition and cautionary items
(1) Lighting condition in surrounding area surrounding lighting

should be lower 10 lux. Try to isolate adj. area into dark
surrounding.

(2) Probe location: Color Analyzer (CA-210) probe should be

within 10cm and perpendicular of the module surface (80°~
100°)

(3) Aging time

1) After Aging Start, Keep the Power ON status during 5

Minutes.

2) In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

※ Required Equipment

▪ Remote controller for adjustment
▪ Color Analyzer : CA100+ or CA-210 or same product (should

be used in the calibrated ch by CS-1000)

- LCD TV : CH-9

- PDP TV : CH-10

- White LED TV : CH-14

- ALEF : CH-18

- RGB LED(MNT) : CH-16

▪ Auto W/B adjustment instrument(only for Auto adjustment)

5.2.1. Adjustment of White Balance :
(For Automatic Adjustment)

Co nnectin g diagra m of eq uipment for me as uring (For
Automatic Adjustment)

1) Set TV in adj. mode using POWER ON key

2) Zero calibrate probe then place it on the center of the
Display

3) Connect Cable(RS-232C)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sing), check adj. status pre
mode(Warm, Medium, Cool)

6) Remove probe and RS-232C cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

5.2.2.2. Equipment
(1) Color Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:

CH14)

(2) Adj. Computer (During auto adj., RS-232C protocol is

needed)
(3) Adjust Remocon
(4) Vi deo Sig nal Genera tor MSP G-925F 720p/216-Gray

(Model: 217, Pattern: 78)

5.2.2.3. Adjustment
(1) Set TV in Adj. mode using POWER ON
(2) Zero Calibrate the probe of Color Analyzer, then place it on

the center of LCD module within 10cm of the surface.

(3) Press ADJ key → EZ adjust using adj. R/C → 6. White-

Balance then press the cursor to the right (KEY►). When
KEY(►) is pressed 216 Gray inte rnal pattern will be

displayed.

(4) One of R Gain / G Gain / B Gain should be fixed at 192,

and the rest will be lowered to meet the desired value.

(5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of

color temperature.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 6.White Balance, you can select one
of 2 Test-pattern:
ON, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.

※ Luminance min value is 150cd in the Cool/Medium/Warm

mode( For LCD)

Only for training and service purposes

- 18 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.2.3. LED White balance table

5.2.3.1.Cool Mode
(1) Purpose : Especially G -g ai n f ix ad ju st leads to the

lu mi nance enhancem en t. Adj us t t he co lo r
tempe rat ure to reduc e the deviation of the
module color temperature.

(2) Principle : To ad ju st t he w hite b al an ce w it hout t he

saturation, Adjust the G gain more than 172 ( If
R gain or G gain is more than 255 , G gain can
adjust less than 172 ) and change the others
(R/B Gain ).

(3) Adjustment mode : mode – Cool

**For 55/65LA97 Models
* R-fix adjustment
Adjust modes (Cool), Fix the R gain to 210 (default data) and
change the others (G/B Gain ).

- Adjust the R gain more than 210 ( If G gain or B gain is less
than 0 , R gain can adjust more than 210 )
and change the others ( G/B Gain ).
Adjust two modes(Medium / Warm), Fix the one of R/G/B gain
to 192 (default data) and decrease the
others.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of

5.2.4.2. Medium Mode
(1) Purpose : Adjust the color temperatur e to reduc e the

deviation of the module color temperature.

(2) Principle : To ad ju st t he w hite b al an ce w it hout t he

saturation, Fix the B gain to 192 (default data)
and decrease the others.

(3) Adjustment mode : mode – Medium

5.2.4.3. Warm Mode
(1) Purpose : Adjust the color temperatur e to reduc e the

deviation of the module color temperature.

(2) Principle : To ad ju st t he w hite b al an ce w it hout t he

saturation, Fix the W gain to 192 (default data)
and decrease the others.

(3) Adjustment mode : mode – Warm

● Standard color coordinate and temperature when using the

CA100+ or CA210 equipment

Mode Color coordinate Temp △uv

X Y

Cool 0.271±0.002 0.270±0.002 13000K 0.0000

Medium 0.285±0.002 0.293±0.002 9,300 K 0.000

Warm 0.313±0.002 0.329±0.002 6,500K 0.003

2 Test-pattern: ON, OFF. Default is inner(ON). By selecting
OFF, you can adjust using RF signal in 216
Gray pattern.

5.2.3.2. Medium / Warm Mode
(1) Purpose : Adju st the col or tempe rature to reduce the

deviation of the module color temperature.

(2) Principle : To ad ju st t he w hite b al an ce w it hout t he

saturation, Fix the one of R/G/B gain to 192
(default data) and decrease the others.

(3) Adjustment mode : Two modes – Medium / Warm

5.2.4. OLED White balance table

5.2.4.1.Cool Mode
(1) Purpose : Especially B -g ai n f ix adjust l eads t o t he

lu mi nance enhancem en t. Adj us t t he co lo r
tempe rat ure to reduc e the deviation of the
module color temperature

(2) Principle : To ad ju st t he w hite b al an ce w it hout t he

saturation, Adjust the B gain more than 192 ( If R
gain or G gain is more than 255 , G gain can
adjust less than 192 ) and change the others (
R/G Gain ).

(3) Adjustment mode : mode – Cool

▪ Change reason : When vivid mode, more detail than other

company set.

● In case of Edge LED module, the color coordinates is

changing by aging, so you have to use the below table.

The Time Table of color coordinates by SET Aging Time

1) Edge LED Models(LA7xxx, LA8XXX, 55LA9600)_nomarl

line

GP3 Aging

time

(Min)

1 271 270 285 293 313 329 342

2 3-5 280 285 294 308 319 340

3 6-9 278 284 292 307 317 339

4 10-19 276 281 290 304 315 336

5 20-35 275 277 289 300 314 332

6 36-49 274 274 288 297 313 329

7 50-79 273 272 287 295 312 327

8 80-119 272 271 286 294 311 326

9 Over 120 271 270 285 293 310 325

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

Only for training and service purposes

- 19 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

2) Edge LED Models(LA7xxx, LA8XXX, 55LA9600)_aging

chamber

GP3 Aging

time

(Min)

1 0-5 280 285 294 308 319 340

2 6-10 276 280 290 303 315 335

3 11-20 272 275 286 298 311 330

4 21-30 269 272 283 295 308 327

5 31-40 267 268 281 291 306 323

6 41-50 266 265 280 288 305 320

7 51-80 265 263 279 286 304 318

8 81-119 264 261 278 284 303 316

9 Over 120 264 260 278 283 303 315

Cool Medium Warm

x y x y x y

270 271 285 293 313 329

3) ALEF (55LA970T/65LA970T-DA)_nomal line

GP3 Aging

time

(Min)

1 0-2 281 287 295 310 320 342

2 3-5 280 285 294 308 319 340

3 6-9 278 284 292 307 317 339

4 10-19 276 281 290 304 315 336

5 20-35 275 277 289 300 314 332

6 36-49 274 274 288 297 313 329

7 50-79 273 272 287 295 312 327

8 80-119 272 271 286 294 311 326

9 Over 120 271 270 285 293 310 325

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

4) ALEF (55LA970T/65LA970T-DA)_aging chamber

GP3 Aging

time

(Min)

1 20 280 283 295 302 320 327

2 21-25 276 278 291 297 316 322

3 26-30 271 272 286 291 311 316

4 31-35 267 268 282 287 307 312

5 36-40 265 263 280 282 305 307

6 41-50 262 260 277 279 302 304

7 51-80 260 258 275 277 300 302

8 81-119 259 256 274 275 299 300

9 Over 120 259 255 274 274 299 299

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

■ In the SET applied LED module (LM9600), cause of the

physical characteristics of LED Module, sets are taken a
120 minutes by aging time to stabilize a color coordinates.
So White Balance Control equipments have to get the SET
Aging Time from the SET and then going to control the W/B
by revise color coordinates at each time

- To check the Coordinates of White Balance, you have to
measure at the below conditions.

Picture Mode : select Vivid and change
Dynamic Contrast : Off ,
Dynamic Colour : Off,
Clear White : Off

->Picture Mode change : Vidid -> Vivid(User)

(If you miss the upper condition, the coordinates of W/B can be
lower than the spec.)

5.3. Intelligent Sensor Inspection Guide

Step 1. Turn on the TV set.
Step 2. Press “EYE” button on the Adjustment remote controller.

Step 3. Block the Intelligent Sensor module on the front C/A
about 6 seconds.
When the “Sensor Data” is lower than 20, you can see the
“OK” message -> If it doesn’t show “OK” message, the Sensor
Module is defected one.
You have to replace that with a good one.

Step 4. After check the “OK” message come out, take out your
hand from the Sensor module.

-> Check “Sensor Data” value change from “0” to “300” or not.

If it doesn’t change the value, the sensor is also defected

one. You have to replace it.

Green Eye-Check

Sensor Data : 492
BackLight : 100

OK

Only for training and service purposes

- 20 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.4. LAN Inspection

1) LAN Port connection with PCB

2) Network setting at MENU Mode of TV

3) Setting automatic IP

4) Setting state conrmation

5) If automatic setting is nished, you conrm IP and MAC

Address

5.5. WIDEVINE Key Inspection

1) Conrm Key input Data at the “IN START” MENU Mode

5.6. Model name & Serial number D/L

5.6.1. Notice

1) Serial number D/L is using of scan equipment.

2) Setting of scan equipment operated by Manufacturing
Technology Group.

3) Serial number D/L must be conformed when it is produced in
production line, because serial number D/L is mandatory by
D-book 4.0

4) Check the model name In-start menu -> Factory name
displayed (ex 42LV5500-DD)

5) Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LV5500-DD)

5.7. Wi-Fi MAC ADDRESS CHECK

5.7.1. Notice

1) Using RS232

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

2) Check the menu on in-start

5.8. Local Dimming Inspection (Optional)

5.8.1. Edge LED models with local dimming

1) Press ‘TILT” key of the Adj. R/C and check moving pat­terns. The black bar patterns moves from left to right. If local
dimming function does not work, a whole screen shows full
white.

5.6.2. Method : Auto

1) Press “Power on” key of service remocon.(Baud rate : 115200
bps)

2) Connect RS232 Signal Cable to RS-232 Jack

3) Write Serial number by use RS-232.

4) Must check the serial number at Instart menu

5.6.3. Method : Manual

* If the TV set is downloaded By OTA or Service man, Sometimes
model name or serial number is initialized.
( Not always) It is impossible to download by bar code scan, so
It need Manual download.

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘6.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like photo.

Only for training and service purposes

- 21 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.9. GND and HI-POT Testing

5.9.1. GND & HI-POT auto-check preparation

(1) Check the POWER CABLE and SIGNAL CABE insertion

condition

5.9.2. GND & HI-POT auto-check

(1) Pallet moves in the station. (POWER CORD / AV CORD is

tightly inserted)
(2) Connect the AV JACK Tester
(3) Controller (GWS103-4) on.
(4) GND Test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)
(5) HI-POT test (Auto)

- If Test is failed, Buzzer operates.

- If Test is passed, GOOD Lamp on and move to next process

automatically

5.9.3. Check Point

(1) Test voltage
3 Poles : GND: 1.5KV/min at 100mA / SIGNAL: 3KV/min at

100mA
(2) TEST time: 1 second
(3) TEST POINT
3 Poles : GND Test = POWER COR D GND and SIGNAL

CABLE GND.
Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms

5.12. 3D Function test

5.12.1. Equipment

Pattern Generator MSPG-3233, HDMI mode 37, pattern No. 81

5.12.2. Equipment

1) Connect HDMI (HDMI mode 371, Pattern No. 81)

2) Insert 3D Mode, Select side by side mode.

3) Without 3D-glasses, Like below gure.

4) With 3D left-glass, Like below gure. (Center is RED)

5.10. Motion Remote controller Inspection

5.10.1. Equipment

Motion remote controller for test, IR-KEY-CODE remote
controller for test
Check battery before test. (Recommend : Change battery for
every Lot.)

5.10.2. Process

1) If you select the ‘start key(wheel)’ on the controller, you can

pairing with the TV SET.

2) You can check the cursor on the TV Screen, when select the

‘Wheel Key’ on the controller .

3) You must remove the pairing with the TV Set by select ‘Back

+ Home Key’ on the controller.

5.11. Audio

No Item Min Typ Max Unit Remark

1 Audio practical

max Output, L/R
(Distortion=10%
max Output)

2 Speaker (8Ω

Impedance)

▪ Measurement condition:

(1) RF input: Mono, 1 KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.4Vrms
(3) RGB PC: 1 KHz sine wave signal 0.7Vrms

9.0 10.0 12.0 W Measure-

8.5 8.9 9.8 Vrms

10.0 15.0 W Measure-

ment
condition
(TBD)

ment
condition
(TBD)

5) With 3Dright-glass, Like below gure.(Center is Blue)

Only for training and service purposes

- 22 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5.13. HDMI ARC Function Inspection

5.13.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

5.13.2. Test method

(1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

(2) Check the sound from the TV Set

5.14. Camera Function Inspection

(1) Objective : To check how it connects between Camera and

PCBA normally, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.

- Slide Camera Up.

- Camera’s Preview picture apeears on TV Set.

- Slide Camera Down.

<Slide Down Status><Slide Up Status>

(3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)

* Remark: Inspect in Power Only Mode and check SW version

in a master equipment

.

5.15. PIP/W&R Function Inspection

(1) Objective : To check the connection between sub tuner and

PCBA, and their Function

(2) Test Method : This Inspection is available only Power-Only

Status.

- Press exit key of the Adj. R/C and Press PIP key.

- Check that the SUB TUNER pop up window on the TV Set.

- Check that the normal operation (picture, sound) of DTV
on the TV Set

5.16. Outgoing condition Configuration

■ When pressing IN-STOP key by SVC remocon, Red LED

are blinked alternatively. And then automatically turn off.

(Must not AC power OFF during blinking)

Only for training and service purposes

- 23 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essenti al that these sp ecial safet y parts shoul d be replac ed with the same compon ents as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

700

710

900

914

400

521

522

570

121

913

912

911

571

540

LV2

530

LV1

580

610

120

600

CAM1

560

AT1

561

500

AV1

200

501

AG1

Only for training and service purposes

310

- 24 -

CA1

A22

A2

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

System Configuration

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

Clock for LG1154D

MAIN Clock(24Mhz)

10pF

C100

10pF

C101

System Clock for Analog block(24Mhz)

PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)

OPT

R100 33

R101 33

OPT

+3.3V_NORMAL

OPT

X-TAL_1

GND_1

1

2

X100

24MHz

4

3

GND_2

X-TAL_2

INSTANT boot MODE
"1 : Instant boot
"0 : normal

3.3K

R150

(internal pull down)

1M

R108

PLLSET1

PLLSET0

INSTANT_BOOT

INSTANT_MODE0

Jtag I/F For Main

TP101

TP102

TP103

TP104

TP105

TP106

+3.3V_NORMAL

TP109

TP108

Model Option

HW_OPT_0
HW_OPT_1

HW_OPT_2

HW_OPT_3

HW_OPT_4

HW_OPT_5

HW_OPT_6

HW_OPT_7

HW_OPT_8

HW_OPT_9

HW_OPT_10

AREA option1

FRC option

Pannel Resol

OLED option

EPI PANEL version

reserved

CP BOX

T2 support

satellite support

AREA option2

EPI selection

C106
33pF
50V

+3.3V_NORMAL

TAIWAN

R110 10K

NON_TAIWAN

R109 10K

10K

R112

INTERNAL_FRC

10K

NO_FRC

R111

XIN_MAIN

XO_MAIN

FHD

R114 10K

UD

R113 10K

TRST_N0
TDI0
TDO0
TMS0
TCK0
SOC_RESET

OLED

R116 10K

NON_OLED

R115 10K

+3.3V_NORMAL

BOOT MODE
"0 : EMMC
"1 : TEST MODE

3.3K

R117

OPT

3.3K

R118

BOOT_MODE0

V13_MODULE

R120 10K

V12_MODULE

R119 10K

OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode

+3.3V_NORMAL

BOOT_MODE

OPT

CP_BOX

R126 10K

R122 10K

R124 10K

DVB_T2_TUNER

NON_CP_BOX

R125 10K

R121 10K

R123 10K

NON_DVB_T2_TUNER

R1EX24256BSAS0A

A0

A1

A2

VSS

OPT

R133 33

R134 33

OPT

AJ_JA

DVB_S_TUNER

R129 10K

R128 10K

NON_AJ_JA

R130 10K

R127 10K

NON_DVB_S_TUNER

NVRAM

EEPROM_RENESAS

IC102

1

2

A0’h

3

4

EPI

R131 10K

NON_EPI

R132 10K

OPM1

OPM0

VCC

8

WP

7

SCL

6

SDA

5

C103

0.1uF

MODEL_OPT_0

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7

MODEL_OPT_8

MODEL_OPT_9

MODEL_OPT_10

+3.3V_TU

R135

3.3K

KR_PIP_NOT

1.5K

KR_PIP

R135-*1

+3.3V_NORMAL

Write Protection

- Low : Normal Operation

- High : Write Protection

R139 33

R140 33

Area1

FRCMODEL_OPT_1

Panel

OLED

Module

Reserved

CP BOX

T2 Tuner

S Tuner

Area2

EPI

+3.3V_TU

+3.3V_NORMAL

R137

3.3K

R138

3.3K

R136

3.3K

KR_PIP_NOT

1.5K

KR_PIP

R136-*1

HIGH

Taiwan

FRC(120Hz)

FHD

OLED

V13

Enable

Support

Support

AJ_JA

Support

R141

3.3K

R142

EPHY_INT

TP100
TP107
TP110
TP111

+3.3V_NORMAL

3.3K

R143

3.3K

I2C_SCL5

I2C_SDA5

IRB_SPI_SS
IRB_SPI_MOSI
IRB_SPI_MISO
IRB_SPI_CK

LOW

non Taiwan

No FRC(60Hz)

UD

NON OLED

V12

Default

Disable

Not Support

Not Support

non AJ_JA

Not Support

I2C PULL UP

R145

3.3K

R144

3.3K

R164331/16W

R146

3.3K

M24256-BRMN6TP

E0

E1

E2

VSS

R147

3.3K

EEPROM_ST

IC102-*1

VCC

8

1

WC

2

7

SCL

3

6

SDA

4

5

XIN_MAIN

XO_MAIN

SOC_RESET

H13A_SCL
H13A_SDA

TRST_N0

PLLSET1
PLLSET0

BOOT_MODE

5%

SOC_RX

SOC_TX
M_REMOTE_RX
M_REMOTE_TX

M_REMOTE_RTS
M_REMOTE_CTS

IRB_SPI_SS
IRB_SPI_MOSI
IRB_SPI_MISO

IRB_SPI_CK

I2C_SCL1

I2C_SDA1
I2C_SCL_MICOM_SOC
I2C_SDA_MICOM_SOC

I2C_SCL2_SOC
I2C_SDA2_SOC

I2C_SCL4

I2C_SDA4

I2C_SCL5

I2C_SDA5

I2C_SCL6

I2C_SDA6

I2C_SDA_MICOM
I2C_SCL_MICOM

I2C_SDA2
I2C_SCL2

R148

3.3K
I2C_SDA1
I2C_SCL1
I2C_SDA_MICOM_SOC

I2C_SCL_MICOM_SOC
I2C_SDA2_SOC

I2C_SCL2_SOC
I2C_SDA4
I2C_SCL4

I2C_SDA5
I2C_SCL5

I2C_SDA6
I2C_SCL6

OPM1
OPM0

TMS0
TCK0
TDI0
TDO0

R152

R149 33

R151 33
R174 33

R10533

33

R106

R10233

33

R104

I2C for tuner

I2C for tuner

560

A26

XIN

B26

XOUT

B27

XTAL_BYPASS

AT37

H13DA_XTAL

AU16

PORES_N

AD34

OPM1

AD33

OPM0

AT26

H13DA_SCL

AU26

H13DA_SDA

AP9

TRST_N0

AN9

TMS0

AP11

TCK0

AN11

TDI0

AN10

TDO0

AM10

TRST_N1

AM9

TMS1

AM11

TCK1

AM12

TDI1

AL11

TDO1

AL9

PLLSET1

AL10

PLLSET0

AE34

BOOT_MODE

Y33

EXT_INTR3/GPIO70

W32

EXT_INTR2/GPIO69

W33

EXT_INTR1/GPIO68

W34

EXT_INTR0/GPIO67

AU12

UART0_RXD

AT12

UART0_TXD

AU13

UART1_RXD

AT13

UART1_TXD

AP12

UART1_RTS

AR12

UART1_CTS

AE35

SPI_CS0/GPIO36

AE36

SPI_DO0/GPIO38

AF36

SPI_DI0/GPIO39

AF35

SPI_SCLK0/GPIO37

AG34

SPI_CS1

AF33

SPI_DO1

AG33

SPI_DI1

AG32

SPI_SCLK1

AR15

SCL0/GPIO66

AP15

SDA0/GPIO65

AR16

SCL1/GPIO64

AP16

SDA1/GPIO79

AP17

SCL2/GPIO78

AR17

SDA2/GPIO77

AP6

SCL3

AR6

SDA3

AH32

SCL4

AJ33

SDA4

AH34

SCL5

AH33

SDA5

I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC

I2C_SDA2_SOC

I2C_SCL2_SOC

+3.3V_NORMAL

CAM_CE1_N

CAM_CE2_N

CAM_CD1_N/GPIO76

F33

F34

D32

E32

/PCM_CE1

/PCM_CE2

CAM_CD1_N

CI

USB_CTL3

/USB_OCD3

/USB_OCD2

USB_CTL2

K35

K36

K37

L35

EB_CS3/GPIO93

EB_CS2/GPIO92

EB_CS1/GPIO91

EB_CS0/GPIO90

EB_WE_N

EB_BE_N1

EB_OE_N

H35

H36

J35

J36

H37

EB_WE_N/GPIO95

EB_WAIT/GPIO94

EB_OE_N/GPIO82

EB_BE_N1/GPIO81

EB_ADDR[0-14]

EB_BE_N0

EB_ADDR[13]

EB_ADDR[14]

EB_ADDR[12]

G37

G36

G35

F36

EB_BE_N0/GPIO80

EB_ADDR15/GPIO89

EB_ADDR14/GPIO88

EB_ADDR13/GPIO103

EB_ADDR12/GPIO102

EB_ADDR[8]

EB_ADDR[6]

EB_ADDR[7]

EB_ADDR[9]

EB_ADDR[11]

EB_ADDR[10]

F35

E36

E37

E35

D37

EB_ADDR9/GPIO99

EB_ADDR8/GPIO98

EB_ADDR7/GPIO97

EB_ADDR11/GPIO101

EB_ADDR10/GPIO100

EB_ADDR[4]

EB_ADDR[5]

EB_ADDR[3]

D36

D35

C36

C35

EB_ADDR6/GPIO96

EB_ADDR5/GPIO111

EB_ADDR4/GPIO110

EB_ADDR3/GPIO109

EB_ADDR[0]

EB_ADDR[1]

EB_ADDR[2]

EB_DATA[7]

B37

B36

B35

C32

EB_ADDR2/GPIO108

EB_ADDR1/GPIO107

EB_ADDR0/GPIO106

EB_DATA[0-7]

EB_DATA[5]

EB_DATA[6]

B33

A33

EB_DATA7/GPIO105

EB_DATA6/GPIO104

EB_DATA5/GPIO119

IC100

LG1154D_H13D

CAM_CD2_N/GPIO75

CAM_VS1_N/GPIO86

CAM_VS2_N/GPIO85

CAM_IREQ_N/GPIO73

CAM_RESET

CAM_INPACK/GPIO74

CAM_VCCEN_N/GPIO87

CAM_WAIT_N/GPIO84

CAM_REG_N/GPIO72

CAM_IOIS16_N/GPIO83

SC_CLK/GPIO130

SC_DETECT/GPIO133

SC_VCCEN/GPIO129

SC_VCC_SEL/GPIO128

SC_RST/GPIO131

SC_DATA/GPIO132

SD_CLK/GPIO125

SD_CMD/GPIO124

SD_CD_N/GPIO123

SD_WP_N/GPIO122

SD_DATA3/GPIO121

SD_DATA2/GPIO120

SD_DATA1/GPIO135

SD_DATA0/GPIO134

USB2_2_DP0

USB2_2_DM0

USB2_2_TXRTUNE

G32

G33

F32

G34

D33

H32

E33

D34

H33

T33

U33

T32

V32

V33

V34

A25

C25

B25

E25

D25

E24

D24

C24

L37

L36

K34

1%

200

CAM_CD2_N

R153

10K

PCM_RESET

CAM_IREQ_N

CAM_INPACK_N

CI

R154

10K

CAM_REG_N

CAM_WAIT_N

PCM_5V_CTL

R155

10K

CI

SMARTCARD_CLK/SD_EMMC_DATA[0]

SMARTCARD_DET/SD_EMMC_DATA[3]

interface

Only SMART CARD

SMARTCARD_DATA/SD_EMMC_CLK

SMARTCARD_VCC/SD_EMMC_CMD

SMARTCARD_RST/SD_EMMC_DATA[2]

SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]

R157

USB2_HUB_IC_IN_DM

USB2_HUB_IC_IN_DP

EB_DATA[2]

EB_DATA[4]

EB_DATA[3]

EB_DATA[0]

EB_DATA[1]

C33

A34

B34

C34

A36

EB_DATA4/GPIO118

EB_DATA3/GPIO117

EB_DATA2/GPIO116

EB_DATA1/GPIO115

EB_DATA0/GPIO114

USB2_1_DP0

USB2_1_DM0

USB2_1_TXRTUNE

USB2_0_DP

M37

M36

K33

AU7

1%

200

R159

WIFI_DP

USB_DM2

USB_DP2

EMMC_DATA[0-7]

EMMC_CLK

EMMC_CMD

EMMC_RST

Y37

Y36

W35

EMMC_CLK

EMMC_CMD

EMMC_RESETN

USB2_0_DM

USB2_0_TXRTUNE

USB3_DP0

AT7

AP7

P37

WIFI_DM

R161 200 1%

USB3_DP

EMMC_DATA[5]

EMMC_DATA[7]

EMMC_DATA[6]

T36

W36

V35

EMMC_DATA7

EMMC_DATA6

EMMC_DATA5

USB3_DM0

USB3_RX0P

USB3_RX0M

P36

N36

N37

USB3_DM

USB3_RX0P

USB3_RX0M

EMMC_DATA[4]

EMMC_DATA[3]

EMMC_DATA[2]

V37

V36

U35

EMMC_DATA4

EMMC_DATA3

EMMC_DATA2

USB3_TX0P

USB3_TX0M

USB3_RESREF

R36

R37

N34

1%

200

R162

C105 0.1uF

C104 0.1uF

USB3_TX0M

USB3_TX0P

U36

EMMC_DATA1

USB3_REFPADCLKM

P33

EPHY_MDIO

EPHY_EN

EPHY_MDC

EPHY_REFCLK

EPHY_CRS_DV

EMMC_DATA[1]

EMMC_DATA[0]

U37

AU11

AU8

AT8

AR8

AR10

AT10

RMII_MDC

RMII_MDIO

RMII_CRS_DV

RMII_REF_CLK

NC_1

NC_2

NC_3

L32

L33

M31

AJ31

RMII_TXEN

NC_4

J32

EMMC_DATA0

USB3_REFPADCLKP

P32

AC-coupling CAP

Place near by LG1154D

EPHY_RXD1

EPHY_TXD0

EPHY_TXD1

AU10

AT11

AR11

RMII_TXD1

RMII_TXD0

RMII_RXD1

GPIO136

GPIO137

GPIO138

J33

K32

J34

EPHY_RXD0

RMII_RXD0

GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25

GPIO24
GPIO23/UART2_TX
GPIO22/UART2_RX

GPIO21

GPIO20

GPIO19

GPIO18

GPIO17

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0

DDCD0_CK
DDCD0_DA

HPD0

PHY0_ARC_OUT_0

PHY0_RX0N_0
PHY0_RX0P_0
PHY0_RX1N_0
PHY0_RX1P_0
PHY0_RX2N_0
PHY0_RX2P_0
PHY0_RXCN_0
PHY0_RXCP_0

HUB_PORT_OVER0

HUB_VBUS_CTRL0

GPIO139

TP112

IR_B_RESET

IR_B_RESET

AL34
AM33
AM32
AF30
AN34
AK34
AL33
AL32
AR9
AM5
AM6
AM7
AL6
AK7
AK6
AK5
AJ5
AJ6
AJ7
AH6
AG7
AG6
AG5
AF5
AH30
AG30
AN33
AK33
AE30
AD30
AN32
AK32

AC32
AC33
AB33

AE37
AC36
AC37
AB36
AB37
AA36
AA37
AD36
AD37

R32

R33

CAM_SLIDE_DET

/RST_PHY
RF_SWITCH_CTL

UART2_TX
UART2_RX
AMP_RESET_N

INSTANT_BOOT

SC_DET
AV1_CVBS_DET

COMP1_DET
M_RFModule_RESET
HP_DET
FRC_RESET
/TU_RESET1
/S2_RESET
VCOM_DYN
PMIC_RESET
/RST_HUB
FE_LNA_Ctrl2
/TU_RESET2
HDMI_S/W_RESET

FE_LNA_Ctrl1
HDMI_INT

R169 3.3K
R170 3.3K

SPDIF_OUT_ARC

HDMI_RX0­HDMI_RX0+
HDMI_RX1­HDMI_RX1+
HDMI_RX2­HDMI_RX2+
HDMI_CLK-

HDMI_CLK+

/USB_OCD1

USB_CTL1

UART2_RX

UART2_TX

local dimming

+3.3V_NORMAL

Debug

+3.3V_NORMAL

R165

3.3K

I2C port

+3.3V_NORMAL

SW100

JTP-1127WEM

4 3

DEBUG

P101

12507WS-04L

1

DEBUG

2

3

4

For ISP

12

DEBUG

5

R103

3.3K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BSD-NC4_H001-HD

2012-11-14

H13 D CHIP

LG1154A

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

LG1154D

AVDD25

VDD25_LTX

VDDC10

GND JIG POINT

AVDD33_CVBS

VDD25_REF

VDD25_LTX

VDD25_AUD

VDD10_XTAL

VDD10_XTAL

AVDD33_XTAL

VSS25_REF

LG1154A

H13A_NON_BRAZIL

AVDD33

E11

F5
F6

F11

G5
H13
J13
P12
P13

R5

R6
N16
T13
T14

N10
N11
N12
N13

U5

N7

N8

N9
F14

M6

N6
M13
F15
F16
H15
J15
J16
K15
K16

R18

G7

G8

G9

H7
H12

J7
J12

K7
K12

L7
L12

M7
M12
T17
T18

M8
G10
G11
G12

V5

C3

D3

D4
D17

E4

F4

F7

F8

F9
F10
F12
F13
F17
F18

G4

G6
G13
G14
G15
G16
G17
G18

H4

H5

H6

H8

H9
H10
H11

JP202

JP203

LG1154AN_H13A

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_XTAL
AVDD33_CVBS_1
AVDD33_CVBS_2

VDD25_CVBS_1
VDD25_CVBS_2
VDD25_VSB_1
VDD25_VSB_2
VDD25_REF
VDD25_COMP_1
VDD25_COMP_2
VDD25_COMP_3
VDD25_APLL
VDD25_AUD_1
VDD25_AUD_2
VDD25_AAD
LTX_LVDD_1
LTX_LVDD_2
SDRAM_VDDQ_1
SDRAM_VDDQ_2
SDRAM_VDDQ_3
SDRAM_VDDQ_4
SDRAM_VDDQ_5

VDD10_XTAL
VDDC10_1
VDDC10_2
VDDC10_3
VDDC10_4
VDDC10_5
VDDC10_6
VDDC10_7
VDDC10_8
VDDC10_9
VDDC10_10
VDDC10_11
VDDC10_12
VDDC10_13
AVDD10_CVBS
AVDD10_VSB
AVDD10_LLPLL
DVDD10_APLL_1
DVDD10_APLL_2
LTX_VDD

VSS25_REF
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29

JP204

JP205

IC101

GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116

H14
J4
J5
J6
J8
J9
J10
J11
J14
K4
K5
K6
K8
K9
K10
K11
K13
K14
L1
L2
L3
L4
L5
L6
L8
L9
L10
L11
L13
L14
L15
L16
L17
L18
M1
M2
M3
M4
M5
M9
M10
M11
M14
M15
M16
N4
N5
N14
N15
N17
P4
P5
P6
P7
P8
P9
P10
P11
P14
P15
P16
R4
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T4
T7
T8
T9
T10
T11
T12
T15
T16
U4
U6
U18
V4
V16

SMD TOP for EMI

NON_LA8600

GASKET_8.0X6.0X8.5H

M200

MDS62110209

+3.3V_Bypass Cap

+3.3V_NORMAL

AVDD33

L209

BLM18PG121SN1D

(2)

4.7uFC241

C218 0.1uF

+2.5V_Bypass Cap

+2.5V_Normal

L220
BLM18PG121SN1D

+2.5V_Normal

L207
BLM18PG121SN1D

+1.0V_Bypass Cap

+1.0V_VDD

L211
BLM18PG121SN1D

+1.0V_VDD

L206
BLM18PG121SN1D

4.7uFC211

VDD25_LTX

4.7uFC275

+3.3V_NORMAL

AVDD25

4.7uFC242

4.7uFC216

C223 0.1uF

VDD10_XTAL

4.7uFC239

VDDC10

4.7uFC214

AVDD33_XTAL

(1)

L216
BLM18PG121SN1D

4.7uFC255

C259 0.1uF

AFE 3CH Power

BLM15BD121SN1

4.7uFC270

BLM15BD121SN1

C274 0.1uF

1005 size bead
Bottom side of chip

+2.5V_Normal

C246 0.1uF

C251 0.1uF

+3.3V_NORMAL

AVDD33_CVBS

L222
BLM18PG121SN1D

VDD25_REF

L225

0.1uF

L226

C288

VSS25_REF

VDD25_AUD

L200

BLM18PG121SN1D

4.7uF

4.7uF

C204 0.1uF

C200

C202

+3.3V_Bypass Cap

+3.3V_NORMAL

L203

BLM18PG121SN1D

4.7uFC279

(2)

C283 0.1uF

VDD33

4.7uFC201

C203 0.1uF

+1.1V_Bypass Cap

+1.1V_VDD

4.7uFC297

4.7uFC351

+1.1V_VDD

L227

BLM18PG121SN1D

VDDC11_XTAL

4.7uFC298

+1.1V_VDD

VDD11_VTXPHY

L201

BLM18PG121SN1D

4.7uFC209

OPT

4.7uFC205

+1.5V_Bypass Cap

+1.5V_DDR

L230

L228

VDDC15_M0

22uF

C303

VDDC15_M1

22uFC299

C302

C307

0.1uF

C306

0.1uF

+1.5V_DDR

BLM18PG121SN1D

BLM18PG121SN1D

+2.5V_Bypass Cap

+2.5V_Normal

L234

BLM18PG121SN1D

0.1uF

C300 0.1uF

C301 0.1uF

C206 0.1uF

C308

C207 0.1uF

0.1uF

OPT

C208 0.1uF

VDDC15_M0

R200

R201

1K 1%

VDDC15_M1

R300

R301

1K 1%

VDD25_XTAL

4.7uFC364

OPT

VREF_M0_0

1K 1%

C296

VREF_M1_0

1K 1%

C304

C368 0.1uF

OPT

0.1uF

OPT

0.1uF

VDDC15_M0

R202

1K 1%

R203

1K 1%

VDDC15_M1

R302

1K 1%

R303

1K 1%

VREF_M0_1

OPT

0.1uF

C344

VREF_M1_1

OPT

0.1uF

C310

+2.5V_Normal

(1)

L238

BLM18PG121SN1D

VDD25_LVDS

4.7uFC378

+0.75V

+3.3V

+2.5V

+1.5V

(4)

C381 0.1uF

VREF_M1_1

VDDC11_XTAL

VDD25_XTAL

VDD33

VDD25_LVDS

VDD25_XTAL

VREF_M0_1

VREF_M1_0

VDDC15_M0

VDDC15_M1

VREF_M0_0

A24

P26
N26

M21
Y30

AA30

AE8

AF8
AK13
AK24
AK25

M22

M23
AK11
AK12
AF25
AF26

R31

AE23
AF23
AE14
AF14

N25
AD26

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

LG1154AN_H13A_ISDB-T (LG1154AN-IT)

M0_DDR_VREF1

A4

M0_DDR_VREF2

A2

M1_DDR_VREF1

Y1

M1_DDR_VREF2

XTAL_VDD
XTAL_VDDP

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8

AVDD33_USB_1
AVDD33_USB_2
AVDD33_BT_USB_1
AVDD33_BT_USB_2
AVDD33_HDMI_1
AVDD33_HDMI_2

SP_VQPS

VDD25_LVRX_1
VDD25_LVRX_2
VTXPHY_VDD25_1
VTXPHY_VDD25_2
VDD25_DR3PLL
GPLL_AVDD25

VDD15_M0_1
VDD15_M0_2
VDD15_M0_3
VDD15_M0_4
VDD15_M0_5
VDD15_M0_6
VDD15_M0_7
VDD15_M0_8
VDD15_M0_9
VDD15_M0_10
VDD15_M0_11
VDD15_M0_12
VDD15_M0_13
VDD15_M0_14
VDD15_M0_15
VDD15_M0_16

H7

VDD15_M1_1

H8

VDD15_M1_2

J8

VDD15_M1_3

K8

VDD15_M1_4

L7

VDD15_M1_5

L8

VDD15_M1_6

M8

VDD15_M1_7

N7

VDD15_M1_8

N8

VDD15_M1_9

P8

VDD15_M1_10

R7

VDD15_M1_11

R8

VDD15_M1_12

T8

VDD15_M1_13

U8

VDD15_M1_14

V8

VDD15_M1_15

W8

VDD15_M1_16

P17

XIN_SUB

P18

XO_SUB

J17

VSB_AUX_XIN

N18

XTAL_BYPASS

D18

CLK_24M

M18

XTAL_SEL0

M17

XTAL_SEL1

E3

PORES_N

K3

OPM0

K2

OPM1

A8

H13A_SCL

B8

H13A_SDA

U13

CVBS_IN3

V14

CVBS_IN2

V15

CVBS_IN1

V13

CVBS_VCM

U15

BUF_OUT1

U14

BUF_OUT2

U7

REFT

V6

REFB

V7

ADC1_COM

U10

ADC2_COM

V12

ADC3_COM

T5

SC1_SID

T6

SC1_FB

U8

PB1_IN

V8

Y1_IN

V9

SOY1_IN

U9

PR1_IN

V10

PB2_IN

U11

Y2_IN

V11

SOY2_IN

U12

PR2_IN

IC100

LG1154D_H13D

VTXPHY_VDD11_1
VTXPHY_VDD11_2
VTXPHY_VDD11_3

H13A_BRAZIL

IC101-*1

AAD_ADC_SIF

AAD_ADC_SIFM

AUDA_VBG_EXT

AUDA_OUTL

AUDA_OUTR
AUD_SCART_OUTL
AUD_SCART_OUTR

AUAD_L_CH4_IN
AUAD_R_CH4_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN
AUAD_L_CH2_IN
AUAD_R_CH2_IN
AUAD_L_CH1_IN
AUAD_R_CH1_IN

AUAD_R_REF
AUAD_M_REF
AUAD_L_REF

AUAD_REF_PO

ANTCON

RFAGC
IFAGC

ADC_I_INCOM

ADC_I_INP

ADC_I_INN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15

VDDC11_1
VDDC11_2
VDDC11_3
VDDC11_4
VDDC11_5
VDDC11_6
VDDC11_7
VDDC11_8

VDDC11_9
VDDC11_10
VDDC11_11
VDDC11_12
VDDC11_13
VDDC11_14
VDDC11_15
VDDC11_16
VDDC11_17
VDDC11_18
VDDC11_19
VDDC11_20
VDDC11_21
VDDC11_22
VDDC11_23
VDDC11_24
VDDC11_25
VDDC11_26
VDDC11_27
VDDC11_28
VDDC11_29
VDDC11_30
VDDC11_31
VDDC11_32
VDDC11_33
VDDC11_34
VDDC11_35

AVDD11_DR3PLL

AVDD11_DCO
GPLL_VDD11

H18
H17

P2
N1
N2
N3
P1

P3
R1
R2
T1
U2
U3
V2
V3
U1
T3
T2
R3

K17
K18
J18

U16
U17
V17

F3
F2
F1
G3
G2
G1
H3
H2
H1
J3
E18
E17
H16
J2
J1
K1

N21
N22
N23
P15
P16
P17
P18
R15
T15
T22
T23
T24
U15
U22
U23
U24
V15
V22
V23
V24
W22
W23
W24
AB15
AB24
AC15
AC24
AD15
AD16
AD17
AD18
AD21
AD22
AD23
AD24

AB14
AC14
AD14

P25
AA15
AC26

+1.1V_VDD

VDD11_VTXPHY

VDDC11_XTAL

+1.1V_VDD

+1.1V

A27

B5

C5
C26
C27

D5
D26

E5

E6

E7

E8
E22
E23
E26

F7

F8
F22
F23
F24
F25
F26
F27
F31

G7

G8

G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31

H9
H26
H27
H28
H29
H30
H31

J7
J30
J31

K7
K30
K31
L30
L31

M7
M12
M13
M14
M15
M16
M17
M18
M19
M20
M24
M25
M26
M30
M32
M33
M34
N12
N13
N14
N15
N16
N17
N18
N19
N20
N24
N30
N31
N32
N33

P7
P12
P13
P14
P19
P20
P21
P22
P23
P24
P30
P31
R12
R13
R14
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R30
R34

T7
T12
T13
T14
T16
T17
T18
T19
T20
T21
T25
T26
T30
T31
T34

U7
U12
U13
U14
U16
U17
U18
U19
U20
U21
U25
U26
U30
U31

V7
V12
V13
V14
V16
V17
V18
V19
V20
V21
V25
V26
V30
V31

W5

W6

W7
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W25
W26
W30
W31

Y3

Y4

LG1154D_H13D

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184

IC100

GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264
GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272
GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
GND_287
GND_288
GND_289
GND_290
GND_291
GND_292
GND_293
GND_294
GND_295
GND_296
GND_297
GND_298
GND_299
GND_300
GND_301
GND_302
GND_303
GND_304
GND_305
GND_306
GND_307
GND_308
GND_309
GND_310
GND_311
GND_312
GND_313
GND_314
GND_315
GND_316
GND_317
GND_318
GND_319
GND_320
GND_321
GND_322
GND_323
GND_324
GND_325
GND_326
GND_327
GND_328
GND_329
GND_330
GND_331
GND_332
GND_333
GND_334
GND_335
GND_336
GND_337
GND_338
GND_339
GND_340
GND_341
GND_342
GND_343
GND_344
GND_345
GND_346
GND_347
GND_348
GND_349
GND_350
GND_351
GND_352
GND_353
GND_354
GND_355
GND_356
GND_357
GND_358
GND_359
GND_360
GND_361
GND_362
GND_363
GND_364
GND_365
GND_366
GND_367
GND_368

Y5

Y8
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y31
Y35
AA8
AA12
AA13
AA14
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA31
AB6
AB8
AB12
AB13
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB25
AB26
AB30
AB31
AC8
AC12
AC13
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC25
AC30
AC31
AD8
AD12
AD13
AD19
AD20
AD25
AD31
AE12
AE13
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE24
AE25
AE26
AE31
AF12
AF13
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF24
AF31
AG8
AG31
AH8
AH31
AJ8
AJ30
AK8
AK9
AK10
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK26
AK27
AK28
AK29
AK30
AK31
AL8
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AM8
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AN6
AN12
AN13
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

11/05/31

BSD-NC4_H002-HD

2012-12-24

MAIN POWER

Place JACK Side

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

AV1_CVBS_IN

SC_CVBS_IN

SC_CVBS_IN_SOY

COMP1_Pb

COMP1_Pr

SCART_Lout

SCART_Rout

HP_LOUT_MAIN

HP_ROUT_MAIN

TU_CVBS

SC_FB

SC_ID

NON_EU
R422-*1

COMP1_Y

5.5V

D404

0

SCART_FB_DIRECT

SC_B
SC_G

SC_R

D403

D401

5.5V

5.5V

Near Place Scart AMP

C6006

1uF 25V
C6001

SC_L_IN

SC_R_IN

COMP1/AV1/DVI_L_IN

COMP1/AV1/DVI_R_IN

+12V

R430

R445

L408

C405
150pF
50V

C408
150pF
50V

EU

C402
150pF
50V

OPT

SCART_FB_DIRECT

R423 100

10K

EU

R435

R422
75

10pF

10pF

C473

C472

50V

50V

OPT

D406

5.5V

EU

EU

10K

1uF25V

R60 06

EU

EU

10K
R6005

EU

EU

R408

100K

R403

100K

EU

C403

2.2uF
10V

EU

EU

R404

100K

R409

100K

R6450

100

C400

0.01uF

22K

R6451

C401

0.01uF

22K

L409

OPT

C430

EU

C474

2.2uF

100

10pF

50V

10V

1uH

C410
150pF

1uH

C462
150pF

EU

EU

R436

2.7K

10pF

EU

50V

OPT

10pF

C431

C470

50V

SCART_AMP_R_FB

SCART_AMP_L_FB

EU

C406

+3.3V_NORMAL

R4641K1/16W

1%

R465

390

1/16W

1%

DAC_START_PULLDOWN

R466821/16W

R410
75
1%

R411
75

EU

1%

NON_EU

R436-*1

0

75

75

EU

75

1%

1%

1%

R416

R414

R412

10pF

50V

SCART_Lout_SOC

SCART_Rout_SOC

AUDA_OUTL

AUDA_OUTR

C404

0.01uF
50V

EU

75

1%

R413

75

1%

R415

1%

75

1%

R417

CLK_54M_VTT

FOR EMI

R418 27K

R419 27K

R420 27K

R421 27K

MAIN Clock(24Mhz)

C426

C427

Place SOC Side

R434

C424 0.047uF

100

R433

C425 0.047uF

100

SC_CVBS_IN_SOY

R432

C423 0.047uF

100

R424

C417 0.047uF

33

R425

C418 0.047uF

33

C428 1000pF

R427

R428
R429

C419

33

C420 0.047uF

33

C421 0.047uF

33

C429 1000pF
C422 0.047uF

33

R431

0.047uF

AUDIO IN

1%

1%

1%

1%

SCART_FB_BUFFER

SC_FB

C432 4.7uF

R437 10K 1%

C433 4.7uF

R438 10K 1%

C434 4.7uF

R439 10K 1%

C435 4.7uF

R440 10K 1%

R401
470

1/16W
5%

R4061K

SCART_FB_BUFFER

SCART_FB_BUFFER

B

1/16W

1%

Clock for H13A

10pF

10pF

+3.3V_NORMAL

R446

4.7K

C

E

X-TAL_1

GND_1

1

2

4

3

GND_2

X-TAL_2

AV1_CVBS_IN_SOC

SC_CVBS_IN_SOC

TU_CVBS_SOC

SC_FB_SOC

SC_ID_SOC

COMP1_PB_IN_SOC
COMP1_Y_IN_SOC
COMP1_Y_IN_SOC_SOY

COMP1_PR_IN_SOC

COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
COMP2_Y_IN_SOC_SOY

COMP2_PR_IN_SOC

SC_FB_BUF

MMBT3904(NXP)

Q400

SCART_FB_BUFFER

R441

X400

24MHz

AUAD_L_CH3_IN

AUAD_R_CH3_IN

AUAD_L_CH2_IN

AUAD_R_CH2_IN

Tuner IF Filter

1M

COMP1_PB_IN_SOC

COMP1_Y_IN_SOC

COMP1_Y_IN_SOC_SOY

COMP1_PR_IN_SOC
COMP2_PB_IN_SOC

COMP2_Y_IN_SOC

COMP2_Y_IN_SOC_SOY

COMP2_PR_IN_SOC

ADC_I_INN

ADC_I_INP

BLM18PG121SN1D

HP_LOUT_AMP

XIN_SUB

XOUT_SUB

XIN_SUB

XOUT_SUB

XTAL_SEL[0]
XTAL_SEL[1]

SOC_RESET

OPM[0]
OPM[1]

H13A_SCL

H13A_SDA

AV1_CVBS_IN_SOC

SC_CVBS_IN_SOC

TU_CVBS_SOC

DTV/MNT_V_OUT_SOC

Placed as close as possible to SOC

REFT
REFB

R447 68
R448 68
R449 68

SC_ID_SOC
SC_FB_SOC

+3.3V_NORMAL

DTV/MNT_V_OUT

To ADC

HP_OUT
L400

HP_OUT
C407

0.22uF
10V

R450

C439

OPT

100pF
50V

C440 0.047uF
C441 0.047uF
C442 0.047uF

MM1756DURE

VCC

6

PS

5

OUT

4

NON_TU_BR/TW

R443

51

NON_TU_W_BR/TW

NON_TU_BR/TW

R444

51

HP_LOUT

C443 0.047uF
68

IC400

Place at JACK SIDE

OP MODE Setting
& Select XTAL Input

OP MODE[0:1] : SW[2:1]
00 => Normal Operaiton Mode
/T32 Debug Mode
01 => Internal Test Purpose
10 => Internal Test Purpose
11 => Internal Test Purpose

XTAL SEL[1:0] : SW[4:3]
00 => Xtal Input
01 => CLK 24M from H13D
10 => XTAL Bypass from H13D

IC101

LG1154AN_H13A

P17

XIN_SUB

IN

1

GND

2

BIAS

3

TU_W_BR/TW

R443-*1

220

0.01uF

0.01uF

BLM18PG121SN1D

HP_ROUT_AMP

P18
J17

N18
D18
M18
M17

E3

K3
K2

A8
B8

U13
V14
V15
V13

U15
U14

U7
V6

V7
U10
V12

T5

T6

U8

V8

V9

U9
V10
U11
V11
U12

EU

TU_W_BR/TW

C437

L406

C438

HP_OUT

L401

XO_SUB
VSB_AUX_XIN

XTAL_BYPASS
CLK_24M
XTAL_SEL0
XTAL_SEL1

PORES_N

OPM0
OPM1

H13A_SCL
H13A_SDA

CVBS_IN3
CVBS_IN2
CVBS_IN1
CVBS_VCM

BUF_OUT1
BUF_OUT2

REFT
REFB
ADC1_COM
ADC2_COM
ADC3_COM
SC1_SID
SC1_FB
PB1_IN
Y1_IN
SOY1_IN
PR1_IN
PB2_IN
Y2_IN
SOY2_IN
PR2_IN

EU

C412

0.1uF

DTV/MNT_V_OUT_SOC

EU

4.7uF

C413

R444-*1

220

OPT

C414

0.1uF

EU

TU_W_BR/TW

HP_OUT
C409

0.22uF
10V

C436-*1
100pF

IF_N

IF_P

HP_ROUT

R453 330

C436
22pF

Placed as close as possible to IC100

H13A_NON_BRAZIL

AAD_ADC_SIF

AAD_ADC_SIFM

AUDA_VBG_EXT

AUDA_OUTL

AUDA_OUTR
AUD_SCART_OUTL
AUD_SCART_OUTR

AUAD_L_CH4_IN
AUAD_R_CH4_IN
AUAD_L_CH3_IN
AUAD_R_CH3_IN
AUAD_L_CH2_IN
AUAD_R_CH2_IN
AUAD_L_CH1_IN
AUAD_R_CH1_IN

AUAD_R_REF
AUAD_M_REF
AUAD_L_REF

AUAD_REF_PO

ANTCON

RFAGC
IFAGC

ADC_I_INCOM

ADC_I_INP

ADC_I_INN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15

Placed as close as possible to IC4300

+3.3V_NORMAL

10K

10K

10K

10K

OPT

OPT

OPT

OPT

R481

R482

R483

OPT
1uF

25V

R479100
R480100

HW_OPT_0
HW_OPT_1

HW_OPT_3
HW_OPT_4
HW_OPT_5

HW_OPT_7
HW_OPT_8
HW_OPT_9

SC_FB_BUF

OPT

R484

R426

22K

EU

ADC_I_INP
ADC_I_INN

HW_OPT_2

HW_OPT_6

HW_OPT_10

MHL_ON_OFF

1%

R45 5

51K

R45 647K 1%

R45421/10W

5%

C448

OPT

4.7uF
10V

H18

C450 0.1uF

H17

C451 0.1uF

C453 2.2uF

P2
N1
N2
N3
P1

P3
R1
R2
T1
U2
U3
V2
V3
U1
T3
T2
R3

K17
K18
J18

U16

C454 0.1uF

U17
V17

F3
F2
F1
G3
G2
G1
H3
H2
H1
J3
E18
E17
H16
J2
J1
K1

AUAD_REF_PO

AUAD_L_REF

AUAD_R_REF

AUAD_M_REF

100

R459

100

R460

100

R461

100

R462

10uFC452

AUDA_OUTL
AUDA_OUTR

EU

EU

AUAD_L_CH3_IN
AUAD_R_CH3_IN
AUAD_L_CH2_IN
AUAD_R_CH2_IN

AUAD_R_REF
AUAD_M_REF
AUAD_L_REF
AUAD_REF_PO

C447

AFE 3CH REF Setting

Placed as close as possible to IC4300

C444

0.1uF

C445

0.1uF

DIMMING

PWM_DIM2

PWM_DIM

C446

0.1uF

R490

R489

REFT

Must be used

REFB

100

100

OPM[0]

OPM[1]
XTAL_SEL[0]
XTAL_SEL[1]

TUNER_SIF

C457

1000pF

OPT

R442

22K

EU

EU

EU

C458 0.01uF

C460 0.01uF

Close to IC4300

NON_TU_W_BR/TW/CO

R487

0

C459

0.1uF

TU_W_BR/TW/CO

TU_W_BR/TW/CO

R487-*1

10K

+2.5V_Normal

C455

10uF

1%
R45 7
51K

C4494.7uF

1%

C456

R45 8

4.7uF

47K

10V

PWM1

PWM2

SCART_Lout_SOC

SCART_Rout_SOC

IF_AGC

L407

LG1154AN_H13A

L/DIM0_VS

L/DIM0_SCLK
L/DIM0_MOSI

IC101

INTR_GBB

INTR_AFE3CH

INTR_AGPIO

AUD_FS20CLK
AUD_FS21CLK
AUD_FS23CLK
AUD_FS24CLK
AUD_FS25CLK

AUDCLK_OUT_SUB

AUD_HDMI_MCLK

AUD_DAC1_LRCK

AUD_DAC1_SCK
AUD_DAC1_LRCH
AUD_DAC0_LRCK

AUD_DAC0_SCK
AUD_DAC0_LRCH

AUD_ADC_LRCK

AUD_ADC_SCK

AUD_ADC_LRCH

BB_SCL

BB_SDA
BB_TP_CLK
BB_TP_ERR
BB_TP_SOP
BB_TP_VAL

BB_TP_DATA7
BB_TP_DATA6
BB_TP_DATA5
BB_TP_DATA4
BB_TP_DATA3
BB_TP_DATA2
BB_TP_DATA1
BB_TP_DATA0

CLK_F54M
CVBS_GC2
CVBS_GC1
CVBS_GC0

CVBS_UP
CVBS_DN

FS00CLK

AUDCLK_OUT

DAC_START
DAC_DATA4
DAC_DATA3
DAC_DATA2
DAC_DATA1
DAC_DATA0

AAD_GC4
AAD_GC3
AAD_GC2
AAD_GC1
AAD_GC0

AAD_DATA9
AAD_DATA8
AAD_DATA7
AAD_DATA6
AAD_DATA5
AAD_DATA4
AAD_DATA3
AAD_DATA2
AAD_DATA1
AAD_DATA0

AAD_DATAEN

ADCO_OUT_CLK

HSR_AP0
HSR_AM0
HSR_BP0
HSR_BM0
HSR_CP0

HSR_CM0
HSR_CLKP0
HSR_CLKM0

HSR_DP0

HSR_DM0

HSR_EP0

HSR_EM0

R402 33
R405 33
R400 33

DPM

H13A_NON_BRAZIL

E1
E2
D1

A6
B6
A5
B5
A4
C4

C18

A2
B2
B1
C2
C1
D2
B4
A3
B3

A7
B7
E8
D8
C8
E7
D7
C7
E6
D6
C6
E5
D5
C5

CLK_54M_VTT

1/16W1%

B10
C9
B9
A9
D9
E9

Close to LG1154A

B11

R492 330

A11

R407 330

D11
C11
E10
D10
C10
A10

R451 330

D13
C13
E12
D12
C12

C17
E16
D16
C16
E15
D15
C15
E14
D14
C14
E13

B18

A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17

PWM1
PWM2

BPL_IN

EO_SOC

GST_SOC

MCLK_SOC
GCLK_SOC

R467 82

DPM

AT16
AU17
AT17

AT24
AU24
AT23
AU23
AT22

AU36

AT20
AU20
AT19
AU19
AT18
AU18
AU22
AT21
AU21

AT25
AU25
AP23
AR23
AP22
AR22
AP21
AR21
AP20
AR20
AP19
AR19
AP18
AR18

AU28
AR24
AU27
AT27
AP24
AR25

AU29

DAC_START_PULLDOWN

AT29

AP27
AR27
AP26
AR26
AP25
AT28

AR30
AP29
AR29
AP28
AR28

AP35
AR35
AP34
AR34
AP33
AR33
AP32
AR32
AP31
AR31
AP30

AT36

AT30
AU30
AT31
AU31
AT32
AU32
AT33
AU33
AT34
AU34
AT35
AU35

AT14
AT15
AU15

NC

AR14
AP14
AN14
AP13

LG1154DLG1154A

INTR_GBB
INTR_AFE3CH
INTR_AGPIO

AUD_FS20CLK
AUD_FS21CLK
AUD_FS23CLK
AUD_FS24CLK
AUD_FS25CLK

AUD_HDMI_MCLK

AUD_DAC1_LRCK
AUD_DAC1_SCK
AUD_DAC1_LRCH
AUD_DAC0_LRCK
AUD_DAC0_SCK
AUD_DAC0_LRCH
AUD_ADC_LRCK
AUD_ADC_SCK
AUD_ADC_LRCH

BB_SCL
BB_SDA
BB_TPI_CLK
BB_TPI_ERR
BB_TPI_SOP
BB_TPI_VAL
BB_TPI_DATA7
BB_TPI_DATA6
BB_TPI_DATA5
BB_TPI_DATA4
BB_TPI_DATA3
BB_TPI_DATA2
BB_TPI_DATA1
BB_TPI_DATA0

CLK_54M
CVBS_GC2
CVBS_GC1
CVBS_GC0
CVBS_UP
CVBS_DN

FS00CLK
H13A_AUDCLK_OUT

DAC_START
DAC_DATA4
DAC_DATA3
DAC_DATA2
DAC_DATA1
DAC_DATA0

AAD_GC4
AAD_GC3
AAD_GC2
AAD_GC1
AAD_GC0

AAD_DATA9
AAD_DATA8
AAD_DATA7
AAD_DATA6
AAD_DATA5
AAD_DATA4
AAD_DATA3
AAD_DATA2
AAD_DATA1
AAD_DATA0
AAD_DATAEN

ADCO_OUT_CLK

HSR_AP
HSR_AM
HSR_BP
HSR_BM
HSR_CP
HSR_CM
HSR_CLKP
HSR_CLKM
HSR_DP
HSR_DM
HSR_EP
HSR_EM

AUD_HPDRV_LRCH
AUD_HPDRV_LRCK
AUD_HPDRV_SCK

AC7

FRC_LR_O_SYNC_FLAG

AN5

L_VSOUT_LD
DIM0_SCLK
DIM0_MOSI
DIM1_SCLK
DIM1_MOSI

AF6

PWM0

AF7

PWM1

AD7

PWM2

AE6

PWM_IN

AP5

EPI_EO

AN8

EPI_VST

AP8

EPI_DPM

AR7

EPI_MCLK

AN7

EPI_GCLK

IC100

LG1154D_H13D

STPI0_CLK/GPIO47
STPI0_SOP/GPIO46
STPI0_VAL/GPIO45
STPI0_ERR/GPIO44

STPI0_DATA/GPIO43

STPI1_CLK/GPIO42
STPI1_SOP/GPIO41
STPI1_VAL/GPIO40
STPI1_ERR/GPIO55

STPI1_DATA/GPIO54

TPIO_DATA0/GPIO58
TPIO_DATA1/GPIO59
TPIO_DATA2/GPIO60
TPIO_DATA3/GPIO61
TPIO_DATA4/GPIO62
TPIO_DATA5/GPIO63
TPIO_DATA6/GPIO48
TPIO_DATA7/GPIO49

DACSLRCH/GPIO127
PCMI3SCK/GPIO112

PCMI3LRCK/GPIO113

DACCLFCH/GPIO126

TP_DVB_CLK
TP_DVB_SOP
TP_DVB_VAL

TP_DVB_ERR
TP_DVB_DATA0
TP_DVB_DATA1
TP_DVB_DATA2
TP_DVB_DATA3
TP_DVB_DATA4
TP_DVB_DATA5
TP_DVB_DATA6
TP_DVB_DATA7

TPI_CLK
TPI_SOP
TPI_VAL

TPI_ERR
TPI_DATA0
TPI_DATA1
TPI_DATA2
TPI_DATA3
TPI_DATA4
TPI_DATA5
TPI_DATA6
TPI_DATA7

TPIO_CLK/GPIO53
TPIO_SOP/GPIO52
TPIO_VAL/GPIO51
TPIO_ERR/GPIO50

AUDCLK_OUT

DACLRCH

DACSCK

DACLRCK

PCMI3LRCH

IEC958OUT

DACSUBMCLK
DACSUBLRCH

DACSUBSCK

DACSUBLRCK

TEST1
TEST2

TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
TX4N
TX4P
TX5N
TX5P
TX6N
TX6P
TX7N
TX7P
TX8N
TX8P
TX9N

TX9P
TX10N
TX10P
TX11N
TX11P
TX12N
TX12P

TX13N
TX13P
TX14N
TX14P
TX15N
TX15P
TX16N
TX16P
TX17N
TX17P
TX18N
TX18P
TX19N
TX19P
TX20N
TX20P
TX21N
TX21P
TX22N
TX22P
TX23N
TX23P

TX_LOCKN

AK35
AK36
AK37
AJ35
AJ36
AH35
AH37
AH36
AG35
AG36

AM36
AL36
AL35
AL37
AM35
AN36
AN37
AN35
AP37
AP36
AR37
AR36

A28
B29
B28
C28
B32
C31
B31
A31
C30
A30
B30
C29

D30
D31
F30
E31
E30
F29
E29
F28
E28
D28
E27
D27

AD5
AD6
Y6
Y7
AC6
AC5
AA6
AB7
AB5
AU14
AA32
AA34
AA33
AB34
AE32
AE33

AT6
AU6
AT5
AU5
AT4
AU4
AU3
AU2
AT2
AT1
AR4
AR3
AP1
AP2
AP4
AP3
AN4
AN3
AM4
AM3
AL4
AL3
AK1
AK2
AK4
AK3

AJ4
AJ3
AH4
AH3
AG4
AG3
AF1
AF2
AF4
AF3
AE4
AE3
AD4
AD3
AC4
AC3
AB1
AB2
AB4
AB3
AA4
AA3

AR5

FE_DEMOD2_TS_CLK
FE_DEMOD2_TS_SYNC
FE_DEMOD2_TS_VAL
FE_DEMOD2_TS_ERROR
FE_DEMOD2_TS_DATA
FE_DEMOD3_TS_CLK
FE_DEMOD3_TS_SYNC
FE_DEMOD3_TS_VAL
FE_DEMOD3_TS_ERROR
FE_DEMOD3_TS_DATA

FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_ERROR

FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[5]
FE_DEMOD1_TS_DATA[6]
FE_DEMOD1_TS_DATA[7]

TPI_CLK
TPI_SOP
TPI_VAL
TPI_ERR

TPI_DATA[0]
TPI_DATA[1]
TPI_DATA[2]
TPI_DATA[3]
TPI_DATA[4]
TPI_DATA[5]
TPI_DATA[6]
TPI_DATA[7]

TPO_CLK
TPO_SOP
TPO_VAL

TPO_ERR
TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

R495 100

R496 100

R497 100
R498 100

R49333
R49433

TXB4N/TX0N
TXB4P/TX0P
TXB3N/TX1N
TXB3P/TX1P
TXBCLKN/TX2N
TXBCLKP/TX2P
TXB2N/TX3N
TXB2P/TX3P
TXB1N/TX4N
TXB1P/TX4P
TXB0N/TX5N
TXB0P/TX5P
TXA4N/TX6N
TXA4P/TX6P
TXA3N/TX7N
TXA3P/TX7P
TXACLKN/TX8N
TXACLKP/TX8P
TXA2N/TX9N

TXA2P/TX9P
TXA1N/TX10N
TXA1P/TX10P
TXA0N/TX11N

TXA0P/TX11P

TXB2N

TXB2P

TXB1N

TXB1P

TXB0N

TXB0P

TXA4N

TXA4P

TXACLKN

TXACLKP

TXA1N

TXA1P
TXC4N

TXC4P
TXC3N
TXC3P

TXCCLKN
TXCCLKP
TXC2N
TXC2P
TXC1N
TXC1P
TXC0N
TXC0P

TP402

C411
10pF
50V
OPT

TPI_ERR

TPI_DATA[0-7]

TP400

+3.3V_NORMAL

H13 Ball Name

EPI Output
TXD4N/TX12N
TXD4P/TX12P

TXD3N/TX13N
TXD3P/TX13P
TXDCLKN/TX14N
TXDCLKP/TX14P
TXD2N/TX15N
TXD2P/TX15P
TXD1N/TX16N
TXD1P/TX16P
TXD0N/TX17N
TXD0P/TX17P

FE_DEMOD1_TS_DATA[0-7]

TPO_ERR

TPO_DATA[0-7]

AUD_MASTER_CLK

AUD_LRCH

FRC_FLASH_WP

AUD_SCK

AUD_LRCK

SPDIF_OUT

EPI_LOCK6

I2S_I/F

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BSD-NC4_H004-HD

2012-11-13

MAIN AUDIO/VIDEO

IC100

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

LG1154D_H13D

M0_DDR_A[10]
M0_DDR_A[11]
M0_DDR_A[12]
M0_DDR_A[13]
M0_DDR_A[14]
M0_DDR_A[15]

M0_DDR_BA[0]
M0_DDR_BA[1]
M0_DDR_BA[2]

M0_DDR_U_CLK

M0_DDR_U_CLKN

M0_DDR_D_CLK

M0_DDR_D_CLKN

M0_DDR_RESET_N

M0_DDR_ZQCAL

M0_DDR_DQS[0]

M0_DDR_DQS_N[0]

M0_DDR_DQS[1]

M0_DDR_DQS_N[1]

M0_DDR_DQS[2]

M0_DDR_DQS_N[2]

M0_DDR_DQS[3]

M0_DDR_DQS_N[3]

M0_DDR_DM[0]
M0_DDR_DM[1]
M0_DDR_DM[2]
M0_DDR_DM[3]

M0_DDR_DQ[0]
M0_DDR_DQ[1]
M0_DDR_DQ[2]
M0_DDR_DQ[3]
M0_DDR_DQ[4]
M0_DDR_DQ[5]
M0_DDR_DQ[6]
M0_DDR_DQ[7]
M0_DDR_DQ[8]

M0_DDR_DQ[9]
M0_DDR_DQ[10]
M0_DDR_DQ[11]
M0_DDR_DQ[12]
M0_DDR_DQ[13]
M0_DDR_DQ[14]
M0_DDR_DQ[15]
M0_DDR_DQ[16]
M0_DDR_DQ[17]
M0_DDR_DQ[18]
M0_DDR_DQ[19]
M0_DDR_DQ[20]
M0_DDR_DQ[21]
M0_DDR_DQ[22]
M0_DDR_DQ[23]
M0_DDR_DQ[24]
M0_DDR_DQ[25]
M0_DDR_DQ[26]
M0_DDR_DQ[27]
M0_DDR_DQ[28]
M0_DDR_DQ[29]
M0_DDR_DQ[30]
M0_DDR_DQ[31]

M0_DDR_A[0]
M0_DDR_A[1]
M0_DDR_A[2]
M0_DDR_A[3]
M0_DDR_A[4]
M0_DDR_A[5]
M0_DDR_A[6]
M0_DDR_A[7]
M0_DDR_A[8]
M0_DDR_A[9]

M0_DDR_CKE

M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

F15

M0_DDR_A0

F13

M0_DDR_A1

F17

M0_DDR_A2

F19

M0_DDR_A3

E10

M0_DDR_A4

E18

M0_DDR_A5

E11

M0_DDR_A6

F18

M0_DDR_A7

F11

M0_DDR_A8

F16

M0_DDR_A9

E9

M0_DDR_A10

E12

M0_DDR_A11

E13

M0_DDR_A12

E16

M0_DDR_A13

F12

M0_DDR_A14

F14

M0_DDR_A15

E19

M0_DDR_BA0

F10

M0_DDR_BA1

E15

M0_DDR_BA2

B10

M0_U_CLK

A10

M0_U_CLKN

A19

M0_D_CLK

B19

M0_D_CLKN

E14

M0_DDR_CKE

F21

M0_DDR_ODT

E21

M0_DDR_RASN

E20

M0_DDR_CASN

F20

M0_DDR_WEN

E17

M0_DDR_RESET_N

F9

B20
A20
C19
D19
A11
B11
C10
D10

D18
C20
D9
C11

D22
C15
C23
D16
B24
B15
D23
A15
C16
D21
D17
C22
C18
C21
C17
D20
C13
D7
D13
C6
D14
D6
C14
A5
C7
D12
D8
B13
C9
C12
C8
D11

R500

240

1%

M0_DDR_DQS0
M0_DDR_DQS_N0
M0_DDR_DQS1
M0_DDR_DQS_N1
M0_DDR_DQS2
M0_DDR_DQS_N2
M0_DDR_DQS3
M0_DDR_DQS_N3

M0_DDR_DM0
M0_DDR_DM1
M0_DDR_DM2
M0_DDR_DM3

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15
M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23
M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

VDDC15_M0

VDDC15_M0

R514

R515

VDDC15_M0

R516

R517

R520
10K

100

1K 1%

1K 1%

1K 1%

1K 1%

M0_DDR_RESET_N

M0_D_CLK

R519

M0_D_CLKN

M0_DDR_VREFCA

0.1uF

C504

M0_DDR_VREFDQ

0.1uF

C505

M0_DDR_CKE

R541
10K

M0_U_CLK

100

R535

M0_U_CLKN

VDDC15_M0

M0_1_DDR_VREFCA

R536

1K 1%

0.1uF

R537

1K 1%

C512

VDDC15_M0

M0_1_DDR_VREFDQ

R538

1K 1%

0.1uF

R539

1K 1%

C513

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9

M0_DDR_A10

M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_D_CLK

M0_D_CLKN

M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DM0
M0_DDR_DM1

M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7

M0_DDR_DQ8
M0_DDR_DQ9

M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15

DDR_SAMSUNG

IC500

K4B4G1646B-HCK0

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

DDR3
4Gbit
(x16)

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

DDR_HYNIX

IC500-*1

M0_DDR_VREFCA

M0_DDR_VREFDQ

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VDDC15_M0

R542

240
1%

H5TQ4G63AFR-PBC

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

T7

N1

A14

VDD_6

M7

N9

A15

VDD_7

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

K7

C1

VDDQ_3

CK

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

F3

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

0.1uF

C534

0.1uF

C535

M0_DDR_A0
M0_DDR_A1
M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_DDR_A6
M0_DDR_A7
M0_DDR_A8

M0_DDR_A9
M0_DDR_A10
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15

M0_DDR_BA0
M0_DDR_BA1
M0_DDR_BA2

M0_U_CLK

M0_U_CLKN
M0_DDR_CKE

M0_DDR_ODT

M0_DDR_RASN
M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2

M0_DDR_DM3

M0_DDR_DQ16
M0_DDR_DQ17
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ20
M0_DDR_DQ21
M0_DDR_DQ22
M0_DDR_DQ23

M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ26
M0_DDR_DQ27
M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
M0_DDR_DQ31

DDR_SAMSUNG

IC502

K4B4G1646B-HCK0

DDR3

N3

4Gbit

A0

P7

(x16)

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

0.1uF

0.1uF

DDR_HYNIX

IC502-*1

H5TQ4G63AFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

VREFCA

H1

VREFDQ

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

M0_1_DDR_VREFCA

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M0_1_DDR_VREFDQ

VDDC15_M0

R544

240
1%

C566
C567

IC100

LG1154D_H13D

M1_DDR_A[10]
M1_DDR_A[11]
M1_DDR_A[12]
M1_DDR_A[13]
M1_DDR_A[14]
M1_DDR_A[15]

M1_DDR_BA[0]
M1_DDR_BA[1]
M1_DDR_BA[2]

M1_DDR_U_CLK

M1_DDR_U_CLKN

M1_DDR_D_CLK

M1_DDR_D_CLKN

M1_DDR_RESET_N

M1_DDR_ZQCAL

M1_DDR_DQS[0]

M1_DDR_DQS_N[0]

M1_DDR_DQS[1]

M1_DDR_DQS_N[1]

M1_DDR_DQS[2]

M1_DDR_DQS_N[2]

M1_DDR_DQS[3]

M1_DDR_DQS_N[3]

M1_DDR_DM[0]
M1_DDR_DM[1]
M1_DDR_DM[2]
M1_DDR_DM[3]

M1_DDR_DQ[0]
M1_DDR_DQ[1]
M1_DDR_DQ[2]
M1_DDR_DQ[3]
M1_DDR_DQ[4]
M1_DDR_DQ[5]
M1_DDR_DQ[6]
M1_DDR_DQ[7]
M1_DDR_DQ[8]

M1_DDR_DQ[9]
M1_DDR_DQ[10]
M1_DDR_DQ[11]
M1_DDR_DQ[12]
M1_DDR_DQ[13]
M1_DDR_DQ[14]
M1_DDR_DQ[15]
M1_DDR_DQ[16]
M1_DDR_DQ[17]
M1_DDR_DQ[18]
M1_DDR_DQ[19]
M1_DDR_DQ[20]
M1_DDR_DQ[21]
M1_DDR_DQ[22]
M1_DDR_DQ[23]
M1_DDR_DQ[24]
M1_DDR_DQ[25]
M1_DDR_DQ[26]
M1_DDR_DQ[27]
M1_DDR_DQ[28]
M1_DDR_DQ[29]
M1_DDR_DQ[30]
M1_DDR_DQ[31]

M1_DDR_A[0]
M1_DDR_A[1]
M1_DDR_A[2]
M1_DDR_A[3]
M1_DDR_A[4]
M1_DDR_A[5]
M1_DDR_A[6]
M1_DDR_A[7]
M1_DDR_A[8]
M1_DDR_A[9]

M1_DDR_CKE

M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

Real USE : 1Gbit

H5TQ1G63DFR-PBC(x16)

1Gbit : T7(NC_6)

N6

M1_DDR_A0

R6

M1_DDR_A1

L6

M1_DDR_A2

J6

M1_DDR_A3

U5

M1_DDR_A4

J5

M1_DDR_A5

T5

M1_DDR_A6

K6

M1_DDR_A7

U6

M1_DDR_A8

M6

M1_DDR_A9

V5

M1_DDR_A10

R5

M1_DDR_A11

P5

M1_DDR_A12

L5

M1_DDR_A13

T6

M1_DDR_A14

P6

M1_DDR_A15

H5

M1_DDR_BA0

V6

M1_DDR_BA1

M5

M1_DDR_BA2

R2

M1_U_CLK

R1

M1_U_CLKN

F1

M1_D_CLK

F2

M1_D_CLKN

N5

M1_DDR_CKE

G6

M1_DDR_ODT

F5

M1_DDR_RASN

G5

M1_DDR_CASN

H6

M1_DDR_WEN

K5

M1_DDR_RESET_N

F6

E2
E1
F3
F4
P1
P2
R3
R4

G4
E3
T4
P3

C4
K3
B3
J4
A3
K2
B4
K1
J3
D4
H4
C3
G3
D3
H3
E4
M3
V4
M4
W3
L4
W4
L3
Y2
V3
N4
U4
M2
T3
N3
U3
P4

R501

240

1%

M1_DDR_DQS0
M1_DDR_DQS_N0
M1_DDR_DQS1
M1_DDR_DQS_N1
M1_DDR_DQS2
M1_DDR_DQS_N2
M1_DDR_DQS3
M1_DDR_DQS_N3

M1_DDR_DM0
M1_DDR_DM1
M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23
M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

VDDC15_M1

R510

R511

VDDC15_M1

R512

R513

VDDC15_M1

100

R518

1K 1%

1K 1%

C500

1K 1%

1K 1%

C501

R521
10K

M1_D_CLK

M1_D_CLKN

M1_DDR_VREFCA

0.1uF

M1_DDR_VREFDQ

0.1uF

M1_DDR_RESET_N

M1_DDR_CKE

M1_DDR_A0

M1_DDR_RASN

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DM0
M1_DDR_DM1

M1_DDR_DQ10

M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15

M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_D_CLK

M1_D_CLKN
M1_DDR_CKE

M1_DDR_ODT

M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7

M1_DDR_DQ8
M1_DDR_DQ9

M1_DDR_DQ11

R540
10K

M1_U_CLK

100

R530

M1_U_CLKN

VDDC15_M1

M1_1_DDR_VREFCA

R531

1K 1%

0.1uF

R532

1K 1%

C508

VDDC15_M1

M1_1_DDR_VREFDQ

R533

1K 1%

0.1uF

R534

1K 1%

C509

DDR_SAMSUNG

IC501

K4B4G1646B-HCK0

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M1_DDR_VREFCA

M1_DDR_VREFDQ

M8

H1

L8

R543

ZQ

VDDC15_M1

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C529

0.1uF

C530

0.1uF

DDR_HYNIX
IC501-*1

H5TQ4G63AFR-PBC

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

A15

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

F3

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

DDR3 1.5V bypass Cap - Place these caps near Memory

4Gbit : T7(A14)

M1_DDR_A0
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8

M1_DDR_A9
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_DDR_A14
M1_DDR_A15

M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2

M1_U_CLK

M1_U_CLKN
M1_DDR_CKE

M1_DDR_ODT

M1_DDR_RASN
M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

M1_DDR_DQS3

M1_DDR_DQS_N3

M1_DDR_DM2
M1_DDR_DM3

M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23

M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31

DDR_SAMSUNG

IC503

K4B4G1646B-HCK0

N3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M1_1_DDR_VREFCA

M1_1_DDR_VREFDQ

M8

H1

L8

R545

ZQ

VDDC15_M1
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

240

C561

0.1uF

C562

0.1uF

DDR_HYNIX

IC503-*1

H5TQ4G63AFR-PBC

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

A15

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

F3

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

DDR3 1.5V bypass Cap - Place these caps near Memory

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BSD-NC4_H005-HD

2012-09-14

MAIN DDR

PCM_RESET

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

/PCM_WAIT

PCM_INPACK

/PCM_IORD
/PCM_IOWR

R701
R702
R700

CI_IN_TS_DATA[0-7]

R704

10K
OPT

CI

33

CI

33

OPT

33

+5V_CI_ON

R706
10K

OPT

+5V_CI_ON

R707

10K

OPT

CI_VS1

PCM_INPACK

/PCM_CE2

10K

R709

CI

R708

10K

OPT

C702

0.1uF
CI

/CI_CD1
CI_TS_DATA[3]
CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

/PCM_CE2

CI_VS1

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]

CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_TS_CLK

/PCM_REG

CI_TS_VAL

CI_TS_SYNC
CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]

/CI_CD2

C703

4.7uF
10V

CI

R710

R711

10K

OPT

+5V_CI_ON

CI_ADDR[11]
CI_ADDR[9]

CI_ADDR[13]

R722 33

C707

0.1uF

16V

CI_ADDR[12]

CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]

CI_ADDR[3]

CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

CI_DATA[0-7]

OPT

+5V_CI_ON

CI_ADDR[10]

CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

/PCM_CE1

+5V_CI_ON

R724

10K

OPT

+5V_CI_ON

R723

10K

CI
CI_DATA[0]
CI_DATA[1]

/PCM_OE

R725

10K

OPT

CI

/PCM_WE
/PCM_IRQA

CI_DATA[0-7]

CI_DATA[2]
CI_DATA[3]

CI_DATA[0-7]

CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

AR712

33

CI

AR713

33

EB_DATA[0]
EB_DATA[1]
EB_DATA[2]
EB_DATA[3]

EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_DATA[7]

EB_DATA[0-7]

EB_DATA[0-7]

R712
10K
OPT

100

R716

CI

0
OPT

0

R715

OPT

CI

R714 0

CI

R717 100

R713

0

OPT

CI

JK700

10120698-015LF

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

R720

R718

R719

10K
OPT

CI_DATA[3]
CI_DATA[4]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]

CI

R721 33

C706 0.1uF

0

OPT

10K

OPT

OPT

C705
12pF
50V

CI

CI_DATA[0]
CI_DATA[1]
CI_DATA[2]

CI_IN_TS_VAL
CI_IN_TS_CLK

CI_IN_TS_SYNC

CI_ADDR[10]

CI_ADDR[8]

CI_ADDR[14]

CI

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

69

TPO_DATA[0-7]

/CI_CD2

/CI_CD1

TPO_CLK
TPO_SOP
TPO_VAL

R703

+5V_NORMAL

10K

R705

CI
C700

0.1uF
16V

TPO_DATA[0]
TPO_DATA[1]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[4]
TPO_DATA[5]
TPO_DATA[6]
TPO_DATA[7]

10K

CI

C701

0.1uF
16V

PCM_INPACK

CI_TS_CLK

CI_TS_VAL

CI_TS_SYNC

CI_TS_DATA[7]

CI_TS_DATA[6]

CI_TS_DATA[5]

CI_TS_DATA[4]

/PCM_WAIT

/PCM_IRQA

CI

AR701

33

AR706

CI

AR705

33

AR702

100

AR703

CI

100

AR704

CI

100

CI
33

CI_IN_TS_DATA[0]
CI_IN_TS_DATA[1]
CI_IN_TS_DATA[2]
CI_IN_TS_DATA[3]
CI_IN_TS_DATA[4]
CI_IN_TS_DATA[5]
CI_IN_TS_DATA[6]
CI_IN_TS_DATA[7]

CI_IN_TS_CLK
CI_IN_TS_SYNC
CI_IN_TS_VAL

CAM_WAIT_N
CAM_IREQ_N

CAM_CD2_N
CAM_CD1_N

CAM_INPACK_N

TPI_VAL
TPI_SOP

TPI_DATA[7]
TPI_DATA[6]
TPI_DATA[5]
TPI_DATA[4]

C704
12pF
50V
OPT

TPI_CLK

CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]

CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]

CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]

CI

AR707

33

CI

AR708

33

CI

AR709

33

EB_ADDR[0]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]

EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[6]
EB_ADDR[7]

EB_ADDR[8]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

/PCM_REG

/PCM_OE
/PCM_WE

/PCM_IORD
/PCM_IOWR

CI

AR711

33

CI

AR710

33

EB_ADDR[12]
EB_ADDR[13]
EB_ADDR[14]
CAM_REG_N

EB_OE_N
EB_WE_N
EB_BE_N1
EB_BE_N0

CI
CI_TS_DATA[3]
CI_TS_DATA[2]
CI_TS_DATA[1]
CI_TS_DATA[0]

AR700

100

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TPI_DATA[3]
TPI_DATA[2]
TPI_DATA[1]
TPI_DATA[0]

BSD-NC4_H007-HD

2012-10-20

PCMCIA

+3.5V_ST

Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes

LGE Internal Use Only

R2300

RL_ON

10K

50V

L2304

UBW2012-121F

C2307

0.1uF
16V

UBW2012-121F

L2303

+3.5V_ST

+12V

C2306

0.1uF

eMMC POWER

+3.3V_NORMAL

+12V

Switching freq: 700K

+12V

Switching freq: 700K

L2302

BLM18PG121SN1D

L2300
BLM18PG121SN1D

C2301
10uF
16V

L2305
BLM18PG121SN1D

C2304
10uF
16V

3.3V_EMMC

POWER_ON/OFF2_3

1

10K

R2301

2

C2305

0.1uF
16V

Q2300 MMBT3906(NXP)

3

C2300
22uF
10V

PWR ON

3.5V

3.5V
GND
24V
GND
12V
12V
GND

P2300

SMAW200-H18S1

1
3
5
7
9
11
13
15
17

19

+1.0V_VDD

R2304
10K

1%

R2302

R1

C2308
100pF

50V

DCDC_TI

R2

11K

R2306

33K

1%

C2310
1uF
10V

VREG5

C2312
3300pF
50V

Vout=0.765*(1+R1/R2)

+3.3V_NORMAL

R2311

POWER_ON/OFF1

R1

C2325
100pF

50V

OPT

10K

1% C2332

R2308

R2319

R2

51K

15K

1%

C2326
1uF
10V

VREG5

C2328
3300pF
50V

Vout=0.765*(1+R1/R2)

INV ON

2

PDIM#1

4

PDIM#2

6

GND

8

24V

10

GND

12

12V

14

24V

16

GND

18

DCDC_TI

TPS54327DDAR

EN

1

VFB

2

3

SS

4

3A

TPS54327DDAR

EN

1

VFB

2

3

SS

4

3A

IC2300

9

THERMAL

IC2301

THERMAL

PANEL_POWER

+12V

L2313

UBW2012-121F

C2331

0.1uF
50V

R2317

33K

R2318

5.6K

C

Q2301

B

IC2302

THERMAL

1.5A

MMBT3904(NXP)

E

8

9

7

6

5

R2314

10K

AP7173-SPG-13 HF(DIODES)

IN

1

PG

2

VCC

3

EN

4

[EP]

OUT

FB

SS

GND

C2333
10uF

16V

Q2302

AO3407A

S

G

C2337
2200pF
50V

D

R2321
2K
1%

R2346

R2347

5.6K

5.6K

LVDS_DISCHARGE

R2322

R1

4.3K
1%

R2

PANEL_20V

PWM_DIM2

R2309
100

L2306

UBW2012-121F

C2316

0.1uF

JP2308

JP2309

JP2310

50V

+3.3V_NORMAL

R2310
1K

INV_CTL

+24V

PWM_DIM

L/DIM0_MOSI
L/DIM0_MOSI

L/DIM0_VS
L/DIM0_VS

L/DIM0_SCLK
L/DIM0_SCLK

+2.5V

POWER_ON/OFF2_1

PANEL_CTL

+3.3V_NORMAL

+5V_NORMAL

R2312
10K

C2327
10uF
10V

Vout=0.8*(1+R1/R2)

LG1154A

+1.23V_CORE

+12V

L2301

+1.1V_VDD

C2303

C2302
180pF
50V

R2303

16K

R2305

15K

10uF
16V

R1

1/16W

1%

R2

1/16W

1%

Vout(1.24V)=0.6*(1+16k/15k)

R2307
120K

1/16W
1%

RT/CLK

PVIN_1

PVIN_2

VSENSE

C2313

4.7uF
16V

GND_1

GND_2

VIN

IC2303

TPS54821RHL

1

2

THERMAL

3

4

5

6

8A

7

[EP]GND

PWRGD

14

C2318

BOOT

15

13

0.1uF
16V

PH_2

12

PH_1

11

EN

10

SS/TR

9

COMP

8

1.3K
R2313

C2315

4700pF 50V

L2308

1uH

C2322
22uF
10V

R2316 1K

C2321

22000pF 50V

C2320

47pF 50V

1/16W

5%

R2315 0

8

7

6

5

[EP]GND

VIN

VBST

SW

GND

0.1uF
C2314

16V

NR5040T2R2N
L2307

2.2uH

+1.0V_VDD

C2317
22uF
10V

+3.3V_NORMAL

C2319
22uF
10V

2.5V

ZD2300

OPT

DCDC_RT

IC2300-*1

RT7266ZSP

[EP]GND

VIN

EN

8

1

FB

BOOT

9

2

7

THERMAL

PVCC

SW

3

6

SS

GND

4

5

Vout=0.6*(1+R1/R2)

[EP]GND

VIN

8

9

7

6

5

VBST

SW

GND

0.1uF

16V

L2309

3.6uH

SM-8040

C2339

22uF

10V

C2340
22uF
10V

5V

ZD2301

POWER UP SEQUENCE

5V/3.3V->2.5V->1.5V/1.1V->1.0V
LG1154D : 3.3V->2.5V->1.5V->1.1V

LG1154AN : 3.3V->2.5V->1.0V

PANEL_VCC

LVDS_DISCHARGE

OPT

C2343
22uF
10V

+1.1V_VDD

C2341

22uF
10V

C2347

0.1uF
50V

+2.5V_Normal

C2346
10uF
10V

C2323
22uF
10V

POWER_ON/OFF2_2

C2348

0.1uF
16V

OPT

2.5V

ZD2302

ZD2304

Power_DET

IC2307-*1
APX803D29

RESET

RESET

2

1

GND

RESET_IC_DIODE

IC2308-*1
APX803D29

2

1

GND

RESET_IC_DIODE

3

3

DDR MAIN 1.5V

5V

+3.5V_ST

L2318

C2350
10uF
10V

+5.0V normal & USB

+24V

+12V

L2311

L2314

BLM18PG121SN1D

OLED

NON_OLED

C2309
10uF
35V

+12V

VCC

VCC

PD_+12V

R2325

2.7K
1%

PD_+12V
R2326

1.2K
1%

VIN_1

VIN_2

GND_1

GND_2

+3.5V_ST

PANEL_20V

R2327

5.6K
1%

R2328

1.3K
1%

EP[GND]

1

2

3

4

PD_+3.5V
R2330
0
5%

10K

R2331

THERMAL

17

IC2305

TPS54319TRE

3A

5

6

AGND

VSENSE

3A

C2354

0.1uF
16V

DCDC_TI

7

COMP

BOOT14PWRGD15EN16VIN_3

13

12

11

10

9

8

RT/CLK

1/16W 5%

$ 0.145

C2355

0.1uF
16V

C2356

0.1uF
16V

PH_3

PH_2

PH_1

SS/TR

R2334
15K

RESET_IC_ONSEMI

VCC

RESET_IC_ONSEMI

VCC

C2358

0.1uF

16V

C2359

0.01uF
50V

R2335

330K1/16W 5%

4700pF

C2360

Vout=0.827*(1+R1/R2)=1.521V

IC2304

C2311

0.1uF
50V

RT8289GSP

C2324

0.01uF
50V

BOOT

1

NC_1

2

NC_2

3

FB

4

5A

1%

51K

R1

R2343

16K

R2344

1%

C2329
150pF
50V

R2

9

THERMAL

8

7

6

5

[EP]GND

SW

VIN

GND

EN

Vout=1.222*(1+R1/R2)

R2337
100K

IC2307

NCP803SN293

3

1

GND

R2336
100K

IC2308

NCP803SN293

3

1

GND

POWER_ON/OFF2_2

L2320

3.3uH

NR5040T3R3N

50V

2

2

C2361
22uF
10V

D2300

B540C

RESET

RESET

+3.5V_ST

R2338
10K
OPT

OLED : 20V DET = POWER_ON/OFF2_4

POWER_DET

C2365

0.1uF
16V

not to RESET at 8kV ESD

R2348

ST_3.5V-->3.5V

POWER_ON/OFF2_4

0

24V-->3.48V
20V-->3.51V
12V-->3.58V

LG1154D

+1.5V_DDR

C2362
22uF
10V

R2339

R1

47K 1%

R2

R2340
56K

1/16W

1%

L2310

L2312

4.7uH

4.7uH

40V

C2335

0.1uF

C2330
22uF
10V

16V

DCDC_TI
C2364
100pF
50V

VIN_1

VIN_2

GND_1

GND_2

1

2

3

4

C2334
22uF
10V

ZD2303

THERMAL

5

AGND

2.5V
OPT

IC2305-*1
RT8079AGQW

DCDC_RT

6FB7

COMP

+5V_NORMAL

C2336
10uF
10V

POWER_ON/OFF1

R2345
10K

BOOT14PGOOD15EN16VIN_317[EP]GND

13

RT/SYNC

SW_3

12

SW_2

11

SW_1

10

SS/TR

9

8

C2338

0.1uF
50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BSD-NC4_H039-HD

NC4_H13

POWER_BLOCK(OLED) 23

2013.03.05