LG 42PA4500-TM, 42PA4520-TJ Schematic

Internal Use Only

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

PLASMA TV

SERVICE MANUAL

CHASSIS : PA23A

MODEL : 42PA4500 42PA4500-TM

MODEL : 42PA4520 42PA4520-TJ

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL67483102 (1205-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ........................................................................ 3

SPECIFICATION ....................................................................................... 4

ADJUSTMENT INSTRUCTION ................................................................ 6

BLOCK DIAGRAM .................................................................................. 13

EXPLODED VIEW .................................................................................. 14

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Only for training and service purposes

- 2 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

To Instrument's
exposed
METALLIC PARTS

Good Earth Ground
such as WATER PIPE,
CONDUIT etc.

AC Volt-meter

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental sh orts of the cir cui try that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 M
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Ω and 5.2 MΩ.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied all of the PDP TV with PA23A chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage

: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.

(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with

BOM.

(5) The receiver must be operated for about 5 minutes prior to the adjustment.

3. Test method

(1) Performance: LGE TV test method followed
(2) Demanded other specification

- Safety : CE, IEC specification

- EMC : CE, IEC

.

4. Module General Specification

- 42" 2D HD

No Item Specication Remark

1 Display Screen Device 106 cm (42 inch) wide Color Display Module PDP

2 Aspect Ratio 16:9

3 PDP Module PDP42T4####,

RGB Closed (Well) Type, Glass Filter (38%)
Pixel Format: 1024 horiz. By 768 ver.

4 Operating Environment 5) Temp. : 0 ~ 40 deg

6) Humidity : 20 ~ 80%

5 Storage Environment 7) Temp. : -20 ~ 60 deg

8) Humidity : 10 ~ 90 %

6 Input Voltage AC100 ~ 240V, 50/60Hz Maker LG

LGE SPEC

Only for training and service purposes

- 4 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model General Specification

No Item Specication Remark

1 Market Australia, New Zealand, Indonesia, Malaysia, Singa-

pore, South Africa, Israel, Iran, Vietnam, Myanmar,
Non-EU analog

2 Broadcasting system 1) PAL/SECAM BG

2) PAL/SECAM DK

3) PAL I / II

4) SECAM L/L’

5) DVB T

6) DVB C

3 Receiving system Analog : Upper Heterodyne

Digital : COFDM

4 Scart Jack (1EA) PAL, SECAM

5 Component Input

(1EA)

6 RGB Input (1EA) RGB-PC Analog (D-Sub 15Pin)

7 RS232C (1EA) SVC

8 HDMI Input (2 or 3EA) HDMI-PC

9 Audio Input (2EA) RGB/DVI Audio, Component L/R Input

10 SPDIF Out (1 EA) SPDIF Out

11 USB (1EA) for SVC, S/W Download, DivX

12 LAN only DVB-T2 models

13 PCMCI (1EA) DVB-T/C Decryption Interface, CI+

Y/Cb/Cr, Y/ Pb/Pr

HDMI-DTV

EU (PAL Market)

HDMI1/DVI, HDMI2,
HDMI3

Only for training and service purposes

- 5 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to PA23A chassis applied PDP TV all
models manufactured in TV factory.

2. Designation

(1) Th e ad justm ent is accord ing to the order whic h is

designated and which must be followed, according to the

plan which can be changed only on agreeing.
(2) Power adjustment : Free Voltage.
(3) Magnetic Field Condition: Nil.
(4) Input signal Unit: Product Specification Standard.
(5) Reserve after operation: Above 5 Minutes (Heat Run)

Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz

(6) Adjustment equipment s : Color Ana lyzer (CA -210 or

CA-110), DDC Adjustment Jig equipment, SVC remote

controller.
(7) The receiver must be operated for about 5 minutes prior to

the adjustment when module is in the circumstance of over

15

- In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2
hours.

- In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above
15°C for 3 hours.

3. Main PCB check process

* APC - After Manual-Insult, executing APC

* Boot file Download

(1) Execute ISP program “Mstar ISP Utility” and then click

“Config” tab.

(2) Set as below, and then click “Auto Detect” and check “OK”

message

If “Error” is displayed, Check connection between computer,

jig, and set.

(3) Click “Read” tab, and then load download file (XXXX.bin)

by clicking “Read”

(4) Click “Connect” tab. If “Can’t ” is displayed, Check

connection between computer, jig, and set.

■ After RGB Full White in HEAT-RUN Mode, the receiver must

be operated prior to the adjustment.

■ Enter into HEAT-RUN MODE

1) Press the POWER ON KEY on R/C for adjustment.

2) OSD display and screen display PATTERN MODE.

● Set is activated HEAT run without signal generator in this

mode.

● Single color pattern ( WHITE ) of HEAT RUN MODE uses to

check panel.

● Caution : If you turn on a still screen more than 20 minutes

(Especially digital pattern, cross hatch pattern), an
after image may be occur in the black level part of
the screen.

(8) Push The “IN STOP KEY” – For memory initialization.

Case1 : Software version up

1) After downloading S/W by USB , Multi-vision set will reboot

automatically

2) Push “In-stop” key

3) Push “Power on” key

4) Function inspection

5) After function inspection, Push “In-stop” key.

Case2 : Function check at the assembly line

1) When TV set is entering on the assembly line, Push “In-

stop” ke y at rst.

2) Push “Power on” key for turning it on.

-> If you push “Power on” key, TV set will recover channel
information by itself.

3) After function inspection, Push “In-stop” key.

(5) Click “Auto” tab and set as below.
(6) Click "Run".
(7) After downloading, check "OK" message.

Only for training and service purposes

- 6 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* USB DOWNLOAD(*.epk file download)

(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is Low,

it didn’t work.

- But your downloade d version is High, USB data is

automatically detecting

(3) Show the message “Copying files from memory”

(4) Updating is staring.

(5) Updating C om pl et ed, T he Mu lt i- vi si on will restart

automatically.

(6) If your Multi-vision is turned on, check your updated

version and Tool option. (explain the Tool option, next
stage)

* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote controller.

2) Select "Tool Option 1" and Push “OK” button.

3) Punch in the number. (Each of mode ls has th eir
number.)

4) Completed selecting Tool option.

42PA4500-T* 42PA4520-T*

Tool option 1 24576 24672

Tool option 2 22922 39306

Tool option 3 3697 3697

Tool option 4 54342 54342

Tool option 5 10 10

* Caution : Using ‘power on’ button of the Adjustment R/C ,

power on Multi-vision.

* ADC Calibration Protocol (RS232)

NO Enter

Adjust MODE

Item Adjust ‘Mode In’ ADC Adjust

CMD 1 A A

CMD 2 A D

Data 0 0 0

1 0

When transfer the
‘Mode In’,
Carry the command.

- Adjust Sequence

▪aa 00 00 [Enter Adjust Mode]
▪xb 00 40 [Component1 Input (480i)]
▪ad 00 10 [Adjust 480i Comp1]
▪xb 00 60 [RGB Input (1024*768)]
▪ad 00 10 [Adjust 1024*768 RGB]
▪aa 00 90 End Adjust mode

* Required equipment : Adjustment R/C.

ADC adjust

Automatically adjustment
(The use of a internal
pattern)

3.2. Function Check

3.2.1. Check display and sound

■ Check Input and Signal items. (cf. work instructions)

1) COMPONENT (480i)

2) RGB (PC : 1024 x 768 @ 60hz)

3) HDMI

4) DVI

5) PC Audio In
* Display and Sound check is executed by Remote control-

ler.

3.1. ADC Process

3.1.1. ADC

■ Enter Service Mode by pushing “ADJ” key,

■ Enter Internal ADC mode by pushing “►” key at “5. ADC

Calibration”

Only for training and service purposes

* Caution : Not to push the INSTOP KEY after completion if

the function inspection.

- 7 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

4. Total Assembly line process

4.1. POWER PCB Assy voltage adjustment

(Vs voltage adjustment)

● Required Equipment for adjustment

- D.M.M

● Condition for adjustment

- No signal with the snow noise in RF mode

4.2. Adjustment Preparation

● Required Equipment

- Remote controller for adjustment

- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same

product : CH 11 (PDP)

* Please adjust CA-210, CA-100+ by CS-1000 before measur-

ing

- Auto W/B adjustment instrument(only for Auto adjust-

ment)

- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO

W/B EQUIPMENT.

Before Adjust of White Balance, Please press
POWER ONLY key

- Adjust Process will start by execute RS232C Command.

● Color temperature standards according to CSM and Module

CSM PLASMA

Cool 11000K

Medium 9300K

Warm 6500K

* Auto-control interface and directions

1) Adjust in the place where the inux of light like oodlight

around is blocked. (Illumination is less than 100Lux).

2) Adhere closely the Color Analyzer ( CA210 ) to the
module less than 10cm distance, keep it with the surface
of the Module and Color Analyzer’s Prove vertically.
(80~100°).

3) Aging time

- After aging start, keep the power on (no suspension of
power supply) and heat-run over 5 minutes.

- Using ‘no signal’ or ‘full white pattern’ or the others,
check the back light on.

■ Auto adjustment Map(RS-232C)

RS-232C COMMAND

[ CMD ID DATA ]

Wb 00 00 White Balance Start
Wb 00 ff White Balance End

RS-232C

COMMAND

[CMD ID DATA]

Cool Mid Warm Cool Mid Warm

R Gain jg Ja jd 00 172 192 192 192

G Gain jh Jb je 00 172 192 192 192

B Gain ji Jc jf 00 192 192 172 192

R Cut 64 64 64 128

G Cut 64 64 64 128

B Cut 64 64 64 128

M

I

N

CENTER

(DEFAULT)

M

A
X

● CS-1000/CA-100+/CA-210(CH 10) White balance adjust­ment coordinates and color temperature.

CSM Color Coordination Temp ± Color

x y

COOL 0.276 0.283 11000K 0.002

MEDIUM 0.285 0.293 9300K 0.002

WARM 0.313 0.329 6500K 0.002

* Connecting picture of the measuring instrument (On Auto-

matic control)

- Inside PATTERN is used when W/B is controlled. Con­nect to auto controller or push Adjustment R/C POWER­ON -> Enter the mode of White-Balance, the pattern will
come out.

Coordination

* Caution

- Color Temperature : COOL, Medium, Warm.

- One of R Gain/G Gain/ B Gain should be kept on 0xC0,
and adjust other two lower than C0. (when R/G/B Gain
are all C0, it is the FULL Dynamic Range of Module)

* Manual W/B process using adjusts Remote control.

■ After enter Service Mode by pushing “ADJ” key,

■ Enter White Balance by pushing “►” key at “6. White

Balance”.

■ Stick the sensor to the center of the screen and select

each items(Red/Green/Blue Gain) using ▲/▼(CH +/-)

key on R/C.

■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.

■ Adjust three modes all(Cool/Medium/Warm) : Fix the one

of R/G/B Gain and Change the others.

■ When the adjustment is completed, Enter “COPY ALL”.

■ Exit adjustment mode using EXIT key on R/C.

Only for training and service purposes

- 8 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* After You nish all adjustments, Press “In-start” button and

compare Tool option and Area option value with its BOM, if it
is correctly same then unplug the AC cable.

If it is not same, then correct it same with BOM and unplug

AC cable.
For correct it to the model’s module from factory JIG model.
* Push The “IN STOP KEY” after completing the function

inspection. And Mechanical Power Switch must be set “ON”
* To check the coordinates of White Balance, you have to

measure at the below conditions.

- Picture mode : Vivid, Energy Saving : Off, Below the Ad-

vanced control, Dynamic Contrast : Off, Dynamic Colour : Off
Colour Temp.

Cool 30

Medium 0

Warm 30

-> Picture Mode change : Vivid -> Vivid(User)

4.3. DDC EDID Write (RGB 128Byte)

-> Not used any more, Use Auto D/L

■ Connect D-sub Signal Cable to D-Sub Jack.

■ Write EDID DATA to EEPROM (24C02) by using DDC2B

protocol.

■ Check whether written EDID data is correct or not.

* For SVC main Ass’y, EDID have to be downloaded to Insert

Process in advance.

4.4. DDC EDID Write (HDMI 256Byte)

-> Not used any more, Use Auto D/L

■ Connect HDMI Signal Cable to HDMI Jack.

■ Write EDID DATA to EEPROM(24C02) by using DDC2B

protocol.

■ Check whether written EDID data is correct or not.

* For SVC main Ass’y, EDID have to be downloaded to Insert

Process in advance.

4.5. EDID DATA

(1) All Data : HEXA Value
(2) Changeable Data :
* : Serial No : Controlled / Data:01
** : Month : Controlled / Data:00
*** : Year : Controlled
**** : Check sum

* Caution : Never connect HDMI & D-sub Cable when EDID

downloaded.

■ Edid data and Model option download (RS232)

- Manual Download

NO Enter

download MODE

Item download ‘Mode In’ download

CMD 1 A A

CMD 2 A E

Data 0 0 00

0 10

When transfer the

‘Mode In’,

Carry the command.

* Caution

● Use the proper signal cable for EDID Download

- Analog EDID : Pin3 exists

- Digital EDID : Pin3 exists

* Caution

- Never connect HDMI & D-sub Cable at the same time.

- Use the proper cables below for EDID Writing.

- Download HDMI1, HDMI2 separately because HDMI1 is dif­ferent from HDMI2.

For Analog EDID For HDMI EDID

D-sub to D-sub DVI-D to HDMI or HDMI to HDMI

EDID data Model

option download

Automatically download

(The use of a internal

pattern)

4.6. EDID DATA Auto Download

(1) Press Adj. key on the Adj. R/C,
(2) Select EDID D/L menu.
(3) By pressing Enter key, EDID download will begin
(4) If Download is successful, OK is display, but If Download is

failure, NG is displayed.

(5) If Download is failure, Re-try downloads.

Only for training and service purposes

No. Item Condition Hex Data

1 Manufacturer ID GSM 1E6D

2 Version Digital : 1 01

3 Revision Digital : 3 03

- 9 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

* 2D HD EDID data

- 2D HD RGB EDID data

- 2D HD HDMI1 EDID data

- 2D HD HDMI2 EDID data

- 2D HD HDMI3 EDID data

* Vender ID

Input HEX

HDMI1 10

HDMI2 20

HDMI3 30

* Checksum: Changeable by total EDID data.

EDID C/S data 2D-FHD

HDMI RGB

check sum

(Hex)

Block 0 0x63 0x7C

Block 1 0x76(HDMI1)

0x66(HDMI2)

0x56(HDMI3)

Only for training and service purposes

EDID C/S data 2D-HD

HDMI RGB

check sum

(Hex)

Block 0 0x3F 0x58

Block 1 0xFC(HDMI1)

0xEC(HDMI2)

0xDC(HDMI3)

4.7. Checking the EYE-Q Operation.

(1) Press the EYE Key on the adjustment remote controller.
(2) Check the Sensor DATA ( It must be under 10) and keep

the data longer than 1.5s

(3) Check ‘OK’

Green Eye-Check(Factory Mode)

Sensor Data 9

Power saving mode 1

OK

(Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)
* IF you press IN-STAP Button, change Green Eye-check

OSD.

- 10 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

5. Model name & Serial number Download

5.1. Model name & Serial number D/L

■ Press “Power on” key of service remocon.(Baud rate :

115200 bps)

■ Connect RS232 Signal Cable to RS-232 Jack.

■ Write Serial number by use RS-232.

■ Must check the serial number at signal test of customer sup-

port. (Refer to below).

5.2. Signal TABLE

CMD LENGTH ADH ADL DATA_1 ... Data_n

CMD: A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
Delay : 20ms

CS DELAY

1) Press the ‘instart’ key of ADJ remote controller.

2) Go to the menu ‘5.Model Number D/L’ like below photo.

3) Input the Factory model name or Serial number like
photo.

4) Check the model name Instart menu -> Factory name
displayed.

5) Check the Diagnostics (DTV country only) -> Buyer
model displayed

5.3. Command Set

* Description

No. 1

Adjust mode EEPROM WRITE

CMD(hex) A0h

LENGTH(hex) 84h+n

Description n-bytes Write (n = 1~16)

FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart,
0, Phase
Data write : Model Name and Serial Number write in EEP­ROM,.

5.4. Method & Notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing

Technology Group.

(3) Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory
by D-book 4.0

* Manual Download (Model Name and Serial Number)
If the TV set is downloaded By OTA or Service man,

Sometimes model name or serial number is initialized.( Not
always)

6. Download MAC Address, CI+ Key
and widevine Key.

- Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).

-> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA).

* Connect TV SET and PC which download keys Writing

program by RS232C-Cable

1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
connect TV and PC.

2) Click (4) to download MAC Address.

3) Click (5) to download CI+ Key.

4) When download succeed, you can see “OK” on (6)

* Each Chassis has it’s own MAC Address. Please be careful

of download.

There is impossible to download by bar code scan, so It need
Manual download.

Only for training and service purposes

- 11 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

■ Check the method of RS232C Command
(1) into the main ass’y mode (RS232 : aa 00 00)

CMD1 CMD2 Data 0

A A 0 0

(2) ch eck the key downlo ad for transmi tted command

(RS232 : ci 00 10)

CMD1 CMD2 Data 0

C 1 1 0

(3) result value

- normally status for download : OKx

- abnormally status for download : NGx

7 . SW Download Guide.

* Put a *.bin to USB Stick and Turn on TV

(1) Put the USB Stick to the USB socket

(2) Automatically detecting update le in USB Stick

* If your downloaded program version in USB Stick is Low,

it didn’t work.

But your downloaded version is High, USB data is auto-

matically detecting.

(3) Show the message “Copying les from memory”

(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ

Remote-control.

* IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OP-

TION MENU.

(6) When TV turn on, check the Updated version on Diagnos-

tics MENU.

Only for training and service purposes

- 12 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

BLOCK DIAGRAM

Only for training and service purposes

- 13 -

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

310

305

301

300

200

302

580

205

206

303

202

207

304

203

204

201

590

601

520

540

501

A12

A9

A10

LV1

400

Only for training and service purposes

240

- 14 -

910

120

A2

900

LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.

Full SCART

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

EU

JK100

PSC008-02

SHIELD

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

AV_DET

COM_GND

SYNC_IN

SYNC_OUT

SYNC_GND2

SYNC_GND1

RGB_IO

R_OUT

RGB_GND

R_GND

D2B_OUT

G_OUT

D2B_IN

G_GND

ID

B_OUT

AUDIO_L_IN

B_GND

AUDIO_GND

AUDIO_L_OUT

AUDIO_R_IN

AUDIO_R_OUT

+3.3V

R106
75

R108
75

R107
75

R104
10K
EU

R105
1K
EU

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

AV/SC1_DET

R115

470K

R116

470K

+5V

E

DUP_DVB

ISA1530AC1

Q103-*1

E
DUP_DVB
2SC3052

SC1_SOG_IN

AV/SC1_CVBS_IN

SC1_VOUT

SC1_FB

SC1_ID

AV/SC1_L_IN

AV/SC1_R_IN

Q100-*1

R129
0
EU

C106

C111
220pF

50V

EU

0EU

R123

R121
10K

R124

C109
27pF

50V

EU

33

EU

R126
12K

EU

EU

10K

R127

EU

12K

EU

C107

5600pF

50V

EU

C108

5600pF

50V

EU

R117

75
EU

R113

R118

5%

75

470K

EU

EU

1/1 6W

R119

75
EU

R114

R120

10K

2.7K
EU

EU

EU

EU

DTV_R_OUT

C

Q100

MMBT3904(NXP)

EU

MMBT3904(NXP)

DUP_DVB

2SC3052
Q101-*1

Q102

MMBT3904(NXP)

EU

R134
100
1/4W

Q101

B

C

B

R136

330

E

EU

R135

0

EU

EU

REC_8

EU

E

B

C

R139

2K

EU

C

E

B

Q103

C

MMBT3906(NXP)
EU

R141

220

DUP_DVB
D112-*1

KDS184

C

R138

2K
EU

R137

2K
EU

C112
10uF
16V

EU

R140

2K
EU

B

EU

EU

MMBD6100

D112

A2

C

A1

A2

A1

C113
10uF
16V

EU

+3.3V_ST

MMBT3904(NXP)

DUP_DVB
2SC3052
Q104*-1

R144

470

EU

C

B

Q104

E

EU

R143
180

EU

EU

MMBT3904(NXP)

Q107

DUP_DVB
2SC3052
Q107-*1

C114
27pF

50V
EU

R145

6.8K
EU

C115
27pF

50V

EU

EU

R189
10K

E

C

E

C

E

C

SCART1_Lout

SCART1_MUTE

B

R146
18K

EU

R147
10K

EU

MMBT3904(NXP)

B

B

R149
15K
EU

R148
15K

EU

Q106

10uF

12K

R160

C116

16V

EU

EU

EU

DUP_DVB
2SC3052
Q106-*1

E

C

R152

6.8K
EU

R154

5.6K

DTV/MNT_VOUT

E

C

B

E

EU

MMBT3904(NXP)

Q105

C

EU

12K

R159

OUT1

IN1-

IN1+

VEE

EU

L103

120-ohm

EU

DUP_DVB

B

2SC3052
Q105-*1

EU
1K

R158

EU
1K

R157

B

R155

IC101

AZ4580MTR-E1

1

2

3

4

L103-*1

CB1608UA121T

DUP_DVB

E

C

EU
3K

P_17V

8

7

6

5

7.5K
R156

VCC

OUT2

IN2-

IN2+

PDP GP4 S7LR3
EAX64696601

B

SC_RE1

SC_RE2

EU

P_17V

EU

5.6K
R153

SCART1_Rout

CI SLOT

BUF2_FE_TS_DATA[0-7]

/CI_CD1

CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

CI_IORD
CI_IOWR

BUF2_FE_TS_SYN

BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]

BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]

BUF2_FE_TS_DATA[0-7]

BUF2_FE_TS_DATA[7]

PCM_RST

/PCM_WAIT

REG
CI_TS_CLK
CI_TS_VAL

CI_TS_SYNC

CI_TS_DATA[0]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]

R150
10K
EU

+5V

/CI_CD2

+5V

R151

R102

10K

100

EU

EU

AR100 33

R100
R101

AR101 33

AR102 33

R103
100
EU

E
DUP_DVB
2SC3052
Q102-*1

+5V_CI_ON

C100

C101

22uF

0.1uF

10V

16V

EU

EU

JK102

10067972-000LF

EU

35
36

R111
10K
EU

R112
0

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

65
66
67
68

2

EU

READY

R109
10K

EU

33

EU

33

EU

EU

EU

R110
0
READY

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

R128 0

18

READY

19
20
21
22
23
24
25
2660
2761
2862
2963
3064
31
32
33
34

G1G2

1

69

AR103

33

EU

R130 33EU

1/16W

R131 33EU

5%

R132 100

AR104

33

EU

PCM_D[3]
PCM_D[4]
PCM_D[5]
PCM_D[6]
PCM_D[7]

EU

PCM_D[0]
PCM_D[1]
PCM_D[2]

CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[12]
CI_ADDR[7]

CI_ADDR[6]
CI_ADDR[5]

CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]

PCM_D[0-7]

R133
10K
EU

/PCM_CE

CI_OE

CI_WE
/PCM_IRQA

BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

CI_ADDR[0-14]

PCM_D[0-7]

B

C

EU

33

+3.3V_CI

EU

R165

TC74LCX244FT

10K

AR105

EU

AR106 33

EU

AR107 33

IC100

1OE

1

20

EU

1A1

19

2

2Y4

18

3

1A2

17

4

2Y3

16

5

1A3

15

6

2Y2

14

7

1A4

13

8

2Y1

12

9

GND

10

11

+3.3V_CI

VCC

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

/PCM_OE
/PCM_WE
/PCM_IORD
/PCM_IOWR

PCM_A[12]
PCM_A[13]
PCM_A[14]
/PCM_REG

PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]

EU

C105

0.1uF
16V

CI_ADDR[0]
PCM_A[7]
CI_ADDR[1]
PCM_A[6]
CI_ADDR[2]

PCM_A[5]

CI_ADDR[3]
PCM_A[4]

BUF2_FE_TS_DATA[0-7]

AR108

33 EU

BUF2_FE_TS_DATA[0]
BUF2_FE_TS_DATA[1]
BUF2_FE_TS_DATA[2]
BUF2_FE_TS_DATA[3]

BUF2_FE_TS_DATA[4]
BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5]
BUF2_FE_TS_DATA[6]
BUF2_FE_TS_DATA[7]

BUF1_FE_TS_SYN

BUF1_FE_TS_VAL_ERR

BUF1_FE_TS_CLK

CI POWER ENABLE CONTROL

PCM_5V_CTL

BUF1_FE_TS_DATA[0]

BUF1_FE_TS_DATA[1]

BUF1_FE_TS_DATA[2]

BUF1_FE_TS_DATA[3]

AR109

33 EU

BUF1_FE_TS_DATA[4]

BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

AR110

33

EU

+5V

R184
10K
READY

BUF2_FE_TS_SYN
BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_CLK

5%

1/1 6W

B

R181
10K
EU

BUF1_FE_TS_DATA[0-7]

Q114
ZXMP3F30FHTA
EU

R187
10K
EU

C

Q113
MMBT3904(NXP)
EU

E

DUP_DVB
2SC3052
Q113*-1

BUF1_FE_TS_DATA[0-7]

L100-*1

CB1608UA121T

DUP_DVB

L100

120-ohm

EU

D

S

C131

0.1uF

G

16V
READY

AO3407A

D

S

G

MULTI

Q114-*1

E

B

C

+5V_CI_ON

C104

0.1uF
16V
EU

R198
10K
READY

3.3V_CI

+3.3V

L101-*1

CB1608UA121T

DUP_DVB

L101

120-ohm

C136

0.1uF
16V
READY

+3.3V_CI

EU

C137

0.1uF
16V
EU

CI_OE

CI_WE
CI_IORD
CI_IOWR

CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]

CI_DET

PCM_A[0]

CI_ADDR[7]

PCM_A[1]

CI_ADDR[6]

PCM_A[2]

CI_ADDR[5]

PCM_A[3]

CI_ADDR[4]

REG

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR3

SCART,CI Slot

2011-12-01

1

7

HDMI_1

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

SHIELD

20

JK200

HDMI_1

19

18

17

16

15

14

13

12

11

CK+

10

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

R200
1K
HDMI_1

R201

1.8K HDMI_1

HDMI_1

JK211

PPJ239-01

NON_EU

+5V

5V_DET_HDMI_1

MMBT3904(NXP)

R204

3.3K
JP201

R281

4N

5M

5L

7L

5K

7K

4J

5J

6J

HDMI_1

R282

10K

10K
HDMI_1

JP2 02

[RD1]E-LUG

6H

[RD1]O-SPRING_2

5H

[RD1]CONTACT_2

4H

[WH1]O-SPRING

5G

[RD1]CONTACT_1

4F

[RD1]O-SPRING_1

5F

[RD1]E-LUG-S

7F

[BL1]O-SPRING

5E

[BL1]E-LUG-S

7E

[GN1]CONTACT

4D

[GN1]O-SPRING

5D

[GN1]E-LUG

6D

[RD2]E-LUG

6N

[RD2]O-SPRING_2

5N

[RD2]CONTACT

[WH2]O-SPRING

[RD2]O-SPRING_1

[RD2]E-LUG-S

[BL2]O-SPRING

[BL2]E-LUG-S

[GN2]CONTACT

[GN2]O-SPRING

[GN2]E-LUG

DUP_DVB
2SC3052
Q200-*1

Q200

HDMI_1

R207
33

HDMI_1

R208
33

C

E

HDMI_1

SPDIF

E

B

C

R202
10K
HDMI_1

B

R217
10K
HDMI_1

DDC_SDA_1

DDC_SCL_1

CEC_REMOTE

CK-_HDMI1

CK+_HDMI1

D0-_HDMI1

D0+_HDMI1

D1-_HDMI1

D1+_HDMI1

D2-_HDMI1

D2+_HDMI1

HPD1

DATA2_SHIELD

DATA1_SHIELD

DATA0_SHIELD

CLK_SHIELD

DDC/CEC_GND

HDMI1_NON Screw

DATA2+

DATA2-

DATA1+

DATA1-

DATA0+

DATA0-

+5V_POWER

CLK+

CLK-

JK200-*1

YKF45-7058V

1

2

3

4

5

6

7

8

9

10

11

12

CEC

13

NC

14

SCL

15

SDA

16

17

18

HPD

19

20

SHIELD

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

JK201

SIDE_HDMI_1

CK+

D0-

9

D0_GND

8

D0+

7

D1-

6

D1_GND

5

D1+

4

D2-

3

D2_GND

2

D2+

1

R226
1K
SIDE_HDMI_1

R227

1.8K SIDE_HDMI_1

R286

10K

SIDE_HDMI_1

+5V

5V_DET_HDMI_2

MMBT3904(NXP)

R287
10K
SIDE_HDMI_1

DUP_DVB
2SC3052
Q201-*1

SIDE_HDMI_1

R230

3.3K
JP204

SIDE_HDMI_1

R231
33
SIDE_HDMI_1

R232
33
SIDE_HDMI_1

JP2 05

Q201

SIDE_HDMI_2SIDE_HDMI_1

E

B

C

C

R203
10K
SIDE_HDMI_1

B

R237
10K
SIDE_HDMI_1

E

DDC_SDA_2

DDC_SCL_2

CEC_REMOTE

CK-_HDMI2

CK+_HDMI2

D0-_HDMI2

D0+_HDMI2

D1-_HDMI2

D1+_HDMI2

D2-_HDMI2

D2+_HDMI2

SIDE_HDMI_2

HPD2

JK202

BODY_SHIELD

20

19

18

17

16

15

14

13

12

11
10

9

8

7

6

5

4

3

2

1

CK+

D0-

D0_GND

D0+

D1-

D1_GND

D1+

D2-

D2_GND

D2+

R240
1K
SIDE_HDMI_2

R241

1.8K SIDE_HDMI_2

R288

10K

SIDE_HDMI_2

+5V

5V_DET_HDMI_3

MMBT3904(NXP)

R289
10K
SIDE_HDMI_2

SIDE_HDMI_2

R244

3.3K
SIDE_HDMI_2

COMPONENT2

JK208

PPJ234-02

EU

R235
470K

NON_EU

R238
470K

NON_EU

NON_EU

R248
10K

NON_EU

R234
10K

NON_EU

R239
10K

+3.3V

R236

12K

R242

12K

NON_EU
R249
1K

NON_EU

NON_EU

SC1_R+/COMP1_Pr+

SC1_B+/COMP1_Pb+

COMP1_DET

SC1_G+/COMP1_Y+

AV/SC1_R_IN

AV/SC1_L_IN

RGB PC

JK205

SPG09-DB-010

6

1

7

2

8

3

9

4

10

5

16

11

12

13

14

15

SHILED

[GN]E-LUG

6A

[GN]O-SPRING

5A

[GN]CONTACT

4A

[BL]E-LUG-S

7B

[BL]O-SPRING

5B

[RD]E-LUG-S

7C

[RD]O-SPRING_1

5C

[RD]CONTACT_1

4C

5D

[WH]O-SPRING

4E

[RD]CONTACT_2

5E

[RD]O-SPRING_2

6E

[RD]E-LUG

RED_GND
GND_2
RED
GREEN_GND
DDC_DATA
GREEN
BLUE_GND
H_SYNC
BLUE
NC
V_SYNC
GND_1
SYNC_GND
DDC_CLOCK
DDC_GND

R297

R205
33

R206
33

+5V_ST

10K

R251
75

R252
75

R253
75

C202
10pF
50V

COMP2_Y+

COMP2_Pb+

COMP2_Pr+

R254

470K

R255

470K

R298
10K

R214
75

R215
75

R216
75

R212
10

R211
10

C203
10pF
50V

+3.3V

R256 10K

R25710K

R259

10K

DSUB_R+

RGB_DDC_SDA
DSUB_G+

DSUB_HSYNC
DSUB_B+

DSUB_VSYNC

RGB_DDC_SCL

PC_SER_DATA

PC_SER_CLK

DUP_DVB
2SC3052
Q202-*1

Q202

JP207

R245
33 SIDE_HDMI_2

R246
33 SIDE_HDMI_2

JP2 08

R266
1K

R265
10K

R267

1K

R262

12K

R263

12K

E

C

C

E

AV2_DET

COMP2_DET

COMP2_L_IN

COMP2_R_IN

+3.3V

R224

10K

B

B

R250
10K
SIDE_HDMI_2

R225

1K

R209
10K

SIDE_HDMI_2

HPD3

DDC_SDA_3

DDC_SCL_3

CEC_REMOTE

CK-_HDMI3

CK+_HDMI3

D0-_HDMI3

D0+_HDMI3

D1-_HDMI3

D1+_HDMI3

D2-_HDMI3

D2+_HDMI3

RS232C

SPG09-DB-009

PC AUDIO

DSUB_DET

JK203

1

2

3

4

5

For CEC

CEC_REMOTE

6

7

8

9

10

PEJ027-04

JK206

MMBT3904(NXP)

E_SPRING

3

T_TERMINAL1

6A

B_TERMINAL1

7A

R_SPRING

4

T_SPRING

5

B_TERMINAL2

7B

T_TERMINAL2

6B

Q204

USA

DUP_AT

2SC3052

Q204*-1

+5V_ST

C

E

E

C

R228
10K

R276

USA

+3.3V_ST

JP241

R278

10K

100

R277

100

R229
100K

USA

B

R233
100K

USA

B

R268
100

JK204

1

2

Fiber Optic

3

4

1234

USB DOWN STR EAM

5

GND

VCC

VINPUT

DUP_AT

+5V_ST

PEN_TOUCH

D225
B140A

40V

PEN_TOUCH

C212

0.1uF
16V

+5V

VIN

C219

0.1uF
16V

IC207

AP2337SA-7

3

1

R285
100

C220
10pF
50V

1A SPEC

VOUT

2

GND

C213
10uF
10V



 



USB1_OCD

SPDIF_OUT

+3.3V

R264

10K

R258
33

SIDE_USB_DM

SIDE_USB_DP

CEC_REMOTE_S7

JST1223-001

FIX_POLE

SIDE USB

3AU04S-305-ZC-(LG)

JK209

10mm

ETHERNET

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

+2.5V

WIRED IR

E_SPRING

3

T_TERMINAL1

6A

B_TERMINAL1

7A

R_SPRING

4

T_SPRING

5

B_TERMINAL2

7B

T_TERMINAL2

6B

C200

0.1uF
16V
ET_NET

JK210

XRJV-01V-0-D12-080

ET_NET

IC206

PC_R_IN

PC_L_IN

PM_TXD

PM_RXD

1

2

3

4

5

6

7

8

C1+

V+

C1-

C2+

C2-

V-

DOUT2

RIN2

+3.3V_ST

C228

0.1uF
16V

C225

0.1uF

16V

C226

0.1uF
16V

C227

0.1uF

16V

C229

0.1uF
16V

9

9

JK207

PEJ027-04

USA

R283 22

22

R284

R279

10K

TX

R220
10K

R218
470K

1/16W

R221
10K

R219
470K

5%

DOU T1

RIN 1

ROU T1

DIN 1

DIN2

ROUT2

R222
12K

R223
12K

VCC

GND

MAX3232CDR

16

15

14

13

12

11

10

9

JK204-*1

2F01TC1-CLM97-4F

SWITCH ADDED

IC204

AP2191SG-13

NC

8

OUT_2

7

OUT_1

6

FLG

5

D200

5.6V
ET_NET

GND

1

Fiber Optic

2

3

4

SHIELD

$0.11

D204

5.6V
ET_NET

R21 0
1

0

USA

1

2

3

4

GND

VCC

VIN

GND

IN_1

IN_2

EN

D205

5.6V
ET_NET

DUP_DVB

R273
0
ET_NET

R280
0
ET_NET

R213
0
NON_USA

+3.3V

D206

5.6V
ET_NET

IR

TX

R270
10K

R271
33

+5V

USB1_CTL

JK210-*1

BS-R430051

TP

ET_NET_UDE

1

1

2

2

3

3

TN

4

4

5

RP

5

6

6

7

7

8

RN

8

9

9

R291
0
ET_NET

R290
0
ET_NET

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR1

JACK INTERFACE

2011-12-1

2

7

TUNER

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

TUNER OPT1
TDSS-G201D
TDSS-H201F
TDSH-T101F
TDSN_B001F

TDSN_G301D

TU304
TDSN-G301D

DVB_T2

+1.25V_TU

C300

C301

10uF

0.1uF

6.3V

16V

FNIM

FNIM

28

SHIELD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DVB-T/C
ATSC

DVB-T_SCA

SBTVD

DVB_T2

NC_1

RESET

SCL

SDA

+B1[3.3V]

SIF

+B2[1.8V]

CVBS

NC_2

NC_3

NC_4

+B3[3.3V]

+B4[1.23V]

NC_5

GND

ERROR

SYNC

VALID

MCLK

D0

D1

D2

D3

D4

D5

D6

D7

OPT2
HNIM

HNIM
HNIM

FNIM
FNIM

SBTVD

28

SHIELD

RF_SW
RF_SW

TU303
TDSN_B001F

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

NC_1

9

NC_2

10

NC_3

11

+B3[3.3V]

12

+B4[1.23V]

13

NC_4

14

GND

15

ERROR

16

SYNC

17

VALID

18

MCLK

19

D0

20

D1

21

D2

22

D3

23

D4

24

D5

25

D6

26

D7

27

OPT3

X
X

X

Close to Tuner Pin

TU302
TDSS-G101D

DVB_T/C

1

2

3

4

5

6

7

8

9

10

11

12

SHIELD

FE_TS_SYN

FE_TS_VAL_ERR

FE_TS_CLK

FE_TS_DATA[0]

FE_TS_DATA[1]

FE_TS_DATA[2]

FE_TS_DATA[3]

FE_TS_DATA[4]

FE_TS_DATA[5]

FE_TS_DATA[6]

FE_TS_DATA[7]

NC

RESET

SCL

SDA

+3.3V

SIF

+1.8V

CVBS

IF_AGC

DIF[P]

DIF[N]

TU301
TDSS-H201F

ATSC

10

11

12

SHIELD

FE_TS_DATA[0-7]

NC_1

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

NC_2

6

+B2[1.8V]

7

NC_3

8

IF_AGC

9

DIF[P]

DIF[N]

G201D_NON_DEMODE
TU302-*1
TDSS-G201D

1

2

3

4

5

6

7

8

9

10

11

12

SHIELD

NC_1

RESET

SCL

SDA

+B1[3.3V]

NC_2

+B2[1.8V]

NC_3

IF_AGC

DIF[P]

DIF[N]

DVB_T_SCA

12

SHIELD

TU300
TDSH-T101F

RF_S/W_CTL

1

RESET

2

SCL

3

SDA

4

+B1[3.3V]

5

SIF

6

+B2[1.8V]

7

CVBS

8

IF_AGC

9

DIF[P]

10

DIF[N]

11

Close to Tuner Pin

+3.3V_TU

C302

0.1uF
16V

DVB_T2

H_NIM

0.1uF

C306

C312

10pF

50V

READY

DVB_T2

16V

C313

READY

10pF

10uF

0

50V

C310

16V

R302

R3030

0.1uF

C303

Close to Tuner Pin

16V

FE_TS_DATA[0-7]

C304
68pF

50V

IF_AGC_MAIN

NON_A_DEMODE

430

R319

C305
68pF
50V

R301

R307

R306

RF_SWITCH

R310
1K

C307

0.1uF

16V

RF_SWITCH

+3.3V_TU

R308

2.2K

100

22

22

R320

NON_A_DEMODE

FE_TS_DATA[0]

FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]

FE_TS_DATA[4]
FE_TS_DATA[5]

FE_TS_DATA[6]

FE_TS_DATA[7]

FE_TS_SYN

FE_TS_VAL_ERR

FE_TS_CLK

RF_SWITCH_CTL

R311

R309

10K

2.2K

TU_SCL

TU_SDA

TUNER_RESET

0.1uF

Close to Tuner Pin

2K

NON_A_DEMODE
430
R322

A_DEMODE

R334

0

A_DEMODE

TU_CVBS

C311

16V

C308

0.1uF
16V

R323
R324

0

R326

0

R325

0
0

R327
R328

0

R330

0

R329

0

0

R331

R333

0

R332

0

0

+1.8V_TU

A_DEMODE

FNIM
FNIM

FNIM
FNIM

FNIM
FNIM

FNIM

FNIM

FNIM

FNIM

A_DEMODE

R312

4.7K

BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]

BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

FNIM

+2.5V_TU

IF_P_MSTAR

IF_N_MSTAR

+5V

R316
470

E

B

C

BUF1_FE_TS_SYN
BUF1_FE_TS_VAL_ERR
BUF1_FE_TS_CLK

A_DEMODE
R317
82

MMBT3906(NXP)
Q301

A_DEMODE

BUF1_FE_TS_DATA[0-7]

TU_SIF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TUNER

Tuner block

3

6

CEC_REMOTE_S7

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

R406

10K

+3.3V

MODEL OPTION

PIN NAME

CK+_HDMI2
CK-_HDMI2
D0+_HDMI2
D0-_HDMI2
D1+_HDMI2
D1-_HDMI2
D2+_HDMI2
D2-_HDMI2
DDC_SDA_2
DDC_SCL_2
HPD2

CK+_HDMI3
CK-_HDMI3
D0+_HDMI3
D0-_HDMI3
D1+_HDMI3
D1-_HDMI3
D2+_HDMI3
D2-_HDMI3
DDC_SDA_3
DDC_SCL_3
HPD3

CK+_HDMI1
CK-_HDMI1
D0+_HDMI1
D0-_HDMI1
D1+_HDMI1
D1-_HDMI1
D2+_HDMI1
D2-_HDMI1
DDC_SDA_1
DDC_SCL_1
HPD1

R412 22
R413 22

R424 33
R425 68
R426 33
R427 68
R428 33
R429 68

R431 33
R432 68
R433
R434
R435 33
R436 68

R430 0
R415 33
R416 68
R417
R418
R419 33
R420 68

A_DEMODE

R421 33
R422 33
R423 33

R414 68

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

C407 0.047uF
C408 0.047uF
C409 0.047uF
C410 0.047uF
C411 0.047uF
C412 0.047uF
C413 1000pF

C414 0.047uF
C415 0.047uF
C416

33

C417

68

C418
C419
C420 1000pF

NON_EU

C421 0.047uF
C422 0.047uF
C423 0.047uF

33
68

C424 0.047uF
C425 0.047uF
C426 0.047uF
C427 1000pF

C428 0.047uF
C429 0.047uF

EU

C430 0.047uF

C406 0.047uF

A_DEMODE

FHD

MODEL_OPT_1

R409 1K

RF_SWITCH_CTL

HD

2D

R410 1K

R405 1K

R411

2.4K

EU

L421

0.047uF

0.047uF

0.047uF

0.047uF

MAIN IC

PIN NO.

AB3

F4

AB2

H3

A_RXCP

H2

A_RXCN

J1

A_RX0P

J2

A_RX0N

K1

A_RX1P

J3

A_RX1N

K3

A_RX2P

K2

A_RX2N

F4

DDCDA_DA/GPIO24

F5

DDCDA_CK/GPIO23

G5

HOTPLUGA/GPIO19

AD6

C_RXCP

AE6

C_RXCN

AD7

C_RX0P

AC6

C_RX0N

AD8

C_RX1P

AC7

C_RX1N

AC8

C_RX2P

AE8

C_RX2N

AE5

DDCDC_DA/GPIO28

AC5

DDCDC_CK/GPIO27

AD5

HOTPLUGC/GPIO21

E3

D_RXCP

E2

D_RXCN

F1

D_RX0P

F2

D_RX0N

G1

D_RX1P

F3

D_RX1N

G3

D_RX2P

G2

D_RX2N

G7

DDCDD_DA/GPIO30

G6

DDCDD_CK/GPIO29

G4

HOTPLUGD/GPIO22

R6

CEC/GPIO5

R5

HSYNC0

R4

VSYNC0

N1

RIN0P

N2

RIN0M

M1

GIN0P

M3

GIN0M

L2

BIN0P

L3

BIN0M

M2

SOGIN0

T3

HSYNC1

T2

VSYNC1

R3

RIN1P

T1

RIN1M

R2

GIN1P

R1

GIN1M

N3

BIN1P

P2

BIN1M

P3

SOGIN1

W1

RIN2P

W2

RIN2M

V1

GIN2P

V3

GIN2M

U2

BIN2P

U3

BIN2M

V2

SOGIN2

T5

CVBS0

T4

CVBS1

T6

CVBS2

T7

CVBSOUT2

U4

VCOM

LOW

FHD

IC400

LGE2111B

I2S_OUT_BCK/GPIO156
I2S_OUT_MCK/GPIO154

HIGH

HD

SIFP
SIFM

IF_AGC

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

XOUT

SPDIF_IN/GPIO152

SPDIF_OUT/GPIO153

USB0_DM
USB0_DP

USB1_DM
USB1_DP

I2S_IN_BCK/GPIO150

I2S_IN_SD/GPIO151
I2S_IN_WS/GPIO149

I2S_OUT_SD/GPIO157
I2S_OUT_WS/GPIO155

AUL1
AUR1
AUL3
AUR3
AUL4
AUR4

AUOUTL2
AUOUTR2

AUVRM

AUVAG
AUVRP

EARPHONE_OUTL
EARPHONE_OUTR

LED0/GPIO55
LED1/GPIO56

IRIN/GPIO4

HWRESET

AC3

IP

AD2

IM

AD1
AD3

AC2

AE3
AE2

AE4

XIN

AD4

B6
M7

D1
D2

AE9
AD9

C10
B10
B9

A9
B8
C9
A8

Y3
AA2
AA1
AA3
W3
Y2

AB4
AB5

AA5

AA4
Y5

AA9
AB9

B2

RP

C2

TP

A2

RN

B1

TN

A3
C3

C6

K4

R437

C447 2.2uF
C448
C449
C450 2.2uF
C451 2.2uF
C452 2.2uF

C454

4.7uF

MODEL OPTION

DSUB_HSYNC
DSUB_VSYNC

DSUB_R+

DSUB_G+

DSUB

DSUB_B+

SC1_ID
SC1_FB

SC1_R+/COMP1_Pr+

SC1_G+/COMP1_Y+

SC1_B+/COMP1_Pb+

SC1_SOG_IN

SCART1_RGB/COMP1

COMP2_Pr+

COMP2_Y+

COMP2

COMP2_Pb+

TU_CVBS

AV/SC1_CVBS_IN

COMP2_Y+

DTV/MNT_VOUT

CVBS In/OUT

Close to MSTAR

D400-*1

KDS181

DUP_DVB

SOC_RESET

+3.3V_ST

D400
BAW56 GEANDE

DUP_AT

C497
22uF
16V

R403

100K

R408

10

C402

0.1uF

SOC_RESET

+1.5V_DDR

C432

0.1uF

DDR3 1.5V

L402-*1

CB1608UA121T

DUP_DVB

L402

BLM18PG121SN1D

DUP_AT

C436

10uF

AVDD_DDR0:55mA

DECAP READY FOR TEST

C442

0.1uF

AVDD_DDR1:55mA

C4003

0.1uF

C4004

0.1uF

AVDD_MIU

C444

0.1uF

C453 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

Normal Power 3.3V

NON-UCC

C438 0.1uF

NON-UCC

C440 0.1uF

NON-UCC

C441 0.1uF

DECAP FOR SOC
(HIDDEN - UCC)

READY

C4002 0.1uF

+1.10V_VDDC

STby 3.3V

+3.3V_ST

L400-*1
CB1608UA121T

DUP_DVB

AVDD_NODIE

L400

BLM18PG121SN1D

DUP_AT

AVDD_NODIE:7.362mA

C401

0.1uF

+3.3V

L401-*1

CB1608UA121T

DUP_DVB

C431 0.1uF

VDD33

L401

BLM18PG121SN1D

DUP_AT

10uFC435

10uFC434

C4002 SHOULD NEAR MAIN IC

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

TUNER_I2C

1M

R474

R473

2.2uF

2.2uF

COMP1_DET
AV/SC1_DET

C445

C446

0.1uF

Close to MSTAR

R442 100

R443 100

A_DEMODE
C458 0.1uF
C459 0.1uF

A_DEMODE

ANALOG SIF

Close to MSTAR

L403-*1
CB1608UA121T

DUP_DVB

TU_SCL
TU_SDA

C461 30pF

X400

24MHz

C462 30pF

22

22

C456

C463

1uF

0.1uF

DUP_AT

C456-*1
1uF
DUP_DVB

R440

49.9

C446-*1
1uF
DUP_DVB

DECAP FOR SOC
(HIDDEN - UCC)

READY

C453

0.1uF

1uF

4V

DUP_AT

10uFC455

10uFC457

C468 0.1uF

H_NIM

C469 0.1uF

H_NIM

A_DEMODE
R446 47
R447 47

A_DEMODE

+3.3V

BLM18PG121SN1D

L403

H_NIM

H_NIM

C470

0.1uF

P_SDA

SPDIF_OUT

SUB_SDA
SUB_SCL
P_SCL

L404 BLM18SG121TN1D

C466

DUP_DVB

10uF

CIS10P121AC

R444

R441

49.9

49.9

C460

0.1uF

L405-*1
CB1608UA121T

DUP_DVB

+2.5V

L405

BLM18PG121SN1D

DUP_AT

L406-*1

CB1608UA121T

DUP_DVB

L406

BLM18PG121SN1D

DUP_AT

BLM18SG121TN1D

L407-*1 CIS10P121AC

VDDC 1.05V

C467-*1
1uF
DUP_DVB

10uF

C465

C467 1uF

H_NIM

H_NIM

NON_A_DEMODE
AGC 1.25V

H_NIM

100 OHM SERIAL

R448
10K

A_DEMODE 0ohm

SIDE_USB_DM
SIDE_USB_DP

I2S_I/F

AUD_SCK
AUD_MASTER_CLK
AUD_LRCH
AUD_LRCK

AV/SC1_L_IN
AV/SC1_R_IN
COMP2_L_IN
COMP2_R_IN
PC_L_IN
PC_R_IN

L404-*1

DUP_AT

RP
TP

RN
TN

*H/W opt :

R445

49.9

ETHERNET

C471

0.1uF

TX
SOC_RESET

AVDD2P5

AVDD2P5:172mA

AVDD25_PGA

C477

0.1uF

L407

DUP_DVB

Close to IC with width trace

DUP_AT

C472-*1
1uF

DUP_DVB

0.1uF

DUP_AT

DUP_AT

C474

C472 1uF

NON-UCC

0.1uF

C478

NON-UCC

0.1uF

C480

AVSS_PGA

NON-UCC

C482 0.1uF

DTV_IF

IF_P_MSTAR

DVB_T_SCA
C483
100pF

IF_N_MSTAR

DVB_T_SCA
C486
100pF

TU_SIF

100

R449

NON_A_DEMODE

0

R449-*1

A_DEMODE

Close to MSTAR

AUDIO IN

C4001 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

UCC

C489

C485

0.1uF

0.1uF
4V

NON-UCC

DECAP FOR SOC (HIDDEN - UCC)

VDDC : 2026mA

NON-UCC

NON-UCC

NON-UCC

C487 0.1uF

C484 0.1uF

C490 0.1uF

C488

0.047uF
25V

H_NIM

IF_AGC_MAIN

/CI_CD1
/CI_CD2

EU
R454 22
R455 22
EU

+5V

to delete CI or gate for

for SYSTEM EEPROM
(IC104)

AUDIO OUT

SCART1_Lout
SCART1_Rout

<CHIP Config(LED_R/BUZZ)>
Boot from SPI CS1N(EXT_FLASH) 1’b0
Boot from SPI_CS0N(INT_FLASH) 1’b1

<CHIP Config>
(I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)

B51_no_EJ : 4’b0000 Boot from 8051 with SPI flash
SB51_WOS : 4’b0001 Secure B51 without scramble
SB51_WS : 4’b0010 Secure B51 with scramble
MIPS_SPE_NO_EJ : 4’b0100 Boot from MIPS with SPI flash
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash
MIPS_WOS : 4’b1001 Secure MIPS without scramble
MIPS_WS : 4’b1010 Scerur MIPS with SCRAMBLE

I2C_SDA
I2C_SCL

RGB_DDC_SDA
RGB_DDC_SCL

Normal 2.5V

READY

C4001

R482

3.3K

0.1uF
4V

R450

R483

3.3K

3.3K

DECAP FOR SOC (HIDDEN - UCC)

UCC

UCC

UCC

4V

0.1uF

0.1uF

4V

C492

C493

C491 0.1uF

+3.3V

R451

3.3K

4V

R453

R452

2.2K

2.2K

+1.10V_VDDC

READY

READY

READY

4V

4V

C4005

0.1uF

C4006

0.1uF

4V

0.1uF

C4000

C4000,C4005,C4006 IS CAP FOR REPAIR
SHOULD BE BOTTOM SIDE

I2C_SDA
I2C_SCL
P_SDA
P_SCL

UART_RXD
UART_TXD

EU

R456
10K

R457
10K

EU

PCM_D[0-7]

PCM_A[0-14]

/PCM_REG

/PCM_OE

/PCM_WE
/PCM_IORD
/PCM_IOWR

/PCM_CE
/PCM_IRQA

/PCM_WAIT

PCM_RST

USB1_OCD
USB1_CTL

UART_RXD
UART_TXD

PM_RXD
PM_TXD

PWM0

PWM1

COMP2_DET

SC_RE2

LED_RED

KEY1
KEY2

AMP_MUTE

5V_DET_HDMI_1
5V_DET_HDMI_2
5V_DET_HDMI_3

AMP_RESET_N

TUNER_RESET

PCM_5V_CTL

MODEL_OPT_1

RF_SWITCH_CTL

SCART1_MUTE

R459 1K

CI_DET
AMP_SCL
AMP_SDA

AV2_DET

DSUB_DET

SC_RE1

PCM_A[0]
PCM_A[1]
PCM_A[2]
PCM_A[3]
PCM_A[4]
PCM_A[5]
PCM_A[6]
PCM_A[7]
PCM_A[8]
PCM_A[9]
PCM_A[10]
PCM_A[11]
PCM_A[12]
PCM_A[13]
PCM_A[14]

R461 1K

PCM_D[0]
PCM_D[1]
PCM_D[2]
PCM_D[3]

PCM_D[5]
PCM_D[6]
PCM_D[7]

EU

C495

0.1uF
16V

R466 22
R467 22

+3.3V

OS

R462 1K

NON_OS

R463 1K

R468 22

R470 1K

AB17

MAIN IC

AB19

AD15
AE15
AD14
AB15
AC16

AA16
AB16
AD16

AE20

AC20
AB18
AD17
AC15
AE17
AA19
AA18
AC19

AE18
AE14
AD19
AD18
AC18

AC17
AD20
AE21

AA17

AA20
AB22

AB20

AB21
AA21

AA22

R472 1K

EU

Y16

Y17

Y18

Y19

W16

Y21

Y20

E5

E4
U24
U25

H5

H4

Y22
V24
U23
T22

C7

E7

D7

J6

F6

C1

R43822 EU

PCMDATA0/GPIO126
PCMDATA1/GPIO127
PCMDATA2/GPIO128
PCMDATA3/GPIO120
PCMDATA4/GPIO119
PCMDATA5/GPIO118
PCMDATA6/GPIO117
PCMDATA7/GPIO116

PCMADR0/GPIO125
PCMADR1/GPIO124
PCMADR2/GPIO122
PCMADR3/GPIO121
PCMADR4/GPIO99
PCMADR5/GPIO101
PCMADR6/GPIO102
PCMADR7/GPIO103
PCMADR8/GPIO108
PCMADR9/GPIO110
PCMADR10/GPIO114
PCMADR11/GPIO112
PCMADR12/GPIO104
PCMADR13/GPIO107
PCMADR14/GPIO106

PCMREG_N/GPIO123
PCMOE_N/GPIO113
PCMWE_N/GPIO197
PCMIORD_N/GPIO111
PCMIOWR_N/GPIO109

PCMCE_N/GPIO115
PCMIRQA_N/GPIO105
PCMCD_N/GPIO130
PCMWAIT_N/GPIO100
PCM_RESET/GPIO129

PCM2_CE_N/GPIO131
PCM2_IRQA_N/GPIO132
PCM2_CD_N/GPIO135
PCM2_WAIT_N/GPIO133
PCM2_RESET/GPIO134

UART1_RX/GPIO44
UART1_TX/GPIO43
UART2_RX/GPIO64
UART2_TX/GPIO65

I2C_SDAM2/DDCR_DA/GPIO71
I2C_SCKM2/DDCR_CK/GPIO72

DDCA_DA/UART0_TX
DDCA_CK/UART0_RX

PWM0/GPIO66
PWM1/GPIO67
PWM2/GPIO68
PWM3/GPIO69
PWM4/GPIO70
PWM_PM/GPIO199

SAR0/GPIO31
SAR1/GPIO32
SAR2/GPIO33
SAR3/GPIO34
SAR4/GPIO35

LED_RED

AUD_SCK

AUD_MASTER_CLK

PWM1

PWM0

IC400

LGE2111B

N5

MAIN IC

GPIO36

A6

GPIO37

M6

GPIO38

R7

GPIO39

P5

GPIO40

D6

GPIO41

M4

GPIO42

C8

GPIO45

C5

GPIO46

E6

GPIO49

H6

GPIO50

K5

GPIO51

B7

GPIO52

J7

GPIO53

J5

GPIO54

AB3

GPIO73

AC4

GPIO74

IC400LGE2111B

TS0CLK/GPIO87

TS0VALID/GPIO85

TS0SYNC/GPIO86

TS0DATA0/GPIO77
TS0DATA1/GPIO78
TS0DATA2/GPIO79
TS0DATA3/GPIO80
TS0DATA4/GPIO81
TS0DATA5/GPIO82
TS0DATA6/GPIO83
TS0DATA7/GPIO84

TS1CLK/GPIO98
TS1VALID/GPI96
TS1SYNC/GPIO97

TS1DATA0/GPIO88
TS1DATA1/GPIO89
TS1DATA2/GPIO90
TS1DATA3/GPIO91
TS1DATA4/GPIO92
TS1DATA5/GPIO93
TS1DATA6/GPIO94
TS1DATA7/GPIO95

NF_WPZ/GPIO198
NF_CEZ/GPIO137
NF_CLE/GPIO136
NF_REZ/GPIO139
NF_WEZ/GPIO140
NF_ALE/GPIO141
NF_RBZ/GPIO142

GPIO_PM[0]/GPIO6

PM_UART_TX/GPIO_PM[1]/GPIO7

GPIO_PM[2]/GPIO8

GPIO_PM[4]/GPIO10

PM_UART_RX/GPIO_PM[5]/GPIO11

PM_SPI_SCZ1/GPIO_PM[6]/GPIO12

GPIO_PM[8]/GPIO14

PM_SPI_SCZ2/GPIO_PM[10]/GPIO16

GPIO_PM[9]/GPIO15

GPIO_PM[11]/GPIO17

PM_SPI_SCK/GPIO1

PM_SPI_CZ0/GPIO_PM[12]/GPIO0

PM_SPI_SDI/GPIO2
PM_SPI_SDO/GPIO3

AC25

LVA0P
LVA0M
LVA1P
LVA1M
LVA2P

LVA2M
LVACKP
LVACKM

LVA3P

LVA3M

LVA4P

LVA4M

LVB0P

LVB0M

LVB1P

LVB1M

LVB2P

LVB2M
LVBCKP
LVBCKM

LVB3P

LVB3M

LVB4P

LVB4M

AC24
AD25
AD24
AE24
AC23
AE23
AD23
AC22
AD22
AC21
AD21

V23
W24
W25
W23
Y25
Y24
Y23
AA24
AA23
AB24
AB25
AB23

RXA4+
RXA4­RXA3+
RXA3­RXACK+
RXACK­RXA2+
RXA2­RXA1+
RXA1­RXA0+
RXA0-

RXB4+
RXB4­RXB3+
RXB3­RXBCK+
RXBCK­RXB2+
RXB2­RXB1+
RXB1­RXB0+
RXB0-

GP4_S7LR

MAIN

AA11
Y11
AC11

AB12
AD11
W9
AE11
AB11
AE12
AC13
AB14

AB13
AC14
W13

Y14
AA14
AD13
Y13
AA13
AD12
AC12
W10

Y9
AA10
Y10
AB10
AC9
AD10
AC10

AR400 22

M5

R476 100
D4
L7

J4
D5
C4

L5
L6
B3
L4

A5

R478 33
D3
B5
B4

R480 33

for SERIAL FLASH

+1.10V_VDDC

AVDD25_PGA

AVSS_PGA

AVDD_NODIE

CI_TS_DATA[0]PCM_D[4]
CI_TS_DATA[1]
CI_TS_DATA[2]
CI_TS_DATA[3]
CI_TS_DATA[4]
CI_TS_DATA[5]
CI_TS_DATA[6]
CI_TS_DATA[7]

BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]
BUF1_FE_TS_DATA[4]
BUF1_FE_TS_DATA[5]
BUF1_FE_TS_DATA[6]
BUF1_FE_TS_DATA[7]

AR401 22

R477100

R479 33

+1.10V_VDDC

AVDD_MIU

AVDD2P5

C496 1uF

VDD33

OS

AC_DET
PM_TXD
DISP_EN

RL_ON
PM_RXD

ERROR_DET
/FLASH_WP
5V_ON

OS

MAIN IC

R481

U17
P17
R17
R18
T17
T18
U18

J11

U11
V10

P18

J14
J15
J16
K16

J17
L16
L17
M16

AA8

AB1
AB2

AB8

AA6

L20
L24

M12
M13
M14
M15
M17
M18
M19
M24

N13
N14
N15
N16
N17
N18
N19
N20
N25
P13
P14
P19
P21
P24

CI_TS_CLK
CI_TS_VAL
CI_TS_SYNC
CI_TS_DATA[0-7]

from CI SLOT

BUF1_FE_TS_CLK

BUF1_FE_TS_VAL_ERR

BUF1_FE_TS_SYN

BUF1_FE_TS_DATA[0-7]

Internal demod out

/PF_WP
/PF_CE0
/PF_CE1
/PF_OE
/PF_WE
PF_ALE
/F_RB

1K

SPI_SCK
/SPI_CS
SPI_SDI
SPI_SDO

IC400

LGE2111B

AVDDLV
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6

J9

VDDC_7
VDDC_8

P8

VDDC_9

R8

VDDC_10
VDDC_11
VDDC_12

DVDD_DDR

AVDD_DDR0_C
AVDD_DDR0_D_1
AVDD_DDR0_D_2
AVDD_DDR0_D_3

AVDD_DDR1_C
AVDD_DDR1_D_1
AVDD_DDR1_D_2
AVDD_DDR1_D_3

AVDD2P5_DADC

AVDD25_PGA
AVSS_PGA

Y8

AVDD25_LAN

AVDD_MOD

Y4

DVDD_NODIE

AVDD_AU33

W6

AVDD_DVI_USB_MPLL

Y6

AVDD_PLL

W7

VDDP

W5

AVDD_DMPLL

W4

AVDD_NODIE

K8

TEST

J8

GND_EFUSE

V4

GND_85
GND_54
GND_55

M8

GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64

N7

GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79

2011-10-20

4

GND_80
GND_81
GND_82
GND_83
GND_84
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98

GND_99
GND_100
GND_101
GND_102
GND_103
GND_104

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53

R19
R23
T23
U5
U6
V11
V15
V16
V17
V18
V19
V20
V21
W11
W15
W17
W18
W20
W21
W22
Y7
AA7
AB6
AB7
A15
A17
A20
B14
B16
B18
B21
C11
C12
C13
C20
C23
C25
D23
E17
E18
E20
E23
F18
G10
G12
G15
G16
G19
G20
G24
H10
H12
H13
H14
H15
H16
H19
H25
J12
J13
J19
J20
J24
K12
K13
K14
K15
K18
K19
K25
L8
L12
L13
L14
L15
L18
L19

6

Key/IR

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

+3.3V_ST

USA

IR

+3.3V_ST

R540

10K

KEY1

KEY2

LED_RED

+3.3V_ST

SUB_SCL

SUB_SDA

ZD503-*1

5.6B

DUP_AT

R515

4.7K

R542
10K

R516
100

R538

4.7K

ZD505-*1

5.6B

DUP_AT

R518
100

R517
100

C535

0.1uF
16V

R539

4.7K

C517
10pF

50V

DUP_DVB

R519
100

C522
10pF

R520

50V

100

READY

READY

ZD504-*1

5.6B

DUP_AT

5.48VTO5.76V

C534

0.1uF
16V

R514
22

ZD500

C520
10pF

50V

C523
10pF

50V

+3.3V_ST

ZD507-*1

5.6B

DUP_AT

ZD502

DUP_DVB

ZD501

ZD503

ZD506

ZD507

C547

0.1uF
16V

DUP_DVB

DUP_DVB

DUP_DVB

DUP_DVB

ZD504

ZD506-*1

5.6B

DUP_AT

DUP_DVB

ZD505

DUP_DVB

12507WS-08L

1

2

3

4

5

6

7

8

ZD502-*1

5.6B

DUP_AT

P501

9

ZD501-*1

5.6B

DUP_AT

ZD500-*1

5.6B

DUP_AT

LVDS

TF05-51S

A2CA1

DUP_AT

+5V

E

DUP_DVB

2SC3052
Q500-*1

C

R512

4.7K

R513

B

4.7K

A2CA1

D500

MMBD6100

DUP_DVB

P500

P503

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

HD

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

104060-8017

RXA0­RXA0+
RXA1­RXA1+

RXA2­RXA2+

RXACK­RXACK+

RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2­RXB2+

RXBCK­RXBCK+

RXB3­RXB3+
RXB4­RXB4+

FHD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

2K

R579

R536
R537 22

RXA0­RXA0+
RXA1­RXA1+

RXA2­RXA2+

RXACK­RXACK+
RXA3­RXA3+
RXA4­RXA4+

RXB0­RXB0+
RXB1­RXB1+

RXB2­RXB2+

RXBCK­RXBCK+
RXB3­RXB3+
RXB4­RXB4+

P_SDA
DISP_EN
P_SCL

PC_SER_DATA
PC_SER_CLK

47K
R578

22

+5V

R577

4.7K

B

UART_RXD
UART_TXD

C

E

Q500

MMBT3904(NXP)

DUP_AT

KDS184

D500-*1

LD500

NAND Flash
1GBit

/F_RB

/PF_OE

/PF_CE0

/PF_CE1

PF_ALE

/PF_WE

/PF_WP

R556

3.3K

SERIAL FLASH
8MBit

IC505-*1

MX25L8006EM2I-12G

MX

VCC

CS#

8

1

SO/SIO1

HOLD#

2

7

WP#

SCLK

3

6

GND

SI/SIO0

4

5

EEPROM
1MBit

IC503-*1

R1EX24256BSAS0A

Renesas_IC503

VCC

A0

8

1

WP

A1

7

2

SCL

A2

6

3

SDA

VSS

5

4

R565
1K

C550

0.1uF

R567
1K

/SPI_CS

SPI_SDO

/FLASH_WP

+3.3V

R568

4.7K

AT24C256C-SSHL-T

A0

A1

A2

GND

H27U1G8F2BTR-BC

NC_1

1

NC_2

2

NC_3

3

NC_4

4

NC_5

5

NC_6

6

R/B

7

RE

8

CE

9

NC_7

10

NC_8

11

VCC_1

12

VSS_1

13

NC_9

14

NC_10

15

CLE

16

ALE

17

WE

18

WP

19

NC_11

20

NC_12

21

NC_13

22

NC_14

23

NC_15

24

+3.3V_ST

+3.3V_ST

R564
10K

IC503

1

8

2

7

ATMEL_IC503

3

6

4

5

IC504

VCC

WP

SCL

SDA

R569

4.7K
READY

DO[IO1]

%WP[IO2]

C552

0.1uF

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

W25Q80BVSSIG

CS

1

2

3

GND

4

+3.3V

IC505

NC_29

NC_28

NC_27

NC_26

I/O7

I/O6

I/O5

I/O4

NC_25

NC_24

NC_23

VCC_2

VSS_2

NC_22

NC_21

NC_20

I/O3

I/O2

I/O1

I/O0

NC_19

NC_18

NC_17

NC_16

R573
22

R574
22

+3.3V

8

7

6

5

AR518

22

C554
10uF

10V

C555

0.1uF

AR519

22

VCC

HOLD[IO3]

CLK

DI[IO0]

I2C_SCL

I2C_SDA

+3.3V_ST

R575
33

PCM_A[7]

PCM_A[6]

PCM_A[5]

PCM_A[4]

PCM_A[3]

PCM_A[2]

PCM_A[1]

PCM_A[0]

C556

0.1uF

SPI_SCK

SPI_SDI

SS

NC_1

NC_2

NC_3

NC_4

NC_5

NC_6

R/B

RE

CE

NC_7

NC_8

VCC_1

VSS_1

NC_9

NC_10

CLE

ALE

WE

WP

NC_11

NC_12

NC_13

NC_14

NC_15

PCM_A[0-7]

IC504-*1

K9F1G08U0D-SCB0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0’h

NC_29

48

NC_28

47

NC_27

46

NC_26

45

I/O7

44

I/O6

43

I/O5

42

I/O4

41

NC_25

40

NC_24

39

NC_23

38

VCC_2

37

VSS_2

36

NC_22

35

NC_21

34

NC_20

33

I/O3

32

I/O2

31

I/O1

30

I/O0

29

NC_19

28

NC_18

27

NC_17

26

NC_16

25

81

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

* LCI: LVDS Connection Indicator

HDCP EEPROM
8KBit

CAT24C08WI-GT3-H-RECV(TV)

R563

4.7K

READY

IC502

NC_1

1

NC_2

2

READY

A2

3

VSS

4

GP4_S7LR

Memory.LVDS,IR

Addr:10101--

+3.3V

VCC

8

R570

WP

4.7K

7

READY

SCL

6

SDA

5

R571

READY

22
R572

22 READY

I2C_SCL

I2C_SDA

2011-10-20

5

6

Power Wafer

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

+3.3V_ST

RL_ON
5V_ON

+5V_ST

AP2121N-3.3TRE1

VIN

C601

C600

0.1uF

10uF

16V

10V

P_17V

R600
10K

P600

SMAW200-H18S1

1
3
5
7
9

10
12

11

14

13

16

15

18

17

19

P_17V

2
4
6
8

C607

0.1uF
16V

MLB-201209-0120P-N2

L600

120

DUP_AT

R609

C606

100

0.1uF
16V

AC_DET

L600-*1

DUP_DVB

ERROR_DET

+5V_ST

C608
10uF
10V

C620

C621

10uF

0.1uF

25V

+5V

C610

0.1uF
16V

50V

R1
R617
59K
1%

R619

17.4K
1%

R661

10K

R2

C624
1uF
10V

VFB

VREG5

C626
3300pF
50V

EN

SS

IC603

TPS54327DDAR

1

9

2

THERMAL

3

4

Vout=0.765*(1+R1/R2)

L613-*1
CB1608UA121T

+3.3V

TJ3940S-2.5V-3L

VIN

3

2

VOUT

C604-*1

DUP_AT

1uF
10V

+3.3V_ST

C604
1uF

6.3V
DUP_DVB

IC600

3

1

GND

IC601

+2.5V

VOUT

2

1

GND

R612
1

C612
10uF

6.3V

DUP_DVB

L613

120-ohm

2A

DVB_T2

C671
10uF
10V
DVB_T2

+2.5V_TU

C682

0.1uF
16V
DVB_T2

1.25V_TU

+3.3V

C617
10uF

6.3V
FNIM

IC602

AP1117EG-13

FNIM

ADJ/GND

R2

R6151FNIM

+1.25V_TU

OUTIN

R620

R618
240
FNIM

R1

1
FNIM

C625
10uF

6.3V
FNIM

Vout=1.25*(1+R2/R1)

3.3V_TU /1.8V_TU3.3Vst 2.5V Multi/2.5_TU

+3.3V

L604

120-ohm

2A

DUP_AT

L604-*1
CB1608UA121T

DUP_DVB

+3.3V Multi

[EP]GND

VIN

8

VBST

7

C628

4700pF

50V

SW

6

GND

5

+3.3V_TU

AZ1117BH-ADJTRE1

INPUT ADJ/GND

C627
10uF

6.3V

Vout=1.25*(1+R2/R1)

L605
NR5040T2R2N

2.2uH

IC604

OUTPUT

SS2

17

5

RLIM1

100K

R648

120K

RLIM2

16

6

EN1

R649

33K

DCON_EN

R662
56K

DCON_EN

R650
33K

EN2

15

7

BST1

MLB-201209-0120P-N2

R634
56K

14

BST2

13

VIN2

12

LX2_2

11

LX2_1

10

LX1_2

9

LX1_1

8

VIN1

L606-*1

DUP_DVB

+5V

L606

CIS21J121

C652

0.047uF
25V

C642 0.01uF

R639

C636 3300pF

C634
10uF
16V

C632

4.7uF
10V

V3V

GND_1

C650
10uF
16V

C629
10uF
16V

+3.3V

C630

0.1uF
16V

PGOOD

GND_2

GND_3

GND_4

GND_5

[EP]GND

R2

+1.8V_TU

5%

100

R613

5%

220

R614

R1

R621
1

C631
10uF

6.3V

10K

LOW_P

V7V

20

21

22

23

24

25

IC605

TPS65253RHDR

26

29

27

THERMAL

28

1

2

FB1

ROSC3CMP1

R630

3K
1%

R635

10K

R631
390K

1%

C645 3300pF

FB2

19

CMP2

18

4

SS1

R647

C649 0.01uF

1.5V DDR / 1.24V Core

DCON_EN

R670

4.7

C655

0.047uF
25V

C654
10uF
25V

READY
C609

3300pF
READY

L607

NR5040T3R3N

L608

NR5040T3R3N

C611
3300pF
50V
READY

R666

4.7
READY

C656
22uF
16V

C683
22uF
16V

DUP_AT

C653
10uF
25V

Vout=0.8*(1+R1/R2)

C651
22uF
16V

C657
22uF
16V

R2

R656
47K
1%

R657
43K
1%

R653

6.8K
1%

R654
51K
1%

R655
100K
1%

C666

0.022uF
16V

C661

0.022uF
16V

+1.5V_DDR

+1.10V_VDDC

R1

R1

R2

L601

500-ohm

AMP_MUTE

AMP_RESET_N

R623 2K

R624 2K

C687
330pF
50V

+3.3V

R625

R626

AUD_MASTER_CLK

AMP_SDA

AMP_SCL

C684
330pF
50V

2.2

0

AUD_SCK

AUD_LRCK

AUD_LRCH

R627
10K

READY

AC_DET

C685
330pF
50V

C633

0.1uF

16V

R628

READY

B

READY

C638

10K

R629

READY

READY

READY

0.1uF

C686
330pF
50V

50V

C

Q600

MMBT3904(NXP)

READY

E

C643

0.1uF
50V

2K

C637
4700pF
50V

C635
22pF
50V

C639
22pF
50V

R633

10K

R636
0

READY

C640
22pF
50V

C644
22pF
50V

R637

TWARN/OUT4A

0

R638

22

C647
680pF
50V

R640

22

R641

22

R642

22

R643

22

R644

22

R645
22

R646
22

C646

0.1uF
50V

EAPD/OUT4B

VDD_DIG_1

GND_DIG_1

PWRDN

VDD_PLL

FILTER_PLL

GND_PLL

XTI

BICKI

LRCKI

SDI

RESET

INT_LINE

SDA

SCL

GND_DIG_2

VDD_DIG_2

[EP]GND

19

20

21

22

23

24

25

26

Close-by

27

28

29

30

31

32

33

34

35

Close-by

36

STA368BWG

THERMAL

37

IC606

Close-by

Close-by

18

OUT3A/FFX3A

17

OUT3B/FFX3B

16

CONFIG

15

VDD

14

GND_REG

13

OUT1A

12

GND1

11

VCC1

10

OUT1B

9

OUT2A

8

VCC2

7

GND2

6

OUT2B

5

VCC_REG

4

VSS

3

TEST_MODE

2

SA

1

GND_SUB

C660

0.1uF
50V

C662

C663 0.1uF 50V

C664 1uF 25V

C665 0.1uF 50V

P_17V

C659

0.1uF
50V

1uF 25V

0.1uF
50V

C667

C669

330pF

C670

330pF

Audio AMP

L609

10.0uH

39

39

R685

R686

C672

0.22uF
50V

L610

50V

10.0uH

L611

10.0uH

50V

39

R687

C668
35V

68uF

39

R688

L612

10.0uH

C673

0.22uF
50V

C674

0.22uF
50V

C675

0.22uF
50V

C676

0.22uF
50V

C677

0.22uF
50V

C678
1000pF
50V

C679
1000pF
50V

C680
1000pF
50V

C681
1000pF
50V

4

3

P601

2

1

SMAW250-H04R

EMI GND

GND

R604
0

R602
0

R601
0

R603
0

R607
0

R605
0

R606
0

R608
0

EMI_GND1

EMI_GND2

EMI_GND3

EMI_GND4

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GP4_S7LR

Power,AMP

2011-04-01

6

AVDD_DDR0

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

R1201

R1202

AVDD_DDR0

1K 1%

0.1uF

1K 1%

C1201

A-MVREFDQ

1000pF

C1202

R1204

R1205

1K 1%

0.1uF

1K 1%

C1203

A-MVREFCA

1000pF

C1204

B-MVREFCA

1000pF

OS

C1247

AVDD_DDR0

OS

0.1uF
C1248

OS

AVDD_DDR0

L1202

CIC21J501NE

DUP_AT

C1251

AVDD_DDR0

10uF

C1218

OS

C1249

0.1uF

OS

OS

C1250

R1227

1K 1%

R1228

1K 1%

R1224

1K 1%

B-MVREFDQ

OS

R1225

1K 1%

1000pF

OS

+1.5V_DDR

L1202-*1

CB2012PK501T

DUP_DVB

DUP_AT

1uF

C1219

DUP_AT

1uF

C1218-*1
1uF
DUP_DVB

C1238

DUP_AT

1uF

C1241

DUP_AT

1uF

C1219-*1
1uF
DUP_DVB

C1238-*1
1uF
DUP_DVB

C1241-*1
1uF
DUP_DVB

CLose to DDR3

A-MVREFCA

A-MVREFDQ

AVDD_DDR0

C1205 10uF
C1207 0.1uF
C1208 0.1uF
C1210 0.1uF
C1211 0.1uF
C1212 0.1uF
C1213 0.1uF
C1214 0.1uF
C1215 0.1uF
C1216 0.1uF

OS

A-MA14

CLose to Saturn7M IC

M8

H1

R1203

L8

240

1%

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

EAN61828901

IC1201

H5TQ1G63DFR-H9C

DDR_1333_HYNIX

VREFCA

VREFDQ

ZQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

CLose to Saturn7M IC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

A-MA0
A-MA1
A-MA2
A-MA3
A-MA4
A-MA5
A-MA6
A-MA7
A-MA8
A-MA9
A-MA10
A-MA11
A-MA12
A-MA13

A-MBA0
A-MBA1
A-MBA2

A-MCKE

A-MODT
A-MRASB
A-MCASB
A-MWEB

A-MRESETB

A-MDQSL
A-MDQSLB

A-MDQSU
A-MDQSUB

A-MDML
A-MDMU

A-MDQL0
A-MDQL1
A-MDQL2
A-MDQL3
A-MDQL4
A-MDQL5
A-MDQL6
A-MDQL7

A-MDQU0
A-MDQU1
A-MDQU2
A-MDQU3
A-MDQU4

A-MDQU6
A-MDQU7

R1235

56

R1236

56

R1231
10K

A-MCK

1%

C1209

0.01uF
50V

1%

A-MCKB

AVDD_DDR0

CLose to DDR3

Hynix_1G_1600

IC1201-*1

H5TQ1G63DFR-PBC

N3

M8

A0

VREFCA

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

ZQ

A6

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

K2

N7

VDD_4

A12/BC

K8

T3

VDD_5

A13

N1

VDD_6

N9

M7

VDD_7

A15

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

SS_1G_1600

IC1201-*2

K4B1G1646G-BCK0

N3

M8

A0

VREFCA

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

SS_1G_1333

IC1201-*3

K4B1G1646G-BCH9

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

EAN61828901

IC400

LGE2111B

C1240

0.01uF
50V

R1232

10K

OS

B-MA10
B-MA11
B-MA12
B-MA13

OS

56

1%

56

1%

OS

B-MODT
B-MRASB
B-MCASB

B-MWEB

B-MRESETB

B-MDQSL

B-MDQSLB

B-MDQSU

B-MDQSUB

B-MDML

B-MDMU

B-MDQL0
B-MDQL1
B-MDQL2
B-MDQL3
B-MDQL4
B-MDQL5A-MDQL7
B-MDQL6
B-MDQL7

B-MDQU0
B-MDQU1
B-MDQU2
B-MDQU3
B-MDQU4
B-MDQU5A-MDQU5
B-MDQU6
B-MDQU7

B-MA0
B-MA1
B-MA2
B-MA3
B-MA4
B-MA5
B-MA6
B-MA7
B-MA8
B-MA9

R1237

B-MCKE

R1238

B-MBA0
B-MBA1
B-MBA2

A_DDR3_A0
A_DDR3_A1
A_DDR3_A2
A_DDR3_A3
A_DDR3_A4
A_DDR3_A5
A_DDR3_A6
A_DDR3_A7
A_DDR3_A8
A_DDR3_A9
A_DDR3_A10
A_DDR3_A11
A_DDR3_A12
A_DDR3_A13
A_DDR3_A14

A_DDR3_BA0
A_DDR3_BA1
A_DDR3_BA2

A_DDR3_MCLK
A_DDR3_MCLKZ
A_DDR3_MCLKE

A_DDR3_ODT
A_DDR3_RASZ
A_DDR3_CASZ
A_DDR3_WEZ

A_DDR3_RESET

A_DDR3_DQSL
A_DDR3_DQSBL

A_DDR3_DQSU
A_DDR3_DQSBU

A_DDR3_DQML
A_DDR3_DQMU

A_DDR3_DQL0
A_DDR3_DQL1
A_DDR3_DQL2
A_DDR3_DQL3
A_DDR3_DQL4
A_DDR3_DQL5
A_DDR3_DQL6
A_DDR3_DQL7

A_DDR3_DQU0
A_DDR3_DQU1
A_DDR3_DQU2
A_DDR3_DQU3
A_DDR3_DQU4
A_DDR3_DQU5
A_DDR3_DQU6
A_DDR3_DQU7

MAIN IC

B_DDR3_A0
B_DDR3_A1
B_DDR3_A2
B_DDR3_A3
B_DDR3_A4
B_DDR3_A5
B_DDR3_A6
B_DDR3_A7
B_DDR3_A8

B_DDR3_A9
B_DDR3_A10
B_DDR3_A11
B_DDR3_A12
B_DDR3_A13
B_DDR3_A14

B_DDR3_BA0
B_DDR3_BA1
B_DDR3_BA2

B_DDR3_MCLK
B_DDR3_MCLKZ
B_DDR3_MCLKE

B_DDR3_ODT
B_DDR3_RASZ
B_DDR3_CASZ

B_DDR3_WEZ

B_DDR3_RESET

B_DDR3_DQSL

B_DDR3_DQSBL

B_DDR3_DQSU

B_DDR3_DQSBU

B_DDR3_DQML
B_DDR3_DQMU

B_DDR3_DQL0
B_DDR3_DQL1
B_DDR3_DQL2
B_DDR3_DQL3
B_DDR3_DQL4
B_DDR3_DQL5
B_DDR3_DQL6
B_DDR3_DQL7

B_DDR3_DQU0
B_DDR3_DQU1
B_DDR3_DQU2
B_DDR3_DQU3
B_DDR3_DQU4
B_DDR3_DQU5
B_DDR3_DQU6
B_DDR3_DQU7

E22
G21
F20
E24
K20
F24
J21
F23
H22
G23
L21
G22
J22
G25
H20

D25
K22
E25

H23
H24
M20

C24
B25
D24
F22

E21

P25
N23

N24
M23

L23
R20

P23
L25
R24
K23
T25
J23
T24
K24

N21
P22
L22
R21
P20
R22
M22
N22

B_MA0
B_MA1
B_MA2
B_MA3
B_MA4
B_MA5
B_MA6
B_MA7
B_MA8
B_MA9
B_MA10
B_MA11
B_MA12
B_MA13
B_MA14

B_MBA0
B_MBA1
B_MBA2

B-MCK
B-MCKB
B_MCKE

B_MODT
B_MRASB
B_MCASB
B_MWEB

B_MRESETB

B-MDQSL
B-MDQSLB

B-MDQSU
B-MDQSUB

B-MDML
B-MDMU

B-MDQL0
B-MDQL1
B-MDQL2
B-MDQL3
B-MDQL4
B-MDQL5
B-MDQL6
B-MDQL7

B-MDQU0A-MDQU0
B-MDQU1
B-MDQU2
B-MDQU3
B-MDQU4
B-MDQU5
B-MDQU6
B-MDQU7

B-MCK

OS

B-MCKB

AVDD_DDR0A_MCASB

A_MA0
A_MA1
A_MA2
A_MA3
A_MA4
A_MA5
A_MA6
A_MA7
A_MA8

A_MA9
A_MA10
A_MA11
A_MA12
A_MA13
A_MA14

A_MBA0
A_MBA1
A_MBA2

A-MCK
A-MCKB
A_MCKE

A_MODT

A_MRASB

A_MWEB

A_MRESETB

A-MDQSL

A-MDQSLB

A-MDQSU

SS_2G_1333

IC1201-*4

K4B2G1646C

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

B2

R3

VDD_1

A9

D9

L7

VDD_2

A10/AP

G7

R7

VDD_3

A11

N7

K2

VDD_4

A12/BC

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

A-MDQSUB

A-MDML
A-MDMU

A-MDQL0
A-MDQL1
A-MDQL2
A-MDQL3
A-MDQL4
A-MDQL5
A-MDQL6

A-MDQU1
A-MDQU2
A-MDQU3
A-MDQU4
A-MDQU5
A-MDQU6
A-MDQU7

F9

E10

G9
C14
F11
A14
F10
C15
D11
C16
G13
E11
F12
B15
D10

B12
G11
B13

B17
C17
F13

A11
B11
A12

E9

G8

B22
C22

A21
C21

B20
D17

B23
B19
A23
C19
B24
C18
A24
A18

D15
F17
F14
E16
D14
D16
E14
F16

IC1202

H5TQ1G63DFR-H9C

DDR_1333_HYNIX

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

OS

R1226

240

1%

C1227 10uF
C1228 0.1uF

OS

C1229 0.1uF

OS

C1230 0.1uF

OS

C1231 0.1uF

OS

C1232 0.1uF

OS

C1233 0.1uF

OS

C1234 0.1uF

OS

C1235 0.1uF

OS

C1236 0.1uF

OS

B-MVREFCA

B-MVREFDQ

AVDD_DDR0

B-MA14

Hynix_1G_1600

IC1202-*1

H5TQ1G63DFR-PBC

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

A15

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

SS_1G_1600

IC1202-*2

K4B1G1646G-BCK0

N3

M8

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

N1

VDD_6

M7

N9

NC_5

VDD_7

R1

VDD_8

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

VDDQ_1

J7

A8

CK

VDDQ_2

K7

C1

CK

VDDQ_3

K9

C9

CKE

VDDQ_4

D2

VDDQ_5

L2

E9

CS

VDDQ_6

K1

F1

ODT

VDDQ_7

J3

H2

RAS

VDDQ_8

K3

H9

CAS

VDDQ_9

L3

WE

J1

NC_1

T2

J9

RESET

NC_2

L1

NC_3

L9

NC_4

F3

T7

DQSL

NC_6

G3

DQSL

C7

A9

DQSU

VSS_1

B7

B3

DQSU

VSS_2

E1

VSS_3

E7

G8

DML

VSS_4

D3

J2

DMU

VSS_5

J8

VSS_6

E3

M1

DQL0

VSS_7

F7

M9

DQL1

VSS_8

F2

P1

DQL2

VSS_9

F8

P9

DQL3

VSS_10

H3

T1

DQL4

VSS_11

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

VSSQ_1

D7

B9

DQU0

VSSQ_2

C3

D1

DQU1

VSSQ_3

C8

D8

DQU2

VSSQ_4

C2

E2

DQU3

VSSQ_5

A7

E8

DQU4

VSSQ_6

A2

F9

DQU5

VSSQ_7

B8

G1

DQU6

VSSQ_8

A3

G9

DQU7

VSSQ_9

SS_1G_1333

SS_2G_1333

IC1202-*3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3

M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

K4B1G1646G-BCH9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13

NC_5

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

IC1202-*4

K4B2G1646C

M8

N3

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

A0

VREFCA

P7

A1

P3

A2

H1

N2

H1

A3

VREFDQ

P8

A4

P2

A5

L8

R8

L8

ZQ

A6

ZQ

R2

A7

T8

A8

B2

B2

R3

VDD_1

A9

D9

D9

L7

VDD_2

A10/AP

G7

G7

R7

VDD_3

A11

K2

N7

K2

VDD_4

A12/BC

K8

T3

K8

A13

VDD_5

N1

N1

VDD_6

N9

M7

N9

NC_5

VDD_7

R1

R1

VDD_8

R9

M2

R9

BA0

VDD_9

N8

BA1

M3

BA2

A1

A1

VDDQ_1

A8

J7

A8

CK

VDDQ_2

C1

K7

C1

CK

VDDQ_3

C9

K9

C9

CKE

VDDQ_4

D2

D2

VDDQ_5

E9

L2

E9

CS

VDDQ_6

F1

K1

F1

ODT

VDDQ_7

H2

J3

H2

RAS

VDDQ_8

H9

K3

H9

CAS

VDDQ_9

L3

WE

J1

J1

NC_1

J9

T2

J9

RESET

NC_2

L1

L1

NC_3

L9

L9

NC_4

T7

F3

T7

DQSL

NC_6

G3

DQSL

A9

C7

A9

DQSU

VSS_1

B3

B7

B3

DQSU

VSS_2

E1

E1

VSS_3

G8

E7

G8

DML

VSS_4

J2

D3

J2

DMU

VSS_5

J8

J8

VSS_6

M1

E3

M1

DQL0

VSS_7

M9

F7

M9

DQL1

VSS_8

P1

F2

P1

DQL2

VSS_9

P9

F8

P9

DQL3

VSS_10

T1

H3

T1

DQL4

VSS_11

T9

H8

T9

DQL5

VSS_12

G2

DQL6

H7

DQL7

B1

B1

VSSQ_1

B9

D7

B9

DQU0

VSSQ_2

D1

C3

D1

DQU1

VSSQ_3

D8

C8

D8

DQU2

VSSQ_4

E2

C2

E2

DQU3

VSSQ_5

E8

A7

E8

DQU4

VSSQ_6

F9

A2

F9

DQU5

VSSQ_7

G1

B8

G1

DQU6

VSSQ_8

G9

A3

G9

DQU7

VSSQ_9

A-MA12
A-MBA1

A-MA10
A-MCKE

A-MA6
A-MA4

A-MA11

A-MA8

A-MRASB

A-MODT

A-MA1

A-MA14

AR1224 22

AR1223 22

AR1221 22

AR1220 22

AR1219 22

A_MA12
A_MBA1

A_MA10
A_MCKE

A_MA6
A_MA4

A_MA11
A_MA8

A_MRASB
A_MODT

A_MA1
A_MA14

A-MA13

A-MA9

A-MA0

A-MWEB

A-MA5
A-MA7

A-MRESETB

A-MA2

A-MCASB

A-MBA0

A-MBA2

A-MA3

AR1217 22

AR1216 22

AR1214 22

AR1218 22

AR1213 22

AR1215 22

A_MA13
A_MA9

A_MA0
A_MWEB

A_MA5
A_MA7

A_MRESETB
A_MA2

A_MCASB
A_MBA0

A_MBA2
A_MA3

B-MA12
B-MBA1

B-MA10
B-MCKE

B-MA6
B-MA4

B-MA11

B-MA8

B-MRASB

B-MODT

B-MA1

B-MA14

AR1211 22

AR1207 22

AR1203 22AR1222 22

AR1212 22

AR1202 22

AR1204 22

B_MA12

B_MA10
B_MCKE

B_MA6
B_MA4

B_MA11
B_MA8

B_MRASB
B_MODT

B_MA1
B_MA14

B-MRESETB

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

B-MA13

B-MA9B_MBA1

B-MA0

B-MWEB

B-MA5

B-MA7

B-MA2

B-MCASB

B-MBA0

B-MBA2

B-MA3

AR1206 22

AR1210 22

AR1205 22

AR1209 22

AR1225 22

AR1208 22

B_MA13
B_MA9

B_MA0
B_MWEB

B_MA5
B_MA7

B_MRESETB
B_MA2

B_MCASB
B_MBA0

B_MBA2
B_MA3

GP4L_S7LR2

DDR_256

2011/06/03

12

GP2R, LM1 Training Manual

Table of contents

1. PCB layout.

2. GP2R vs LM1

3. GP2R. (Block, Power, I2C)

4. LM1. (Block, Power, I2C)

5. LM1 SOC Power sequence.

6. Memory test.

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

7. Pen touch overview.

LGE Internal Use Only

1. PCB Layout.

GP2R (206 x 183)

※ LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP)

LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LM1 (206 x 141.5)

LGE Internal Use Only

2. GP2R vs GP4 LM1.

Difference GP2R 50PZ550 LM1 50PA6500 Changes

PDP Module

Tool

PCB

VSC

Main IC

Jack Layout

Sub Assy

PSU

SW
JIG

-

Power Wafer 18P 18P Stand by 0.3W ↓

Stand by 3.5V O O Stand by 3.5V .

R3(FHD) R4(FHD) New module. 50R4 Initial model.

PZ Tool PA Tool 12’ years New tool.

206x183 206x141.5 change PCB Size. (smaller than GP2R.)

S7R S7LR Internal sub-Micom .(PM block)

Slim Depth Slim Depth Same.

PZ Tool PA Tool GP2R 15pin, LM1 8pin

50R3 XP5 B’d 50R4 UP1 B’d Reduce po wer on time.

GP2R LM1 PDP only code.
GP2R LM1 Support DFT JIG.

. . Develop new WAFER and CABLE. (12 years)

12V_secondary X X Not use 12V.

IR Wafer 15P 8P LM1 not support 3D.

USB O O SIDE USB.

Memory DDR3 DDR3 DDR3 1Gbit . 2ea

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3. GP2R Power measure Summary

Power Line Voltage Spec [V] Voltage [V] Ripple spec [Vpp] Ripple [mV] Current [A] Remark

+5V_ST 4.845~5.355 5.01 86 0.009

+5V_ST_EN 4.845~5.355 5.00 17 0.710

+3.3V_AVDD 3.14~3.6 3.31 0.5 15 0.285

+2.5V_AVDD 2.38~2.62 2.53 20 0.200

+1.5V_DDR_IN 1.425~1.575 1.57 1.5V +/-5% 20 0.310

+1.26V_VDDC 1.2~1.32 1.27 30 0.770

+3.3V_ST 3.234~3.366 3.30 0.5 19 0.024

+17V 16.15~17.85 17.03 1.09A 1.420

+5V_TU 4.75~5.25 4.99 None 20 0.170

+5V 4.845~5.355 5.03 57 2.600

+3.3V_TU 3.15~3.46 3.26 None 26 0.320

+1.2V_TU 1.20~1.32 1.27 None 21 0.300

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-1. GP2R Power Block Diagram

5Vst

17V

L603
MAX 3A

C619
100u
16V

+5V_ST

C627

0.1u
16V

C654
22u
16V

C655

0.01u
25V

Q600
RTR030P02

+5V_ST_EN

C656
100u
16V

IC601

C636

0.01u
50V

AP2121N
300mA

IC605
TPA54319

C601

0.1u
16V

+17V +5V_TU

C634

C635

4.7u

4.7u

50V

50V

C657

0.1u
16V

+3.3V_ST

C605
100u
16V

C606

0.1u
16V

C641
10u
16V

C600

0.1u
16V

C642
10u
16V

C609
10u
16V

C610
10u
16V

IC600
AZ1085S

3.3V

C611

0.1u
16V

C612

0.1u
16V

C607
22u

6.3V

C608

0.1u
16V

IC602
TPA54319

IC603
TPA54319

L602

C615

2A

0.1u
16V

+1.5V_DDR_IN

C637

C647

10u

10u

10V

10V

+1.26V_VDDC

C651

C652

10u

10u

10V

10V

L610
2A

+3.3V_AVDD

IC604
TJ3964

C650

0.1u
16V

C653

0.1u
16V

2A/3ea

C616
22u

6.3V

C304
22u
10V

C219

0.1u
16V

10u

2ea

+2.5V_AVDD

C623

0.1u
16V

2A/2ea

2A/2ea

C552

0.1u
16V

C307

0.1u
16V

0.1u

13ea

2A 2A/2ea

10u

2ea

10u

4ea

10u

2ea

10u
1ea

IC205
AT24C02BN
RGB EDID

S7_3.3V_AVDD

NAND Flash/HDCP/EEPROM

2.5V_AVDD

10u

0.1u

1ea

4ea

0.1u

32ea

0.1u

10ea

0.1u

2ea

0.1u

8ea

DDR

S7 AVDD_DDR

DVDD

VDDC

IC203
MAX3232CDR

S7_MPLL

IC503(S-FLASH)
MX25L8005M2I-15G

SUB ASSY

5V_TU

C341

C344
68u
35V

68u
35V

C340

0.1u
50V

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

IC303 Audio AMP
STA338BWG13TR

LGE Internal Use Only

3-2. GP2R Power Block Diagram

+5V

L604
3A

L605
3A

C621

100u

16V

+5V

C624

100u

16V

C628

0.1u
16V

C631
22u
16V

C658

0.1u
16V

C750

0.1u
16V

L708
2A

IC606
AZ1085S

C725
10u
16V

C728

0.1u
16V

IC706
AZ1085S

C659
22u

6.3V

IC704
TPS54319

C753
22u
16V

C660

0.1u
16V

L101
2A

C754

0.1u
16V

L601
2A

C746
10u
10V

L708
2A

C661

0.1u
16V

C747
10u
10V

C748

0.1u
16V

+3.3V_3D

C751

0.1u
16V

L300
2A

IC206
AP2191

C126

0.1u
16V

L709
2A

IC707
AZ1117ST

L705
2A

L706
2A

L707
2A

L100
2A

+3.3V_TU

C309
22u
10V

C313

0.1u
16V

C223
100u

C752
22u
16V

C128

0.1u
16V

16V

C789
10u
16V
C753
10u
16V

C222

0.1u
16V

L710
2A

0.1u
16V

C755

0.1u
16V

C805
100p
50V
C754
100p
50V

IC301
AZ1117H

13ea

R834
0Ω1/10W

0.1u
16V

0.1u
16V

0.1u
16V

+1.2V_TU

C325
22u
10V

C103
22u
10V

7ea

7ea

3ea

C322

0.1u
16V

0.1u
16V

C104

0.1u
16V

C235

0.1u
16V

C735

0.1u
16V

C120

0.1u
16V

C332

0.1u
50V

C302

0.1u
16V

33ea

C300

0.1u
16V

+5V_CI_ON

IC205
AT24C02 EDID

USB

SPDIF

1.0V_LTX

1.0V

IC702 MX25L4005

1.8V

3.3V_LTX

3.3V_VDD

3.3V_PLL

+3.3V_CI

IC101 74LCX244

IC303 Audio AMP

+3.3V_TU

+1.2V_TU

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-3. LDO/DC-DC Start up

■ IC600 (+3.3V_AVDD/AZ1085S)

Vout

Vin

■ IC604(+2.5V_AVDD/TJ3964S)

■ IC602 (+1.5V_DDR_IN/TPS54319)

Vin

Ve
n

Vo
Io

■ IC603 (+1.26V_VDDC/TPS54319)

Vout

Vin

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

Vin

Ve
n

Vo
Io

LGE Internal Use Only

3-4. LDO/DC-DC Start up

■ IC606 (+3.3V/AZ1085S)

Vout

Vin

■ IC605 (+5V_TU/TPS54231)

Vin
Ve

n
Vo

Io

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

3-5. GP2R I2C MAP

+5V_HD
MI

+3.3V_S
T

DDC_SCL/SDA_1~3

1 (R208,209)
2 (R233,234)

10K

3 (R256,257)

HDMI1,2,3

HDMI1,2,3

0xA0 Ch10,12,11

0xA0 Ch10,12,11

SUB_SCL
SUB_SDA

4.7K (R635,R633)

TOUCH

TOUCH

0x52

0x52

Ch7

Ch7

G_EYE

G_EYE

0x20

0x20

Ch7

Ch7

SATURN7R

SATURN7R

I2S_IN_WS/GPIO174

(F15)

I2S_IN_BCK/GPIO175

(F14)

DDCR_CK/GPIO72
DDCR_DA/GPIO71

TGPIO2/I2C_CLK

TGPIO3/I2C_SDA

TGPIO0/UPGAIN
TGPIO1/DNGAIN

I2S_IN_SD/GPIO176

SPDIF_IN/GPIO177

(N22)
(M22)

(R3)
(T3)

(U1)
(U2)

(F13)

(G14)

<I2C-SCL>
<I2C-SDA>

<TU_SCL>
<TU_SDA>

<P_SCL>
<P_SDA>

LG8300

LG8300

0x74

0x74

Ch4

Ch4

2.2K (R480,R482)

EEPROM

EEPROM

0xA0

0xA0

Ch2

Ch2

4.7K (R319,R326)

TUNER

TUNER

TDTJ-S001D 0x10/C2

TDTJ-S001D 0x10/C2

Ch6

Ch6

AMP STA338BWG13TR

AMP STA338BWG13TR

0x38

0x38

Ch5

Ch5

3.3K (R1412,R1411)

2K (R360,R359)

4.7K (R780,R781)

MODULE

MODULE

0x1C

0x1C

Ch4

Ch4

HDCP

HDCP

EEPROM

EEPROM

0xA8

0xA8

Ch2

Ch2

<EEPROM-SCL>
<EEPROM-SDA>

<SCL1>
<SDA1>

<AMP_SCL>
<AMP_SDA>

<MODULE_SCL/3DF_SCL>
<MODULE_SDA/3DF_SDA>

+3.3
V

+3.3V_T

+3.3
V

+3.3
V_A
VDD

DDCA_CK/UART0_RX

DDCA_DA/UART0_TX

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

<RGB_DDC_SCL>

(B5)

<RGB_DDC_SDA>

(A5)

10K (R237,R247)

EEPROM

EEPROM

RGB 0xA0

RGB 0xA0

Ch8

Ch8

ISP

ISP

<DDC_SCL/UART_RX>

<DDC_SDA/UART_TX>

+5.0
V_ST

LGE Internal Use Only

4. LM1 Power Block optimization.

1. GP2R vs LM1 Power Block.

17V

5.1V

St 5V

AOZ1073 3A

FET SW

AP2191

USB

3.3V Multi
LDO (3A)

3.3V 3D

LDO (3A)

1V 3D core

3.3V Standby

LDO(AP2121)

Amp

5V Tuner

TPS54231 2A

1.25V Tuner
LDO

1.8V 3D DDR

LDO

3.3V AVDD
LDO (3A)

1.5V DDR

AOZ1073 3A

1.26V Core

AOZ1073 3A

2.5V
LDO

17V

5.1V

3.5V
St.

Amp

3.3V Multi

TPS54327(3A)

AP2191

USB

1.24V core

1.5V DDR

TPS65253(3A)

3.3V ST
AP2121

1.8V Tuner
LDO (1A)

1.25V _TU
LDO (1A)

2.5V

LDO (1A)

DC/DC : 4
LDO : 7

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

GP2R Power Block

DC/DC : 2
LDO : 4

LM1 Power Block

LGE Internal Use Only

4-1. P_17V

1
7
V

C620
10uF

25V

3216

OP-Amp
for SC

C667

0.1uF
50V

1608

C693
10uF

25V

3225

Spec) 850mV↓

16mVrms
283mVpp

C621

0.1uF
50V

2012

C668
68uF

35V

8PI/6.3H

C694

0.01uF
50V

1005

C711
10uF

16V

3216

17V to 3.3V
TPS54327
(3A, $0.14)

Audio
AMP

17V to 12V
TPS54231D
(2A)

C712

0.1uF
50V

1608

L605

2.2uH

3.5A

4.9x4.9

LNB

C629/50

10uF

16V

→6.3V

3216

→1608

0.00586↓

change

Spec) 165mV ↓

8.66mVrms

37.5mVpp

C630

0.1uF
16V

1005

L604

120 Ohm

2A

1608

Spec) 165mV↓

23.4mVrms

166.6mVpp

C643

0.1uF
50V

1608

C638
C646

0.1uF
50V

1608

+3.3V

C627
10uF

1608

Audio
AMP

120 Ohm

6.3V

L101

2A

1608

Spec) 165mV ↓

13.5mVrms
158mVpp

C137

0.1uF
16V

1005

+3.3V_TU

Spec) 165mV ↓

4.7mVrms

46.6mVpp

3.3V to 1.8V
AP1117E18G
(850mW)

Spec) 165mV↓

8.5mVrms

186.6mVpp

+3.3V_CI

C631

10uF

6.3V

1608

C614

0.1uF
16V

1005

Buffer for
CI_ADDR
[0:7]

Spec) 90mV↓

4.6mVrms

41.6mVpp

C618

0.1uF
16V

1005

C615
10uF

16V

→6.3V

3216

→1608

change

Tuner

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-2. P_17V

1
7
V

+3.3V

C605
10uF

6.3V

1608

L408/9

120 Ohm

2A

1608

x3

0.1uF
16V

1005

3.3V to 2.5V
TJ3940S-2.5V
(714mW)

* W18/9

x5

0.1uF
16V

1005

C427
10uF

10V

→6.3V

2012

→1608

0.00636↓

change

C612
10uF

6.3V

1608

Spec) 165mV↓

9.7mVrms

67.5mVpp

X4

10uF

10V

→6.3V

2012

→1608

change

* L7

Spec) 165mV↓

8.5mVrms
45mVpp

+2.5V

LM1

x3

120 Ohm

2A

1608

* Y17

C1417

10uF

10V

→6.3V

2012

→1608

change

Spec) 165mV↓

7.8mVrms

47.5mVpp

x6

0.1uF
16V

1005

x2

0.1uF
16V

1005

HDCP

C552

0.1uF
16V

1005

C554

10uF

10V

→6.3V

2012

→1608

change

NVR

LM1

DVB_T2

Nand
Flash

NOT_HNIM

L613

120 Ohm

2A

1608

3.3V to 1.25V
AP1117EG-13
(???mW)

C682

0.1uF
16V

1005

C625
10uF

1608

C684

0.1uF
16V

1005

6.3V

C671
10uF

10V

→6.3V

2012

→1608

change

+1.25V_TU

C685
10uF

6.3V

1608

Tuner

Tuner

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-3. P_5V

5
V

L600

120 Ohm

5A

2012

C608
10uF

10V

→16V

2012

→3216

0.0005↓

change

Spec) 250mV↓

7mVrms
70mVpp

C610

0.1uF
16V

1005

+5V

USB OCD

C219

0.1uF
16V

1005

MOFET
Switch

SPDIF

L100

120 Ohm

2A

1608

+5V_CI_ON

C104

0.1uF
16V

1005

C100
22uF

10V

→16V

3216

→3225

0.017↓

change

Spec) 250mV↓

31mVrms

135.4mVpp

C101

0.1uF
16V

1005

PCMCI

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

4-4. P_5V

5
V

+5V

L606

120 Ohm

5A

2012

C653/4

10uF

25V

3225

5V to 1.1V
TPS65253RH
D
(adjustable)
$0.25

+1.24V_VDDC

C683/57

22uF

16V

3225

C651/56

22uF

16V

3225

* M14

L405

120 Ohm

2A

1608

+1.5V_DDR_IN

1000pF

x2

0.1uF
16V

1005

x3

0.1uF
16V

1005

C467

50V

1005

Spec) 55mV↓

9.4mVrms

48.3mVpp???mVrms

C1413

10uF

10V

→6.3V

2012

→1608

change

x3

10uF

10V

→6.3V

2012

→1608

change

L412

120 Ohm

2A

1608

???mVrms

* R15

Spec) 55mV↓

17.7mVrms
70mVpp

* M17

x4

10uF

10V

→6.3V

2012

→1608

change

LM1

x4

0.1uF
16V

1005

Spec) 55mV↓

15.9mVrms
90mVpp

C468

1uF
10V

1005

LM1
MIU0/1

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

L500

500 Ohm

3A

???

C544

10uF

10V

→6.3V

2012

→1608

change

VCC_1.5V_DDR

C545

0.1uF
16V

1005

* IC501 / G7

x2

1000pF

50V

1005

Spec) 55mV↓

19.69mVrms

120.8mVpp

x2

0.1uF
16V

1005

DDR1/2

LGE Internal Use Only

4-5. STBY

C600
10uF

10V

→16V

2012

→3216

0.0005↓

change

S
T
B
Y

C601

0.1uF
16V

1005

5V to 3.3V
AP2121N-3.3
(0.3A)

Spec) 250mV↓

23mVrms
150mVpp

C604

1uF

6.3V
1005

+3.3V_ST

C228

0.1uF
16V

1005

L406

120 Ohm

2A

1608

C556

0.1uF
16V

1005

RS232C

C469

0.1uF
16V

1005

Serial Flash

LM1

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

C547

0.1uF
16V

1005

SUB Ass’y

LGE Internal Use Only

4-6. GP4 LM1 I2C MAP

EAX64337201_0

+3.3V_TU

I2C_SCKM1/GPIO75
I2C_SDAM1/GPIO76

IC400

I2S_IN_WS/GPIO149

SPDIF_IN/GPIO152

I2S_IN_SD/GPIO151

I2S_IN_BCK/GPIO150

GPIO49
GPIO50

AE6
AD6

AB5
AB3

D9
D7

D8
C8

TU_SCL

TU_SDA

AMP_SCL

AMP_SDA

P_SCL

P_SDA

SUB_SCL

SUB_SDA

R3082.2K

R624 2K

+3.3V_AVDD

R468 3.3K

R539 4.7K

R309 2.2K

+3.3V

R466 3.3K

+3.3V_ST

R538 4.7K

R623 2K

TU300
TDSS-G201D

IC300
STA368BWG

SCL_3.3V_MOD
SDA_3.3V_MOD

P501
KEY/IR PIN8

P500
LVDS

I2C_SCKM2/DDCR_CK/GPIO72
I2C_SDAM2/DDCR_DA/GPIO71

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

P23
P24

I2C_SCL

I2C_SDA

+3.3V_AVDD

R469 2.2K

R468 2.2K

IC503 EEPROM
IC502 HDCP (OTP)

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure

▶Hot Point

SOC_RESET

Multi_PWR

SOC_RESET

+3.3V_AVDD

0ms

288ms / [Spec] before a ll pwr input raise

+3.3V_AVDD
+1.10V_VDDC
+1.5V_DDR_IN

Threshold

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

+1.10V_VDDC

+1.5V_DDR_IN

◈ SOC_RESET timing and Power sequence are ok.

LGE Internal Use Only

5. GP4 LM1 SOC Power Sequence Procedure

◈ Solution

█ Value of Capacitor and resister.

① Cap Æ 22uF.

0CK226DC67A 22uF 6.3V $0.0117

② Resister Æ 100㏀.

+3.3V_AVDD

1

SOC_RESET

2

Threshold

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)

STEP1. Setting like below. (Red box) STEP2. Call “direct MIU Auto BIST” function from Menu.

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

6. Memory margin test. (DDR)

STEP3. Setting like below and push “Start DQS”. (Red box) STEP4. below picture is test result. Red box is timing margin.

※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU.

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7. Pen touch overview. (Installation_Pentouch Program.)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-1. Pen touch overview. (Check the installation status.)

Currently installed programs

1

Check the LG Pentouch Multi-touch Driver or Pentouch TV

Check USB Dongle Driver in Device Manager

2

-LG Pentouch Multi-touch Driver(MultiTouch)

-LG Pentouch Multi-touch Driver(BUS)

-LG Pentouch Multi-touch Driver(Dongle)
the Dongle Driver should be displayed when connected USB Dongle

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-4. Pen touch overview. (Using the Pentouch Function)

■ Image shown may differ from your monitor. You need the following items to use the Pentouch functions:

1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function.
2 Select the correct computer input connection to enter the Pentouch mode.

3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.

■ Viewing the Screen Settings

I
mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen
settings have been updated successfully.

① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode.
② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(Seep.38)

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

LGE Internal Use Only

7-5. Pen touch overview. (PDP Pen Touch Concept)

Principle 2. The position data processed Pentouch TV
Application looks like PC mouse.
Step 1. USB Dongle receive the position data.

Principle 1. The Pen using PDP Cell’s light energy
Step 1. The pen detect the PDP Cell’s light
Step 2. The pen convert detected light to voltage
Step 3. The pen calculate X,Y position
Step 4. The pen transfer the X,Y data through RF

RF Wireless communication

(2.4GHz)

Pen

Step 2. USB Dongle Driver parsing the positon
Step 3. Pentouch TV application drawing and click function.
Step 4. The result was displayed PDP TV through HDMI or
RGB cable.

The photo sensor in the

pen detect the light

Plasma
Display

The HDMI or RGB signal is PC’s output that configuration set by clone mode.

Copyright © 2012 LG Electronics Inc. All rights reserved.
Only for training and service purposes

USB

Dongle

It can use Multi-Touch function by support 2 pens.

Pentouch TV Application

- It was developed by LG.

- It can be using internet for web surfing , Flash Game etc.

LGE Internal Use Only