LG 42LV3700-SA Schematic

LED LCD TV

SERVICE MANUAL

CAUTION

BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

CHASSIS : LJ12B

MODEL : 42LV3700 42LV3700-SA

North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com

Internal Use Only

Printed in KoreaP/NO : MFL66981616 (1107-REV00)

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

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CONTENTS

CONTENTS .............................................................................................. 2

SAFETY PRECAUTIONS ......................................................................... 3

SPECIFICATION....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 12

EXPLODED VIEW .................................................................................. 20

SVC. SHEET ...............................................................................................

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 3 -

SAFETY PRECAUTIONS

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.

It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1W), keep the resistor 10mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check.

Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to

0.5mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Leakage Current Hot Check circuit

1.5 Kohm/10W

To Instrument's
exposed
METALLIC PARTS

Good Earth Ground
such as WATER PIPE,
CONDUIT etc.

AC Volt-meter

IMPORTANT SAFETY NOTICE

0.15uF

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Only for training and service purposes

- 4 -

CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the

following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board

module or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.

2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its
assemblies.

4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10% (by volume) Acetone and 90% (by
volume) isopropyl alcohol (90%-99% strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.

7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.

8. Use with this receiver only the test fixtures specified in this

service manual.

CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the

unit under test.

2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.

4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.

6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).

7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500°F to 600°F.

2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wire­bristle (0.5 inch, or 1.25cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.

(500°F to 600°F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature

(500°F to 600°F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

SERVICING PRECAUTIONS

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- 5 -

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.

2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and
solder it.

3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor
Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as
possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.

Power Output, Transistor Device
Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit
board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as
possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit
board.

3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

Fuse and Conventional Resistor
Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.

2. Securely crimp the leads of replacement component around
notch at stake top.

3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC
connections).

1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.

1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

1. Application range

This spec sheet is applied all of the 32”,42”,47”LCD TV with
LJ12B chassis.

2. Requirement for Test

Each part is tested as below without special appointment.

1) Temperature: 25 ºC ± 5 ºC, CST : 40 ± 5 ºC

2) Relative Humidity: 65 ± 10 %

3) Power Voltage : Standard input voltage(100-240V~, 50/60Hz)
* Standard Voltage of each product is marked by models

4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to
the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC: CE,IEC

- 6 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement.

4. General Specification(TV)

No Item Specification Remark

1 Receivable System 1) Digital : SBTVD /

2) Analog : NTSC / PAL-M / PAL-N

2 Available Channel 1) VHF : 02 ~ 13

2) UHF : 14 ~ 69

3) DTV : 02 ~ 69

4) CATV : 01 ~ 135
3 Input Voltage 1) AC 100 - 240V~ 50/60Hz
4 Market Central and South AMERICA
5 Screen Size 32 inch Wide(1920x1080) 32LV3700

42 inch Wide(1920x1080) 42LV3700

47 inch Wide(1920x1080) 47LV3700
6 Aspect Ratio 16:9
7 Tuning System FS
8 LCD Module LC320EUN-SDV2 32LV3700

LC420EUN-SDV3 42LV3700

LC470EUE-SDV1 47LV3700
9 Operating Environment Temp : 0 ~ 40 deg

Humidity : ~ 80 %

10 Storage Environment Temp : -20 ~ 60 deg

Humidity : -85 %

- 7 -

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Only for training and service purposes

5. Chrominance & Luminance

5.1 LJ12B(32/42/47LV3700-SA)

No Item Min Typ Max Unit Remark

1 Max Luminance

Module

290 360 cd/m

2

(Center 1-point / SET 250 320 cd/m

2

Full White Pattern) DCR 1M:1 3M:1
2 Luminance uniformity 77
3 Color coordinate RED X Typ. 0.637 Typ. 32LV3700-SA

Y -0.03 0.341 +0.03

GREEN X 0.320

Y 0.606

BLUE X 0.152

Y 0.055

WHITE X 0.279

Y 0.292

RED X Typ. 0.637 Typ. 42LV3700-SA

Y -0.03 0.341 +0.03

GREEN X 0.325

Y 0.600

BLUE X 0.152

Y 0.051

WHITE X 0.279

Y 0.292

RED X Typ. 0.639 Typ. 47LV3700-SA

Y -0.03 0.343 +0.03

GREEN X 0.316

Y 0.595

BLUE X 0.152

Y 0.058

WHITE X 0.279

Y 0.292

4. Contrast ratio 1000 1400 NORMAL

5. Color Temperature Cool 0.267 0.269 0.271 <Test Condition>

0.271 0.273 0.275 * The W/B Tolerance is ±0.015 for

Standard 0.283 0.285 0.287 Adjustment

0.291 0.293 0.295

** In the case of LED Model, Measure the color

Warm 0.311 0.313 0.315

temperature at the warm mode after heat run

0.327 0.329 0.331

T.V more than 60 minutes at Cinema mode.

- 8 -

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Only for training and service purposes

6. Component Video Input (Y, CB/PB, CR/PR)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I

2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I

3. 720*480 31.50 60 27.027 SDTV 480P

4. 720*480 31.47 59.94 27.0 SDTV 480P

5. 720*576 15.625 50* 13.5 SDTV 576I

6. 720*576 31.25 50* 13.5 SDTV 576P

7. 1280*720 37.5 50* 74.25 HDTV 720P

8. 1280*720 45.00 60.00 74.25 HDTV 720P

9. 1280*720 44.96 59.94 74.176 HDTV 720P

10. 1929*1080 28.125 50* 74.25 HDTV 1080I

11. 1920*1080 33.75 60.00 74.25 HDTV 1080I

12. 1920*1080 33.72 59.94 74.176 HDTV 1080I

13. 1920*1080 56.25 50* 148.5 HDTV 1080P

14. 1920*1080 67.500 60 148.50 HDTV 1080P

15. 1920*1080 67.432 59.94 148.352 HDTV 1080P

16. 1920*1080 27.000 24.000 74.25 HDTV 1080P

17. 1920*1080 26.97 23.976 74.176 HDTV 1080P

18. 1920*1080 33.75 30.000 74.25 HDTV 1080P

19. 1920*1080 33.71 29.97 740176 HDTV 1080P

7. RGB Input (PC)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 640*350 31.468 70.09 25.17 EGA X

2. 720*400 31.469 70.08 28.32 DOS O

3. 640*480 31.469 59.94 25.17 VESA(VGA) O

4. 800*600 37.879 60.31 40.00 VESA(SVGA) O

5. 1024*768 48.363 60.00 65.00 VESA(XGA) O

6. 1360*768 47.712 60.015 85.50 VESA(WXGA) X

7. 1600*1200 75.00 60.00 162 VESA (UXGA) O

8. 1920*1080 67.50 60.00 148.5 HDTV 1080P O

• RGB PC Monitor Range Limits

Min Vertical Freq - 56 Hz
Max Vertical Freq - 62 Hz
Min Horiz. Freq - 30 kHz
Max Horiz. Freq - 80 kHz
Pixel Clock - 170 MHz

(* Except Brazil)

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- 9 -

8. HDMI input (PC/DTV)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 640*350 31.468 70.09 25.17 EGA X

2. 720*400 31.469 70.08 28.32 DOS O

3. 640*480 31.469 59.94 25.17 VESA(VGA) O

4. 800*600 37.879 60.31 40.00 VESA(SVGA) O

5. 1024*768 48.363 60.00 65.00 VESA(XGA) O

6. 1280*768 47.776 59.870 79.5 CVT(WXGA) O

7. 1360*768 47.712 60.015 85.50 VESA (WXGA) O

8. 1280*1024 63.981 60.020 108.00 VESA (SXGA) O

9. 1600*1200 75.00 60.00 162 VESA (UXGA) O

10. 1920*1080 67.500 60.000 148.50 HDTV 1080P O

DTV

1 720*480 31.50 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 720*576 31.25 50* 13.5 SDTV 576P
4 1280*720 37.5 50* 74.25 HDTV 720P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1929*1080 28.125 50* 74.25 HDTV 1080I
8 1920*1080 33.75 60.00 74.25 HDTV 1080I

9 1920*1080 33.72 59.94 74.176 HDTV 1080I
10 1920*1080 56.25 50* 148.5 HDTV 1080P
11 1920*1080 67.500 60 148.50 HDTV 1080P
12 1920*1080 67.432 59.939 148.352 HDTV 1080P
13 1920*1080 27.000 24.000 74.25 HDTV 1080P
14 1920*1080 26.97 23.976 74.176 HDTV 1080P
15 1920*1080 33.75 30.000 74.25 HDTV 1080P
16 1920*1080 33.71 29.97 74.176 HDTV 1080P

(* Except Brazil)

• HDMI Monitor Range Limits
Min Vertical Freq - 56 Hz
Max Vertical Freq - 62 Hz
Min Horiz. Freq - 30 kHz
Max Horiz. Freq - 80 kHz
Pixel Clock - 170 MHz

- 10 -

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* Only 3DTV

9. HDMI Input(1.4a)

10. HDMI Input(1.3a)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing
2 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing
3 1280*720 75 50 148.5 HDTV 720P Frame packing
4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom
5 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side(half), Top and bottom,
6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom
7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom
8 1920*1080 33.75 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom

9 1920*1080 28.125 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom
10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom
11 1920*1080 33.75 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom

3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom

5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

- 11 -

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11. Wireless Input(1.3)

12. RGB input 3D(PC)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed 3D input proposed mode

1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom

2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom

3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom

4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom

5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard

Single Frame Sequential

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

PC DDC

1. 1920*1080 67.50 60.00 148.5 WUXGA (Reduced Blanking) (Side by Side), Top and Bottom

O

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- 12 -

ADJUSTMENT INSTRUCTION

1. Application Range

This specification sheet is applied all of the LJ12B/C/D/E/F/N
LCD TV models, which produced in manufacture department
or similar LG TV factory

2. Notice

(1) Because this is not a hot chassis, it is not necessary to use

an isolation transformer. However, the use of isolation

transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of

25 ºC ± 5 ºC of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.

(4) The input voltage of the receiver must keep AC 100-220

V~ 50 / 60Hz.
(5) Before adjustment, execute Heat-Run for 5 minutes.

A After Receive 100% Full white pattern (06CH) then

process Heat-run

(or “8. Test pattern” condition of Ez-Adjust status)

A How to make set white pattern

1) Press Power ON button of Service Remocon

2) Press ADJ button of Service remocon. Select “8. Test
pattern” and, after select “White” using navigation
button, and then you can see 100% Full White pattern.

* In this status you can maintain Heat-Run useless any

pattern generator

* Notice: if you maintain one picture over 20 minutes

(Especially sharp distinction black with white
pattern – 13Ch, or Cross hatch pattern – 09Ch)
then it can appear image stick near black level.

3. Adjustment Items

3.1. PCB Assembly Adjustment

A MAC Address Download
A Adjust 480i Comp1

A Adjust 1080p Comp1/RGB

• If it is necessary, it can adjustment at Manufacture Line

• You can see set adjustment status at “1. ADJUST
CHECK” of the “In-start menu”

A EDID (The Extended Display Identification Data)/DDC

(Display Data Channel) download

3.2. Set Assembly Adjustment

A Color Temperature (White Balance) Adjustment
A Using RS-232C
A PING Test
A Selection Factory output option

4. PCB Assembly Adjustment

4.1. MAC Address

4.1.1. Equipment & Condition

• Play file: Serial.exe

• MAC Address edit

• Input Start / End MAC address

4.1.2 Download method

4.1.2.1 Communication Prot connection

Connect: PCBA Jig-> RS-232C Port== PC-> RS-232C Port

4.1.2.2 MAC Address Download

• Com 1,2,3,4 and 115200(Baudrate)

• Port connection button click(1)

• Load button click(2) for MAC Address write.

• Start MAC Address write button(3)

• Check the OK Or NG

4.1.3 Equipment & Condition

• Each other connection to LAN Port of IP Hub and Jig

PCBA

PC(RS-232C)

RS-23 2C Po r t

- 13 -

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4.1.4 LAN inspection solution

• LAN Port connection with PCB

• Network setting at MENU Mode of TV

• Setting automatic IP

• Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC
Address.

4.1.5 LAN Port Inspection (PING Test)

4.1.5.1 Equipment setting

1) Play the LAN Port Test PROGRAM.

2) Input IP set up for an inspection to Test Program.

*IP Number : 12.12.2.2

4.1.6 LAN Port Inspection (PING Test)

1) Play the LAN Port Test Program.

2) connect each other LAN Port Jack.

3) Play Test (F9) button and confirm OK Message.

4) remove LAN CABLE

4.2. Using RS-232C

Adjust 3 items at 3.1 PCB assembly adjustments “adjustment
sequence” one after the order.

A Adjustment protocol

See ADC Adjustment RS232C Protocol_Ver1.0

A Necessary items before Adjustment items

• Pattern Generator : (MSPG-925FA)

•Adjust 480i Comp1 (MSPG-925FA:model :209 , pattern
:65) – Comp1 Mode

• Adjust 1080p Comp1 (MSPG-925FA:model :225 ,

pattern :65) – Comp1 Mode

• Adjust RGB (MSPG-925FA:model :225 , Pattern :65) –

RGB-PC Mode

* If you want more information then see the below

Adjustment method (Factory Adjustment)

A Adjustment sequence

• aa 00 00: Enter the ADC Adjustment mode.

• xb 00 40: Change the mode to Component1 (No actions)

• ad 00 10: Adjust 480i Comp

• ad 00 10: Adjust 1080p Comp

• xb 00 60: Change to RGB-PC mode(No action)

• ad 00 10: Adjust 1080p RGB

• xb 00 90: Endo of Adjustmennt

- 14 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5 Factory Adjustment

5.1 Manual Adjust Component 480i/1080p
RGB 1080p

A Summary : Adjustment component 480i/1080i and RGB

1080p is Gain and Black level setting at Analog to Digital
converter, and compensate the RGB deviation

A Using instrument

• Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V±0.1V p-p correctly)

<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern >

A You must make it sure its resolution and pattern cause

every instrument can have different setting

A Adjustment method 480i Comp1, Adjust 1080p Comp1/RGB

(Factory adjustment)

• ADC 480i Component1 adjustment

- Check connection of Component1

- MSPG-925FA -> Model: 209, Pattern 65

• Set Component 480i mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”

• ADC 1080p Component1 / RGB adjustment

- Check connection both of Component1 and RGB

- MSPG-925FA -> Model: 225, Pattern 65

• Set Component 1080p mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to
Component1 mode and its screen to “NORMAL”

• After get each the signal, wait more a second and enter
the “IN-START” with press IN-START key of Service
remocon. After then select “7. External ADC” with
navigator button and press “Enter”.

• After Then Press key of Service remocon “Right
Arrow(VOL+)”

• You can see “ADC Component1 Success”

• Component1 1080p, RGB 1080p Adjust is same method.

• Component 1080p Adjustment in Component1 input

mode

• RGB 1080p adjustment in RGB input mode

• If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”

5.2 EDID (The Extended Display
Identification Data) / DDC (Display Data
Channel) Download.

A Summary

• It is established in VESA, for communication between PC
and Monitor without order from user for building user
condition. It helps to make easily use realize “Plug and
Play” function.

• For EDID data write, we use DDC2B protocol.

A Auto Download

• After enter Service Mode by pushing “ADJ” key,

• Enter EDID D/L mode.

• Enter “START” by pushing “OK” key.

=> Caution : - Never connect HDMI & D-sub Cable when

the user downloading .

- Use the proper cables below for EDID
Writing.

§ Edid data and Model option download (RS232)

- 15 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.2.1 Manual Download

A Write HDMI EDID data

• Using instruments

- Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.

- S/W for DDC recording (EDID data write and read)

- D-sub jack

- Additional HDMI cable connection Jig.

• Preparing and setting.

- Set instruments and Jig. Like pic.5), then turn on PC and
Jig.

- Operate DDC write S/W (EDID write & read)

- It will operate in the DOS mode.

Pic.3) For write EDID data, setting Jig and another instruments.
See Working Guide if you want more information about EDID
communication.

• EDID data for Non 3DTV (Model name = LG TV )

- HDMI EDID table (0x1E : Physical Address)

1) HDMI 1 Check sum : 0x7F, 0xD9 (CEA Block 0x1E :10)

2) HDMI 2 Check sum : 0x7F, 0xC9 (CEA Block 0x1E :20)

3) HDMI 3 Check sum : 0x7F, 0xB9 (CEA Block 0x1E :30)

4) HDMI 4 Check sum : 0x7F, 0xA9 (CEA Block 0x1E :40)

- Analog (RGB) EDID table

1) RGB CheckSum : 1C

• EDID data for 3DTV ( Model name = LG TV )

- HDMI EDID table (0x1E : Physical Address)

1) HDMI 1 Check sum : 0x7F, 0xCB (CEA Block 0x1E :10)

2) HDMI 2 Check sum : 0x7F, 0xBB (CEA Block 0x1E :20)

3) HDMI 3 Check sum : 0x7F, 0xAB (CEA Block 0x1E :30)

4) HDMI 4 Check sum : 0x7F, 0x9B (CEA Block 0x1E :40)

- Analog (RGB) EDID table

1) CheckSum : 1C

PC

VSC

B/D

- 16 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.3 Adjustment Color Temperature (White

balance)

A Using Instruments

• Color Analyzer: CA-210 (CH 9)

- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.

• Auto-adjustment Equipment (It needs when Auto­adjustment – It is availed communicate with RS-232C :
Baud rate: 115200)

• Video Signal Generator MSPG-925F 720p, 216Gray
(Model: 217, Pattern 78)

A Connection Diagram (Auto Adjustment)

• Using Inner Pattern

• Using HDMI input

<Pic.5 Connection Diagram for Adjustment White balance>

A White Balance Adjustment

If you can’t adjust with inner pattern, then you can adjust it
using HDMI pattern. You can select option at “Ez-Adjust
Menu – 7. White Balance” there items “NONE, INNER,
HDMI”. It is normally setting at inner basically. If you can’t
adjust using inner pattern you can select HDMI item, and
you can adjust.

In manual Adjust case, if you press ADJ button of service
remocon, and enter “Ez-Adjust Menu – 7. White Balance”,
then automatically inner pattern operates. (In case of

“Inner” originally “Test-Pattern. On” will be selected in The
“Test-Pattern. On/Off”.

• Connect all cables and equipments like Pic.5)

• Set Baud Rate of RS-232C to 115200. It may set 115200

orignally.

• Connect RS-232C cable to set

• Connect HDMI cable to set

A RS-232C Command (Commonly apply)

• “wb 00 00”: Start Auto-adjustment of white balance.

• “wb 00 10”: Start Gain Adjustment (Inner pattern)

• “jb 00 c0” :

• …

• “wb 00 1f”: End of Adjustment

* If it needs, offset adjustment (wb 00 20-start, wb 00 2f-

end)

• “wb 00 ff”: End of white balance adjustment (inner pattern
disappear)

CA-100+

COL OR
ANALYZER
TYPE; CA-100+

Full W hite Pattern

RS-232C

-- 17 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

O Notice) Adjustment Mapping information

• When Color temperature (White balance) Adjustment
(Automatically)

- Press “Power only key” of service remocon and operate
automatically adjustment.

- Set BaudRate to 115200.

• If it needs, then adjustment “Offset”.

A White Balance Adjustment (Manual adjustment)

• Test Equipment: CA-210

- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.

• Manual adjustment sequence is like bellowed one.

- Turn to “Ez-Adjust” mode with press ADJ button of
service remocon.

- Select “10.Test Pattern” with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.

- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.

- Press “ADJ” button of service remocon and select
“7.White-Balance” in “Ez-Adjust” then press “

G ” button

of navigation key.

(When press “

G ” button then set will go to full white

mode)

- Adjust at three mode (Cool, Medium, Warm)

- If “cool” mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then
control R, G gain adjustment High Light adjustment.

- If “Medium” and “Warm” mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.

- All of the three mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.

- With volume button (+/-) you can adjust.

- After all adjustment finished, with Enter (A key) turn to
Ez-Adjust mode. Then with ADJ button, exit from
adjustment mode

Attachment: White Balance adjustment coordination and

color temperature.

• Using CS-1000 Equipment.

- COOL : T=11000K, ∆uv=0.000, x=0.276 y=0.283

- MEDIUM : T=9300K, ∆uv=0.000, x=0.285 y=0.293

- WARM : T=6500K, ∆uv=0.000, x=0.313 y=0.329

• Using CA-210 Equipment. (9 CH)

- Contrast value: 216 Gray

• Using CA-210 Equipment. (14 CH)

- White Balance adjustment coordination and color
temperature for Edge / IOP LED, ALEF

-White Balance adjustment table for Edge (IOP) LED

Color coordination is different according to heat run time.
LGD IOP LED, LGD EDGE LED, LGD 3D EDGE LED
(for LV5500, LW5700)

White Balance adjustment table for ALEF Model
(LW9500)

White Balance adjustment table for IOL LED MODEL
(LZ9700)

Color Coordination

Color temperature Test Equipment

x y

COOL

CA-210
CA-210

CA-210

0.269±0.002 0.273±0.002

MEDIUM

0.285±0.002 0.293±0.002

WARM

0.313±0.002 0.329±0.002

Cool 13,000k

K

o

X=0.269 (±0.002)
Y=0.273 (±0.002)

Medium 9,300k

K

X=0.285 (±0.002)
Y=0.293 (±0.002)

Color

Temperature

Warm 6,500k

K

X=0.313 (±0.002)
Y=0.329 (±0.002)

<Test Signal>

Inner pattern

(216gray,85IRE)

o

o

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329

1 0-2

3-5
6-9

10-19

279 308
2 278 306
3 277 305
4 276 303
5 20-35 274 300
6 36-49 272 297
7 50-79 271 295
8 80-149 270 294
9 Over 150 269

288
286
285
283
280
277
275
274
273

295
294
293
292
290
288
287
286
285

319
318
317
316
314
312
311
310
309

338
336
335
333
330
327
325
324
323293

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329
1 0-2

3-5
6-9

10-19

282 314
2 281 312
3 280 311
4 279 309
5 20-35 277 304
6 36-49 274 299
7 50-79 271 297
8 80-149 270 294
9 Over 150 269

294
292
291
289
284
279
277
274
273

298
297
296
295
293
290
287
286
285

322
321
320
319
317
314
311
310
309

343
341
340
338
333
328
326
323
322293

Aging time Cool Medium Warm

(Min) x y x y x y

GP3

269 273 285 293 313 329

1 0-2

3-5
6-9

10-19

278 307
2 277 305
3 276 304
4 274 302
5 20-35 272 298
6 36-49 270 295
7 50-79 269 293
8 Over80 269 293

288
286
284
282
278
275
273
273

295
294
293
291
289
287
285
285

316
315
314
313
311
309
308
308

334
332
331
329
325
322
323
323

- 18 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

5.4 EYE-Q function check

1) Turn on TV

2) Press EYE key of Adj. R/C

3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds

4) Confirm that R/G/B value is lower than 10 of the “Raw Data
(Sensor data, Back lignt )” . If after 6 seconds, R/G/B value
is not lower than 10, replace Eye Q II sensor

5) Remove your hand from the Eye Q II sensor and wait for 6
seconds

6) Confirm that “ok” pop up.
If change is not seen, replace Eye Q II sensor

5.5 HDCP (High-Bandwidth Digital
Contents Protection) Setting

• No Need.

5.6 Test of RS-232C control.

Press In-Start button of Service Remocon then set the
“4.Baud Rate” to 115200. Then check RS-232C control and

5.7 Selection of Country option.

Selection of country option is allowed only North American
model (Not allowed Korean model). It is selection of Country
about Rating and Time Zone.

Models: All models which use LA75A Chassis (See the first
page.)
Press “In-Start” button of Service Remocon, then enter the
“Option” Menu with “PIP CH-“ Button
Select one of these three (USA, CANADA, MEXICO) defends
on its market using “Vol. +/-“button.

* Caution : Don’t push The INSTOP KEY after completing

the function inspection.

6. GND and ESD Testing

6.1 Prepare GND and ESD Testing.

A Check the connection between set and power cord

6.2 Operate GND and ESD auto-test.

A Fully connected (Between set and power cord) set enter the

Auto-test sequence.

A Connect D-Jack AV jack test equipment.
A Turn on Auto-controller(GWS103-4)
A Start Auto GND test.
A If its result is NG, then notice with buzzer.
A If its result is OK, then automatically it turns to ESD Test.
A Operate ESD test
A If its result is NG, then notice with buzzer.
A If its result is OK, then process next steps. Notice it with

Good lamp and STOPER Down.Check Items.

A Test Voltage

• GND: 1.5KV/min at 100mA

• Signal: 3KV/min at 100mA

A Test time: just 1 second.
A Test point

• GND test: Test between Power cord GND and Signal
cable metal GND.

• ESD test: Test between Power cord GND and Live and

neutral.

A Leakage current: Set to 0.5mA(rms)

7. Preset Ch information.

In case of POWER ONLY, System color is operated multi
system
In case of IN STOP, System color is operated default system
(PAN-M)

- 19 -

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

8. Default Service option.

8.1 ADC-Set.

A R-Gain adjustment Value (default 128)
A G-Gain adjustment Value (default 128)
A B-Gain adjustment Value (default 128)
A R-Offset adjustment Value (default 128)
A G-Offset adjustment Value (default 128)
A B-Offset adjustment Value (default 128)

8.2 White balance. Value.

9. USB DOWNLOAD (*.epk file
download)

9.1 Put the USB Stick to the USB socket

9.2 Press Menu key, and move OPTION

9.3 Press “FAV” Press 7 times.

9.4 Select download file (epk file)

9.5 After download is finished, remove the

USB stick.

9.6 Press “IN-START” key of ADJ remote

control, check the S/W version.

LGE Internal Use OnlyCopyright LG Electronics. Inc. All right reserved.

Only for training and service purposes

- 20 -

300

200

LV1

400

540

530

521

900

910

800

710

120

511

510

A2

A21

A10

310

320

A5

* Set + Stand

* Stand Base + Body

EXPLODED VIEW

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

IMPORTANT SAFETY NOTICE

L/DIM1_VS
L/DIM0_VS

L/DIM1_SCLK
L/DIM1_MOSI
L/DIM0_SCLK
L/DIM0_MOSI

Serial Flash Boot Mode
GPIO[1:0]="00": 50MHz(Default Value)
"01": 20MHz
"10": 33.333MHz
"11": 25MHz

+3.3VD

R169

10K

GPIO_0

R170
10K

OPT

GPIO[13:11]=Boot Code Selection
(S/W control for boot code start position)

GPIO[18]=External BLU Control sync(120Hz) out
(GPIO[18],[30] connection)

GPIO[22],TP1=BLU sync Reference
(Video sync(240Hz) out monitoring)

R1004

FLASH_WP

33

W/P

Flash Memory Write Protection

RESET

+3.3VD

R1005

R1006

JTP-1127WEM

R102 33

C1160
33pF
50V
OPT

R171
10K

GPIO_1

R172
10K

OPT

+3.3VD

4.7K
OPT

4.7K
OPT

SW100

+3.3VD

R103
10K

TXA0P_2D3D
TXA0N_2D3D
TXA1P_2D3D
TXA1N_2D3D
TXA2P_2D3D

TXA2N_2D3D
TXACLKP_2D3D
TXACLKN_2D3D

TXA3P_2D3D

TXA3N_2D3D

TXA4P_2D3D

TXA4N_2D3D

TXB0P_2D3D

TXB0N_2D3D

TXB1P_2D3D

TXB1N_2D3D

TXB2P_2D3D

TXB2N_2D3D
TXBCLKP_2D3D
TXBCLKN_2D3D

TXB3P_2D3D

TXB3N_2D3D

TXB4P_2D3D

TXB4N_2D3D

C1161
33pF
50V

OPT

AGP_EN

MODE_SEL

LR_IND

I2C_SDA
I2C_SCL

R182 0

C102
33pF
50V
OPT

RBF

C104
33pF
50V
OPT

R195

47K

+3.3VD

RESET_LG1121

R106
100

1%

R107
100

1%

C105
33pF
50V
OPT

R190
10K

R196

47K

R1051KR109

+3.3VD

3.3K
R188

RESET_LG1121

+3.3VD

3.3K

R110
100

1%

R111
100

1%

C1162
33pF
50V

OPT

OUTPUT_OPT1
OUTPUT_OPT2

INCH_OPT_1
INCH_OPT_2

OUTPUT_OPT3
OUTPUT_OPT4

R189
10K

R191
R192
R193
R194

OPT

3D_SYNC_Out

SPI_SCLK

1K

3.3K

R187

XTAL_OUT

GPIO_0
GPIO_1

UART_RX
UART_TX

SPI_CS
SPI_DI
SPI_DO

R186

TRST_N

XTAL_IN

R112
100

1%

R113
100

1%

33
33
33
33

3.3K
R185

TMODE[1]

TDO
TDI
TCK
TMS

R114
100

1%

R115
100

1%

R177 33

R139 33
R120

R173
R174
R175

R147 100K
R126 33

R117
100

1%

R118
100

1%

R116 10K
R167 10K
R168 10K

R179 33

R180 33
R181 33
R137 33
R138 33

OPT

OPT
OPT

33

10K
10K
10K

R183

0

R123

R124

R140 33
R141 33

R142 33

R143 33
R144 33
R145 33
R146 33

R125 10K

TP1

33

33

R148
100

1%

R149
100

1%

AN2

RXA0P

AN1

RXA0N

AM2

RXA1P

AM1

RXA1N

AL2

RXA2P

AL1

RXA2N

AK2

RXACLKP

AK1

RXACLKN

AJ2

RXA3P

AJ1

RXA3N

AH2

RXA4P

AH1

RXA4N

AG2

RXB0P

AG1

RXB0N

AF2

RXB1P

AF1

RXB1N

AE2

RXB2P

AE1

RXB2N

AD2

RXBCLKP

AD1

RXBCLKN

AC2

RXB3P

AC1

RXB3N

AB2

RXB4P

AB1

RXB4N

J2

DPM

H1

GSP/VST/GST1

D1

H_CONV

E2

POL

E1

SOE

F2

OPT_N

D2

GSC/VGH_ODD

C1

GOE/VGH_EVEN/EO

J1

FLK/GCLK1/GCLK

H2

OPT_P/GCLK2/MCLK

G1

GCLK3/GST2

H3

GCLK4

G2

GCLK5

F1

GCLK6

D18

RMLVDS

L3

TEMPSEL0

K2

TEMPSEL1

K1

TEMPSEL2

E31

L_VSOUT_LD

M3

R_VSOUT_LD

E33

M0_SCLK

E34

M0_MOSI

G33

M1_SCLK

G34

M1_MOSI

L2

M2_SCLK

M2

M2_MOSI

L1

M3_SCLK

M1

M3_MOSI

AM10

GPIO[0]

AN10

GPIO[1]/VSYNC_IN

AP10

GPIO[2]

AP9

GPIO[3]/DE_IN

AN9

GPIO[4]

AN8

GPIO[5]

AP8

GPIO[6]

AP7

GPIO[7]

AN7

GPIO[8]/DE_OUT

AM7

GPIO[9]/LED_GPIO[0]

AM6

GPIO[10]/LED_GPIO[1]

AN6

GPIO[11]

AP6

GPIO[12]

AP5

GPIO[13]

E32

GPIO[14]/SSP0_HS

F32

GPIO[15]/SSP0_MISO

F33

GPIO[16]/SSP0_CS

F34

GPIO[17]/SSP0_INTR

AN5

GPIO[18]/SCAN_BLK1

AN4

GPIO[19]/SCAN_BLK2

AP4

GPIO[20]/SCAN_BLK3

AP3

GPIO[21]/SCAN_BLK4

AN3

GPIO[22]/SCAN_BLK5

C34

GPIO[23]/SSP1_VS

G32

GPIO[24]/SSP1_HS

H32

GPIO[25]/SSP1_MISO

H33

GPIO[26]/SSP1_CS

H34

GPIO[27]/SSP1_INTR

N1

GPIO[28]/SSP2_HS

N2

GPIO[29]/SSP2_MISO

D34

GPIO[30]/LED_VSYNC

AP2

GPIO[31]/3D_SYNC_OUT

T1

UART_RXD

T2

UART_TXD

R1

SPI_SCLK

R2

SPI_CS

P2

SPI_DI

P1

SPI_DO

V1

SDA_M

V2

SCL_M

U1

SDA_S

U2

SCL_S

W2

SMODE

Y1

TMODE0

Y2

TMODE1

AA1

TMODE2

AA2

TMODE3

AP12

TRST_N

AP11

TDO

AN11

TDI

AP13

TCK

AN13

TMS

W1

PORES_N

AP15

XTALO

AP14

XTALI

IC101

LG1121A

I2C Slave Address
0x1C (Direct access)
0x70 (In-direct access)

TXA0P/RRV7P
TXA0N/RRV7N
TXA1P/RRV6P
TXA1N/RRV6N
TXA2P/RRV5P

TXA2N/RRV5N
TXACLKP/RRV4P
TXACLKN/RRV4N
TXA3P/RRVCLKP
TXA3N/RRVCLKN

TXA4P/RRV3P

TXA4N/RRV3N

TXB0P/RRV2P

TXB0N/RRV2N

TXB1P/RRV1P

TXB1N/RRV1N

TXB2P/RRV0P

TXB2N/RRV0N

TXBCLKP
TXBCLKN

TXB3P
TXB3N
TXB4P
TXB4N

TXC0P/RLV7P

TXC0N/RLV7N

TXC1P/RLV6P

TXC1N/RLV6N

TXC2P/RLV5P

TXC2N/RLV5N
TXCCLKP/RLV4P
TXCCLKN/RLV4N
TXC3P/RLVCLKP
TXC3N/RLVCLKN

TXC4P/RLV3P

TXC4N/RLV3N

TXD0P/RLV2P

TXD0N/RLV2N

TXD1P/RLV1P

TXD1N/RLV1N

TXD2P/RLV0P

TXD2N/RLV0N

TXDCLKP
TXDCLKN

TXD3P
TXD3N
TXD4P
TXD4N

TXE0P/LRV7P

TXE0N/LRV7N

TXE1P/LRV6P

TXE1N/LRV6N

TXE2P/LRV5P

TXE2N/LRV5N
TXECLKP/LRV4P
TXECLKN/LRV4N
TXE3P/LRVCLKP
TXE3N/LRVCLKN

TXE4P/LRV3P

TXE4N/LRV3N

TXF0P/LRV2P

TXF0N/LRV2N

TXF1P/LRV1P

TXF1N/LRV1N

TXF2P/LRV0P

TXF2N/LRV0N

TXFCLKP
TXFCLKN

TXF3P
TXF3N
TXF4P
TXF4N

TXG0P/LLV7P

TXG0N/LLV7N

TXG1P/LLV6P

TXG1N/LLV6N

TXG2P/LLV5P

TXG2N/LLV5N
TXGCLKP/LLV4P
TXGCLKN/LLV4N
TXG3P/LLVCLKP
TXG3N/LLVCLKN

TXG4P/LLV3P

TXG4N/LLV3N

TXH0P/LLV2P

TXH0N/LLV2N

TXH1P/LLV1P

TXH1N/LLV1N

TXH2P/LLV0P

TXH2N/LLV0N

TXHCLKP
TXHCLKN

TXH3P
TXH3N
TXH4P
TXH4N

A2
B2
C3
C2
B3
A3
A4
B4
C5
C4
B5
A5

A6
B6
C7
C6
B7
A7
A8
B8
C9
C8
B9
A9

A10
B10
C11
C10
B11
A11
A12
B12
C13
C12
B13
A13

A14
B14
C15
C14
B15
A15
A16
B16
C17
C16
B17
A17

A18
B18
C19
C18
B19
A19
A20
B20
C21
C20
B21
A21

A22
B22
C23
C22
B23
A23
A24
B24
C25
C24
B25
A25

A26
B26
C27
C26
B27
A27
A28
B28
C29
C28
B29
A29

A30
B30
C31
C30
B31
A31
A32
B32
C33
C32
B33
A33

TXA0P
TXA0N
TXA1P
TXA1N
TXA2P
TXA2N
TXACLKP
TXACLKN
TXA3P
TXA3N
TXA4P
TXA4N

TXB0P
TXB0N
TXB1P
TXB1N
TXB2P
TXB2N
TXBCLKP
TXBCLKN
TXB3P
TXB3N
TXB4P
TXB4N

TXC0P
TXC0N
TXC1P
TXC1N
TXC2P
TXC2N
TXCCLKP
TXCCLKN
TXC3P
TXC3N
TXC4P
TXC4N

TXD0P
TXD0N
TXD1P
TXD1N
TXD2P
TXD2N
TXDCLKP
TXDCLKN
TXD3P
TXD3N
TXD4P
TXD4N

TXE0P
TXE0N
TXE1P
TXE1N
TXE2P
TXE2N
TXECLKP
TXECLKN
TXE3P
TXE3N
TXE4P
TXE4N

TXF0P
TXF0N
TXF1P
TXF1N
TXF2P
TXF2N
TXFCLKP
TXFCLKN
TXF3P
TXF3N
TXF4P
TXF4N

TXG0P
TXG0N
TXG1P
TXG1N
TXG2P
TXG2N
TXGCLKP
TXGCLKN
TXG3P
TXG3N
TXG4P
TXG4N

TXH0P
TXH0N
TXH1P
TXH1N
TXH2P
TXH2N
TXHCLKP
TXHCLKN
TXH3P
TXH3N
TXH4P
TXH4N

+3.3V_IO Decaps

+3.3V_IO

C106

0.1uF
16V

C124

0.1uF
16V

XTAL_IN

+3.3VD

R150

10K
LVDS

R151

10K

MINI_LVDS

Output LVDS Data Mapping Selection

- GPIO[3] = 1 : FRC2 LVDS out

- GPIO[3] = 0 : FRC2 MINI_LVDS out

+3.3VD

R1000

10K

DP

R1001

10K

NON_DP

Output LVDS Data Mapping Selection

- GPIO[3] = 1 : Display Port

- GPIO[3] = 0 : Non Display Port

+3.3VD

R152

10K
OPT

R153

10K

C127

C156

0.1uF

0.1uF

16V

16V

C120
27pF
50V

OUTPUT_OPT1

OUTPUT_OPT3

INCH_OPT_1

+1.0VDC Decaps

+1.0VDC

+1.0VDC

+1.0AVDD Decaps

+1.0AVDD

C162

0.1uF
16V

XTAL

24.75MHz

X-TAL_1

GND_13X-TAL_2

C170

0.1uF
16V

C1165

0.22uF

6.3V

C148
10uF
25V

C174

C169

10uF

10uF

25V

25V

1

2

C172

0.1uF
16V

C1166

0.22uF

6.3V

C1180

0.22uF

6.3V

R154
1M

X100

GND_2

4

C133
27pF
50V

+3.3VD

R155

10K

SHARP

OUTPUT_OPT2

R156

10K
XTR

Output LVDS Data Mapping Selection

- GPIO[4] = 1 : GP3 SHARP module

- GPIO[4] = 0 : GP3 XTR T-con

+3.3VD

R1002

10K
OPT

OUTPUT_OPT4

R1003

10K

+3.3VD

R157

10K
OPT

INCH_OPT_2

R158

10K

C185

C179

0.1uF

0.1uF
16V

16V

+1.0VDC

C1167

1uF

6.3V

+3.3V_IO

C1179

C181

0.22uF

10uF

6.3V

25V

XTAL_OUT

C1101

0.22uF

6.3V

C1168

C1113
10uF
25V

6.3V

IC101

SPI FLASH(4Mbit)

IC102

MX25L4006EM2I-12G

R160

R159

10K

4.7K

SPI_CS

SPI_DI

C

W/P

Q100

C187

0.1uF
16V

L103

CIS21J121

+3.3V_IO

+3.3VD

R184

1K

+1.0AVDD

R1009 0

R1007 0

R1008 0

C1172

1uF

6.3V

C1106

1uF

6.3V

B

C198

0.1uF
16V

SPI_CS

SPI_DO

SPI_SCLK

SPI_DI

TMODE[1]

W/P

E

TRST_N

KRC103S

C1173

FLASH_WP

I2C_SDA

I2C_SCL

1uF

6.3V

C1107

1uF

6.3V

FLASH_WP

For SPI/I2C Interface

P100

12507WR-10L

1

2

3

4

5

6

7

8

9

10

11

C1117

C147

10uF

0.1uF

25V

16V

C1169

1uF

+1.0V

CIS21J121

C167

0.1uF
16V

C1102

0.22uF

6.3V

C1170

1uF

1uF

6.3V

6.3V

+1.0VDC

L102

C175

0.1uF
16V

C1103

0.22uF

6.3V

C1104

0.22uF

6.3V

C154

0.1uF
16V

+1.0VDC

C1105

0.22uF

6.3V

C1171

C160

0.1uF
16V

1uF

6.3V

CS#

R161

SO/SIO1

33

WP#

GND

1

2

3

4

Serial Flash

8

7

6

5

For JTAG Interface

P102

YFW254-07

OPT

C1174

C1175

1uF

1uF

6.3V

6.3V

+3.3VD

C1109

R162

+3.3VD

0.1uF

3.3K

SPI_SCLK

SPI_DO

UART

P101

12507WR-04L

1

2

+3.3VD

3

4

5

+2.5VLVDS_RX Decaps

+2.5LVDS_RX

C1141

C1133

0.1uF

0.1uF
16V

16V

UART_TX

R166

33

UART_RX

C1136

0.1uF
16V

C1147

C1150

0.1uF

10uF

16V

25V

+2.5V

C1177

1uF

6.3V

CIS21J121

C1118

0.1uF
16V

C1140

0.1uF
16V

TDI

TMS

TCK

TDO

TRST_N

C1178

1uF

6.3V

+2.5LVDS_RX

L104

C1124

0.1uF
16V

VCC

HOL

SCL

SI/S

1

2

R163 33

3

R164 33

4

R165 33R136 33

5

R176 33

6

7

C1176

1uF

6.3V

+1.0VDC

LG1121A

F5

VDD_1

F6

VDD_2

F7

VDD_3

F9

VDD_4

F11

VDD_5

F13

VDD_6

F15

VDD_7

F17

VDD_8

F20

VDD_9

F22

VDD_10

F24

VDD_11

F26

VDD_12

F28

VDD_13

F30

VDD_14

G5

VDD_15

G30

VDD_16

H5

VDD_17

H30

VDD_18

J5

VDD_19

J30

VDD_20

K5

VDD_21

K30

VDD_22

L5

VDD_23

L30

VDD_24

M5

VDD_25

N5

VDD_26

P5

VDD_27

P30

VDD_28

R5

VDD_29

R30

VDD_30

T5

VDD_31

T30

VDD_32

U5

VDD_33

U30

VDD_34

V5

VDD_35

W5

VDD_36

Y5
Y30
AA5

AA30

AB5

AB30

AC5

AC30

AD5

AD30

AE5

AE30

AF5

AF30

AG5

AG30

AH5

AH30

AJ5
AJ6
AJ7
AJ8
AJ9

AJ10
AJ11
AJ12
AJ17
AJ18
AJ19
AJ20
AJ21
AJ23
AJ24
AJ25
AJ27
AJ28
AJ29
AJ30

VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74

AVDD33_XTAL

LVRX_LVDD_1
LVRX_LVDD_2
LVRX_LVDD_3
LVRX_LVDD_4

LVTX_LVCC_1
LVTX_LVCC_2
LVTX_LVCC_3
LVTX_LVCC_4
LVTX_LVCC_5
LVTX_LVCC_6
LVTX_LVCC_7
LVTX_LVCC_8
LVTX_LVCC_9

LVTX_LVCC_10

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8

VDD33_9
VDD33_10
VDD33_11
VDD33_12
VDD33_13
VDD33_14
VDD33_15
VDD33_16
VDD33_17
VDD33_18
VDD33_19
VDD33_20
VDD33_21
VDD33_22
VDD33_23
VDD33_24
VDD33_25
VDD33_26
VDD33_27
VDD33_28
VDD33_29
VDD33_30
VDD33_31
VDD33_32
VDD33_33
VDD33_34
VDD33_35

AVDD10_1
AVDD10_2
AVDD10_3
AVDD10_4

AVDD25_1
AVDD25_2
AVDD25_3

D4
D5
D6
D29
D30
D31
D32
D33
E4
F4
G4
H4
J4
K4
L4
M4
N4
P4
R4
T4
U4
V4
W4
Y4
AA4
AJ4
AK4
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12

AK13

AC3
AE3
AJ3
AL3

D8
D10
D12
D14
D16
D19
D21
D23
D25
D27

AJ13
AJ14
AJ15
AJ16

AM14
AM15
AM16

+3.3V_IO

+3.3V_XTAL

+2.5LVDS_RX

+2.5LVDS_TX

+1.0AVDD

+2.5AVDD

IC101

LG1121A

B1

VSS_1

B34

VSS_2

D3

VSS_3

D7

VSS_4

D9

VSS_5

D11

VSS_6

D13

VSS_7

D15

VSS_8

D17

VSS_9

D20

VSS_10

D22

VSS_11

D24

VSS_12

D26

VSS_13

D28

VSS_14

E3

VSS_15

E5

VSS_16

E6

VSS_17

E7

VSS_18

E8

VSS_19

E9

VSS_20

E10

VSS_21

E11

VSS_22

E12

VSS_23

E13

VSS_24

E14

VSS_25

E15

VSS_26

E16

VSS_27

E17

VSS_28

E18

VSS_29

E19

VSS_30

E20

VSS_31

E21

VSS_32

E22

VSS_33

E23

VSS_34

E24

VSS_35

E25

VSS_36

E26

VSS_37

E27

VSS_38

E28

VSS_39

E29

VSS_40

E30

VSS_41

F3

VSS_42

F8

VSS_43

F10

VSS_44

F12

VSS_45

F14

VSS_46

F16

VSS_47

F18

VSS_48

F19

VSS_49

F21

VSS_50

F23

VSS_51

F25

VSS_52

F27

VSS_53

F29

VSS_54

F31

VSS_55

G3

VSS_56

G31

VSS_57

H31

VSS_58

J3

VSS_59

K3

VSS_60

M12

VSS_61

M13

VSS_62

M14

VSS_63

M15

VSS_64

M16

VSS_65

M17

VSS_66

M18

VSS_67

M19

VSS_68

M20

VSS_69

M21

VSS_70

M22

VSS_71

M23

VSS_72

M30

VSS_73

M31

VSS_74

N3

VSS_75

N12

VSS_76

N13

VSS_77

N14

VSS_78

N15

VSS_79

N16

VSS_80

N17

VSS_81

N18

VSS_82

N19

VSS_83

N20

VSS_84

N21

VSS_85

N22

VSS_86

N23

VSS_87

N30

VSS_88

N32

VSS_89

P3

VSS_90

P12

VSS_91

P13

VSS_92

P14

VSS_93

P15

VSS_94

P16

VSS_95

P17

VSS_96

P18

VSS_97

P19

VSS_98

P20

VSS_99

P21

VSS_100

P22

VSS_101

P23

VSS_102

P32

VSS_103

R3

VSS_104

R12

VSS_105

R13

VSS_106

R14

VSS_107

R15

VSS_108

R16

VSS_109

R17

VSS_110

R18

VSS_111

R19

VSS_112

R20

VSS_113

R21

VSS_114

R22

VSS_115

R23

VSS_116

R32

VSS_117

T3

VSS_118

T12

VSS_119

T13

VSS_120

T14

VSS_121

T15

VSS_122

T16

VSS_123

T17

VSS_124

T18

VSS_125

T19

VSS_126

T20

VSS_127

T21

VSS_128

T22

VSS_129

T23

VSS_130

T32

VSS_131

U3

VSS_132

U12

VSS_133

U13

VSS_134

U14

VSS_135

U15

VSS_136

U16

VSS_137

U17

VSS_138

U18

VSS_139

U19

VSS_140

U20

VSS_141

U21

VSS_142

U22

VSS_143

U23

VSS_144

U32

VSS_145

V3

VSS_146

V12

VSS_147

V13

VSS_148

V14

VSS_149

V15

VSS_150

VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300

V16
V17
V18
V19
V20
V21
V22
V23
V30
V31
V32
W3
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W30
W32
Y3
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y32
AA3
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA32
AB3
AB4
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB32
AC4
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC32
AD3
AD4
AD32
AE4
AF3
AF4
AF32
AG3
AG4
AG32
AH3
AH4
AH32
AJ31
AJ32
AK3
AK14
AK15
AK16
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AM3
AM4
AM5
AM8
AM9
AM11
AM12
AM13
AM23
AM25
AM26
AM30
AM34
AN12
AN14
AN15
AN16

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+3.3VD +3.3V_IO

L100

CIS21J121

C108

0.1uF
16V

C111

0.1uF
16V

+3.3V_IO

C116

0.1uF
16V

L101

CIS21J121

+3.3V_XTAL

C119

0.1uF
16V

+3.3V_XTAL

C125

0.1uF
16V

+2.5V

+2.5V

CIS21J121

C1119

0.1uF
16V

CIS21J121

C1120

0.1uF
16V

L105

L106

+2.5LVDS_TX

+2.5AVDD

C1125

0.1uF
16V

C1126

0.1uF
16V

+2.5VLVDS_TX Decaps

+2.5LVDS_TX

C1142

C1134

0.1uF

0.1uF
16V

16V

+2.5AVDD Decaps

+2.5AVDD

C1135

C1143

0.1uF

0.1uF

16V

16V

C1148

0.1uF
16V

C1149
10uF
25V

C1151

0.1uF
16V

C1152

0.1uF
16V

C1153

0.1uF
16V

C1154

0.1uF
16V

C1155

0.1uF
16V

C1156

0.1uF
16V

C1157

0.1uF
16V

C1158

0.1uF
16V

C1159
10uF
25V

LG1121 GP3 2010. 10. 20

1LG1121 7

DDR0_A[0-13]

DDR0_RESET_N

DDR0_DATA[0-15]

+1.5VQ0

100 1%

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3

M7

M2
N8
M3

J7
K7
K9

L2
K1
J3
K3
L3

T2

F3
G3

C7
B7

E7
D3

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]

DDR0_BA[0]
DDR0_BA[1]
DDR0_BA[2]

DDR0_CLK

DDR0_CLKN

+1.5VQ0

R200

10K

DDR3 1.5V Decaps - Place these caps near Memory

DDR0_CKE

DDR0_ODT
DDR0_RASN
DDR0_CASN

DDR0_WEN

DDR0_DQS_N[0]

DDR0_DQS[1]

DDR0_DQS_N[1]

DDR0_DM[0]
DDR0_DM[1]

R203

DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]

DDR0_DATA[8]
DDR0_DATA[9]
DDR0_DATA[10]
DDR0_DATA[11]
DDR0_DATA[12]

DDR0_DATA[14]
DDR0_DATA[15]

IC201

H5TQ1G63DFR-PBC

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13

A15

BA0
BA1
BA2

CK
CK
CKE

CS
ODT
RAS
CAS
WE

RESET

DQSL
DQSL

DQSU
DQSU

DML
DMU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+0.75V_VREF0_M0

R204

240 1%

+0.75V_VREF0_M1

+1.5VQ0

DDR3 1.5V/0.75V Decap

- Place these caps near IC101

+0.75V_VREF0_D0

C231

0.1uF

+0.75V_VREF0_D1 +0.75V_VREF1_D1+0.75V_VREF1_D0

C235

0.1uF

DDR0_A[0-13]

DDR0_DATA[0-15]

+0.75V_VREF0_D0

+0.75V_VREF0_D1

DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]

DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]
DDR0_DATA[8]
DDR0_DATA[9]
DDR0_DATA[10]
DDR0_DATA[11]
DDR0_DATA[12]
DDR0_DATA[13]
DDR0_DATA[14]
DDR0_DATA[15]

DDR0_CLK

DDR0_CLKN

DDR0_DQS[0]

DDR0_DQS_N[0]

DDR0_DQS[1]

DDR0_DQS_N[1]

DDR0_CKE

DDR0_WEN
DDR0_RASN
DDR0_CASN

DDR0_ODT

DDR0_DM[0]
DDR0_DM[1]
DDR0_BA[0]
DDR0_BA[1]
DDR0_BA[2]

DDR0_RESET_N

R214 240

+1.5VQ0

IC101

LG1121A

AJ33

DDR0_A[0]

J34

DDR0_A[1]

AK34

DDR0_A[2]

AG33

DDR0_A[3]

K34

DDR0_A[4]

AG34

DDR0_A[5]

K33

DDR0_A[6]

AH33

DDR0_A[7]

K32

DDR0_A[8]

AK33

DDR0_A[9]

L34

DDR0_A[10]

J33

DDR0_A[11]

L32

DDR0_A[12]

AJ34

DDR0_A[13]

J32

DDR0_A[14]

AB33

DDR0_DQ[0]

P34

DDR0_DQ[1]

AB34

DDR0_DQ[2]

P33

DDR0_DQ[3]

AC34

DDR0_DQ[4]

N33

DDR0_DQ[5]

AC33

DDR0_DQ[6]

N34

DDR0_DQ[7]

T34

DDR0_DQ[8]

Y33

DDR0_DQ[9]

R34

DDR0_DQ[10]

AA33

DDR0_DQ[11]

U33

DDR0_DQ[12]

Y34

DDR0_DQ[13]

T33

DDR0_DQ[14]

W34

DDR0_DQ[15]

M34

DDR0_CK

M33

DDR0_CK_N

W33

DDR0_DQS[0]

V34

DDR0_DQS_N[0]

V33

DDR0_DQS[1]

U34

DDR0_DQS_N[1]

M32

DDR0_CKE

AE34

DDR0_WE_N

AD33

DDR0_RAS_N

AD34

DDR0_CAS_N

AE33

DDR0_ODT

R33

DDR0_DM[0]

AA34

DDR0_DM[1]

AF33

DDR0_BA[0]

L33

DDR0_BA[1]

AF34

DDR0_BA[2]

AH34

DDR0_RST_N

AE32

AA31
AB31
AC31
AD31
AE31
AF31
AG31
AH31

W31
N31

J31
K31
L31
P31
R31
T31
U31
Y31

DDR0_ZQ_CAL

DDR0_VREF0
DDR0_VREF1

DDR0_VDDQ_1
DDR0_VDDQ_2
DDR0_VDDQ_3
DDR0_VDDQ_4
DDR0_VDDQ_5
DDR0_VDDQ_6
DDR0_VDDQ_7
DDR0_VDDQ_8
DDR0_VDDQ_9
DDR0_VDDQ_10
DDR0_VDDQ_11
DDR0_VDDQ_12
DDR0_VDDQ_13
DDR0_VDDQ_14
DDR0_VDDQ_15
DDR0_VDDQ_16

1%

DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[12]
DDR1_DQ[13]
DDR1_DQ[14]
DDR1_DQ[15]

DDR1_DQS[0]

DDR1_DQS_N[0]

DDR1_DQS[1]

DDR1_DQS_N[1]

DDR1_ZQ_CAL

DDR1_VDDQ_1
DDR1_VDDQ_2
DDR1_VDDQ_3
DDR1_VDDQ_4
DDR1_VDDQ_5
DDR1_VDDQ_6
DDR1_VDDQ_7
DDR1_VDDQ_8

DDR1_VDDQ_9
DDR1_VDDQ_10
DDR1_VDDQ_11
DDR1_VDDQ_12
DDR1_VDDQ_13
DDR1_VDDQ_14
DDR1_VDDQ_15
DDR1_VDDQ_16

DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]

DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]
DDR1_A[13]
DDR1_A[14]

DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[4]
DDR1_DQ[5]
DDR1_DQ[6]
DDR1_DQ[7]
DDR1_DQ[8]
DDR1_DQ[9]

DDR1_CK

DDR1_CK_N

DDR1_CKE

DDR1_WE_N
DDR1_RAS_N
DDR1_CAS_N

DDR1_ODT
DDR1_DM[0]
DDR1_DM[1]
DDR1_BA[0]
DDR1_BA[1]
DDR1_BA[2]
DDR1_RST_N

DDR1_VREF0
DDR1_VREF1

AM17
AN33
AP16
AP19
AN32
AM18
AM32
AN18
AP33
AP17
AN31
AM33
AP32
AN17
AN34

AM22
AM28
AN22
AP29
AN21
AM29
AP22
AN29
AN27
AN24
AP28
AN23
AP27
AP24
AM27
AM24

AP30
AN30
AP25
AN25
AP26
AN26
AP31
AP20
AP21
AM20
AN20
AN28
AP23
AM19
AM31
AN19
AP18
AM21

AJ22
AJ26

AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32

DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]

DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]
DDR1_DATA[8]
DDR1_DATA[9]

DDR1_DATA[10]
DDR1_DATA[11]
DDR1_DATA[12]
DDR1_DATA[13]
DDR1_DATA[14]
DDR1_DATA[15]

R219 240

1%

DDR1_CLK
DDR1_CLKN
DDR1_DQS[0]
DDR1_DQS_N[0]
DDR1_DQS[1]
DDR1_DQS_N[1]
DDR1_CKE
DDR1_WEN
DDR1_RASN
DDR1_CASN
DDR1_ODT
DDR1_DM[0]
DDR1_DM[1]
DDR1_BA[0]
DDR1_BA[1]
DDR1_BA[2]
DDR1_RESET_N

+1.5VQ1

DDR1_A[0-13]

DDR1_DATA[0-15]

+0.75V_VREF1_D0

+0.75V_VREF1_D1

DDR3 1.5V/0.75V Decap

- Place these caps near IC101

C279

0.1uF

C284

0.1uF

DDR1_A[0-13]

DDR1_RESET_N

DDR1_DATA[0-15]

+1.5VQ1

DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]

DDR1_BA[0]
DDR1_BA[1]
DDR1_BA[2]

DDR1_CLK

DDR1_CLKN

DDR1_CKE

+1.5VQ1

DDR1_ODT

DDR1_RASN

R226

DDR1_CASN

10K

DDR1_WEN

DDR1_DQS[0]DDR0_DQS[0]

DDR1_DQS_N[0]

DDR1_DQS[1]

DDR1_DQS_N[1]

DDR1_DM[0]
DDR1_DM[1]

DDR3 1.5V beCaps - Place these caps near Memory

R227

DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]

DDR1_DATA[8]
DDR1_DATA[9]
DDR1_DATA[10]
DDR1_DATA[11]
DDR1_DATA[12]
DDR1_DATA[13]DDR0_DATA[13]
DDR1_DATA[14]
DDR1_DATA[15]

100

1%

IC202

H5TQ1G63DFR-PBC

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

VREFCA

VREFDQ

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

NC_1
NC_2
NC_3
NC_4
NC_6

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

+0.75V_VREF1_M0

M8

H1

L8

ZQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

J1
J9
L1
L9
T7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R228

240 1%

+0.75V_VREF1_M1

+1.5VQ1

C218

C204

C200

10uF
10V

0.1uF

C205

0.1uF

C208

0.1uF

C211

0.1uF

C213

0.1uF

C214

0.1uF

C216

0.1uF

DDR0 PHY VTT DDR1 PHY VTTDDR0 PHY VREF DDR1 PHY VREF

+1.5VQ0

C201
10uF

+0.75V_VTT0

CIS21J121

C202
10uF

+0.75V_VTT0

L204

C203

0.1uF
16V

R201

10K

R202

C223

10K

1000pF

VLDOIN

C287
10uF

C210

C206

10uF

10uF

C207

C209

0.1uF

0.1uF

16V

16V

REFIN

PGND

VOSNS

VO

C212

0.1uF
16V

IC200

TPS51200DRCR

1

2

3

4

5

0.1uF

C215

0.1uF
16V

11

THERMAL

C219

0.1uF

C221

0.1uF

[EP]

VIN

10

PGOOD

9

GND

8

EN

7

REFOUT

6

C217

0.1uF
16V

C225

C224

0.1uF

C288

0.1uF

0.1uF

L205

CIS21J121

C290

4700pF

C226

0.1uF

+3.3VD

C222

0.1uF

DDR0_A[0-13]

Close to REFOUT pin Close to REFOUT pin

C220

0.1uF
16V

C229

C228

C227

0.1uF

C230

0.1uF

0.1uF

0.1uF

+0.75V_VTT0

AR200

AR201

AR202

AR203

AR204

R205

68

68

68

68

68

68

DDR0_A[10]

DDR0_BA[1]

DDR0_A[12]
DDR0_A[8]

DDR0_A[6]
DDR0_A[4]
DDR0_A[1]
DDR0_A[11]

DDR0_A[0]
DDR0_A[2]
DDR0_A[9]
DDR0_A[13]

DDR0_A[7]
DDR0_A[5] DDR1_A[5]
DDR0_A[3]

DDR0_BA[2]

DDR0_BA[0]

DDR0_WEN
DDR0_ODT

DDR0_CASN

DDR0_RASN

+1.5VQ0 +0.75V_VREF0_M0

R206
1K
1%

R207
1K
1%

+1.5VQ0

0.1uF

R208

1K
1%

C1207

C244

0.1uF

C237

0.1uF

+1.5VQ0

R209
1K
1%

C247

0.1uF

C241
1000pF

C238

0.1uF

C1228

0.22uF

6.3V

R210
1K
1%

R211
1K
1%

C242

1000pF

C1229

0.22uF

6.3V

+0.75V_VREF0_M1

C249

C245

1000pF

0.1uF

+1.5VQ0

R212

1K
1%

C1225

0.1uF

C1230

0.22uF

6.3V

R213
1K
1%

C1231

0.22uF

6.3V

CIC21J501NE

C253

0.1uF
16V

+0.75V_VREF0_D1+0.75V_VREF0_D0

C246

0.1uF

L202

+1.5VQ0+1.5VQ0 +1.5V0

C250

1000pF

C257

0.1uF
16V

+1.5VQ1

C259

0.1uF

+0.75V_VREF1_M0

R217
1K
1%

R215
1K
1%

+1.5VQ1 +0.75V_VREF1_D1

R218

C1226

0.1uF

C264

C260

0.1uF

1000pF

1K
1%

R216

1K
1%

C1232

0.22uF

6.3V

R220
1K
1%

R221

1K
1%

+0.75V_VREF1_D0

C265

C261

0.1uF

1000pF

C1233

0.22uF

6.3V

+0.75V_VREF1_M1

C269

0.1uF

C1234

0.22uF

6.3V

+1.5VQ1

C1227

0.1uF

C273

1000pF

R222

1K
1%

R223
1K
1%

C1235

0.22uF

6.3V

+1.5V1+1.5VQ1

C1236

0.22uF

6.3V

CIC21J501NE

C276

0.1uF
16V

C270

0.1uF

L203

+1.5VQ1+1.5VQ1

C274

1000pF

C281

0.1uF
16V

C294
10uF

+0.75V_VTT1

+0.75V_VTT1

C289

0.1uF
16V

+1.5VQ1

R224

L206

CIS21J121

C1218
10uF

10K

R225

10K

C291

0.1uF
16V

C1219
10uF

C292

10uF
10V

C1221

1000pF

C1222
10uF

C1220
10uF

C293

0.1uF
16V

C297

0.1uF

C1200

0.1uF

VLDOIN

REFIN

PGND

VOSNS

C296

0.1uF
16V

C1202

0.1uF

VO

C1206

C1205

0.1uF

0.1uF

IC203

TPS51200DRCR

1

2

THERMAL

3

4

5

C298

0.1uF
16V

11

C1201

0.1uF
16V

C1210

0.1uF

10

9

8

7

6

C1212

0.1uF

[EP]

VIN

PGOOD

GND

EN

REFOUT

C1203

0.1uF
16V

C1215

0.1uF

DDR1_A[0-13]

C1223

0.1uF

C1237

1uF

6.3V

L207

CIS21J121

C1224
4700pF

+3.3VD

C1238

1uF

6.3V

DDR1_A[10]

DDR1_BA[1]

DDR1_A[12]
DDR1_A[8]

DDR1_A[6]
DDR1_A[4]
DDR1_A[11]
DDR1_A[1]

DDR1_A[0]
DDR1_A[2]
DDR1_A[9]
DDR1_A[13]

DDR1_A[7]

DDR1_A[3]

DDR1_BA[2]

DDR1_BA[0]

DDR1_WEN
DDR1_ODT

DDR1_CASN

DDR1_RASN

AR205

AR206

AR207

AR208

AR209

R229

68

+0.75V_VTT1

68

68

68

68

68

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1121 GP3

LG1121_DDR

2010. 10. 20

2

7

C300
22uF
25V

VLCD_POWER

(+12V)

L301
CIS21J121

C303

0.1uF

50V

R301
10K

C306
2200pF

C332

100pF

50V

OPT

MAX 782mA

+1.5V0

C334
22uF
10V

C336
22uF
10V

AOZ1072AI-3

PGND

VIN

AGND

FB

DCDC_Revision

IC303-*1

1

2

3

4

LX_2

8

LX_1

7

EN

6

COMP

5

+3.3VD

R306
47K

C308

0.1uF
16V

EN

6

FB

4

COMP

5

EAN60660601

50V

+1.0V_Normal

VIN

2

IC302

AOZ1024DI

3

AGND

1

PGND

LX

7

L303

3.6uH

R310

2.7K
1%

R1

R311

1.2K
1%

R312
10K

R2

1%

Vout=0.8*(1+R1/R2)

C312
3300pF
50V

OPT

MAX 2.92A

C315
22uF

10V

C318
22uF

10V

+1.0V

C321

0.1uF
16V

VLCD_POWER

(+12V)

L304

CIS21J121

C322
10uF
25V

C324
10uF
25V

C326

0.1uF
16V

+1.5V_DDR0

DCDC_Old

IC303

AOZ1072AI

PGND

AGND

1

VIN

2

3

FB

4

8

7

6

5

EAN60922901

LX_2

LX_1

EN

COMP

R302
15K

C328

0.1uF
16V

L306

3.6uH

C329
2200pF

R319
47K

+2.5V

R1

R321

6.2K
1%

R322

2.7K
1%

R323

R2

10K
1%

Vout=0.8*(1+R1/R2)

PGND

VIN

AGND

FB

DCDC_Revision

IC300-*1

AOZ1072AI-3

1

2

3

4

VLCD_POWER

+3.3V_Normal

(+12V)

L300

CIS21J121

DCDC_Old

IC300

AOZ1072AI

LX_2

8

LX_1

7

EN

6

COMP

5

R300

0

1/10W

C302
10uF
10V

+3.3VD

C301
10uF
25V

C304

0.1uF
16V

C305
10uF
25V

VLCD_POWER

R303
47K

(+12V)

PGND

1

VIN

AGND

FB

2

3

4

EAN60922901

C307

0.1uF
16V

+2.5V_Normal

AP2132MP-2.5TRG1

C309

0.1uF
16V

R304

1.5K
1%

R305

Vout=0.6*(1+R1/R2)

1K
1%

VCTRL

LX_2

8

LX_1

7

EN

6

COMP

5

1

PG

2

EN

3

VIN

4

EAN61387601

IC301

C310

0.1uF
16V

OPT

R307
43K

9

THERMAL

8

7

6

5

L302

3.6uH

C311
2200pF

[EP]

GND

ADJ

VOUT

NC

R308
18K

R309
47K

R1

R313
27K
1%

R314

4.3K
1%

R315

R2

10K
1%

Vout=0.8*(1+R1/R2)

R316

R2

16K
1%

R317
51K

R1

1%

C314
10uF
25V

C313

100pF

50V

OPT

MAX 435mA

C316
22uF
10V

MAX 405mA

C317
10uF
25V

+3.3VD

+2.5V

C319
22uF
10V

C320

0.1uF
16V

VLCD_POWER

(+12V)

VLCD_POWER

(+12V)

L305

CIS21J121

C323
10uF
25V

L308

CIS21J121

C338
10uF
25V

+1.5V_DDR1

DCDC_Old

IC304

AOZ1072AI

C325
10uF
25V

C327

0.1uF
16V

PGND

AGND

VIN

FB

1

2

3

4

EAN60922901

LX_2

8

LX_1

7

C330

EN

0.1uF

6

16V

COMP

5

R318
15K

2D to 3D LG1131 Core

DCDC_Old

IC305

AOZ1072AI

C339
10uF
25V

C340

0.1uF
16V

PGND

AGND

VIN

FB

1

2

3

4

EAN60922901

LX_2

8

LX_1

7

C341

EN

6

0.1uF
16V

COMP

5

R327

5.1K

L307

3.6uH

C331
2200pF

L309

3.6uH

C342
2200pF

R328
47K

+2.5V

R320
47K

R1

R2

Vout=0.8*(1+R1/R2)

+2.5V

R1

R329
2K
1%

R330

1.5K
1%

R324

6.2K
1%

R325

2.7K
1%

R326
10K
1%

100pF

C343

100pF

50V

OPT

C333

50V

OPT

MAX 782mA

C335
22uF
10V

MAX 467mA

+1.0V_2D3D

C344
22uF
10V

+1.5V1

C345
22uF
10V

C337
22uF
10V

PGND

VIN

AGND

FB

PGND

VIN

AGND

FB

DCDC_Revision

IC304-*1

AOZ1072AI-3

1

2

3

4

DCDC_Revision

IC305-*1

AOZ1072AI-3

1

2

3

4

LX_2

8

LX_1

7

EN

6

COMP

5

LX_2

8

LX_1

7

EN

6

COMP

5

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

R331

R2

12K
1%

Vout=0.8*(1+R1/R2)

LG1121 GP3

LG1121_POWER

2010. 10. 20

3

7

VLCD_POWER

(+12V)

HVDD

(+8.4V)

R453

0

1/10W

C401
10uF
25V

VL

(+5V)

R408
150K

1%

R410

TH400
47k-ohm

120K

R409 0

1/10W

Place Bottom

C403
10uF
25V
OPT

R454
10

1/10W

C404
10uF
25V

R405

2.7K

C402
10uF
25V

VDD_LCM

(+16.8V)

to prevent inrush current

TCOMP

L400
22uH

D400
1N4148W

100V

C405
10uF
25V

C409

C406
10uF
25V
OPT

Place Bottom

R411

C407

0.47uF
50V

C408

0.47uF
50V

D401
1N4148W

100V

[PMIC Block]

VLCD_POWER

(+12V)

R451
1/10W

C410
10uF
25V

VL

(+5V)

1uF
25V

L401
10uH

3.1A

R412 0

D402
SMAB34

40V

C413

2.2

1000pF

C411

0.1uF
50V

C412

0.1uF
50V

0

TCOMP

C415

1uF
25V

C414
10uF
25V

VLCD_POWER

R452

0

1/10W

C417

0.1uF
50V

C416

0.01uF
50V

Place Bottom

C418
10uF
25V
OPT

(+12V)

C419

0.1uF
50V

C420
10uF
25V
OPT

EN1

TCOMP

AGND
AVIN

PVINB3

BST3
SWB3
OUT3

PGND3

C422
120pF
50V

C421
10uF
25V

MMBT3906(NXP)

R413
680

1
2

VL

3
4
5
6
7
8
9
10

C424

0.1uF
50V

R414

C425

2200pF

Q400

EBC

C427

0.1uF
50V

[EP]AGND

NC_5

40

THERMAL

11SS12

33K

50V

C423
10uF
25V

PVINB12_2

39

41

MAX17139

13

COMP

PGND_114PGND_2

C426
10uF
25V
OPT

Place Bottom

SWB

IC401

15

SW_116SW_2

C428

4.7uF
50V

NC_435SWB1_136SWB1_237BST138PVINB12_1

34

17

SWI18SWO

C429
10uF
25V
OPT

D403
SMAB34

19

NC_1

C430

4.7uF
50V

40V

LQM2HPN2R2MG0L

PGND232SWB233VLOGIC1

31

30
29
28
27
26
25
24
23
22
21

20

CTRLP

CTRLP

R415 0

1/10W

L402
22uH

2.2A

L403

2.2uH

VLOGIC2
SDA
SCL
A0
RST
NC_3
CTRLN
NC_2
VGL
VGH

R423 33
R424 33

R449 33

VGH_S

(+27V)

C431
10uF
25V

R416
18K
1/10W

VCC_LCM
(+3.3V)

R427 0

1/10W

C432

C435

1uF

22uF

25V

10V

R450 0

C457

C458

10uF

10uF

25V

25V

VCC_LCM
(+3.3V)

I2C_SDA
I2C_SCL

VGL_FB VGL_FB

VCC_LCM
(+3.3V)

R455
10K

R456
10K

OPT

C433

C434

10uF

10uF

25V

25V

VGH_S

(+27V)

R417
18K
1/10W

C438
22uF
10V

VCORE

(+1.0V)

1/10W

R448

10K

Place Bottom

C439
10uF
25V
OPT

C441

0.1uF
50V

TCON_RST

R426 680

C442
10uF
25V
OPT

B

R429 0

1/10W

R430

5.1K

C

Q401
2SC3052

E

VDD_LCM

(+16.8V)

R432

9.1K
1/8W

D404

1N4148W

100V

C444

0.22uF
50V

OPT

C445

0.22uF
50V

OPT

1N4148W

C447

0.22uF
50V

C448

0.22uF
50V

SWB

D405

100V

R435
0

R436
2K
1/8W
1%

C449

0.1uF
50V

OPT

OPT

R437 0

OPT

VCC_LCM
(+3.3V)

C450
10uF
25V

R440 0

C451
10uF
25V

1/10W

VGL

(-5V)

R442

3.6K
1/10W

[GPM Block]

OPT

VGH

(+27V)

VGH_S

(+27V)

R400 15K

1%

C400
56pF
50V

VGH_M

VGH

RE

CE

IC400

KIA3820FK

1

2

3

4

R401 33

R402 33

VCC_LCM

R403

OPT

(+3.3V)

VFLK

8

GND

7

VDPM

6

VDD

5

R404 33

GSC

FLK

VDD_LCM

(+16.8V)

R406

0

1/10W

DPM

R407

OPT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

CTRLP

VCC_LCM
(+3.3V)

VDD_LCM

(+16.8V)

I2C_SDA

R418

10K

R419 0

R420 22

C437
1uF
10V

C436

4.7uF
50V

R425 33

C440

4.7uF
50V

DVDD

VCOM_GND

VCOM_OUT

R433

HVDD

(+8.4V)

I2C_SCL

R428 33

EP[GND]

SDA

1

THERMAL THERMAL

A0

2

21

3

IC402

BUF08630

4

0xEA

5

7

6

AVDD_1

VCOM_FB

AVDD_AVDD

0

C443

0.1uF
50V

C446
1uF
25V

NC_117HVDD18GM719GM820SCL

16

GM6

15

GM5

14

GM4

13

GM3

12

GM2

11

9

10

8

GM1

BKSEL

R431
10K

[P-Gamma Block]

V14

V13

V12

V10

V4

V3

V2

V1

VCC_LCM
(+3.3V)

VDD_LCM

(+16.8V)

I2C_SDA

R441

R438 0

R439 22

R443 33

C453
1uF

10K

10V

C452

C454

4.7uF

4.7uF

50V

50V

LG1121 GP3

T-Con Power/P-Gamma/GPM

DVDD

VCOM_GND

VCOM_OUT

SDA

A0

C455

0.1uF
50V

EP[GND]

1

2

3

4

5

VCOM_FB

I2C_SCL

R444 33

21

IC403

BUF08630

0xE8

7

6

AVDD_1

AVDD_AVDD

8

HVDD

(+8.4V)

9

BKSEL

R445
10K

C456
1uF
25V

NC_117HVDD18GM719GM820SCL

16

GM6

15

GM5

14

GM4

13

GM3

12

GM2

11

10

GM1

R446 0

R447 0

V18

V17

V16

V15

V9

V7

V6

V5

VCOMOUT

VCOMFB

2010. 10. 20

4

7

[FRC-II 51P LVDS input wafer]

P500

FI-RE51S-HFK-A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

R500 33

R502 33

CIS21J121

C500
10uF
25V

VLCD_POWER

L500

RXB4P

RXB4N

RXB3P

RXB3N

RXBCLKP

RXBCLKN

RXB2P

RXB2N

RXB1P

RXB1N

RXB0P

RXB0N

RXA4P

RXA4N

RXA3P

RXA3N

RXACLKP

RXACLKN

RXA2P

RXA2N

RXA1P

RXA1N

RXA0P

RXA0N

I2C_SCL

I2C_SDA

3D_SYNC_Out

(+12V)

RESET

C501
10uF
25V

[FRC-II 80P mini-LVDS output wafer] [To LED Driver]

VDD_LCM

(+16V)

P503

12507WR-08L

9

P504

12507WR-08L

9

M2

MDS62110204

GASKET_5.5T

M4

MDS62110204

GASKET_5.5T

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

P501

104060-8017

81

C502

C503

0.1uF

10uF

50V

25V

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

OPT_P

GOE
GSC

VCOMFB
VCOMOUT

Z_OUT

V1
V2
V3
V4
V5
V6
V7
V9
V10
V12
V13
V14
V15
V16
V17
V18

GSP
POL

SOE
H_CONV
OPT_N

RLV0P
RLV0N
RLV1P
RLV1N
RLV2P
RLV2N

RLVCLKP
RLVCLKN

RLV4P
RLV4N
RLV5P
RLV5N
RLV6P
RLV6N

RRV0P
RRV0N
RRV1P
RRV1N
RRV2P
RRV2N

RRVCLKP
RRVCLKN

RRV4P
RRV4N
RRV5P
RRV5N
RRV6P
RRV6N

C504
10uF
25V

HVDD
(+8V)

VGL

(-5V)

VGH

(+27V)

C505
10uF
25V

C506
10uF
25V

C508
10uF
25V

C507

0.1uF
50V

VCC_LCM
(+3.3V)

C510
10uF
25V

C509

0.01uF
50V

P502

104060-8017

81

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

LLV0P
LLV0N
LLV1P
LLV1N
LLV2P
LLV2N

LLVCLKP
LLVCLKN

LLV4P
LLV4N
LLV5P
LLV5N
LLV6P
LLV6N

LRV0P
LRV0N
LRV1P
LRV1N
LRV2P
LRV2N

LRVCLKP
LRVCLKN

LRV4P
LRV4N
LRV5P
LRV5N
LRV6P
LRV6N

OPT_N
H_CONV
GSP
POL

SOE

V1
V2
V3
V4
V5
V6
V7
V9
V10
V12
V13
V14
V15
V16
V17
V18

Z_OUT

VCOMOUT
VCOMFB

GSC
GOE

C518

0.1uF
50V

VGH

(+27V)

VGL

(-5V)

VCC_LCM

(+3.3V)

HVDD

(+8V)

C519

0.01uF
50V

M1

MDS62110204

GASKET_5.5T

M3

MDS62110204

GASKET_5.5T

R503 33

R506 33

R504

R505 33

SMD Gasket 4.5TSMD Gasket 4.5T

M1-*1

MDS62110208

GASKET_4.5T

M3-*1

MDS62110208

GASKET_4.5T

L/DIM0_SCLK

L/DIM0_MOSI

I2C_SCL

I2C_SDA

L/DIM0_VS

L/DIM1_SCLK

L/DIM1_MOSI

33

I2C_SCL

I2C_SDA

L/DIM1_VS

M2-*1

MDS62110208

GASKET_4.5T

M4-*1

MDS62110208

GASKET_4.5T

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

C511
10uF
25V

C512
10uF
25V

C513
10uF
25V

C514
10uF
25V

C515
10uF
25V

VDD_LCM

C516
10uF
25V

(+16V)

C517

0.1uF
50V

M5

MDS62110204

GASKET_5.5T

M7

MDS62110204

OPT

M6

MDS62110204

GASKET_5.5T

M5-*1

MDS62110208

GASKET_4.5T

M6-*1

MDS62110208

GASKET_4.5T

[LEFT FFC CONNECTOR][RIGHT FFC CONNECTOR]

LG1121 GP3

LVDS/mini-LVDS wafer

2010. 10. 20

5

7

TXA0P
TXA0N
TXA1P
TXA1N
TXA2P

TXA2N
TXACLKP
TXACLKN

TXA3P

TXA3N

TXA4P

TXA4N

TXB0P

TXB0N

TXB1P

TXB1N

TXB2P

TXB2N
TXBCLKP
TXBCLKN

TXB3P

TXB3N

TXB4P

TXB4N

TXC0P

TXC0N

TXC1P

TXC1N

TXC2P

TXC2N
TXCCLKP
TXCCLKN

TXC3P

TXC3N

TXC4P

TXC4N

TXD0P

TXD0N

TXD1P

TXD1N

TXD2P

TXD2N
TXDCLKP
TXDCLKN

TXD3P

TXD3N

TXD4P

TXD4N

TXE0P

TXE0N

TXE1P

TXE1N

TXE2P

TXE2N
TXECLKP
TXECLKN

TXE3P

TXE3N

TXE4P

TXE4N

TXF0P

TXF0N

TXF1P

TXF1N

TXF2P

TXF2N
TXFCLKP
TXFCLKN

TXF3P

TXF3N

TXF4P

TXF4N

TXG0P

TXG0N

TXG1P

TXG1N

TXG2P

TXG2N
TXGCLKP
TXGCLKN

TXG3P

TXG3N

TXG4P

TXG4N

TXH0P

TXH0N

TXH1P

TXH1N

TXH2P

TXH2N
TXHCLKP
TXHCLKN

TXH3P

TXH3N

TXH4P

TXH4N

IC601

LGE5811A

L17

RXA0P

L18

RXA0N

K18

RXA1P

K17

RXA1N

J18

RXA2P

J17

RXA2N

H16

RXACLKP

J16

RXACLKN

H17

RXA3P

H18

RXA3N

G18

RXA4P

G17

RXA4N

F16

RXB0P

G16

RXB0N

F17

RXB1P

F18

RXB1N

E18

RXB2P

E17

RXB2N

D16

RXBCLKP

E16

RXBCLKN

D17

RXB3P

D18

RXB3N

B18

RXB4P

C18

RXB4N

A17

RXC0P

B17

RXC0N

C16

RXC1P

C17

RXC1N

B16

RXC2P

A16

RXC2N

A15

RXCCLKP

B15

RXCCLKN

C14

RXC3P

C15

RXC3N

B14

RXC4P

A14

RXC4N

A13

RXD0P

B13

RXD0N

C12

RXD1P

C13

RXD1N

B12

RXD2P

A12

RXD2N

A11

RXDCLKP

B11

RXDCLKN

C10

RXD3P

C11

RXD3N

B10

RXD4P

A10

RXD4N

A9

RXE0P

B9

RXE0N

C8

RXE1P

C9

RXE1N

B8

RXE2P

A8

RXE2N

A7

RXECLKP

B7

RXECLKN

C6

RXE3P

C7

RXE3N

B6

RXE4P

A6

RXE4N

A5

RXF0P

B5

RXF0N

C4

RXF1P

C5

RXF1N

B4

RXF2P

A4

RXF2N

A3

RXFCLKP

B3

RXFCLKN

C2

RXF3P

C3

RXF3N

B2

RXF4P

A2

RXF4N

C1

RXG0P

B1

RXG0N

D1

RXG1P

D2

RXG1N

E3

RXG2P

D3

RXG2N

E2

RXGCLKP

E1

RXGCLKN

F1

RXG3P

F2

RXG3N

G3

RXG4P

F3

RXG4N

G2

RXH0P

G1

RXH0N

H1

RXH1P

H2

RXH1N

J3

RXH2P

H3

RXH2N

J2

RXHCLKP

J1

RXHCLKN

K2

RXH3P

K1

RXH3N

L1

RXH4P

L2

RXH4N

LLV0P
LLV0N
LLV1P
LLV1N
LLV2P

LLV2N
LLVCLKP
LLVCLKN

LLV3P

LLV3N

LLV4P

LLV4N

LLV5P

LLV5N

LRV0P

LRV0N

LRV1P

LRV1N

LRV2P

LRV2N
LRVCLKP
LRVCLKN

LRV3P

LRV3N

LRV4P

LRV4N

LRV5P

LRV5N

RLV0P

RLV0N

RLV1P

RLV1N

RLV2P

RLV2N
RLVCLKP
RLVCLKN

RLV3P

RLV3N

RLV4P

RLV4N

RLV5P

RLV5N

RRV0P

RRV0N

RRV1P

RRV1N

RRV2P

RRV2N
RRVCLKP
RRVCLKN

RRV3P

RRV3N

RRV4P

RRV4N

RRV5P

RRV5N

H_CONV

OPT_P

OPT_N

EEP_ADDR

LR_IND
AGP_EN

MODE_SEL

RMLVDS

TEMPSEL0
TEMPSEL1
TEMPSEL2

TMODE0
TMODE1
TMODE2
TMODE3

SCL_M

SDA_M

SCL_S

SDA_S

PORES_N

SOE
GSP
GOE
GSC
POL
FLK
DPM

RBF

I2C Slave Address : 0x72

LG5811 will be change LG5811A.
Please use LG5811 unitil revision.

R1
R2
T1
U1
U2
V2
T2
T3
V3
U3
U4
V4
T4
T5

V5
U5
U6
V6
T6
T7
V7
U7
U8
V8
T8
T9
V9
U9

U10
V10
T10
T11
V11
U11
U12
V12
T12
T13
V13
U13
U14
V14

T14
T15
V15
U15
U16
V16
T16
T17
V17
U17
U18
T18
R17
R18

M1

R614 33

M2

R600 33

N1

R601 33

P1

R602 33

N2

R603 33

P2

R604 33

L3

R605 33

M3

R606 33

N3

R607 33

P3

R608 33

K3
R3
K16

R609 33

WP

L16
P17
P18
R9

R615 15K

L4
P4
R4

M16
N16
P16
R16

N18
N17
M18
M17

R15

1%

R610 33
R611 33
R612 33
R613 33

LLV0P
LLV0N
LLV1P
LLV1N
LLV2P
LLV2N
LLVCLKP
LLVCLKN
LLV4P
LLV4N
LLV5P
LLV5N
LLV6P
LLV6N

LRV0P
LRV0N
LRV1P
LRV1N
LRV2P
LRV2N
LRVCLKP
LRVCLKN
LRV4P
LRV4N
LRV5P
LRV5N
LRV6P
LRV6N

RLV0P
RLV0N
RLV1P
RLV1N
RLV2P
RLV2N
RLVCLKP
RLVCLKN
RLV4P
RLV4N
RLV5P
RLV5N
RLV6P
RLV6N

RRV0P
RRV0N
RRV1P
RRV1N
RRV2P
RRV2N
RRVCLKP
RRVCLKN
RRV4P
RRV4N
RRV5P
RRV5N
RRV6P
RRV6N

SOE
GSP
GOE
GSC
POL
FLK
DPM
H_CONV
OPT_P
OPT_N

RBF

<- EEPROM Address = 0xA6

WP_EEPROM_TCON
LR_IND
AGP_EN
MODE_SEL

TCON_SCL
TCON_SDA
I2C_SCL
I2C_SDA

TCON_RST

SW600

JTP-1127WEM

1. RBF

- Pattern selection of No Video input
LOW : Rolling Pattern
HIGH : Black Pattern

2. LR_IND

- Left/Right frame Indicator
LOW : Left
HIGH : Right

3. AGP_EN

- NO input indicator
LOW : Normal
HIGH : No input

4. MODE_SEL

- 2D/3D mode selection
LOW : 2D mode
HIGH : 3D mode

R617
10K

+3.3VDD

+1.0VDD

+3.3AVDD_RX

+3.3AVDD_TX

[T-Con EEPROM[64KBIT)]

R618
10K

AT24C64D-SSHM-T

A0

A1

A2

GND

I2C Slave Address : 0xA6

- Write Protection
HIGH : Write Protection
LOW or NC : Normal Operation

F14

G5

G14

H5

H14

J5

J14

K5

K14

L5

L14

M5

M14

N5

F5
G7
G8

G9
G10
G11
G12

H7
H12

J7
J12

K7
K12

L7
L12

M7

M8

M9
M10
M11
M12

D6

D7

D8

D9
D10
D11
D12
D13
D14

R5

R6

R7

R8
R10
R11
R12
R13
R14

IC600

1

2

3

4

VDD_33_1
VDD_33_2
VDD_33_3
VDD_33_4
VDD_33_5
VDD_33_6
VDD_33_7
VDD_33_8
VDD_33_9
VDD_33_10
VDD_33_11
VDD_33_12
VDD_33_13
VDD_33_14

VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4
VDD_10_5
VDD_10_6
VDD_10_7
VDD_10_8
VDD_10_9
VDD_10_10
VDD_10_11
VDD_10_12
VDD_10_13
VDD_10_14
VDD_10_15
VDD_10_16
VDD_10_17
VDD_10_18
VDD_10_19
VDD_10_20
VDD_10_21

RX_AVDD33_1
RX_AVDD33_2
RX_AVDD33_3
RX_AVDD33_4
RX_AVDD33_5
RX_AVDD33_6
RX_AVDD33_7
RX_AVDD33_8
RX_AVDD33_9

TX_AVDD33_1
TX_AVDD33_2
TX_AVDD33_3
TX_AVDD33_4
TX_AVDD33_5
TX_AVDD33_6
TX_AVDD33_7
TX_AVDD33_8
TX_AVDD33_9

VCC

8

WP

7

SCL

6

SDA

5

LGE5811A

C600

0.1uF
16V

IC601

VCC_LCM
(+3.3V)

R619

10K

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58

D4
D5
D15
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
F4
F15
G4
G15
H4
H8
H9
H10
H11
H15
J4
J8
J9
J10
J11
J15
K4
K8
K9
K10
K11
K15
L8
L9
L10
L11
L15
M4
M15
N4
N14
N15
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

+3.3VDD Decaps

VCC_LCM
(+3.3V)

C601

0.1uF
16V

L600

CIS21J121

+3.3VDD

+1.0VDD Decaps

VCORE

(+1.0V)

C602

0.1uF
16V

L601

CIS21J121

+1.0VDD

+3.3AVDD_RX Decaps

VCC_LCM
(+3.3V)

C603

0.1uF
16V

L602

CIS21J121

+3.3AVDD_RX

+3.3AVDD_TX Decaps

VCC_LCM
(+3.3V)

L603

CIS21J121

C604

0.1uF
16V

C605

0.1uF
16V

C606

0.1uF
16V

C607

0.1uF
16V

C608

0.1uF
16V

+3.3VDD

C609

0.1uF
16V

+1.0VDD

C659

0.1uF
16V

+3.3AVDD_RX

C611

0.1uF
16V

+3.3AVDD_TX+3.3AVDD_TX

C612

0.1uF
16V

C633

0.1uF
16V

C660

0.1uF
16V

C627

0.1uF
16V

C632

0.1uF
16V

C651

0.1uF
16V

C661

0.1uF
16V

C643

0.1uF
16V

C680
1uF
25V

C676

0.22uF

6.3V

C681
1uF
25V

C682
1uF
25V

C677

0.22uF

6.3V

+3.3VDD

+1.0VDD

+3.3AVDD_TX

C670

1uF

6.3V

C672

1uF

6.3V

C678

1uF

6.3V

C671
1uF

6.3V

C673
1uF

6.3V

C679
1uF

6.3V

C674

1uF

6.3V

C675

1uF

6.3V

[T-Con EEPROM Debug]

P600

12507WR-03L

R620
2K

R621
2K

WP_EEPROM_TCON

TCON_SCL

TCON_SDA

1

2

3

4

TCON_SDA

TCON_SCL

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

LG1121 GP3

XTR T-Con block 6

2010. 10. 20

7

+3.3V_LG1131_LVDS_Rx

+3.3VD

RXB4P
RXB4N
RXB3P

RXB3N
RXBCLKP
RXBCLKN

RXB2P

RXB2N

RXB1P

RXB1N

RXB0P

RXB0N

RXA4P

RXA4N

RXA3P

RXA3N
RXACLKP
RXACLKN

RXA2P

RXA2N

RXA1P

RXA1N

RXA0P

RXA0N

C729

0.1uF
16V

L702

CIS21J121

C726
10uF
25V

+3.3V_LG1131_Rx

R700
100

1%

R701
100

1%

C731
1uF
25V

R702
100

1%

R703
100

1%

C703

0.1uF
16V

R704
100

1%

R705
100

1%

C705

0.1uF
16V

R706
100

1%

R707
100

1%

C701

0.1uF
16V

R708
100

1%

R709
100

1%

+3.3V_LG1131_Rx +1.0V_LG1131

R710
100

1%

R711
100

1%

VDD10_1

RXB4P
RXB4N
RXB3P

RXB3N
RXBCLKP
RXBCLKN

RXB2P

RXB2N

RXB1P

RXB1N

RXB0P

RXB0N

AVDD33_1

GND_1

RXA4P

RXA4N

RXA3P

RXA3N
RXACLKP
RXACLKN

RXA2P

RXA2N

RXA1P

RXA1N

RXA0P

RXA0N

AVDD33_6

[EP]

109

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

I2C_SDA

I2C_SCL

GND_19

107

108

THERMAL

VDD10_11

GND_18

VDD10_12

104

105

106

RESET_LG1131

R712 33

SCL

RESET

102

103

R713 33

SDA

101

VDD10_10

T_DOUT6

99

100

+3.3V_LG1131_VDD

VDD33_4

GND_17

98

IC700

LG1131A

I2C Slave Address : 0x8E

28

29

31

33

34

35

38

t_dout(4) : rst_pix2_n

R716
0

VDD33_3

GND_16

VDD10_9

TEST1

TEST2

T_DOUT4

T_DOUT5

90

91

92

93

94

95

96

97

39

40

41

44

45

EXTCLK_IN

TEST0

88

89

47

48

T_ENB

+3.3V_LG1131_TX

AVDD33_5

GND_14

VDD10_8

GND_15

83

84

85

86

87

49

50

51

52

53

AVDD33_4

82

81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

GND_13
TXB4P
TXB4N
TXB3P
TXB3N
TXBCLKP
TXBCLKN
TXB2P
TXB2N
TXB1P
TXB1N
TXB0P
TXB0N
GND_12
AVDD33_3
TXA4P
TXA4N
TXA3P
TXA3N
TXACLKP
TXACLKN
TXA2P
TXA2N
TXA1P
TXA1N
TXA0P
TXA0N

TXB4P_2D3D
TXB4N_2D3D
TXB3P_2D3D
TXB3N_2D3D
TXBCLKP_2D3D
TXBCLKN_2D3D
TXB2P_2D3D
TXB2N_2D3D
TXB1P_2D3D
TXB1N_2D3D
TXB0P_2D3D
TXB0N_2D3D

TXA4P_2D3D
TXA4N_2D3D
TXA3P_2D3D
TXA3N_2D3D
TXACLKP_2D3D
TXACLKN_2D3D
TXA2P_2D3D
TXA2N_2D3D
TXA1P_2D3D
TXA1N_2D3D
TXA0P_2D3D
TXA0N_2D3D

RESET

R714 1K

+3.3VD

SW700

JTP-1127WEM

R715
10K

RESET_LG1131

RESET_LG1131

GND_230GND_3

AVDD33_2

+3.3V_LG1131_VDD

GND_4

VDD33_132VDD10_2

T_DIN036T_DIN137T_DIN2

VDD10_3

t_dout(0) : PLL CLOCK OUTPUT(1x)

GND_5

VDD10_4

R717

0

T_DIN3

GND_6

T_DOUT042T_DOUT143VDD10_5

T_DOUT246VDD33_2

R718
0

GND_7

+3.3V_LG1131_LVDS_Tx +3.3V_LG1131_VDD

+3.3VD +3.3V_LG1131_TX

L703

CIS21J121

C730

0.1uF
16V

C728
10uF
25V

C732
1uF
25V

C710

0.1uF
16V

C712

0.1uF
16V

C708

0.1uF
16V

+3.3VD

C714

0.1uF
16V

+3.3V_LG1131_VDD

L701

CIS21J121

C727
10uF
25V

C733
1uF
25V

C718

0.1uF
16V

C720

0.1uF
16V

C722

0.1uF
16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

GND_8

GND_9

VDD10_6

C725

0.1uF
16V

GND_1054GND_11

VDD10_7

T_DOUT3

t_dout(2) : VCO CLOCK OUTPUT

+1.0V_LG1131 Decaps

+1.0V_LG1131

C700

C702

0.1uF
16V

C704

0.1uF
16V

0.1uF
16V

C707

0.1uF
16V

C709

0.1uF
16V

CIS21J121

C706

0.1uF
16V

C711

0.1uF
16V

L700

+1.0V_LG1131+1.0V_2D3D

C715

0.1uF
16V

C713

0.1uF
16V

C717

0.1uF
16V

2010. 10. 4LG1121 GP3

C719

0.1uF
16V

C721

0.1uF
16V

C723

0.1uF
16V

C724

0.1uF
16V

772D to 3D block(LG1131)

NAND FLASH MEMORY 8Gbit

+3.3V_Normal

NC_1

1

NC_2

2

NC_3

3

NC_4

4

NC_5

5

NC_6

6

RY/BY

7

RE

8

CE

9

NC_7

10

NC_8

11

VCC_1

12

VSS_1

13

NC_9

14

NC_10

15

CLE

16

ALE

17

WE

18

WP

19

NC_11

20

NC_12

21

NC_13

22

NC_14

23

NC_15

24

LGE35230(BCM35230KFSBG)

B5
C5

A4
B4

A3
B3

A2
B2

W2

V4
W4

V3
V2

D13

E6

R106
3K

IC101

NON_BCM_CAP

HDMI0_CLKN
HDMI0_CLKP

HDMI0_D0N
HDMI0_D0P

HDMI0_D1N
HDMI0_D1P

HDMI0_D2N
HDMI0_D2P

CEC

DDC0_SCL
DDC0_SDA

HDMI0_HTPLG_IN
HDMI0_HTPLG_OUT

HDMI0_ARC
HDMI0_RESREF

LT0VCAL_MONITOR

NAND_RBb

NAND_REb

NAND_CEb

NAND_CEb2

NAND_CLE

NAND_ALE

R101

4.7K

FLASH_WP

R105

4.7K

NAND_WEb

R104

4.7K

R195

4.7K

Write Protection

- High : Normal Operation

- Low : Write Protection

+3.3V_Normal

R107 2.7K

R148

+3.3V_Normal

R103

4.7K

HDMI_CLK­HDMI_CLK+

HDMI_RX0­HDMI_RX0+

HDMI_RX1­HDMI_RX1+

HDMI_RX2­HDMI_RX2+

HDMI_ARC

16Gbit

R149 0

16Gbit

0

C102
4700pF

C101

0.1uF

OPT

IC102

TC58DVG3S0ETA00

NAND_8Gbit

TXOUT0_L0N
TXOUT0_L0P
TXOUT0_L1N
TXOUT0_L1P
TXOUT0_L2N
TXOUT0_L2P

TXCLK_LN

TXCLK_LP
TXOUT0_L3N
TXOUT0_L3P
TXOUT0_L4N
TXOUT0_L4P

TXOUT0_U0N
TXOUT0_U0P
TXOUT0_U1N
TXOUT0_U1P
TXOUT0_U2N
TXOUT0_U2P

TXCLK_UN

TXCLK_UP
TXOUT0_U3N
TXOUT0_U3P
TXOUT0_U4N
TXOUT0_U4P

TXOUT1_L0N
TXOUT1_L0P
TXOUT1_L1N
TXOUT1_L1P
TXOUT1_L2N
TXOUT1_L2P

TXCLK1_LN

TXCLK1_LP
TXOUT1_L3N
TXOUT1_L3P
TXOUT1_L4N
TXOUT1_L4P

TXOUT1_U0N
TXOUT1_U0P
TXOUT1_U1N
TXOUT1_U1P
TXOUT1_U2N
TXOUT1_U2P

TXCLK1_UN

TXCLK1_UP
TXOUT1_U3N
TXOUT1_U3P
TXOUT1_U4N
TXOUT1_U4P

GPIO_BL_ON

BL_PWM/GPIO

AE27
AE28
AF27
AF28
AG27
AG28
AE26
AF26
AH27
AG26
AF25
AE25

AH26
AG25
AE24
AD24
AH25
AF24
AE23
AD23
AG24
AF23
AC22
AD22

AG23
AH23
AE22
AE21
AF22
AH22
AG22
AF21
AG21
AF20
AD21
AC21

AG20
AH20
AD19
AE19
AF19
AH19
AE18
AD18
AG19
AF18
AG18
AF17

AC18
AH16
AG16

16Gbit

IC102-*1

TH58DVG4S0ETA20

SDA0_3.3V
SCL0_3.3V

SCL2_3.3V
SDA2_3.3V

R199 22
R197 22

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

NC_26

NC_25

NC_24

NC_23

I/O8

I/O7

I/O6

I/O5

NC_22

PSL

NC_21

VCC_2

VSS_2

NC_20

NC_19

NC_18

I/O4

I/O3

I/O2

I/O1

NC_17

NC_16

NC_15

NC_14

+3.3V_Normal

NC_1

1

NC_28

48

NC_27

47

NC_26

46

NC_25

45

I/O8

44

NAND_DATA[7]

I/O7

43

NAND_DATA[6]

I/O6

42

NAND_DATA[5]

I/O5

41

NAND_DATA[4]

NC_24

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

PSL

NC_23

VCC_2

VSS_2

NC_22

NC_21

NC_20

I/O4

I/O3

I/O2

I/O1

NC_19

NC_18

NC_17

NC_16

16Gbit

R151

+3.3V_Normal

C104 10uF

NAND_DATA[3]

NAND_DATA[2]

NAND_DATA[1]

NAND_DATA[0]

TXB4P
TXB4N
TXB3P
TXB3N
TXBCLKP
TXBCLKN
TXB2P
TXB2N
TXB1P
TXB1N
TXB0P
TXB0N

TXA4P
TXA4N
TXA3P
TXA3N
TXACLKP
TXACLKN
TXA2P
TXA2N
TXA1P
TXA1N
TXA0P
TXA0N

TXD4P
TXD4N
TXD3P
TXD3N
TXDCLKP
TXDCLKN
TXD2P
TXD2N
TXD1P
TXD1N
TXD0P
TXD0N

TXC4P
TXC4N
TXC3P
TXC3N
TXCCLKP
TXCCLKN
TXC2P
TXC2N
TXC1P
TXC1N
TXC0P
TXC0N

+3.3V_Normal

0

C103

0.1uF

10V

R194

2.7K

R108 10K

NAND_DATA[0-7]

RGB_DDC_SDA

RGB_DDC_SCL

BBS CONNECT

P101

TJC2508-4A

1

2

3

4

C105

2.2uF
10V

Q101
BSS83

Q102
BSS83

+3.3V_Normal

VCC

SCL

SDA

GND

A_DIM

RY/BY2

RY/BY1

VCC_1

VSS_1

NC_10

NC_11

NC_12

NC_13

NC_2

NC_3

NC_4

NC_5

NC_6

NC_7

NC_8

NC_9

SBD

G

SBD

G

CE1

CE2

CLE

ALE

RE

WE

WP

C106

4.7uF

DEV_NAND_16Gbit

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

+3.3V_Normal

R196
10K

C118

0.1uF
16V

+3.3V_Normal

R198
10K

C119

0.1uF
16V

R110

R109

1.5K

1.5K

DVB_S Option: apply EU Satellite model

FOR HDMI STANDARD
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO

Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)

+3.3V_Normal

OPT

R113
10K

R114
10K

R117
10K
OPT

R118
10K

R122
10K

R123
10K

OPT

R127
10K
OPT

R128
10K

CI_ADDR[4]
NAND_DATA[7]
NAND_DATA[2]
NAND_DATA[1]

NAND ECC (FA3, FA2, FALE)

+3.3V_Normal

R119

R115

R111
10K

OPT

R112
10K

10K

R116
10K

OPT

10K
OPT

R120
10K

CI_ADDR[3]
CI_ADDR[2]
NAND_ALE

DUAL COMPONENT

IC102 1ST : EAN61000101 2ND : T-TH58DVG4S0ETA20

IC102-*1

LGE35230(BCM35230KFSBG)

AG6

TVM_XTALIN

AF6

TVM_XTALOUT

V5

IRRXDA

AB4

FP_IN0

Y4

FP_IN1

AA4

SPARE_ADC1

Y5

SPARE_ADC2

AB2

FS_IN1

AB5

FS_IN2

U3

VGA_SDA

U2

VGA_SCL

Y2

RDA

Y1

TDA

33

AA3

BSCDATAA

AA2

BSCCLKA

H3

RDB/GPIO

H2

TDB/GPIO

H4

BSC_S_SCL

H5

BSC_S_SDA

F25

NMIB

W5

POWER_CTRL

U5

AON_HSYNC

U4

AON_VSYNC

W3

AON_GPIO_36

W1

AON_GPIO_37

AB6

AON_RESETOUTB

Y6

TVM_BYPASS

Y3

RESETB

G24

RESETOUTB

J6

TMODE

W6

TESTEN

F7

VDAC_VREG

E7

VDAC_RBIAS

BCM REFRENCE is 562ohm

R121

1.2K

C107
33pF
50V

DVB_S

+3.3V_Normal

+3.3V_Normal

R124
1K

OPT

R125
1K

R126

1.2K

C108
33pF
50V

DVB_S

R129

1.2K

C109
33pF
50V

5V_HDMI_3

R130

OPT

2K

R132 4.7K

+3.3V_Normal

C111 0.01uF
C112 0.1uF

54MHz_XTAL_P

54MHz_XTAL_N

R131

1.2K

C110
33pF
50V

PCM_5V_CTL

5V_HDMI_1

5V_HDMI_2

5V_HDMI_4

SOC_RESET

LNB_INT

SC_ID

BCM_RX
BCM_TX

R135
R136 33

+3.3V_Normal

R141 4.7K

R142 22
R143 22

R144 22
R145 22

R139 0

SRST

R140
560
1%

OPT

OPT
OPT

OPT

0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
0111: 3B dual IO Serial Flash
1001: BB dual IO Serial Flash
1011: fast Serail Flash > 50Mhz
1100: OneNAND Flash (always 16-bit)
1110: Reserved
1101, 1111: Reserved

000 = ECC disabled
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
011 = ECC 8-bit BCH, 27 byte spare
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
110, 111 = Reservedd

IC101

NON_BCM_CAP

AVS_NDRIVE_1
AVS_PDRIVE_1

FAD_7
FAD_6
FAD_5
FAD_4
FAD_3
FAD_2
FAD_1
FAD_0

FALE
FCEB_0
FCEB_1
FCEB_2
FCEB_3

NFWPB

FRDYB

FA_0

FA_1

FA_2

FA_3

FA_4

FA_5

FA_6

FA_7

FA_8

FA_9

FA_10
FA_11
FA_12
FA_13
FA_14
FA_15

TRSTB

TDI/GPIO

TMS/GPIO
TCK/GPIO

DINT/GPIO

AVS_VFB
AVS_VSENSE
AVS_RESETB

VDAC_1
VDAC_2

AB1

NAND_DATA[7]

AB3

NAND_DATA[6]

AC1

NAND_DATA[5]

AC2

NAND_DATA[4]

AC3

NAND_DATA[3]

AD2

NAND_DATA[2]

AD3

NAND_DATA[1]

AE2

NAND_DATA[0]

AG1
AF1
AC5
AE6
AG5

AF3
AG2

FWE

AE3

FRD

AA5

AF2
AE1
AC4
AD5
AD4
AE4
AE5
AD6
AH3
AF4
AH4
AG4
AF5
AG3
AH2
AH5

AD15
AF14
AH14

TDO

AD14
AG14
AC16

AH7
AG7
AD7
AF7
AH8

C6
D7

NAND_ALE
NAND_CEb
NAND_CEb2
/CI_CE1
/CI_CE2

FLASH_WP
NAND_WEb
NAND_REb
/PCM_WAIT

NAND_CLE
NAND_RBb

CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]

CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[14]

R146 10K

NAND_DATA[0-7]

R147
1K

DTV/MNT_V_OUT

Strap Setting

CI_ADDR[2-14]

+3.3V_Normal

R156

R153

R150
1K

1K

1K

SRST

+3.3V_Normal

R166
1K

R157
10K

OPT

R158
10K

R160
10K

OPT

R161
10K

R164
10K

OPT

R165
10K

R154
10K

OPT

R155
10K

NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian

CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash

NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.

CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz

NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed

NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)

R162

R159

1K

1K

R163
1K

R167
10K

OPT

R168
10K

R175
10K

OPT

R176
10K

R177
10K

R178
10K

OPT

R170
10K

R171
10K

OPT

CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved

CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)

NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM

NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE

R179
10K

OPT

R180
10K

R181
10K

OPT

R182
10K

R183
10K

R184
10K

OPT

R187
10K

OPT

R188
10K

NVRAM

+3.3V_Normal

R169
0

R173

R172

4.7K

4.7K

OPT

R174

4.7K

BCM_NVM_1M

IC103

M24M01-HRMN6TP

OPT

NC

1

E1

2

A8’h

E2

3

VSS

4

+3.3V_Normal

VCC

8

WP

7

SCL

6

SDA

5

R190 33

R191 33

54MHz X-TAL

C113
12pF

50V

3

X-TAL_2

4

GND_2

54MHz

X101

CRYSTAL_BCM_Sunny

C114
12pF

EAW58812611

50V

SUNNY ELECTRONICS CORPORATION

2

1

GND_1

X-TAL_1

R185 0

R186 0

R189
1M
OPT

54MHz_XTAL_N

54MHz_XTAL_P

R192
10K

OPT

NAND_DATA[0]
CI_ADDR[7]
NAND_DATA[6]
CI_ADDR[6]
NAND_CLE
NAND_DATA[4]
CI_ADDR[9]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[8]
NAND_DATA[3]
NAND_DATA[5]

R193
10K

BCM_NVM_256K

IC103-*1

AT24C256C-SSHL-T

A0

1

A1

2

A2

3

GND

4

Write Protection

- Low : Normal Operation

- High : Write Protection

X101-*2

54MHz

X-TAL_1

1

GND_1

2

CRYSTAL_BCM_KDS

EAW58239604

DAISHINKU CORPORATION.

X101-*1

54MHz

X-TAL_1

1

GND_1

2

CRYSTAL_BCM_Lihom

EAW60763703

LIHOM CO., LTD.

VCC

8

WP

7

SCL

6

SDA

5

SCL3_3.3V

SDA3_3.3V

GND_2

4

X-TAL_2

3

GND_2

4

X-TAL_2

3

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BCM35230

MAIN & NAND FLASH

2010.09.18

1

+3.3V_Normal

FHD

R252

1K

HD

R262

1K

FE_TS_DATA[0-7]

OLED

LCD

BCM
internal
FRC

00 11

1 100

HIGH

Support

CHBO_TS_CLK

CHBO_TS_SERIAL

CHBO_TS_SYNC

CHBO_TS_VAL_ERR

R251

1K

1K

1K

BCM_FRC/URSA5

R261

1K

NO_FRC/FRC2

R250

FRC2/URSA5

R260

NO_FRC/BCM_FRC

MODEL OPTION

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3

MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6

MODEL_OPT_7 Enable Disable

NO_FRC

DDR speed

T2 Tuner

S Tuner

PHM

R253

R263

1K

1K

R254

1K

OPT

R264

1K

LG FRC2

LOW

HDFHD

LCDOLED

16001333

Not Support

Not SupportSupport

R255

1K

T2_TUNER

R265

1K

NO_T2_TUNER

external
URSA5

SIDE_USB_OCD1

SIDE_USB_OCD2

PCM_TS_DATA[0-7]

R201 0

F/NIM_EU_CN

PCM_MDI[0-7]

OPT

R202

0

R256

1K

S_TUNER

R266

1K

NO_S_TUNNER

+3.3V_Normal

R286
10K

WIFI

TU_TS_CLK

FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]

PHM

NO_PHM

R287
10K

WIFI

R257

1K

R267

1K

R203 0
R204 0
R205 0
R206 0

R207 0
R208 0
R209 0

C201
100pF

OPT

F/NIM_EU_CN
F/NIM_EU_CN

F/NIM_EU_CN

PCM_MDI[0]
PCM_MDI[1]
PCM_MDI[2]
PCM_MDI[3]
PCM_MDI[4]
PCM_MDI[5]
PCM_MDI[6]
PCM_MDI[7]

R211

6.04K
EPHY_TDP

EPHY_TDN
EPHY_RDP
EPHY_RDN

R210

4.87K
1%

SIDE_USB_DM
SIDE_USB_DP

SIDE_USB_CTL1

WIFI_DM
WIFI_DP

SIDE_USB_CTL2

PCM_TS_CLK

PCM_TS_DATA[0]
PCM_TS_DATA[1]
PCM_TS_DATA[2]
PCM_TS_DATA[3]
PCM_TS_DATA[4]
PCM_TS_DATA[5]
PCM_TS_DATA[6]
PCM_TS_DATA[7]

PCM_TS_SYNC

PCM_TS_VAL

F/NIM_EU_CN

F/NIM_EU_CN
F/NIM_EU_CN
F/NIM_EU_CN

TU_TS_SYNC
TS_VAL_ERR

PCM_MCLKI

PCM_MISTRT

PCM_MIVAL_ERR

/PCM_IRQA

MODEL_OPT_0

MODEL_OPT_1

MODEL_OPT_2

MODEL_OPT_3
MODEL_OPT_4

MODEL_OPT_5

MODEL_OPT_6
MODEL_OPT_7

LGE35230(BCM35230KFSBG)

F26
D26

F27
F28
E27
E26

F5
E5

C2
D1

E1
D2

B1
C1

C3
C4

M4
L5
M5
L6
N3
N1
N2
M3
M2
L4
N4

K6
J4
K5
J2
J3
K2
K1
K3
L1
L3
L2

P4
T2
R3
R2
P3
P2
P1
R6
N5
T4
P5

R4
U1
T3
T1
T5

IC101

NON_BCM_CAP
EPHY_VREF
EPHY_RDAC

EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN

USB_MONCDR
USB_RREF

USB_PORT1DN
USB_PORT1DP

USB_PWRFLT_1/GPIO
USB_PWRON_1/GPIO

USB_PORT2DN
USB_PORT2DP

USB_PWRFLT_2/GPIO
USB_PWRON_2/GPIO

TCLKA/GPIO
TDATA_0/GPIO
TDATA_1/GPIO
TDATA_2/GPIO
TDATA_3/GPIO
TDATA_4/GPIO
TDATA_5/GPIO
TDATA_6/GPIO
TDATA_7/GPIO
TSTRTA/GPIO
TVLDA/GPIO

TCLKD/GPIO
TDATD_0/GPIO
TDATD_1/GPIO
TDATD_2/GPIO
TDATD_3/GPIO
TDATD_4/GPIO
TDATD_5/GPIO
TDATD_6/GPIO
TDATD_7/GPIO
TSTRTD/GPIO
TVLDD/GPIO

MPEG_CLK/GPIO
MPEG_D_0/GPIO
MPEG_D_1/GPIO
MPEG_D_2/GPIO
MPEG_D_3/GPIO
MPEG_D_4/GPIO
MPEG_D_5/GPIO
MPEG_D_6/GPIO
MPEG_D_7/GPIO
MPEG_SYNC/GPIO
MPEG_DATA_EN/GPIO

MCIF_RESET/GPIO
MCIF_SCLK/GPIO
MCIF_SCTL/GPIO
MCIF_SDI/GPIO
MCIF_SDO/GPIO

PCI_DEVSELB/GPIO

PCI_FRAMEB/GPIO

C225

0.22uF

6.3V

VI_IFP0
VI_IFM0

VDDR_AGC

AGC_SDM_2
AGC_SDM_1

GPIO_0
GPIO_1
GPIO_2
GPIO_3

PCI_VIO_0
PCI_VIO_1
PCI_VIO_2

GPIO_4
GPIO_5
GPIO_6

GPIO_7
GPIO_70
GPIO_71
GPIO_72
GPIO_73
GPIO_74
GPIO_75
GPIO_76
GPIO_77
GPIO_78
GPIO_79

PCI_AD05
PCI_AD06
PCI_AD07

PCI_AD08
PCI_AD09/GPIO
PCI_AD10/GPIO
PCI_AD11/GPIO
PCI_AD12/GPIO
PCI_AD13/GPIO
PCI_AD14/GPIO
PCI_AD15/GPIO
PCI_AD16/GPIO
PCI_AD17/GPIO
PCI_AD18/GPIO
PCI_AD19/GPIO
PCI_AD20/GPIO
PCI_AD21/GPIO

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_CBE00
PCI_CBE01/GPIO
PCI_CBE02/GPIO

PCI_CBE03

PCI_IRDYB/GPIO

PCI_PAR/GPIO

PCI_PERRB/GPIO

PCI_REQ1B
PCI_SERRB/GPIO
PCI_STOPB/GPIO
PCI_TRDYB/GPIO

+0.9V_CORE

C221

0.1uF

C17
B17
D15

B16
A16

A15
C16
G28
G26

W14
W15
W13

J5
R5
V6
H6
AE15
AF15
AG15
AF16
AD16
AE16
AG17
AH17
AE17
AD17

AB13
AC15
AB12
AB11
AE14
AG13
AH13
AF13
AE13
AD12
AF12
AG10
AF10
AE10
AD10
AE9
AE8
AC10
AC11
AC8
AB8

AC14
AG12
AH10
AB7

AG11
AD11
AE11
AD13
AE12
AC12
AC13
AH11
AF11

C223

0.01uF

C203
10uF
10V

Non_CHB

R212
1K

closed to soc

R213 2K

+3.3V_Normal

R280
22

R214 22

R215 22
R281 22
R282 22

R216 22

R218 22

R220 22

R221 22

R222 22

R283
22

R223 22

R284 22

R224 22

R235

R225 0

R226 22

R285 22

R227 22

C207

C205

4.7uF

10uF

10V

10V

close to soc

C217

16V

100

0.1uF
R241

C218

100

0.1uF
R242

16V

C216 0.01uF

M_REMOTE_RX

CI_DET
M_RFModule_RESET
EPHY_ACTIVITY
EPHY_LINK

DTV_ATV_SELECT
RF_SWITCH_CTL_2

INSTANT_MODE

BCM_L/DIM
BCM_L/DIM

100

OPT

NFM18PS105R0J

C233

6.3V

OUTIN

GND

C232

4.7uF
10V

C209

4.7uF
10V

IF_P

IF_N

IF_AGC

3D_SYNC

MODEL_OPT_0

MODEL_OPT_1
MODEL_OPT_2
MODEL_OPT_3

SC_DET/COMP2_DET

CHB_RESET

TW9910_RESET

AV2_CVBS_DET
RF_BOOSTER_CTL
DSUB_DET
PCM_RST

MODEL_OPT_4
DC_MREMOTE
DD_MREMOTE

L/DIM0_MOSI
L/DIM0_SCLK

COMP1_DET

MODEL_OPT_5

3D_GPIO_0
MODEL_OPT_6
MODEL_OPT_7

ERROR_OUT

RF_SWITCH_CTL

3D_GPIO_1

3D_GPIO_2

NFM18PS105R0J

C234

0.1uF

C211

0.1uF

+3.3V_Normal

+3.3V_Normal

R228 22
R230 22

BCM_L/DIM

R231 100

C204

6.3V

GND

C236

0.1uF

C213

0.1uF

BLM18PG121SN1D

0.1uF

R240

2.7K

R231-*1 0

FRC2_RESET

URSA_RESET

OUTIN

NFM18PS105R0J

C238

4.7uF
10V

C215

0.01uF

L201

C229

NON_NTP

PWM_DIM
L/DIM0_VS

+3.3V_Normal

4.7K

C244

6.3V

GND

C220

0.1uF

+3.3V_Normal

4.7K

R232

URSA_RESET

+0.9V_CORE

+3.3V_Normal

OUTIN

+1.5V_DDR

C222

0.01uF

R233

1.2K

C227
33pF
50V

R232-*1

FRC2_RESET

R234

1.2K

C231
33pF
50V

C247
22uF

C248
10uF

10V

NON_NTP

FRC_RESET

SDA1_3.3V
SCL1_3.3V

POWER 2.5V

+2.5V_BCM35230

+2.5V_BCM35230

Place Cap

Very close to R22 Ball

L202

BLM18PG121SN1D

C249
10uF
10V

L203

BLM18PG121SN1D

C251

0.1uF
16V

+2.5V_BCM35230

BLM18PG121SN1D

C250

4.7uF
10V

+1.5V_DDR

Place Cap
Very close to R22 Ball

C242

0.1uF

+3.3V_Normal

C253
10uF
10V

EPHY_VDD25

C252

4.7uF
10V

VAFE3_VDD25

L204

C254

4.7uF

MLG1005S22NJT

C224

L220

1uF
25V

OPT

+0.9V_CORE

AADC_AVDD25

C256

0.1uF

C255

0.1uF

C257

0.1uF

+0.9V_CORE

C226

0.1uF
16V
OPT

+3.3V_Normal

+2.5V_BCM35230

L205

BLM18PG121SN1D

C258

0.1uF

+2.5V_BCM35230

C260

C259

4.7uF

10uF
10V

+2.5V_BCM35230

+2.5V_BCM35230

NON_BCM_CAP

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42

POR_VDD

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12

DDR_LDO_VDDO

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
VDDR3_9
VDDR3_10
VDDR3_11

AON_VDDC_1
AON_VDDC_2
AON_POR_VDD

AON_VDDR3

AON_VDDR10_1
AON_VDDR10_2

IC101

LGE35230(BCM35230KFSBG)

V12

V7
M10
N10
P10
R10
T10
U10
V10
W10
V13
L11
M11
N11
P11
R11
T11
U11
V11
W11
V14
L18
M18
N18
P18
R18
T18
U18
V18
W18
V15
L19
M19
N19
P19
R19
T19
U19
V19
W19
V16
V17

L10

L22

AA28

V28
R28
M28
J28
K23
M22
T22
T23
U22
Y22

R22

G15
H22
G23
AB9

K7

AB15

L7

AB14

M7

N6

P6

AA6
AA7

Y7

U7

T7

T6

C261
10uF
10V

C262
10uF

L206

BLM18PG121SN1D

L207

BLM18PG121SN1D

K10

VSS_1

K11

VSS_2

K12

VSS_3

L12

VSS_4

M12

VSS_5

N12

VSS_6

P12

VSS_7

R12

VSS_8

T12

VSS_9

U12

VSS_10

W12

VSS_11

K13

VSS_12

L13

VSS_13

M13

VSS_14

N13

VSS_15

P13

VSS_16

R13

VSS_17

T13

VSS_18

U13

VSS_19

W16

VSS_20

K14

VSS_21

L14

VSS_22

M14

VSS_23

N14

VSS_24

P14

VSS_25

R14

VSS_26

T14

VSS_27

U14

VSS_28

K15

VSS_29

L15

VSS_30

M15

VSS_31

N15

VSS_32

P15

VSS_33

R15

VSS_34

T15

VSS_35

U15

VSS_36

K16

VSS_37

L16

VSS_38

M16

VSS_39

N16

VSS_40

P16

VSS_41

R16

VSS_42

T16

VSS_43

U16

VSS_44

K17

VSS_45

L17

VSS_46

M17

VSS_47

N17

VSS_48

P17

VSS_49

R17

VSS_50

T17

VSS_51

U17

VSS_52

W17

VSS_53

K18

VSS_54

K19

VSS_55

H7

VSS_56

G14

VSS_57

AB16

VSS_58

R7

VSS_59

M6

VSS_60

AB23

VSS_61

P7

VSS_62

W7

VSS_63

J7

VSS_64

N7

VSS_65

AB10

VSS_66

AC23

VSS_67

AC6

VSS_68

G19

VSS_69

AA22

VSS_70

J23

VSS_71

J22

VSS_72

K22

VSS_73

J25

VSS_74

N22

VSS_75

N23

VSS_76

M25

VSS_77

P22

VSS_78

R25

VSS_79

V22

VSS_80

W22

VSS_81

W23

VSS_82

V25

VSS_83

AA25

VSS_84

ADAC_AVDD25

C263

4.7uF

PLL_VAFE_AVDD25

C264

4.7uF

C271

C267

0.01uF

0.1uF

C266

C270

0.1uF

C269

0.1uF

C268

0.1uF

C272

0.01uF

4.7uF C277

VAFE2_VDD25

C265

4.7uF

CORE 0.9V

+0.9V_CORE

L209

BLM18PG121SN1D

C274
22uF

+0.9V_CORE

L210

BLM18PG121SN1D

+0.9V_CORE

L211

BLM18PG121SN1D

POWER 3.3V

+3.3V_Normal

Place as close as possible to the pad

use only for A0/B0 chip

C210-*1
220pF
50V

BCM_A0/B0

PLL_VAFE_AVDD25

+0.9V_CORE

Place as close as possible to the pad

C281

0.1uF

C282

0.1uF

L212

VAFE2_DVDD

VAFE3_DVDD

C208
390pF
50V

C206
390pF
50V

+0.9V_CORE

+0.9V_CORE

USB_AVDD33

C283

0.1uF

+3.3V_Normal

+2.5V_BCM35230

+2.5V_BCM35230

VDAC_AVDD33

BCM_C0

PLL_MIPS_AVDD

C273

0.1uF

BLM18PG121SN1D

C284
22uF

BLM18PG121SN1D

L213

BLM18PG121SN1D

ADAC_AVDD25

EPHY_VDD25

HDMI_AVDD33

C275

0.1uF
OPT

USB_AVDD33

C212
390pF
50V

C210
390pF
50V

PLL_MAIN_AVDD

C276

0.01uF

OPT

HDMI_AVDD

C280

0.1uF

PLL_AUD_AVDD

4.7uF

PLL_VAFE_AVDD

C279

4.7uF

BLM18PG121SN1D

VAFE2_VDD25

VAFE3_VDD25

Place as close as possible to the pad

PLL_VAFE_AVDD

C202
390pF
50V

L214

L215

+3.3V_Normal

AADC_AVDD25

HDMI_AVDD

USB_AVDD

C214
390pF
50V

PLL_AUD_AVDD

+3.3V_Normal

C288

0.1uF

C290

0.1uF

L216

BLM18PG121SN1D

C289

0.1uF

+0.9V_CORE

+0.9V_CORE

+0.9V_CORE

C291

4.7uF

USB_AVDD

C285

4.7uF

VAFE3_DVDD

C287

4.7uF

VDAC_AVDD33

C286

4.7uF

LGE35230(BCM35230KFSBG)

F19

AADC_AVDD25

D25

ADACA_AVDD25

D24

ADACC_AVDD25

E24

ADACD_AVDD25

F24

EPHY_BVDD25

E25

EPHY_AVDD25

D5

HDMI0_AVDD

D4

HDMI0_AVDD33

AE20

LT0VDD25_1

AD20

LT0VDD25_2

AC20

LT0VDD25_3

AB20

LT0VDD25_4

D14

SPDIF_IN_AVDD25

E4

USB_AVDD

D3

USB_AVDD33

D6

VDAC_AVDD33

D18

VAFE2_DVDD

E17

VAFE2_AVDD25_1

D16

VAFE2_AVDD25_2

D17

VAFE2_DVDD25

D9

VAFE3_DVDD

D8

VAFE3_AVDD25_1

E8

VAFE3_AVDD25_2

F9

VAFE3_AVDD25_3

E9

VAFE3_DVDD25

F8

POR_VDD25

G25

PLL_AUD_AVDD

K4

PLL_MAIN_AVDD

AD25

PLL_MIPS_AVDD

D11

PLL_VAFE_AVDD

D12

PLL_VAFE_AVDD25

AE7

TVM_OSC_AVDD

U6

AUX_AVDD33

C278

0.1uF

BLM18PG121SN1D

C292
22uF

L217

BLM18PG121SN1D

BLM18PG121SN1D

HDMI_AVDD33

C293

0.1uF

IC101

NON_BCM_CAP

HDMI0_AVSS_1
HDMI0_AVSS_2

SPDIF_IN_AVSS

VAFE2_VSS_1
VAFE2_VSS_2
VAFE2_VSS_3
VAFE2_VSS_4
VAFE2_VSS_5
VAFE2_VSS_6
VAFE2_VSS_7

VAFE3_VSS_1
VAFE3_VSS_2
VAFE3_VSS_3
VAFE3_VSS_4
VAFE3_VSS_5
VAFE3_VSS_6

PLL_MIPS_AVSS

TVM_OSC_AVSS

L219

PLL_MAIN_AVDD

L218

AADC_AVSS

ADACA_AVSS
ADACC_AVSS
ADACD_AVSS

EPHY_AVSS

LT0VSS_1
LT0VSS_2
LT0VSS_3
LT0VSS_4
LT0VSS_5
LT0VSS_6
LT0VSS_7

USB_AVSS_1
USB_AVSS_2

VDAC_AVSS

VAFE2_DVDD

C299

C296

0.1uF

4.7uF

C294

C297

4.7uF

0.1uF

PLL_MIPS_AVDD

C295

C298

4.7uF

0.1uF

F20

G22
G21
F22

F23

F6
G6

AB22
AB21
AB19
AC19
AB18
AB17
AC17

F15

G7
G8

G9

G20
E18
G18
G17
F18
G16
F16

G13
G12
F12
G11
G10
F10

AD26

AC7

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BCM35230

MAIN POWER

2

50

AV2_CVBS_IN

INCM_VID_AV2

INCM_VID_COMP1

C303 0.1uF
C304 0.1uF
R303

36

TU_CVBS

AV1_CVBS_IN

INCM_VID_AV1

TU_SIF

DSUB_R+

INCM_R

DSUB_B+

INCM_B

COMP1_Y
COMP1_Pr
COMP1_Pb

EU

R325-*1

10

C317 0.1uF
C318 0.1uF
R304

36

C320 0.1uF
C321 0.1uF

R311
36

C322 0.1uF
C323 0.1uF
R312

36

R310
0

SC_R/COMP2_Pr

SC_G/COMP2_Y

SC_B/COMP2_Pb

INCM_VID_SC/COMP2

SC_CVBS_IN

INCM_VID_SC

NON_EU
R325 0

INCM_TUNER

R306
75
1%

OPT

+2.5V_BCM35230

C319 0.1uF

R305
240

OPT

INCM_SIF

DSUB_G+

INCM_G

C325 0.1uF
C326 0.1uF
R316

36

R313
10K

+2.5V_BCM35230

R314
12K

C324 0.1uF
R315

120
OPT

C327 0.1uF
C328 0.1uF
R317

36

DSUB_HSYNC
DSUB_VSYNC

C329 0.1uF
C330 0.1uF
C331 0.1uF
C332 0.1uF

C333 0.1uF
C334 0.1uF
C335 0.1uF
C336 0.1uF

R318
0

SC_FB

R319
10K

OPT

R320
12K

OPT

LGE35230(BCM35230KFSBG)

B6
A6
C7
A7
B7
C8

C13
A13

C9
A9
B9
B8

C11
A10
B10
C10

D10
F13

A12
C12
B12
B11

E12
E14

E15
F17
E16
F14
E11

C18
B18
A18
C19
A19
B19
C20
B20

E19
D19
E10
F11

IC101

NON_BCM_CAP

VI_R
VI_INCM_R
VI_G
VI_INCM_G
VI_B
VI_INCM_B

HSYNC_IN
VSYNC_IN

VI_Y1
VI_PR1
VI_PB1
VI_INCM_COMP1

VI_SC_R1
VI_SC_G1
VI_SC_B1
VI_INCM_SC1

VI_FB_1/GPIO
VI_FS1

VI_SC_R2
VI_SC_G2
VI_SC_B2
VI_INCM_SC2

VI_FB_2/GPIO
VI_FS2

VI_L1
VI_C1_1
VI_INCM_LC1_1
VI_C1_2
VI_INCM_LC1_2

VI_CVBS1
VI_INCM_CVBS1
VI_CVBS2
VI_INCM_CVBS2
VI_CVBS3
VI_INCM_CVBS3
VI_CVBS4
VI_INCM_CVBS4

VI_SIF1_1
VI_INCM_SIF1_1
VI_SIF1_2
VI_INCM_SIF1_2

Near

Near

Near

Near

Near

Near

Near
Near

P801

P801

P801

JK1101

JK1104

TU2101/2
TU2201/2/3

JK1102

JK1103
JK2501

VIDEO INCM

Run Along DSUB_R Trace

Run Along DSUB_G Trace

Run Along DSUB_B Trace

Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace

Run Along AV2_CVBS Trace

Run Along TUNER_CVBS_IF_P Trace

Run Along AV1_CVBS Trace

Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN/SC R,G,B Trace

INCM_R

INCM_G

INCM_B

INCM_VID_COMP1

INCM_VID_AV2

INCM_TUNER

INCM_VID_AV1

INCM_VID_SC/COMP2

BCM35230_with_CAP_220pF

IC101-*1
LGE35230

B6

BCM_CAP

VI_R

A6

VI_INCM_R

C7

VI_G

A7

VI_INCM_G

B7

VI_B

C8

VI_INCM_B

C13

HSYNC_IN

A13

VSYNC_IN

C9

VI_Y1

A9

VI_PR1

B9

VI_PB1

B8

VI_INCM_COMP1

C11

VI_SC_R1

A10

VI_SC_G1

B10

VI_SC_B1

C10

VI_INCM_SC1

D10

VI_FB_1/GPIO

F13

VI_FS1

A12

VI_SC_R2

C12

VI_SC_G2

B12

VI_SC_B2

B11

VI_INCM_SC2

E12

VI_FB_2/GPIO

E14

VI_FS2

E15

VI_L1

F17

VI_C1_1

E16

VI_INCM_LC1_1

F14

VI_C1_2

E11

VI_INCM_LC1_2

C18

VI_CVBS1

B18

VI_INCM_CVBS1

A18

VI_CVBS2

C19

VI_INCM_CVBS2

A19

VI_CVBS3

B19

VI_INCM_CVBS3

C20

VI_CVBS4

B20

VI_INCM_CVBS4

E19

VI_SIF1_1

D19

VI_INCM_SIF1_1

E10

VI_SIF1_2

F11

VI_INCM_SIF1_2

SCL3_3.3V
SDA3_3.3V

+3.3V_Normal

R301

1.2K

C301
33pF
50V

PHONE JACK

INCM_AUD_SC/COMP2

R302

1.2K
M_REMOTE_TX

C302
33pF
50V

PC_L_IN
PC_R_IN

AV1_L_IN
AV1_R_IN

INCM_AUD_AV1

AV2_L_IN
AV2_R_IN

INCM_AUD_AV2

SC/COMP2_L_IN
SC/COMP2_R_IN

C305 1uF 10V
C306 1uF 10V
C307 1uF 10V

C308 1uF 10V
C309 1uF 10V
C310 1uF 10V

C311 1uF 10V
C312 1uF 10V
C313 1uF 10V

C314 1uF 10V
C315 1uF 10V
C316 1uF 10V

NON_BCM_CAP

SPDIF_INC_P
SPDIF_INC_N

SPDIF_IND_P
SPDIF_IND_N

I2SSCK_IN/GPIO
I2SWS_IN
I2SSD_IN/GPIO

AADC_LINE_L1
AADC_LINE_R1
AADC_INCM1

AADC_LINE_L2
AADC_LINE_R2
AADC_INCM2

AADC_LINE_L3
AADC_LINE_R3
AADC_INCM3

AADC_LINE_L4
AADC_LINE_R4
AADC_INCM4

AADC_LINE_L5
AADC_LINE_R5
AADC_INCM5

AADC_LINE_L6
AADC_LINE_R6
AADC_INCM6

AADC_LINE_L7
AADC_LINE_R7
AADC_INCM7

IC101

I2SSCK_OUTA/GPIO

I2SWS_OUTA/GPIO

I2SSD_OUTA0/GPIO

I2SSOSCK_OUTA/GPIO

I2SSD_OUTA1/GPIO
I2SSD_OUTA2/GPIO

I2SSCK_OUTC/GPIO

I2SWS_OUTC/GPIO
I2SSD_OUTC/GPIO

I2SSOSCK_OUTC/GPIO

I2SSCK_OUTD/GPIO

I2SWS_OUTD/GPIO
I2SSD_OUTD/GPIO

I2SSOSCK_OUTD/GPIO

SPDIF_OUTA/GPIO

LGE35230(BCM35230KFSBG)

B15
C15

C14
B14

G4
F4
G5

C25
B24
A24

E22
E23
D23

C24
C23
B23

E21
D21
D22

B22
C22
A22

F21
D20
E20

A21
C21
B21

AUDMUTE_0/GPIO

AUDMUTE_1

ADAC_AL_N
ADAC_AL_P

ADAC_AR_N
ADAC_AR_P

ADAC_CL_N
ADAC_CL_P

ADAC_CR_N
ADAC_CR_P

ADAC_DL_N
ADAC_DL_P

ADAC_DR_N
ADAC_DR_P

AF8
AF9
AG9
AC9
AD8
AD9

E2
F2
E3
F3

G2
G3
G1
H1

B13

AG8
E13

C28
C27

D28
D27

C26
A27

B27
B28

B25
A25

A26
B26

R326 100
R327 100
R328 100
R329 100

TU_RESET_SUB

HP_DET
AV1_CVBS_DET
TU_RESET

SC_RE1
SC_RE2INCM_AUD_PC
/RST_HUB
S2_RESET

SPDIF_OUT

HP_LOUT_N
HP_LOUT_P

HP_ROUT_N
HP_ROUT_P

SCART1_Lout_N
SCART1_Lout_P

SCART1_Rout_N
SCART1_Rout_P

C337
22pF

OPT

C338
22pF

OPT

C339
22pF

OPT

C340
33pF

OPT

AUD_SCK
AUD_LRCK
AUD_LRCH
AUD_MASTER_CLK

Near

Near

Near

Near

Near

JK1102

JK1103
JK2501

JK1104
JK801

TU2101/2
TU2201/2/3

R321 0

R322 0

R323 0

R324 0

AUDIO INCM

Route Between AV1_L_IN & AV1_R_IN Trace

Route Between SC/COMP2_L_IN & SC/COMP2_R_IN Trace

Route Between AV2_L_IN & AV2_R_IN Trace

Route Between PC_L_IN & PC_R_IN Trace

Route Along With TUNER_SIF_IF_N

INCM_AUD_AV1

INCM_AUD_SC/COMP2

INCM_AUD_AV2

INCM_AUD_PC

INCM_SIF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

BCM35230

MAIN AUDIO/VIDEO

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