Lenovo LA-B131P ZIVY1, Y40, Y50 Schematic
A
B
C
D
E
Compal Confidential
MODEL NAME :
PCB NO :
1 1
BOM P/N :
2 2
ZIVY1
LA-B131P
SKU1_4519RY38L05 (I5-4200U 1.6GHZ - Hynix 2G)
SKU2_4519RY38L05 (I5-4200U 1.6GHZ - Micro 2G)
SKU3_4519RY38L08 (I7-4500U 1.8GHZ - Hynix 4G) FAI
SKU3_4519RY38L08 (I7-4510U 1.8GHZ - Hynix 4G) main SMT
SKU4_4519RY38L07 (I2-4200U 1.6GHZ - Micro 4G)
SKU5_4519RY38L05 (I5-4200U 1.6GHZ - Samsung 2G)
SKU6_4519RY38L07 (I5-4200U 1.6GHZ - Samsung 4G)
Compal Confidential
Lamborghini Y40 M/B Schematics Document
Intel Haswell / Broadwell ULT Processor + AMD Venus XTX
3 3
2014-03-03
REV:1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-B131P
E
1 52Tuesday, March 04, 2014
of
1.0
A
Compal confidential
File Name :ZIVY1
B
C
D
E
AMD Venus XTX (M2)
VRAM 256X16, 128X16
1 1
DDR3 x 8
page 17~24
EDP Conn.
page 25
PCIE x4
eDP x1
2 Lane
Memory BUS
1.35V DDR3L 1600
SATA 3.0
Intel Haswell / Broadwell
ULT Processor
HDMI Conn.
page 28
2 2
LAN( 10/100/1GbE)
RJ45 Conn
Int. Speaker Conn.
page 27
page 26
Realtek RTL8111GUL-CG
page 26
AUDIO CODEC
HDMI x 4 lanes
port 3
PCIe 2.0 5GT/s
HD Audio
DDI x1
PCIE x1
Realtek ALC283
Combo jack & S/PDIF
page 27
Audio/B
3 3
SYS BIOS ROM 8M
WINBOND W25Q64FVSSIQ
page 7
SPI
1168pin BGA
page 04~14
USB 3.0
USB 2.0x8
PCIE x1
PCIE x1
USB 3.0
conn x2
page 32 page 25
WLAN+BT
(NGFF E type)
page 29
204pin DDR3L-SO-DIMM X2
page 15~16
SATA3.0 HDD (SSD)
page 29
USB Charger
TPS2544
page 32
USB 2.0
conn x1
CMOS
Camera
port 3 (Right)port 1, 2 (Left)
Audio/B
Touch Panel
Card Reader
RTS5249-GR
page 25
Card Reader
Conn.
LPC BUS
CLK=24MHz
Sub-board
Power Board
LED Board
4 4
AUDIO Board
Audio/B
Card Reader Board
A
B
Lid SW
TCS20DLR
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
KBC
NUVOTON
NPCE288N
page 30
PS/2
Int.KBDTouch Pad
page 31 page 31
2014/03/03 2015/03/03
C
Thermal Sensor
EMC1403-2-AIZL-TR
Compal Secret Data
Deciphered Date
page 31
D
Card Reader/B
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-B131P
E
of
2 52Tuesday, March 04, 2014
1.0
1
2
3
4
5
Voltage Rails
STATE
power
plane
+5VALW
+3VALW
+1.35V
A A
B+
State
S0
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
B B
O
O
O
O
O
O
X
X
X
X X X
+5VS
+3VS
+1.5VS
+1.05VS
+CPU_CORE
+0.675VS
+VGA_CORE
+MEM_GFX
+3VGA
+1.8VGA
+VGA_PCIE
O
X X
X
OO
X
X
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
BOM Structure Table
BTO Item BOM Structure
Unpop
CPU OPTION CPU1@ ~ CPU4@
VRAM Option
DS3
NOD
LAN RTL8111GUS
EMI PART EMI@
ESD PART
Crystal
Green CLK
SATA Repeater TI@ / Parade @
EC 902 2@ / 9012@
Connector CO
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ONONON ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ZZZ
H5TC2G63FFR-11C
U21
HYN2@
LOW
OFF
OFF
OFF
V2G@
U16
HYN2@
PCB part
2G
X7654038L01
HYN2@
ZZZ
@
DA8000ZQ010
PCB 14P LA-B131P REV1 M/B 4
CPU part (R1)
U9
HSW
I5-4200U_1.6G
SA00006SMC0
BDW
HYN2@
RV6
U20
ZZZ
DAZ14P00100
PCB ZIVY1 LA-B131P LS-B131P/B132/B133 02
CPU3@
U9
R3
CPU1@
R1
I5-4210U_1.7GHZ
SA00007LO10
VRAM * 8 (R1)
H5TC4G63AFR-11C
HYN2@
U14
ZZZ
HYN4@U15
U9
R3
I7-4500U_1.8G
SA00006SLA0
V4G@
SVT
U9
CPU2@
CPU4@
R1
I7-4510U_2GHZ
SA00007M700
SVT
4G
X7654038L04
RV6
U16
HYN4@
U18
HYN4@
U20
HYN4@
HYN4@
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
HIGHHIGHHIGH
HIGH
LOWLOWLOW
HIGH
LOW LOW LOW LOW
@
@CONN@ / @DIS@
@EMI@ / @ESD@
DIS@AMD Venus XTX
V2G@ / V4G@
HYN2@ / HYN4@
SAM2@ / SAM4@
MIC2@ / MIC4@
BDW@ / HSW@Platform
S3
DS3@
NODS3@
SWR@ / LDO@
ESD@
NOGCLK@
GCLK@
NN@
EC SM Bus1 address
Device
Smart Battery
Address
0001 0010
PCH SM Bus address
Device Address
DDR_JDIMM1
DDR_JDIMM2
TP module
C C
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
USB2.0
Port 0
D D
Flexible I/O Cap able Ports
HSIO Port
USB 3.0
PCIe
SATA
1010 000x A0h
1010 010x A4h
SOURCEECBATT SODIMM
PCH
PCH
PCH
Left USB3.0 Right USB2.0 Touch Panel BT (NGFF)Left USB3.0
1
1
USB3.0_12USB3.0_2
VGA
X
V
X
X
X
XXX
X
V
1
EC SM Bus2 address
Device
Thermal Sensor
EC-KB9022
X
X
X
V
X
V
432 8765 1211109 1413
CardReader LAN GPU_Venus GPU_VenusGPU_VenusGPU_Venus
Address
1001 101xb
TP
Smart Charge
X
V
X
X
321 64
4321 5-L0
WLAN
V
X
X
X
Thermal Sensor
X
X
X
V
5
Camera
2
7
5-L35-L25-L1
3 2 1
6-L36-L26-L16-L0
0
HDD(SSD)
H5TC2G63FFR-11C
U19
HYN2@
H5TC2G63FFR-11C
SA00006H410
Hynix_X7654038L01
U21
MIC2@
MT41J128M16JT-093G:K
MT41J128M16JT-093G:K
U20
SA000067510
MT41J128M16JT-093G:K
MIC2@
MT41J128M16JT-093G:K
Micron_X7654038L02
U15
SAM2@
K4W2G1646Q-BC1A
U20
SAM2@
K4W2G1646Q-BC1A
SA000068U50
Samsung_X7654038L03
3
HYN2@
MIC2@
MIC2@
SAM2@
SAM2@
Compal Secret Data
4
10K_0402_5%
RV8
HYN2@
10K_0402_5%
RV10
HYN2@
10K_0402_5%
RV6
MIC2@
10K_0402_5%
RV8
MIC2@
10K_0402_5%
RV9
MIC2@
10K_0402_5%
RV6
SAM2@
10K_0402_5%
RV7
SAM2@
10K_0402_5%
RV10
SAM2@
10K_0402_5%
Deciphered Date
H5TC2G63FFR-11C
H5TC2G63FFR-11C
U18
U16
K4W2G1646Q-BC1A
K4W2G1646Q-BC1A
H5TC2G63FFR-11C
U17
HYN2@
H5TC2G63FFR-11C
U14
MIC2@
MT41J128M16JT-093G:K
U15
MIC2@
MT41J128M16JT-093G:K
U21
SAM2@
K4W2G1646Q-BC1A
U19
SAM2@
K4W2G1646Q-BC1A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
H5TC2G63FFR-11C
U14
U17
U16
U18
HYN2@
H5TC2G63FFR-11C
U19
MIC2@
MT41J128M16JT-093G:K
MIC2@
U17
MT41J128M16JT-093G:K
SAM2@
U14
K4W2G1646Q-BC1A
U18
SAM2@
K4W2G1646Q-BC1A
2014/03/03 2015/03/03
H5TC4G63AFR-11C
U15
HYN4@
H5TC4G63AFR-11C
SA00006E830
Hynix_X7654038L04
U20
MIC4@
MT41J256M16HA-093G
U21
MIC4@
MT41J256M16HA-093G
SA000077K10
Micron_X7654038L05
U21
SAM4@
K4W4G1646D-BC1A
U20
SAM4@
K4W4G1646D-BC1A
SA000076P10
Samsung_X7654038L06
H5TC4G63AFR-11C
H5TC4G63AFR-11C
U14
MT41J256M16HA-093G
U15
MT41J256M16HA-093G
U14
K4W4G1646D-BC1A
U17
K4W4G1646D-BC1A
H5TC4G63AFR-11C
U17
HYN4@
H5TC4G63AFR-11C
MIC4@
U17
MT41J256M16HA-093G
MIC4@
U16
MT41J256M16HA-093G
U16
SAM4@
K4W4G1646D-BC1A
SAM4@
U15
K4W4G1646D-BC1A
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
Date: Sheet
U19
MIC4@
MIC4@
SAM4@
SAM4@
H5TC4G63AFR-11C
U21
HYN4@
H5TC4G63AFR-11C
U18
MT41J256M16HA-093G
U19
MT41J256M16HA-093G
U19
K4W4G1646D-BC1A
U18
K4W4G1646D-BC1A
Notes List
LA-B131P
5
MIC4@
MIC4@
SAM4@
SAM4@
HYN4@
10K_0402_5%
RV7
10K_0402_5%
RV9
10K_0402_5%
RV5
10K_0402_5%
RV8
10K_0402_5%
RV10
10K_0402_5%
RV5
10K_0402_5%
RV8
10K_0402_5%
RV9
10K_0402_5%
of
3 52Tuesday, March 04, 2014
HYN4@
HYN4@
MIC4@
MIC4@
MIC4@
SAM4@
SAM4@
SAM4@
1.0
5
D D
4
U9A
HASWELL_MCP_E
3
2
1
C54
DDI1_TXN0
C55
DDI1_TXP0
B58
DDI1_TXN1
C58
DDI1_TXP1
B55
DDI1_TXN2
A55
DDI1_TXP2
A57
DDI1_TXN3
B57
C51
C50
C53
B54
C49
B50
A53
B53
D61
K61
N62
K63
C61
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
U9B
PROC_DETECT
CATERR
PECI
PROCHOT
PROCPWRGD
T1 @
R4
56_0402_5%
1 2
CPU_DP2_N0
CPU_DP2_P0
CPU_DP2_N1
CPU_DP2_P1
CPU_DP2_N2
CPU_DP2_P2
CPU_DP2_N3
CPU_DP2_P3
T2 @
H_PROCHOT#_R
H_CPUPWRGD
C1 0.1U_0402_16V7K
HDMI_TX2-_CK28
HDMI_TX2+_CK28
HDMI_TX1-_CK28
HDMI
C C
HDMI_TX1+_CK28
HDMI_TX0-_CK28
HDMI_TX0+_CK28
HDMI_CLK-_CK28
HDMI_CLK+_CK28
H_PECI30
+1.05VS
H_PROCHOT#30
1 2
C2 0.1U_0402_16V7K
1 2
C3 0.1U_0402_16V7K
1 2
C4 0.1U_0402_16V7K
1 2
C5 0.1U_0402_16V7K
1 2
C6 0.1U_0402_16V7K
1 2
C7 0.1U_0402_16V7K
1 2
C8 0.1U_0402_16V7K
1 2
R3
1 2
62_0402_5%
R5 10K_0402_5%
1 2
DDI EDP
1 OF 19
HASWELL_MCP_E
MISC
JTAG
THERMAL
PWR
EDP_RCOMP
EDP_DISP_UTIL
DDR3 Compensation Signals
B B
DDR3 Compensation Signals:
20mils to comp signals
25mils to non-comp signals
500mil for Max trace length
R6 200_0402_1%
1 2
R7 120_0402_1%
1 2
R8 100_0402_1%
1 2
DDR_PG_CTRL15
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DIMM_DRAMRST#
DDR_PG_CTRL
AU60
AV60
AU61
AV15
AV61
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
DDR3
2 OF 19
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
Rev1p2
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
PRDY
PREQ
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
Rev1p2
C45
B46
A47
B47
C47
C46
A49
B49
A45
B45
EDP_COMP
D20
CPU_INV_PWM
A43
EDP_COMP:
Trace width=20 mils,Spacing=25mil,Max length=100mils
J62
K62
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
EDP_TXN0 25
EDP_TXP0 25
EDP_TXN1 25
EDP_TXP1 25
EDP_AUXN 25
EDP_AUXP 25
R1 24.9_0402_1%
1 2
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
@
eDP
T20
T3@
T4@
T5@
T6@
T7@
+VCCIOA_OUT
+1.35V
12
R9
470_0402_5%
ESD@
H_CPUPWRGD
1
C9
100P_0402_50V8J
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
Custom
2
Date: Sheet
Title
Size Document Number Rev
Compal Electronics, Inc.
BDW ULT(1/11) DDI,MSIC,XDP
LA-B131P
1
of
4 52Tuesday, March 04, 2014
1.0
DIMM_DRAMRST#
1
C338
ESD@
100P_0402_50V8J
A A
5
2
DIMM_DRAMRST# 15,16
4
5
D D
U9C
DDR_A_D0
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
C C
B B
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
HASWELL_MCP_E
3 OF 19
DDR CHANNEL A
4
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
DDRA_ODT0
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_CLK_DDR#0 15
SA_CLK_DDR0 15
SA_CLK_DDR#1 15
SA_CLK_DDR1 15
DDRA_CKE0_DIMM 15
DDRA_CKE1_DIMM 15
DDRA_CS0_DIMM# 15
DDRA_CS1_DIMM# 15
T9@
DDR_A_RAS# 15
DDR_A_WE# 15
DDR_A_CAS# 15
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15
SM_DIMM_VREFCA 15
SA_DIMM_A_VREFDQ 15
SA_DIMM_B_VREFDQ 16
3
U9D
DDR_B_D0
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
2
HASWELL_MCP_E
DDR CHANNEL B
4 OF 19
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDRB_ODT0
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
1
SA_CLK_DDR#2 16
SA_CLK_DDR2 16
SA_CLK_DDR#3 16
SA_CLK_DDR3 16
DDRB_CKE2_DIMM 16
DDRB_CKE3_DIMM 16
DDRB_CS2_DIMM# 16
DDRB_CS3_DIMM# 16
T8@
DDR_B_RAS# 16
DDR_B_WE# 16
DDR_B_CAS# 16
DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16
Rev1p2
Rev1p2
DDR_B_D[0..63]16
DDR_A_D[0..63]15
DDR_A_MA[0..15]15
DDR_A_DQS#[0..7]15
A A
5
DDR_A_DQS[0..7]15
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
DDR_B_MA[0..15]16
DDR_B_DQS#[0..7]16
DDR_B_DQS[0..7]16
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
BDW ULT(2/11) DDRIII
LA-B131P
1
5 52Tuesday, March 04, 2014
1.0
of
5
4
3
2
1
GCLK (RG3 close to Y1.1)
RG3
CPU_RTCX1_GCLK34
NOGCLK@
1 2
R10 10M_0402_5%
Y1
D D
C C
1 2
32.768KHZ 12.5PF 9H03200031
NOGCLK@
1
C12
NOGCLK@
15P_0402_50V8J
2
PCH_INTVRMEN
INTVRMEN (+1.05V A)
H：Integrated VRM e nable
*
L：Integrated VRM d isable
RTC CONN place to PWR side
1 2
1
C13
NOGCLK@
15P_0402_50V8J
2
R14 330K_0402_5%
1 2
R15 330K_0402_5%@
1 2
0_0402_5%
PCH_RTCX1
PCH_RTCX2
RTC Battery
W=20mils W=20mils
+RTCVCC
R17 0_0402_5%
C14
1U_0402_6.3V6K
1 2
1
2
+RTCBATT
SIV
SVT
+RTCVCC
PCH_RTCX1
+RTCVCC
R11 20K_04 02_1%
R12 20K_04 02_1%
1U_0603_10V6K
1 2
1 2
C10
1U_0603_10V6K
+RTCVCC
1
C11
Clear ME (TOP)
JME2
SHORT PADS
1 2
2
@
1
Clear CMOS (BOT)
JME1
SHORT PADS
1 2
2
@
CMOS
R13 1M_0402_5%
SVT
HDA_SDIN027
1 2
T10@
T11@
T12@
T13@
T14@
T91@
PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TCK_JTAGX
PCH_RSVD
U9E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
HASWELL_MCP_E
RTC
5 OF 19
JTAG
SATA_IREF
RSVD
RSVD
SATALED
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
SATA_RCOMP
PCH_SATALED#
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATAAUDIO
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_RCOMP
SATA_PRX_DTX_N0 29
SATA_PRX_DTX_P0 29
SATA_PTX_DRX_N0 29
SATA_PTX_DRX_P0 29
PCH_GPIO35 9
PCH_GPIO36 9
PCH_GPIO37 9
within 500 mils
R16 3.01K_0402_1%
1 2
PCH_SATALED# 9,33
HDD(SSD)
+1.05VS_ASATA3PLL
+3V_PCH
B B
R18 1K_0402_5%@
1 2
HDA_SDOUT
ME debug mode,th is signal has a weak internal PD
Low = Disabled ( Default)
*
High = Enabled [ Flash Descriptor Security Overide ]
1 2
R20 51_0402_5%@
A A
HDA_SDOUT
RP1
EMI@
HDA_SDOUT_AUDIO27
HDA_SYNC_AUDIO27
HDA_RST_AUDIO#27
HDA_BITCLK_AUDIO27
C15
@EMI@
68P_0402_50V8J
PCH_JTAG_TCK
ME_EN30
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
1
2
R21 0_0402_5%
1 2
SIV
2014/03/03 2015/03/03
HDA_SDOUT
HDA_SYNC
HDA_RST#
HDA_BIT_CLK
Compal Secret Data
Deciphered Date
2
+3VS
R19 10K_0402_5%
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
BDW ULT(3/11)RTC,SATA,JTAG
PCH_GPIO34
LA-B131P
1
1.0
of
6 52Tuesday, March 04, 2014
5
PCH_GPIO189
CLK_PCIE_CR#33
Card Reader
D D
LAN
WLAN(NGFF)
dGPU
+3VS
12
R154
10K_0402_5%
GPUCLK_REQ#
R1443
10K_0402_5%
C C
B B
To SPI 8MByte ROM From PCH
A A
1 2
From EC
(For share ROM)
@
SPI ROM ( 8MByte )
CLK_PCIE_CR33
CRCLK_REQ#9,33
CLK_PCIE_LAN#26
CLK_PCIE_LAN26
LANCLK_REQ#9,26
CLK_PCIE_WLAN#29
CLK_PCIE_WLAN29
WLANCLK_REQ#9,29
CLK_PCIE_VGA#17
CLK_PCIE_VGA17
GPUCLK_REQ#18
PCH_GPIO239
+3V_PCH
PCH_SPI_HOLD#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
PCH_SPI_CS0#_R
EC_SPI_CS0#30
EC_SPI_CLK30
EC_SPI_MOSI30
EC_SPI_MISO30
22P_0402_50V8J
PCH_SPI_CS0#_R
PCH_SPI_WP#_R
5
PCH_GPIO23
R36 1K_0402_1%
1 2
R37 1K_0402_1%
1 2
R42 33_0402_5%
1 2
RP30
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
EMI@
R38
1 2
RP12
1 8
2 7
3 6
4 5
12
@EMI@
C19
1
2
3
4
33_0804_8P4R_5%
EMI@
U10
@
/CS
DO(IO1)
/HOLD(IO3)
/WP(IO2)
GND
W25Q64FVSSIQ_SO8
LPC_AD030
LPC_AD130
LPC_AD230
LPC_AD330
LPC_FRAME#30
22P_0402_50V8J
0_0402_5%
VCC
CLK
DI(IO0)
8
7
6
5
@EMI@
C325
SVT
+3V_PCH
+3V_ROM
PCH_SPI_HOLD#_RPCH_SPI_SO_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
12
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_WP#
PCH_SPI_HOLD#
PCH_SPI_WP#PCH_SPI_WP#_R
PCH_SPI_HOLD#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS0#
PCH_SPI_CS0#_R
PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
4
C43
C42
U2
B41
A41
Y5
C41
B42
AD1
B38
C37
N1
A39
B39
U5
B37
A37
T2
AU14
AW12
AY12
AW11
AV12
@
C20 0.1U_0402_16V7 K
1 2
SIV
4
U9F
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
U9G
LAD0
LAD1
LAD2
LAD3
LFRAME
AA3
SPI_CLK
Y7
SPI_CS0
Y4
SPI_CS1
AC2
SPI_CS2
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
To SPI 8MByte ROM
3
HASWELL_MCP_E
DIFFCLK_BIASREF
CLOCK
SIGNALS
6 OF 19
HASWELL_MCP_E
LPC
SMBUS
SPI C-LINK
7 OF 19
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
SMBALERT/GPIO11
SML0ALERT/GPIO60
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
SDV for HSW SDV for BDW
U10
HSW@
W25Q64FVSSIQ_SO8
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
Rev1p2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK
CL_DATA
CL_RST
Rev1p2
8
7
6
5
2
RG9
1 2
+1.05VS_AXCK_LCPLL
SIV
1
C18
68P_0402_50V8J
2
SML
2
GCLK (RG9 close to Y2.1)
CPU_XTAL24_IN_GCLK34
XTAL24_IN
A25
XTAL24_OUT
B25
K21
M21
XCLK_BIASREF
C26
C35
C34
AK8
AL8
CLKOUT_LPC0
AN15
AP15
CLK_BCLK_ITP#
B35
CLK_BCLK_ITP
A35
AN2
SMBCLK
AP2
SMBDATA
AH1
PCH_GPIO60
AL2
SML0CLK
AN1
SML0DATA
AK1
PCH_GPIO73
AU4
SML1CLK
AU3
SML1DATA
AH3
AF2
AD2
AF4
2014/03/03 2015/03/03
R23 3.01K_0402_1%
1 2
RP31 10K_8P4R_5%
3
4
1
2
R28 22_0402_5%EMI@
T17@
T18@
T19@
12
T15@
T16@
PCH_GPIO11 9
PCH_GPIO60 9
PCH_GPIO73 9
Compal Secret Data
Deciphered Date
0_0402_5%
@EMI@
SMBus :DIMMA,DIMMB,TP
FootPrint :DMN66D0LDW-7_SOT363-6
SMBDATA
SMBCLK
SMBDATA PCH_SMB_DATA
SMBCLK
1 Bus :EC,Thermal Sensor
FootPrint :DMN66D0LDW-7_SOT363-6
SML1CLK
SML1DATA
PCH_SMB_DATA
PCH_SMB_CLK
EC_SMB_DA2
EC_SMB_CK2
SML1CLK
SML1DATA
SMBCLK
SMBDATA
SML0CLK
SML0DATA
XTAL24_IN
SVT
C16
15P_0402_50V8J
NOGCLK@
+3VS
2
@
6 1
ME2N7002D1KW-G 2N SOT363-6
Q1A
Q1B ME2N7002D1KW-G 2N SOT363-6
R34
R35
5
@
3 4
1 2
0_0402_5%
1 2
0_0402_5%
+3VS
@
6 1
ME2N7002D1KW-G 2N SOT363-6
Q2A
3 4
Q2B ME2N7002D1KW-G 2N SOT363-6
SML1CLK
SML1DATA
R41 2.2K_0402_5%
R43 2.2K_0402_5%
1 2
R39
1 2
R40
RP32
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
RP4
@
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
1 2
1 2
Title
BDW ULT(4/11)CLK,SPI,SMBUS
Size Document Number Rev
Custom
Date: Sheet
Y2
1
1
1
NOGCLK@
2
PCH_SMB_CLK
2
5
@
0_0402_5%
0_0402_5%
Compal Electronics, Inc.
1
NOGCLK@
12
R221M_0402_5%
24MHZ_12PF_7V24000020
GND
2
CK_LPC_KBC 30
EC_SMB_CK2
EC_SMB_DA2
3
3
GND
4
PCH_SMB_DATA 15,16,31
PCH_SMB_CLK 15,16,31
SIT
EC_SMB_CK2 30,31
EC_SMB_DA2 30,31
+3VS
SIV
+3V_PCH
LA-B131P
1
XTAL24_IN
XTAL24_OUT
1
2
SIT
7 52Tuesday, March 04, 2014
C17
15P_0402_50V8J
NOGCLK@
of
1.0
5
D D
+3VALW
12
R50
200K_0402_5%
AC_PRESENT30
SYS_PWROK EC_RSMRST#
C C
1
C339
ESD@
100P_0402_50V8J
2
+3V_PCH
R211 10K_0402_5%
1 2
1
C340
ESD@
100P_0402_50V8J
2
SUSWARN#_R
AC_PRESENT
4
Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit
CAN be NC ,if not support Deep Sx
SUSWARN#_R
R210 0_0402_5%@
1 2
DS3
R47 0_0402_5%DS3@
SUSACK#30
SYS_RESET#9
SYS_PWROK30
PCH_PWROK30
EC_RSMRST#30
SUSWARN#30
PBTN_OUT#30
PCH_GPIO729
PCH_GPIO299
ESD
1 2
0_0402_5%
1 2
R46
C21 100P_0402_50V8 J
12
ESD@
DS3
R209 0_0402_5%DS3@
1 2
INVPWM25
ENBKL25,30
PCH_ENVDD25
DGPU_PWROK9,45
DGPU_PWR_EN9,19,30,41,42
DGPU_HOLD_RST#17
WLBT_OFF#9,29
PCH_GPIO559
PCH_GPIO529
PCH_GPIO549
PCH_GPIO519
PCH_GPIO539
SIT
R51
PCH_GPIO55
PCH_GPIO52
PCH_GPIO54
PCH_GPIO53
T25 @
SIT
0_0402_5%
1 2
SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK_R
CPU_PLT_RST#
EC_RSMRST#
SUSWARN#_R
PBTN_OUT#
AC_PRESENT
PCH_GPIO72
PCH_GPIO29
EDP_BKCTL
T28 @
3
U9H
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPW RDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
U9I
B8
EDP_BKLCTL
A9
EDP_BKLEN
C6
EDP_VDDEN
U6
PIRQA/GPIO77
P4
PIRQB/GPIO78
N4
PIRQC/GPIO79
N2
PIRQD/GPIO80
AD4
PME
U7
GPIO55
L1
GPIO52
L3
GPIO54
R5
GPIO51
L4
GPIO53
HASWELL_MCP_E
SYSTEM POWER MANAGEMENT
HASWELL_MCP_E
eDP SIDEBAND
GPIO
DPWROK: Tired to ghter with RSMRS T#
that do not supp ort Deep Sx
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
Rev1p2
8 OF 19
DISPLAY
2
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
DDI1_CTRL_CK
B9
C9
DDI2_CTRL_CK
D9
DDI2_CTRL_DATA
D11
C5
B6
B5
A6
C8
A8
D6
DSWODVRENSUSACK#_R
DPWROK
PCH_GPIO32
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_A#
DSWODVREN - On Die DSW VR Enable
(*) H：：：：Enable(DEFAULT)
( ) L：：：：Disable
R44 330K_0402_5%
1 2
R45 330K_0402_5%@
1 2
DS3
R212 0_0402_5%DS3@
1 2
R48 0_0402_5%NODS3@
1 2
R49 10K_0402_5%
PCH_PCIE_WAKE#
1 2
T21
@
T22
@
T24@
T27@
DDI2_CTRL_CK 28
DDI2_CTRL_DATA 28
T99@
DDI2_HDMI_HPD 9,28
EDP_HPD 25
T23
@
DS3
DDI1_CTRL_CK
DDI1_CTRL_DATADDI1_CTRL_DATA
1
+RTCVCC
EC_RSMRST#
PCH_PCIE_WAKE# 9,29
PCH_GPIO32 9
SUSCLK 29
PM_SLP_S5# 30
PM_SLP_S4# 30
PM_SLP_S3# 30
SLP_SUS# 30
R58 2.2K_0402_5%@
1 2
R52 2.2K_0402_5%@
1 2
DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA: Port C Detected
1: Port B or C is detected
*
0: Port B or C is not detected
(Have internal PD)
DPWROK_EC 30
+3VS
9 OF 19
B B
SIT
0_0402_5%
R53
1 2
V0.2
CPU_PLT_RST#
MC74VHC1G08DFT2G_SC70-5
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
+3VS
SVT
5
U11
@
2
P
B
4
Y
1
A
2014/03/03 2015/03/03
12
G
3
R54
100K_0402_5%
Compal Secret Data
Deciphered Date
Rev1p2
PLT_RST# 17,26,29,30,33
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
BDW ULT(5/11) PM,GPIO,DDI
LA-B131P
1
of
8 52Tuesday, March 04, 2014
1.0
5
+3VS
1 8
2 7
3 6
4 5
D D
C C
B B
A A
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 2
R276 10K_0402_5%
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 2
R170 1K_0402_5%
PCH_GPIO50
SERIRQ
PCH_GPIO17
RP5 10K_8P4R_5%
PCH_GPIO83
PCH_GPIO2
RP6 10K_8P4R_5%
PCH_GPIO65
PCH_GPIO64
PCH_GPIO1
PCH_GPIO3
RP7 10K_8P4R_5%
KB_RST#
RP8 10K_8P4R_5%
PCH_GPIO33
RP9 10K_8P4R_5%
PCH_GPIO48
PCH_GPIO71
RP2 10K_8P4R_5%
PCH_GPIO87
PCH_GPIO94
PCH_GPIO69
RP23 10K _8P4R_5%
PCH_GPIO38
RP26 10K _8P4R_5%
PCH_GPIO0
EC_SCI#
PCH_GPIO68
PCH_GPIO67
RP24 10K _8P4R_5%
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
RP25 2.2K_0 804_8P4R_5%
PCH_GPIO49
PCH_GPIO16
RP13 10K _8P4R_5%
PCH_GPIO89
PCH_GPIO85
PCH_GPIO92
RP28 10K _8P4R_5%
PCH_GPIO84
PCH_GPIO90
PCH_GPIO93
PCH_GPIO91
RP29 10K _8P4R_5%
HDA_SPKR
@
5
PCH_GPIO18 7
PCH_GPIO51 8
WLBT_OFF# 8,29
PCH_GPIO36 6
CRCLK_REQ# 7,33
LANCLK_REQ# 7,26
PCH_GPIO53 8
PCH_GPIO52 8
WLANCLK_REQ# 7,29
DGPU_PWR_EN 8,19,30,41,42
PCH_SATALED# 6,33
PCH_GPIO35 6
DGPU_PWROK 8,45
PCH_GPIO55 8
PCH_GPIO32 8
PCH_GPIO54 8
SYS_RESET# 8
PCH_GPIO37 6
SIT
PCH_GPIO23 7
SIV
SIT
+3V_PCH
SIV
4
1 8
2 7
3 6
4 5
RP14 10K _8P4R_5%
1 8
2 7
3 6
4 5
RP16 10K _8P4R_5%
1 8
2 7
3 6
4 5
RP18 10K _8P4R_5%
1 8
2 7
3 6
4 5
RP11 10K _8P4R_5%
1 8
2 7
3 6
4 5
RP15 10K _8P4R_5%
1 8
2 7
3 6
4 5
RP17 10K _8P4R_5%
4
PCH_GPIO58
PCH_GPIO10
PCH_GPIO13
PCH_GPIO8
PCH_GPIO12
PCH_GPIO26
PCH_GPIO57
PCH_GPIO24
PCH_GPIO46
PCH_GPIO14
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO28
PCH_GPIO45
PCH_GPIO56
3
U9J
3
1 8
2 7
3 6
4 5
P1
BMBUSY/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
PCH_GPIO25
PCH_GPIO27
RP27 10K_8P4R_5%
2014/03/03 2015/03/03
DDI2_HDMI_HPD8,28
SIV
EC_SCI#30
HDA_SPKR27
PCH_GPIO60 7
PCH_GPIO11 7
USB_OC1# 10,32
PCH_GPIO72 8
PCH_GPIO43 10
PCH_GPIO42 10
USB_OC0# 10,32
PCH_GPIO73 7
PCH_GPIO8
PCH_GPIO12
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO26
PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46
PCH_GPIO10
PCH_GPIO33
PCH_GPIO38
EC_SCI#
HDA_SPKR
+3VALW
SIT
SIT
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
HASWELL_MCP_E
GPIO
10 OF 19
PCH_GPIO29 8
PCH_PCIE_WAKE# 8,29
+3VS
Compal Secret Data
Deciphered Date
CPU/
MISC
LPIO
Platform
BDW => R200 stuff (BDW@)
HSW => R202 stuff (HSW@)
1 2
R200 10K_0402_5%
1 2
R202 10K_0402_5%
BDW@
HSW@
2
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
PCH_GPIO88
2
D60
V4
T4
AW15
AF20
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
+1.05VS
12
R56
1K_0402_1%
H_THERMTRIP#
PCH_OPIRCOMP
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
PCH_GPIO86
PCH_GPIO88
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
PCH_GPIO68
PCH_GPIO69
1 2
R57
49.9_0402_1%
SIT
PCH_GPIO87 25
GPIO87 : Touch / Non-Touch
1: Non-Touch
*
0: Touch
H_THERMTRIP#
PCH_GPIO86
R60 1K_0402_1%@
R61 1K_0402_1%
KB_RST# 30
SERIRQ 30
SDV
ESD@
C22 100P_0402_50V8J
1 2
1 2
1 2
GSPI0_MOSI / GPIO86 : Boot BIOS Strap
1: LPC BUS
0: SPI BUS
*
PCH_GPIO66
(Have internal PD)
R205
1 2
SDIO_D0 / GPIO66 : Top-Block Swap Override
1: DISABLED
*
0: ENABLED
+3V_PCH
(Have internal PD)
R69
@
1 2
1K_0402_1%
GPIO15 : TLS Confidentiality
1: Intel ME TLS with confidentiality
0: Intel ME TLS with no confidentiality
*
(Have internal PD)
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
BDW ULT(6/11) GPIO,LPIO
LA-B131P
1
150K_0402_1%
PCH_GPIO15
1
+3VS
+3VS
1.0
of
9 52Tuesday, March 04, 2014
5
4
3
2
1
PCIe
HASWELL_MCP_E
11 OF 19
AN8
USB2N0
AM8
USB2P0
AR7
USB2N1
AT7
USB2P1
AR8
USB2N2
AP8
USB2P2
AR10
USB2N3
AT10
USB2P3
AM15
USB2N4
AL15
USB2P4
AM13
USB2N5
AN13
USB2P5
AP11
USB2N6
AN11
USB2P6
AR13
USB2N7
AP13
USB2P7
G20
USB3RN1
H20
USB
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBRBIAS
R71 22.6_0402_1%
1 2
T92@
T93@
USB20_N0 32
USB20_P0 32
USB20_N1 32
USB20_P1 32
USB20_N2 32
USB20_P2 32
USB20_N4 25
USB20_P4 25
USB20_N5 25
USB20_P5 25
USB20_N6 29
USB20_P6 29
USB3_RX1_N 32
USB3_RX1_P 32
USB3_TX1_N 32
USB3_TX1_P 32
USB3_RX2_N 32
USB3_RX2_P 32
USB3_TX2_N 32
USB3_TX2_P 32
CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils
USB_OC0# 9,32
USB_OC1# 9,32
PCH_GPIO42 9
PCH_GPIO43 9
Left USB2/3 IO (MB)
Left USB2/3 IO (MB)
Right USB2.0 (IO/B)
Touch Panel
Camera
BT (NGFF)
USB2/3 IO (MB)
USB2/3 IO (MB)
D D
PCIE_CRX_GTX_N017
PCIE_CRX_GTX_P017
PCIE_CTX_GRX_N017
PCIE_CTX_GRX_P017
PCIE_CRX_GTX_N117
PCIE_CRX_GTX_P117
dGPU
LAN
C C
WLAN(NGFF)
Card Reader
PCIE_CTX_GRX_N117
PCIE_CTX_GRX_P117
PCIE_CRX_GTX_N217
PCIE_CRX_GTX_P217
PCIE_CTX_GRX_N217
PCIE_CTX_GRX_P217
PCIE_CRX_GTX_N317
PCIE_CRX_GTX_P317
PCIE_CTX_GRX_N317
PCIE_CTX_GRX_P317
PCIE_PRX_DTX_N326
PCIE_PRX_DTX_P326
PCIE_PTX_C_DRX_N326
PCIE_PTX_C_DRX_P326
PCIE_PRX_DTX_N429
PCIE_PRX_DTX_P429
PCIE_PTX_C_DRX_N429
PCIE_PTX_C_DRX_P429
PCIE_PRX_DTX_N233
PCIE_PRX_DTX_P233
PCIE_PTX_C_DRX_N233
PCIE_PTX_C_DRX_P233
+1.05VS_AUSB3PLL
C23 0.22U_0402_10V6K
1 2
C24 0.22U_0402_10V6K
1 2
C25 0.22U_0402_10V6K
1 2
C26 0.22U_0402_10V6K
1 2
C27 0.22U_0402_10V6K
1 2
C28 0.22U_0402_10V6K
1 2
C29 0.22U_0402_10V6K
1 2
C30 0.22U_0402_10V6K
1 2
C31 0.1U_0402_16V7K
1 2
C32 0.1U_0402_16V7K
1 2
C33 0.1U_0402_16V7K
1 2
C34 0.1U_0402_16V7K
1 2
C35 0.1U_0402_16V7K
1 2
C36 0.1U_0402_16V7K
1 2
R72 3.01K_0402_1%
1 2
PCIE_PTX_DRX_N5_L0
PCIE_PTX_DRX_P5_L0
PCIE_PTX_DRX_N5_L1
PCIE_PTX_DRX_P5_L1
PCIE_PTX_DRX_N5_L2
PCIE_PTX_DRX_P5_L2
PCIE_PTX_DRX_N5_L3
PCIE_PTX_DRX_P5_L3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_RCOMP
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3
C31
PETP1/USB3TP3
F15
PERN2/USB3RN4
G15
PERP2/USB3RP4
B31
PETN2/USB3TN4
A31
PETP2/USB3TP4
E15
RSVD
E13
RSVD
A27
PCIE_RCOMP
B27
PCIE_IREF
U9K
B B
USB2.0
Port 0
Left USB3.0 Ri ght USB2.0 Touch Panel BT (NGFF)Left USB3.0
321 64
5 7
Camera
Flexible I/O Capable Ports
HSIO Port
USB 3.0
PCIe
A A
SATA
1
1
USB3.0_12USB3.0_2
5
432 8765 1211109 1413
CardReader
4321 5-L0
WLANLAN GPU_Venus GPU_VenusGPU_VenusGPU_Venus
4
5-L35- L25-L1
3 2 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
6-L36- L26- L16-L0
0
HDD(SSD)
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
BDW ULT(7/11) PCIE,USB
LA-B131P
1
10 52Tuesday, March 04, 2014
of
1.0
5
D D
VCCST_PWRGD30
C C
VCCST_PWRGD
SVID ALERT
+1.05VS
12
VR_SVID_ALRT#46
Place the PU
resistors close to C PU
R74
75_0402_5%
R75
43_0402_1%
12
H_CPU_SVIDALRT#
SVID DATA
+1.05VS
Place the PU
resistors close to C PU
12
R77
B B
VR_SVID_DAT46
SIT
1 2
R79
0_0402_5%
+CPU_CORE
110_0402_5%
H_CPU_SVIDDATA
R77:
CRB r0.7 changed from 130 Ohms to
110 Ohms
+1.05VS
12
4
R73
10K_0402_5%
+1.05VS
@
@
R76
150_0402_1%
1 2
R78
10K_0402_5%
1 2
connect to PWR
R76: CPU_PWR_DEBUG
CRB mount
Check list ,XDP use only
CPU_PWR_DEBU G
VR_SVID_CLK46
VR_ON46
VGATE46
RF
C38
@
68P_0402_50V8J
3
+VCCIOA_OUT
VR_SVID_CLK
1
2
+1.35V
1
2
SIV
+1.35V
+CPU_CORE
T29
@
R151 10K_0402_5%
+CPU_CORE
1 2
+1.05VS
VCCSENSE
+VCCIO_OUT_R
H_CPU_SVIDALRT#
VR_SVID_CLK
H_CPU_SVIDDATA
VCCST_PWRGD
CPU_PWR_DEBU G
T30 @
T31 @
T32 @
T33 @
T34 @
T35 @
T36 @
T37 @
T38 @
T39 @
T40 @
T41 @
T42 @
T43 @
VDDQ DECOUPLING
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
C42
C41
1
2
CRB:
+1.35V : 470UF/2V/7343 *2 (Un-mount)
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
C49
C43
1
2
10U_0603_6.3V6M
1
1
1
C50
2
2
2
2
U9L
L59
RSVD
J58
RSVD
AH26
VDDQ
AJ31
VDDQ
AJ33
VDDQ
AJ37
VDDQ
AN33
VDDQ
AP43
VDDQ
AR48
VDDQ
AY35
VDDQ
AY40
VDDQ
AY44
VDDQ
AY50
VDDQ
F59
VCC
N58
RSVD
AC58
RSVD
E63
VCC_SENSE
AB23
RSVD
A59
VCCIO_OUT
E20
VCCIOA_OUT
AD23
RSVD
AA23
RSVD
AE59
RSVD
L62
VIDALERT
N63
VIDSCLK
L63
VIDSOUT
B59
VCCST_PWRGD
F60
VR_EN
C59
VR_READY
D63
VSS
H59
PWR_DEBUG
P62
VSS
P60
RSVD_TP
P61
RSVD_TP
N59
RSVD_TP
N61
RSVD_TP
T59
RSVD
AD60
RSVD
AD59
RSVD
AA59
RSVD
AE60
RSVD
AC59
RSVD
AG58
RSVD
U59
RSVD
V59
RSVD
AC22
VCCST
AE22
VCCST
AE23
VCCST
AB57
VCC
AD57
VCC
AG57
VCC
C24
VCC
C28
VCC
C32
VCC
10U_0603_6.3V6M
10U_0603_6.3V6M
C44
10U_0603_6.3V6M
1
2
@
1
C51
C45
2
SIV
HASWELL_MCP_E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
12 OF 19
HSW ULT POWER
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
C52
C46
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Rev1p2
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
1
+CPU_CORE
12
R80
100_0402_1%
CAD Note: PU resistor should be close to CPU
CAD Note: PD resistor should be close to CPU
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
Custom
2
Date: Sheet
Title
Size Document Number Rev
Compal Electronics, Inc.
BDW ULT(8/11) Power
LA-B131P
1
of
11 52Tuesday, March 04, 2014
1.0
12
R81
100_0402_1%
VCCSENSE
VSSSENSE
VCCSENSE46
A A
VSSSENSE13,46
5
5
D D
4
3
2
1
Check Power Source
+1.05VS +1.05VS_AUSB3PLL
L1
1 2
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VS_ASATA3PLL
L2
1 2
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VS_APLLOPI
C C
B B
A A
L3
1 2
2.2UH_LQM2MPN2R2NG0L_30%
L4
1 2
2.2UH_LQM2MPN2R2NG0L_30%
L5
1 2
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VS
+1.05VS
+3V_PCH
+3V_PCH
C57 1U_0402_6.3V6K@
C80 1U_0402_6.3V6K
C82 1U_0402_6.3V6K
C84 22U_0603_6.3V6M
C85 22U_0603_6.3V6M
+3VS
C86 1U_0402_6.3V6K
+1.05VS
C87 1U_0402_6.3V6K
+1.05VS
C88 1U_0402_6.3V6K
+3VALW
C83 0.47U_0402_16V4Z
5
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
Close to N8
1 2
Close to K9,M9
1 2
1 2
Close to AC9/AA9/AE20/AE21
1 2
Close to V8
1 2
Close to J17
1 2
Close to R21
1 2
Close to AH14
V1.0
1 2
C58 1U_0402_6.3V6K
C59 22U_0805_6.3V6M
C37 47U_0805_6.3V6M@
C60 1U_0402_6.3V6K
C62 47U_0805_6.3V6M@
C138 22U_0805_6.3V6M
C65 1U_0402_6.3V6K
C66 22U_0805_6.3V6M@
C333 47U_0805_6.3V6M@
C68 1U_0402_6.3V6K
C70 47U_0805_6.3V6M@
C334 22U_0805_6.3V6M
C73 1U_0402_6.3V6K
C75 22U_0805_6.3V6M
C335 47U_0805_6.3V6M@
12
@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+PCH_VCCDSW
SIT
SIT
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL
+1.05VS_APLLOPI
SIT
SIV
SIT
+3VALW
SIT
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
4
+1.05VS
+1.05VS
T44 @
+3VALW
T45 @
+3V_PCH
+3VS
+1.05VS
+1.05VS
+3V_PCH
AA21
W21
AH14
AH13
AC9
AH10
M20
AE20
AE21
L10
M9
N8
B18
B11
Y20
J13
AA9
W9
J18
K19
A20
J17
R21
T21
K18
V21
K9
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
P9
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
V8
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
18mA
U9M
HASWELL_MCP_E
mPHY
OPI
USB3
AXALIA/HDA
VRM/USB2/AZALIA
13 OF 19
GPIO/LCC
THERMAL SENSOR
LPT LP POWER
SUS OSCILLATOR
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
RTC
SPI
CORE
SDIO/PLSS
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
USB2
VCC1_05
VCC1_05
Rev1p2
2014/03/03 2015/03/03
C61 1U_0402_6.3V6K
AH11
AG10
AE7
+VCCRTCEXT
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
C64 0.1U_0 402_16V7K
C67 10U_0603_6.3V6M
C69 1U_0402_6.3V6K
C71 1U_0402_6.3V6K
+PCH_VCCDSW
C74 22U_0603_6.3V6M@
C76 1U_0402_6.3V6K
T46 @
T47 @
C77 0.1U_0 402_16V7K
1 2
C78 1U_0402_6.3V6K
1 2
T48 @
+1.05VS
C81 1U_0402_6.3V6K
1 2
Compal Secret Data
1 2
C63 0.1U_0 402_16V7K
1 2
1 2
@
+1.05VS
1 2
1 2
1 2
1 2
1 2
Deciphered Date
+RTCVCC
+3V_PCH
+1.5VS
+3VS
+3VS
2
+3V_PCH
C72
1U_0402_6.3V6K
1 2
+RTCVCC
Share ROM
+1.05VS
1
C79
2
1U_0402_6.3V6K
658mA
+1.05VS
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
BDW ULT(9/11) Power
LA-B131P
1
1.0
of
12 52Tuesday, March 04, 2014
5
D D
4
3
2
1
HASWELL_MCP_E
U9N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
C C
B B
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U9O
HASWELL_MCP_E
15 OF 19
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
U9P
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
D62
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
H13
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
VSS
16 OF 19
VSS_SENSE
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSSSENSE 11,46
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
BDW ULT(10/11) GND
LA-B131P
1
1.0
of
13 52Tuesday, March 04, 2014
1
12
12
HASWELL_MCP_E
18 OF 19
R82
1K_0402_1%
@
R83
1K_0402_1%
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Rev1p2
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
U9Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
T49 @
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
T51 @
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
T55 @
T56 @
T57 @
T58 @
T59 @
T60 @
T61 @
T62 @
T63 @
T64 @
A A
T65 @
T66 @
T67 @
T68 @
T69 @
T70 @
T71 @
T72 @
T73 @
T74 @
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
TD_IREF
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
U9S
AC60
CFG0
AC62
CFG1
AC63
CFG2
AA63
CFG3
AA60
CFG4
Y62
CFG5
Y61
CFG6
Y60
CFG7
V62
CFG8
V61
CFG9
V60
CFG10
U60
CFG11
T63
CFG12
T62
CFG13
T61
CFG14
T60
CFG15
AA62
CFG16
U63
CFG18
AA61
CFG17
U62
CFG19
V63
CFG_RCOMP
A5
RSVD
E1
RSVD
D1
RSVD
J20
RSVD
H18
RSVD
B12
TD_IREF
HASWELL_MCP_E
17 OF 19
HASWELL_MCP_E
RESERVED
19 OF 19
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
PROC_OPI_RCOMP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
VSS
VSS
RSVD
RSVD
Rev1p2
A3
A4
A60
A61
A62
AV1
AW1
DC_TEST_AY2_AW2
AW2
DC_TEST_AY3_AW3
AW3
DC_TEST_AY61_AW61
AW61
DC_TEST_AY62_AW62
AW62
AW63
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
AV62
D58
P22
N21
P20
R20
DC_TEST_A3_B3
DC_TEST_A61_B61
OPI_COMP
T50@
V1.0
T52@
T53@
T54@
U9R
AT2
RSVD
AU44
RSVD
AV44
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
CFG Straps for Processor
CFG3
Physical Debug Enable (DFX Privacy)
1: DISABLED
CFG3
0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR
CFG4
R84 49.9_0402_1%
R85 49.9_0402_1%
R86 8.2K_0402_5%
12
12
12
CFG_RCOMP
OPI_COMP
TD_IREF
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
Custom
Date: Sheet
Title
Size Document Number Rev
Compal Electronics, Inc.
BDW ULT(11/11) RSVD
LA-B131P
of
14 52Tuesday, March 04, 2014
1.0
A
SA_DIMM_A_VREFDQ5
1 1
+1.35V
C93
1U_0402_6.3V6K
1
@
2
SIV
+1.35V
C98
1U_0402_6.3V6K
2 2
3 3
1
@
2
SIV
+1.35V
C102
10U_0603_6.3V6M
1
2
+1.35V
C109
10U_0603_6.3V6M
1
2
Layout Note:
Place near JDIMMA
Everage by each side
C89
0.022U_0402_16V7K
12
@
12
@
SIT
C94
1U_0402_6.3V6K
C96
1U_0402_6.3V6K
1
1
@
@
2
2
C100
1U_0402_6.3V6K
C99
1U_0402_6.3V6K
1
1
2
1
2
1
2
@
@
2
C104
10U_0603_6.3V6M
C103
10U_0603_6.3V6M
1
1
2
2
C110
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
1
1
+
@
@
2
2
CRB1.0 10uF *8 /1uF *8
+0.675VS
C115
1U_0402_6.3V6K
C113
10U_0603_6.3V6M
1
1
@
2
2
4 4
SIV
Layout Note:
Place near JDIMM1.203,204
C116
1U_0402_6.3V6K
C114
1U_0402_6.3V6K
1
@
@
2
1
1
2
2
+1.35V
12
R88
1 2
0_0402_5%
R90
24.9_0402_1%
10U_0603_6.3V6M
C112
12
C95
1U_0402_6.3V6K
1
2
C101
1U_0402_6.3V6K
1
2
C105
100U_B2_6.3VM_R45M
+3VS
+0.675VS
C117
1U_0402_6.3V6K
CRB1.0 0.1uF *1 /2.2uF *1
R87
1.8K_0402_1%
C90
2.2U_0402_6.3V6M
@
R89
1.8K_0402_1%
CRB1.0 0.1uF *1 /2.2uF *1
2.2uF (reserved\)
DDRA_CKE0_DIMM5
DDR_A_BS25
SA_CLK_DDR05
SA_CLK_DDR#05
DDR_A_BS05
DDR_A_WE#5
DDR_A_CAS#5
DDRA_CS1_DIMM#5
C118
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
1
1
2
2
C119
2.2U_0402_6.3V6M
1
@
2
SIV
C91
DDRA_CKE0_DIMM
DDR_A_BS2
DDRA_CS1_DIMM#
+V_DDR_REFA
DDR_A_D13
DDR_A_D8
DDR_A_D14
DDR_A_D10
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
SA_CLK_DDR0
SA_CLK_DDR#0
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
CRB1.0 10uF *1 /1uF *4
A
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_SA0
DDR_A_SA1
B
JDIMM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
LCN_DAN06-K4406-0103
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1#
VDD
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
GND2
BOSS2
+1.35V+1.35V
2
DDR_A_D9
4
DDR_A_D12
6
8
DDR_A_DQS#1
10
DDR_A_DQS1
12
14
DDR_A_D15
16
DDR_A_D11
18
20
DDR_A_D25
22
DDR_A_D24
24
26
28
DIMM_DRAMRST#
30
32
DDR_A_D27
34
DDR_A_D26
36
38
DDR_A_D45
40
DDR_A_D40
42
44
46
48
DDR_A_D42
50
DDR_A_D46
52
54
DDR_A_D52
56
DDR_A_D53
58
60
DDR_A_DQS#6
62
DDR_A_DQS6
64
66
DDR_A_D54
68
DDR_A_D55
70
72
DDRA_CKE1_DIMM
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC
SCL
VTT
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDRA_CS0_DIMM#
SA_ODT0
SA_ODT1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
PCH_SMB_DATA
PCH_SMB_CLK
+0.675VS
C
All VR\EF traces should
have 10 mil trace width
C92 0 .1U_0402_16V7K
1 2
@
DDRA_CKE1_DIMM 5
SA_CLK_DDR1 5
SA_CLK_DDR#1 5
DDR_A_BS1 5
DDR_A_RAS# 5
DDRA_CS0_DIMM# 5
+VREF_CA
2.2U_0402_6.3V6M
C106
1
@
2
CRB1.0 0.1uF *1 /2.2uF *1
2.2uF (reserved\)
PCH_SMB_DATA 7,16,31
PCH_SMB_CLK 7,16 ,31
CHANN\EL A /TYP\E :Reverse / H:4mm
PN:SP07000LT00
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DIMM_DRAMRST# 4,16
C108
0.1U_0402_16V7K
1
2
D
DDR_A_D[0..63] 5
DDR_A_MA[0..15] 5
DDR_A_DQS#[0..7] 5
DDR_A_DQS[0..7] 5
+1.35V
12
R97
1.8K_0402_1%
R98
1 2
0_0402_5%
12
R99
1.8K_0402_1%
DDR_PG_CTRL4
C107
0.022U_0402_16V7K
12
@
12
R100
@
24.9_0402_1%
SIV
U13
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
SM_DIMM_VREFCA 5
SIT
Address : 00
R101 0_0402_5%
1 2
R102 0_0402_5%
1 2
SIV
2014/03/03 2015/03/03
Compal Secret Data
Deciphered Date
D
0.1U_0402_16V7K
C97
DDR_A_SA0
DDR_A_SA1
E
+1.35V
+5VALW
1
@
2
5
4
Y
+5VS
R91220K_0402_5%
R92220K_0402_5%
12
12
V0.2
@
Custom
+1.35V
Q3
13
D
LBSS138LT1G_SOT-23-3
2
G
S
M_A_B_DIMM_ODT
DDR_VTT_PG_CTRL 40
SA_ODT216
SA_ODT316
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDR3L_DIMMA
LA-B131P
1 2
R93 66.5_0402_1%
1 2
R94 66.5_0402_1%
1 2
R95 66.5_0402_1%
1 2
R96 66.5_0402_1%
SA_ODT2
SA_ODT3
E
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
1.0
of
15 52Tuesday, March 04, 2014
A
SA_DIMM_B_VREFDQ5
1 1
+1.35V
C124
1U_0402_6.3V6K
1
@
2
SIV
+1.35V
C128
1U_0402_6.3V6K
2 2
3 3
1
@
2
SIV
+1.35V
C132
10U_0603_6.3V6M
1
2
+1.35V
C139
10U_0603_6.3V6M
1
2
Layout Note:
Place near JDIMMB
Everage by each side
C120
0.022U_0402_16V7K
12
@
12
@
SIT
C127
1U_0402_6.3V6K
C126
1U_0402_6.3V6K
1
1
@
2
1
2
1
2
1
2
@
2
C131
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
1
@
@
2
C133
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
1
1
2
2
C140
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
1
1
+
@
@
2
2
CRB1.0 10uF *8 /1uF *8
+0.675VS
C146
C143
10U_0603_6.3V6M
C144
1U_0402_6.3V6K
1
1
@
@
2
4 4
2
SIV
Layout Note:
Place near JDIMMB.203,204
1U_0402_6.3V6K
C147
1U_0402_6.3V6K
1
1
@
2
1
2
2
+1.35V
12
R104
1 2
0_0402_5%
R106
24.9_0402_1%
10U_0603_6.3V6M
C142
12
C125
1U_0402_6.3V6K
1
2
C130
1U_0402_6.3V6K
1
2
C135
100U_B2_6.3VM_R45M
+0.675VS
C145
1U_0402_6.3V6K
CRB1.0 0.1uF *1 /2.2uF *1
R103
1.8K_0402_1%
C121
2.2U_0402_6.3V6M
@
R105
1.8K_0402_1%
CRB1.0 0.1uF *1 /2.2uF *1
2.2uF (reserved\)
DDRB_CKE2_DIMM5
DDR_B_BS25
SA_CLK_DDR25
SA_CLK_DDR#25
DDR_B_BS05
DDR_B_WE#5
DDR_B_CAS#5
DDRB_CS3_DIMM#5
C148
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
1
1
2
2
C149
2.2U_0402_6.3V6M
1
@
2
C122
DDRB_CKE2_DIMM
DDR_B_BS2
DDRB_CS3_DIMM#
+V_DDR_REFB
DDR_B_D8
DDR_B_D14
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
DDR_B_D4
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D36
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
CRB1.0 10uF *1 /1uF *4
A
B
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
SA_CLK_DDR2
SA_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_SA0
DDR_B_SA1 PCH_SMB_CLK
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
LCN_DAN06-K4406-0103
DQS0#
RESET#
DQS3#
VREF_CA
DQS5#
DQS7#
EVENT#
BOSS2
VSS
DQ4
DQ5
VSS
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1#
VDD
RAS#
VDD
ODT0
VDD
ODT1
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7
VSS
DQ62
DQ63
VSS
SDA
GND2
+1.35V+1.35V
2
DDR_B_D12
4
DDR_B_D9
6
8
DDR_B_DQS#1
10
DDR_B_DQS1
12
14
DDR_B_D13
16
DDR_B_D15
18
20
DDR_B_D25
22
DDR_B_D24
24
26
28
DIMM_DRAMRST#
30
32
DDR_B_D30
34
DDR_B_D31
36
38
DDR_B_D45
40
DDR_B_D44
42
44
46
48
DDR_B_D47
50
DDR_B_D43
52
54
DDR_B_D61
56
DDR_B_D60
58
60
DDR_B_DQS#7
62
DDR_B_DQS7
64
66
DDR_B_D63
68
DDR_B_D62
70
72
DDRB_CKE3_DIMM
74
76
DDR_B_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC
SCL
VTT
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SA_CLK_DDR3
SA_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDRB_CS2_DIMM#
SA_ODT2
SA_ODT3
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
PCH_SMB_DATA
+0.675VS
CHANN\EL B /TYP\E :Reverse / H:4mm
PN:SP07000LT00
B
C
All VR\EF traces should
have 10 mil trace width
DIMM_DRAMRST# 4,15
C123 0.1U_ 0402_16V7K
1 2
@
DDRB_CKE3_DIMM 5
SA_CLK_DDR3 5
SA_CLK_DDR#3 5
DDR_B_BS1 5
DDR_B_RAS# 5
DDRB_CS2_DIMM# 5
SA_ODT2 15
SA_ODT3 15
+VREF_CA
2.2U_0402_6.3V6M
C136
1
1
@
2
2
CRB1.0 0.1uF *1 /2.2uF *1
2.2uF (reserved\)
C137
0.1U_0402_16V7K
DDR_B_D[0..63] 5
DDR_B_MA[0..15] 5
DDR_B_DQS#[0..7] 5
DDR_B_DQS[0..7] 5
D
Address : 01
R111 0_0402_5%
1 2
R112 0_0402_5%
1 2
+3VS
PCH_SMB_DATA 7,15,31+3VS
PCH_SMB_CLK 7,15 ,31
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SIV
2014/03/03 2015/03/03
DDR_B_SA0
DDR_B_SA1
Compal Secret Data
Deciphered Date
D
E
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
DDR3L_DIMMB
LA-B131P
E
of
16 52Tuesday, March 04, 2014
1.0
Loading...