LENOVO Y485P Schematics

A

B

C

D

E

1

Compal Confidential

2

QAWYA M/B Schematics Document

AMD Fs1r2 Processor with DDRIII + Bolton M3 FCH

AMD VGA Mars XTX

2

3

2012-11-01

3

REV:0.1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA8642P M/B

1 57Thursday, November 01, 2012

E

of

4

0.1

A

ompal confidential

C

ile Name : Y485P

F

GA Thermal Sensor

1

V

ADM1032ARMZ-2R

age 17

p

LVDS translator

RTD2132S

page 27 page 30

MD Mars XTX

A

V

RAM 128Mx16 GDDR5 x 8

HDMI Conn.

B

page 16~25

G

DP Port0

DP Port2

DP Port1

C

D

en2PCIE x 8

M

AMD FS1r2 APU

Richland

emory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1600

04pin DDRIII-SO-DIMM X2

2

BANK 0, 1, 2

page 9,10

E

1

uPGA 722 pin 35mm x 35mm

page 5,6,7,8

4 * x1 PCI-E 2.0

LVDS Conn.

page 28

2

Card Reader

JBM389C SD/MMC/MS/XD

Audio Board Page41

PCI Express Mini card Slot 1

WLAN

3

page 31

PCI Express

GPP3

GPP1

WLAN

page 31

CRT Conn.

USB(reserve for WiMAX)

PCI-E(WLAN)

SATA(SSD)

GPP0

LAN(Gbe)

REKTEK RTL8111E/ RTL8111F

page 32

RJ45 CONN

page 33

page 29

FCH CRT (VGA DAC)

SPI ROM

page 13

Mini card Slot 2

page 31

Sub-borad

POWER BOARD

Function Board

Audio Board

4

Touch Pad

x4 UMI Gen. 1

2.5GT/s per lane

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

page 11,12,13,14,15

LPC BUS

EC

ENE KB9012

page 38

Thermal Sensor

page 37

page 34

AZALIA

14*USB2.0/ 4*USB3.0,10*USB2.0

6*SATA serial

Int.KBD

page 38

SATA0

SATA1

SATA2

2Channel Speaker

page 36

Array Digital MIC

page 28

Audio Codec

RealTek ALC269-VC

page 36

CMOS Camera

BlueTooth CONN

USB PORT 3.0 x2(Left)

USB PORT 2.0 x2(Right)

WLAN

page 28

page 39

page 31

Audio Jacks

Stereo HeadPhone Output Microphone Input

page 40

page 41

USB PORT 3.0 x1 with USB charger (Right Option)

SATA3.0 HDD (SSD)

SATA3.0 HDD CONN

SATA ODD CONN

page 35

page 31

page 41

2

3

4

www.schematic-x.blogspot.com

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

MB Block Diagram

LA8642P M/B

E

of

2 57Thursday, November 01, 2012

of

2 57Thursday, November 01, 2012

of

2 57Thursday, November 01, 2012

0.1

V

oltage Rails

power plane

1

State

S0

S3

2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2_SUS SMB_EC_DA2_SUS

FCH_SCLK0 FCH_SDATA0

3

SMB_EC_CK2 SMB_EC_DA2

KB9012

+3VALW

KB9012

+3VALW

FCH

+3VS

KB9012

+3VS (LV shifter)

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

4

Device Address

DDR DIMM0

DDR DIMM2

Address Address

0001 011X b

1001 000Xb

1001 010Xb

A

+

B

O

X

VGA BATT KB9012 SODIMM

X V

+3VALW

+5VALW

+3VALW

+1.1VALW

O

X

X X X

X

V V V

X

X X

X

X X

+1.5V

+

1.5V_APU

O

X X

X

WLAN WWAN

X X

V

+3VS +3VS

B

+5VS

+3VS

+2.5VS

+1.5VS

+

1.2VS

+1.1VS

+0.75VS

APU_CORE

+

+APU_CORE_NB

+VGA_CORE

+3.3VGS

+1.8VGS

+1.5VGS

+0.95VGS

OO

X

Thermal Sensor

X

FCH

X XX

V

X

XX XX

X

APU RTD2132

X X

V

+1.5V

X X

X

EC SM Bus2 address

Device

Thermal Sen sor

SB-TSI(default)

VGA(int. thermal)

RTD2132S

VGA(ext. thermal)

A

1001_101xb

1001_100xb

1000_001xb

1010_1000b

0100_1101b

B

C

TATE

S

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

O

HIGH HIGH

HIGHHIGH

HIGH

LOW

LOW LOW

HIGH

N

ON

D

ONONON ON

ON

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

ID BRD ID Ra Rb Vab

R10 MP0

R03 PVT

1

R02 DVT

2

3

USB Port Table

USB 3.0USB 2.0 Port

0 1 2 3 4

4 External USB Port

USB Port (Right Side)

USB Port (Right Side/option)

Mini Card(WLAN) Camera Blue Tooth

5 6 7 8 9

0

10

USB Port (Left Side)

11

USB Port (Left Side)

USB Port (Right Side/option)

12 13

XHCI

1 2 3

USB OC MAPPING

OC# USB Port

USB20 port10,port11

0

USB20 port0

1

USB20 port1,port12

2 3

APU PCIE PORT LIST

Port Device

1

LAN

2

WLAN

FCH PCIE PORT LIST

Port Device

3 4

Card Reader

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

USB30 port0,port1

USB30 port2

1 2 3 4

Compal Secret Data

Deciphered Date

D

BOM Structure Table

PX@ CHG@ NOCHG@ BT@ CMOS@ 8111E@ 8111F@ LAN_E@ LAN_F@ X76@ S1G@ S2G@ H1G@ H2G@ 1403@ 2103@ HDMI@ KBL@ ME@ USBR3@ USBR2@ SSD@ @ 45@ HDMI Logo

LOW

OFF

x

100K

E

0

0V

Ra = R310

8.2K

18K

33K

0.25V

0.5V

0.82VR01 EVT

Rb = R311

BTO ItemBOM Structure

VGA circuit

USB charger part

No USB charger part

Blue Tooth part

CMOS Camera part

RTL8111E LAN part

RTL8111F LAN part

RTL8111E X76

RTL8111F X76

X76 Level part for VRAM

X76 P/N for Samsun VRAM 1G

X76 P/N for Samsun VRAM 2G

X76 P/N for Hynix VRAM 1G

X76 P/N for Hynix VRAM 2G

EMC1403 thermal part

EMC2103 thermal part

HDMI part

K/B Light part

ME part

Right port 3.0

Right port 2.0

SSD

Unpop

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA8642P M/B

E

1

2

3

4

0.1

of

3 57Thursday, November 01, 2012

of

3 57Thursday, November 01, 2012

of

3 57Thursday, November 01, 2012

A

B

C

D

E

Power-Up/Down Sequence

Mars" has the following requirements with regards to power-supply sequencing to

" avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms

‧

f the start of the ramp-up sequence, though a shorter ramp-up duration is

o

1

preferred. The maximum slew rate on all rails is 50mV/us.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up

‧

b

efore or after both VDDC and VDD_CT have ramped up.

‧

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should

reach 90% before VDD_CT starts to ramp up (or vice versa).

‧

For power down, reversing the ramp-up sequence is recommended.

ars XTX VRAM STRAP

M

Total Capacity

Z

ZZ2

H2G@

ZZZ3 S2G@

2

2GB

SK Hynix Gemma 2Gb SA00004GD40/SA00004GD60

GB

128Mx16 H5GQ2H24AFR-T2C Samsung D-die 2Gb SA00005B700/SA00005B710 128Mx16 K4G20325FD-FC04

X76@

Vendor

UV3,UV4,UV5,UV6 UV7,UV8,UV9,UV10

0 0

X76@

PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]

R_pu

R24

0

N

8.45K 2K

10 0

4.53K 2K

00 1

R_pd

R26

C 4.75K

1

VDDR3(+3VGS)

PCIE_VDDC(+0.95VGS)

VDDR1(+1.5VGS)

ZZZ3

ZZZ2

2

VDDC/VDDCI(+VGA_CORE)

VDD_CT(+1.8VGS)

ZZZ2

H1G

H2G@

X7638438Lx1

ZZZ3

S1G

S2G@

X7638438Lx2

0 1 1

1 1 0

6.98K 4.99K

3.4K 10K

2

PERSTb

REFCLK

Straps Reset

Straps Valid

Global ASIC Reset

3

4

A

T4+16clock

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

VGA Notes List

LA8642P M/B

E

of

4 57Thursday, November 01, 2012

of

4 57Thursday, November 01, 2012

of

4 57Thursday, November 01, 2012

3

4

0.1

A

B

C

D

E

CIE_CRX_GTX_P[0..7]

CIE_CRX_GTX_P[0..7]<16>

P

CIE_CRX_GTX_N[0..7]<16>

1

PCIE_CRX_DTX_P0<31>

PCIE_CRX_DTX_N0<31>

PCIE_CRX_DTX_P1<30>

2

PCIE_CRX_DTX_N1<30>

PCIE_CRX_DTX_P3<40> PCIE_CRX_DTX_N3<40>

UMI_RXP0<11>

UMI_RXN0<11> UMI_RXP1<11> UMI_RXN1<11>

UMI_RXP2<11> UMI_RXN2<11> UMI_RXP3<11>

UMI_RXN3<11>

+1.2VS

P

CIE_CRX_GTX_N[0..7]

P

CIE_CRX_GTX_P0

P

CIE_CRX_GTX_N0

P

CIE_CRX_GTX_P1

CIE_CRX_GTX_N1

P P

CIE_CRX_GTX_P2

P

CIE_CRX_GTX_N2

P

CIE_CRX_GTX_P3

P

CIE_CRX_GTX_N3

P

CIE_CRX_GTX_P4

P

CIE_CRX_GTX_N4 CIE_CRX_GTX_P5

P PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7

PCIE_CRX_GTX_N7

1

2

R1 196_0402_1%

P_ZVDDP

AG11

AB8 AB7

AA9 AA8 AA5

AA6

AE5 AE6 AD8

AD7 AC9 AC8

AC5 AC6

AG8

AG9 AG6 AG5

AF7 AF8 AE8

AE9

W9 W8 W5

W6

M8 M7

P P

P P P

P

Y8

P

Y7

P

P P P_GFX_RXP5

P_GFX_RXN5

V8

P_GFX_RXP6

V7

P_GFX_RXN6

U9

P_GFX_RXP7

U8

P_GFX_RXN7

U5

P_GFX_RXP8

U6

P_GFX_RXN8

T8

P_GFX_RXP9

T7

P_GFX_RXN9

R9

P_GFX_RXP10

R8

P_GFX_RXN10

R5

P_GFX_RXP11

R6

P_GFX_RXN11

P8

P_GFX_RXP12

P7

P_GFX_RXN12

N9

P_GFX_RXP13

N8

P_GFX_RXN13

N5

P_GFX_RXP14

N6

P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15

P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1

P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2

P_GPP_RXP3 P_GPP_RXN3

P_UMI_RXP0

P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1

P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3

P_UMI_RXN3

P_ZVDDP

J

CPU1A

_GFX_RXP0 _GFX_RXN0

_GFX_RXP1 _GFX_RXN1 _GFX_RXP2

_GFX_RXN2 _GFX_RXP3 _GFX_RXN3

_GFX_RXP4 _GFX_RXN4

P

CI EXPRESS

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

GPP GRAPHICS

UMI

P

_GFX_TXP0

P

_GFX_TXN0

P

_GFX_TXP1

P

_GFX_TXN1 _GFX_TXP2

P

_GFX_TXN2

P

_GFX_TXP3 _GFX_TXN3

P P

_GFX_TXP4

P

_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5

P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7

P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8

P_GFX_TXP9 P_GFX_TXN9

P_GFX_TXP10

P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11

P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13

P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14

P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2

P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AB2

P

CIE_CTX_C_GRX_P0

AB1

P

CIE_CTX_C_GRX_N0

AA3

P

CIE_CTX_C_GRX_P1

AA2

CIE_CTX_C_GRX_N1

P

Y5

P

CIE_CTX_C_GRX_P2

Y4

P

CIE_CTX_C_GRX_N2

Y2

P

CIE_CTX_C_GRX_P3

Y1

P

CIE_CTX_C_GRX_N3

W3

P

CIE_CTX_C_GRX_P4

W2

P

CIE_CTX_C_GRX_N4

V5

CIE_CTX_C_GRX_P5

P

V4

PCIE_CTX_C_GRX_N5

V2

PCIE_CTX_C_GRX_P6

V1

PCIE_CTX_C_GRX_N6

U3

PCIE_CTX_C_GRX_P7

U2

PCIE_CTX_C_GRX_N7

T5 T4

T2 T1 R3

R2 P5 P4

P2 P1 N3

N2 M5 M4

M2 M1

AD5

PCIE_CTX_C_DRX_P0

AD4

PCIE_CTX_C_DRX_N0

AD2

PCIE_CTX_C_DRX_P1

AD1

PCIE_CTX_C_DRX_N1

AC3 AC2 AB5

PCIE_CTX_C_DRX_P3

AB4

PCIE_CTX_C_DRX_N3

AG2

UMI_TXP0_C

AG3

UMI_TXN0_C

AF4

UMI_TXP1_C

AF5

UMI_TXN1_C

AF1

UMI_TXP2_C

AF2

UMI_TXN2_C

AE2

UMI_TXP3_C

AE3

UMI_TXN3_C

AH11

P_ZVSS

1

R2 196_0402_1%

CIE_CTX_GRX_P[0..7]

P

CIE_CTX_GRX_N[0..7]

1

C

1 0.1U_0402_16V7KPX@

1

C

2 0.1U_0402_16V7KPX@

1

C

3 0.1U_0402_16V7KPX@

1

C

4 0.1U_0402_16V7KPX@

1

5 0.1U_0402_16V7KPX@

C

1

6 0.1U_0402_16V7KPX@

C

1

C

7 0.1U_0402_16V7KPX@

1

C

8 0.1U_0402_16V7KPX@

1

C

9 0.1U_0402_16V7KPX@

1

C

10 0.1U_0402_16V7KPX@

1

C

11 0.1U_0402_16V7KPX@

1

C12 0.1U_0402_16V7KPX@

1

C13 0.1U_0402_16V7KPX@

1

C14 0.1U_0402_16V7KPX@

1

C15 0.1U_0402_16V7KPX@

1

C16 0.1U_0402_16V7KPX@

C33 0.1U_0402_16V7K

C34 0.1U_0402_16V7K

C35 0.1U_0402_16V7K

C36 0.1U_0402_16V7K

C461 0.1U_0402_16V7K

C462 0.1U_0402_16V7K

1

C37 0.1U_0402_16V7K

1

C38 0.1U_0402_16V7K

1

C39 0.1U_0402_16V7K

1

C40 0.1U_0402_16V7K

1

C41 0.1U_0402_16V7K

1

C42 0.1U_0402_16V7K

1

C43 0.1U_0402_16V7K

1

C44 0.1U_0402_16V7K

2

CIE_CTX_GRX_P[0..7] <16>

P

CIE_CTX_GRX_N[0..7] <16>

2

1

2

1

2

1

2

1

2

1

2

1

2

P

CIE_CTX_GRX_P0

P

CIE_CTX_GRX_N0

P

CIE_CTX_GRX_P1

CIE_CTX_GRX_N1

P P

CIE_CTX_GRX_P2

P

CIE_CTX_GRX_N2

P

CIE_CTX_GRX_P3

P

CIE_CTX_GRX_N3

P

CIE_CTX_GRX_P4

P

CIE_CTX_GRX_N4

CIE_CTX_GRX_P5

P PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6

PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_CTX_DRX_P0 <31> PCIE_CTX_DRX_N0 <31>

PCIE_CTX_DRX_P1 <30> PCIE_CTX_DRX_N1 <30>

PCIE_CTX_DRX_P3 <40>

PCIE_CTX_DRX_N3 <40>

UMI_TXP0 <11> UMI_TXN0 <11> UMI_TXP1 <11>

UMI_TXN1 <11> UMI_TXP2 <11> UMI_TXN2 <11>

UMI_TXP3 <11> UMI_TXN3 <11>

LAN

WLAN

Card reader

1

2

3

ZZZ1

LA8642P

DA80000VD00

3

Power Sequence of APU

+1.5V

+2.5VS

+1.5VS

+APU_CORE

4

+APU_CORE_NB

+1.2VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

FS1r2 PCIE/UMI

LA8642P M/B

E

5 57Thursday, November 01, 2012

Group A

Group B

of

4

0.1

A

B

C

D

E

1

J

M28 M27 M24

M25

W26

AF25 AG22 AH18

AD14

AG24 AG25 AG21

AF21 AG17 AG18

AH14 AG14

W27

T27 P24

P25 N27 N26

L26 U26

L27 K27

K25 K24

U27

T28 K28

D14

A18 A22 C25

C15 B15

E18 D18 E22

D22 B26 A26

R26

R27 P27 P28

J26 J27

Y28

V25 Y27

V24 V27 V28

J25 T25

J

CPU1C

MB_ADD0 MB_ADD1

MB_ADD2 MB_ADD3 MB_ADD4

MB_ADD5 MB_ADD6 MB_ADD7

MB_ADD8 MB_ADD9 MB_ADD10

MB_ADD11 MB_ADD12 MB_ADD13

MB_ADD14 MB_ADD15

MB_BANK0

MB_BANK1 MB_BANK2

MB_DM0

MB_DM1 MB_DM2 MB_DM3

MB_DM4 MB_DM5 MB_DM6

MB_DM7

MB_DQS_H0 MB_DQS_L0

MB_DQS_H1 MB_DQS_L1 MB_DQS_H2

MB_DQS_L2 MB_DQS_H3 MB_DQS_L3

MB_DQS_H4 MB_DQS_L4 MB_DQS_H5

MB_DQS_L5 MB_DQS_H6 MB_DQS_L6

MB_DQS_H7 MB_DQS_L7

MB_CLK_H0

MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0

MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

M

EMORY CHANNEL B

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

MB_DATA0 MB_DATA1 MB_DATA2

MB_DATA3 MB_DATA4 MB_DATA5

MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11

MB_DATA12 MB_DATA13 MB_DATA14

MB_DATA15

MB_DATA16 MB_DATA17

MB_DATA18 MB_DATA19 MB_DATA20

MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26

MB_DATA27 MB_DATA28 MB_DATA29

MB_DATA30 MB_DATA31

MB_DATA32

MB_DATA33 MB_DATA34 MB_DATA35

MB_DATA36 MB_DATA37 MB_DATA38

MB_DATA39

MB_DATA40 MB_DATA41

MB_DATA42 MB_DATA43 MB_DATA44

MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50

MB_DATA51 MB_DATA52 MB_DATA53

MB_DATA54 MB_DATA55

MB_DATA56

MB_DATA57 MB_DATA58 MB_DATA59

MB_DATA60 MB_DATA61 MB_DATA62

MB_DATA63

A14 B14 D16

E16 B13 C13

B16 A16

C17

B18 B20 A20

E17 B17 B19

C19

C21 B22

C23 A24 D20

B21 E23 B23

E24 B25 B27

D28 B24 D24

D26 C27

AG26

AH26 AF23 AG23

AG27 AF27 AH24

AE24

AE22 AH22

AE20 AH20 AD23

AD22 AD21 AD20

AF19 AE18 AE16

AH16 AG20 AG19

AF17 AD16

AG15

AD15 AG13 AD13

AG16 AF15 AE14

AF13

DDRB_SDQ0

DDRB_SDQ1

DDRB_SDQ2

DDRB_SDQ3

DDRB_SDQ4

DDRB_SDQ5

DDRB_SDQ6

DDRB_SDQ7

DDRB_SDQ8

DDRB_SDQ9

DDRB_SDQ10

DDRB_SDQ11

DDRB_SDQ12

DDRB_SDQ13

DDRB_SDQ14

DDRB_SDQ15

DDRB_SDQ16

DDRB_SDQ17

DDRB_SDQ18

DDRB_SDQ19

DDRB_SDQ20

DDRB_SDQ21

DDRB_SDQ22

DDRB_SDQ23

DDRB_SDQ24

DDRB_SDQ25

DDRB_SDQ26

DDRB_SDQ27

DDRB_SDQ28

DDRB_SDQ29

DDRB_SDQ30

DDRB_SDQ31

DDRB_SDQ32

DDRB_SDQ33

DDRB_SDQ34

DDRB_SDQ35

DDRB_SDQ36

DDRB_SDQ37

DDRB_SDQ38

DDRB_SDQ39

DDRB_SDQ40

DDRB_SDQ41

DDRB_SDQ42

DDRB_SDQ43

DDRB_SDQ44

DDRB_SDQ45

DDRB_SDQ46

DDRB_SDQ47

DDRB_SDQ48

DDRB_SDQ49

DDRB_SDQ50

DDRB_SDQ51

DDRB_SDQ52 DDRB_SDQ53

DDRB_SDQ54

DDRB_SDQ55

DDRB_SDQ56

DDRB_SDQ57

DDRB_SDQ58

DDRB_SDQ59

DDRB_SDQ60

DDRB_SDQ61

DDRB_SDQ62

DDRB_SDQ63

DDRB_SDQ[63..0] <10>

J

CPU1B

M

EMORY CHANNEL A

DDRA_SMA[15..0]<9>

DDRA_SBS0#<9> DDRA_SBS1#<9> DDRA_SBS2#<9>

DDRA_SDM[7..0]<9>

2

DDRA_SDQS0<9> DDRA_SDQS0#<9> DDRA_SDQS1<9>

DDRA_SDQS1#<9> DDRA_SDQS2<9> DDRA_SDQS2#<9>

DDRA_SDQS3<9> DDRA_SDQS3#<9> DDRA_SDQS4<9>

DDRA_SDQS4#<9> DDRA_SDQS5<9> DDRA_SDQS5#<9>

DDRA_SDQS6<9> DDRA_SDQS6#<9> DDRA_SDQS7<9>

DDRA_SDQS7#<9>

DDRA_CLK0<9> DDRA_CLK0#<9>

DDRA_CLK1<9>

DDRA_CLK1#<9>

DDRA_CKE0<9> DDRA_CKE1<9>

DDRA_ODT0<9>

DDRA_ODT1<9>

3

DDRA_SCS0#<9> DDRA_SCS1#<9>

DDRA_SRAS#<9> DDRA_SCAS#<9> DDRA_SWE#<9>

MEM_MA_RST#<9> MEM_MA_EVENT#<9>

+MEM_VREF

+1.5V_APU

Place them close to APU within 1"

Place them close to APU within 1"Place them close to APU within 1"

15mil

DDRA_SMA0

DDRA_SMA1

DDRA_SMA2 DDRA_SMA3

DDRA_SMA4 DDRA_SMA5

DDRA_SMA6 DDRA_SMA7

DDRA_SMA8

DDRA_SMA9

DDRA_SMA10 DDRA_SMA11

DDRA_SMA12

DDRA_SMA13

DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1

DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6

DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0#

DDRA_SDQS1 DDRA_SDQS1#

DDRA_SDQS2 DDRA_SDQS2#

DDRA_SDQS3

DDRA_SDQS3#

DDRA_SDQS4

DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5#

DDRA_SDQS6 DDRA_SDQS6#

DDRA_SDQS7

DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0#

DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0

DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1

2

R3 39.2_0402_1%

M_ZVDDIO

M21

M22

AA25

AD27

AC23 AD19 AC15

AE26

AD26 AB22 AA22

AB18 AA18 AA14

AA15

AA27

AA26

W24 W23

W20

W21

U20 R20 R21

P22 P21 N24

N23 N20 N21

U23

L24

L21

L20

U24 U21

L23

E14

J17

E21 F25

G14 H14 G18

H18

J21

H21

E27 E26

T21 T22

R23 R24

H28

H27

Y25

V22

V21

H25

T24

MA_ADD0 MA_ADD1 MA_ADD2

MA_ADD3 MA_ADD4 MA_ADD5

MA_ADD6 MA_ADD7 MA_ADD8

MA_ADD9 MA_ADD10 MA_ADD11

MA_ADD12 MA_ADD13 MA_ADD14

MA_ADD15

MA_BANK0 MA_BANK1

MA_BANK2

MA_DM0 MA_DM1

MA_DM2 MA_DM3 MA_DM4

MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1

MA_DQS_L1 MA_DQS_H2 MA_DQS_L2

MA_DQS_H3 MA_DQS_L3 MA_DQS_H4

MA_DQS_L4 MA_DQS_H5 MA_DQS_L5

MA_DQS_H6 MA_DQS_L6 MA_DQS_H7

MA_DQS_L7

MA_CLK_H0 MA_CLK_L0

MA_CLK_H1 MA_CLK_L1

MA_CKE0

MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L

MA_CAS_L MA_WE_L

MA_RESET_L

MA_EVENT_L

M_VREF

M_ZVDDIO

EMORY CHANNEL A

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

MA_DATA0

MA_DATA1 MA_DATA2 MA_DATA3

MA_DATA4 MA_DATA5 MA_DATA6

MA_DATA7

MA_DATA8 MA_DATA9

MA_DATA10 MA_DATA11 MA_DATA12

MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18

MA_DATA19 MA_DATA20 MA_DATA21

MA_DATA22 MA_DATA23

MA_DATA24

MA_DATA25 MA_DATA26 MA_DATA27

MA_DATA28 MA_DATA29 MA_DATA30

MA_DATA31

MA_DATA32 MA_DATA33

MA_DATA34 MA_DATA35 MA_DATA36

MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42

MA_DATA43 MA_DATA44 MA_DATA45

MA_DATA46 MA_DATA47

MA_DATA48

MA_DATA49 MA_DATA50 MA_DATA51

MA_DATA52 MA_DATA53 MA_DATA54

MA_DATA55

MA_DATA56 MA_DATA57

MA_DATA58 MA_DATA59 MA_DATA60

MA_DATA61 MA_DATA62 MA_DATA63

E13

J13 H15 J15

H13 F13 F15

E15

H17 F17

E19 J19 G16

H16 H19 F19

H20 F21 J23

H23 G20 E20

G22 H22

G24

E25 G27 G26

F23 H24 E28

F27

AB28 AC27

AD25 AA24 AE28

AD28 AB26 AC25

Y23 AA23 Y21

AA20 AB24 AD24

AA21 AC21

AA19

AC19 AC17 AA17

AB20 Y19 AD18

AD17

AA16 Y15

AA13 AC13 Y17

AB16 AB14 Y13

DDRA_SDQ0

DDRA_SDQ1

DDRA_SDQ2

DDRA_SDQ3

DDRA_SDQ4

DDRA_SDQ5 DDRA_SDQ6

DDRA_SDQ7

DDRA_SDQ8

DDRA_SDQ9

DDRA_SDQ10

DDRA_SDQ11

DDRA_SDQ12

DDRA_SDQ13

DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18

DDRA_SDQ19

DDRA_SDQ20

DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24

DDRA_SDQ25 DDRA_SDQ26

DDRA_SDQ27

DDRA_SDQ28

DDRA_SDQ29

DDRA_SDQ30

DDRA_SDQ31

DDRA_SDQ32

DDRA_SDQ33

DDRA_SDQ34

DDRA_SDQ35

DDRA_SDQ36

DDRA_SDQ37

DDRA_SDQ38

DDRA_SDQ39

DDRA_SDQ40

DDRA_SDQ41

DDRA_SDQ42

DDRA_SDQ43

DDRA_SDQ44

DDRA_SDQ45

DDRA_SDQ46

DDRA_SDQ47

DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ52

DDRA_SDQ53

DDRA_SDQ54

DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDQ58

DDRA_SDQ59 DDRA_SDQ60

DDRA_SDQ61

DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] <9>

DDRB_SMA[15..0]<10>

DDRB_SBS0#<10> DDRB_SBS1#<10>

DDRB_SBS2#<10>

DDRB_SDM[7..0]<10>

DDRB_SDQS0<10>

DDRB_SDQS0#<10>

DDRB_SDQS1<10>

DDRB_SDQS1#<10>

DDRB_SDQS2<10>

DDRB_SDQS2#<10>

DDRB_SDQS3<10>

DDRB_SDQS3#<10>

DDRB_SDQS4<10>

DDRB_SDQS4#<10>

DDRB_SDQS5<10>

DDRB_SDQS5#<10>

DDRB_SDQS6<10>

DDRB_SDQS6#<10>

DDRB_SDQS7<10>

DDRB_SDQS7#<10>

DDRB_CLK0<10>

DDRB_CLK0#<10>

DDRB_CLK1<10> DDRB_CLK1#<10>

DDRB_CKE0<10> DDRB_CKE1<10>

DDRB_ODT0<10> DDRB_ODT1<10>

DDRB_SCS0#<10>

DDRB_SCS1#<10>

DDRB_SRAS#<10>

DDRB_SCAS#<10> DDRB_SWE#<10>

MEM_MB_RST#<10> MEM_MB_EVENT#<10>

DDRB_SMA0

DDRB_SMA1

DDRB_SMA2

DDRB_SMA3

DDRB_SMA4

DDRB_SMA5

DDRB_SMA6

DDRB_SMA7

DDRB_SMA8

DDRB_SMA9

DDRB_SMA10

DDRB_SMA11

DDRB_SMA12

DDRB_SMA13

DDRB_SMA14

DDRB_SMA15

DDRB_SBS0# DDRB_SBS1#

DDRB_SBS2#

DDRB_SDM0

DDRB_SDM1

DDRB_SDM2

DDRB_SDM3

DDRB_SDM4

DDRB_SDM5

DDRB_SDM6

DDRB_SDM7

DDRB_SDQS0

DDRB_SDQS0#

DDRB_SDQS1 DDRB_SDQS1#

DDRB_SDQS2 DDRB_SDQS2#

DDRB_SDQS3 DDRB_SDQS3#

DDRB_SDQS4 DDRB_SDQS4#

DDRB_SDQS5

DDRB_SDQS5#

DDRB_SDQS6 DDRB_SDQS6#

DDRB_SDQS7 DDRB_SDQS7#

DDRB_CLK0

DDRB_CLK0#

DDRB_CLK1

DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_SCS0# DDRB_SCS1#

DDRB_SRAS# DDRB_SCAS#

DDRB_SWE#

MEM_MB_RST# MEM_MB_EVENT#

1

2

3

EVENT# pull high 0.75V reference voltage

+1.5V_APU

4

1

R5 1K_0402_5%

R6 1K_0402_5%

2

1

2

MEM_MA_EVENT#

MEM_MB_EVENT#

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V_APU

2

1

2

1

B

1

C45

1000P_0402_50V7K

2

15mil

+MEM_VREF

2

C46

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

LA8642P M/B

6 57Thursday, November 01, 2012

E

of

4

0.1

1

M M

M

ML_VGA_TXP2< 12> ML_VGA_TXN2<12>

ML_VGA_TXP3< 12> ML_VGA_TXN3<12>

C61~C68 Close Connector

2

APU_RST#< 11>

APU_PWRGD<11,51>

ESD request

2

@

3

C

1

2

48 0.1U_0402_16V7K

C

1

2

50 0.1U_0402_16V7K

C

1

2

C

51 0.1U_0402_16V7K

1

2

C

52 0.1U_0402_16V7K

LVDS_HPD <26>

FCH_CRT_HPD <12> HDMI_DET <29>

DP_INT_PWM <26>

1

R15 150_0402_1%

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

2

1

R16 1K_0402_5%

R17 1K_0402_5%

R18 1K_0402_5%

R1457 1K_0402_5%

R21 510_0402_1%

R25 510_0402_1%

R27 39.2_0402_1%

R29 300_0402_5%HDM I@

R30 300_0402_5%@

R32 10K_0402_5%

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

ALLOW_STOP <11>

P0_AUXP_C <26>

D

P0_AUXN_C <26>

D

M

L_VGA_AUXP_C <12>

M

L_VGA_AUXN_C <12>

H

DMI_CLK <29>

DMI_DATA <29>

H

+1.2VS

+1.5V_APU

+3VALW

To LVDS Translater

To FCH

To HDMI

P0_TXP0

D

P0_TXN0

D

P1_TXP0

D

P1_TXN0

D

P1_TXP1

D

P1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3

DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2

DP2_TXN2

DP2_TXP3 DP2_TXN3

AE11

AD11

AB11 AA11

AG12 AH12

AF10

AB12

AC10 AE12

AF12

B

L3

L2

K5 K4

K2 K1

J3

J2

H5 H4

H2 H1

G3

G2

F2 F1

L9 L8

L5

L6

K8 K7

J6 J5

B3 A3

C3

H10

J10

F10 G10

F9

G9 H9

B4

C5

A4 A5

C4

B5

NALOG/DISPLAY/MISC

A

P0_TXP0

D

P0_TXN0

D

P0_TXP1 P0_TXN1

D

P0_TXP2

D

P0_TXN2

D

P0_TXP3

D

P0_TXN3

P1_TXP0

D D

P1_TXN0

D

P1_TXP1

D

P1_TXN1

DP1_TXP2

DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1

DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

CLKIN_H

CLKIN_L

DISP_CLKIN_H DISP_CLKIN_L

SVC SVD

SVT

SIC SID

RESET_L

PWROK

PROCHOT_L THERMTRIP_L

ALERT_L

TDI TDO

TCK TMS TRST_L

DBRDY DBREQ_L

VSS_SENSE

VDDP_SENSE VDDNB_SENSE VDDIO_SENSE

VDD_SENSE VDDR_SENSE

VDS

L

To FCH

HDMI

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

CTRL SER. CLK

JTAG

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY P ORT 1

SENSE

J

CPU1D

DISPLAY PORT MISC.

DP_VARY_BL

DP_AUX_ZVSS

TEST

DMAACTIVE_L

RSVD

P0_AUXP

D

P0_AUXN

D

P1_AUXP P1_AUXN

D

P2_AUXP

D

P2_AUXN

D

P3_AUXP

D

P3_AUXN

P4_AUXP

D D

P4_AUXN

D

P5_AUXP

D

P5_AUXN

DP0_HPD

DP1_HPD DP2_HPD DP3_HPD

DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

TEST6 TEST9

TEST10

TEST14 TEST15 TEST16

TEST17 TEST18 TEST19

TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

FS1R2

TEST4

TEST5

RSVD1 RSVD2

RSVD3 RSVD4

D1

P0_AUXP

D

D2

P0_AUXN

D

E1

M

L_VGA_AUXP

E2

M

L_VGA_AUXN

D5 D6

E5

E6

F5 F6

G5 G6

D3

E3 D7 E7

F7 G7

C6

B6 A6

C1

DP_AUX_ZVSS

AD12 M18 N18

F11 G11 H11

J11 F12

APU_TEST18

G12

APU_TEST19

J12

APU_TEST20

H12

APU_TEST24

AE10

TEST25_H

AD10

TEST25_L

L10 M10

P19 R19 K22

APU_TEST31

T19 N19 AA12

APU_TEST35

W10

FS1R2

AC12

P18

R18

Y10 AA10

Y12 K21

A

P

lace near APU

1

2

47 0.1U_0402_16V7K

C

P0_TXP0_C<26>

D

P0_TXN0_C<26 >

D

L_VGA_TXP0<12> L_VGA_TXN0<12>

L_VGA_TXP1<12>

L_VGA_TXN1<12>

HDMI_TX2P<29> HDMI_TX2N<29>

HDMI_TX1P<29> HDMI_TX1N<29>

HDMI_TX0P<29>

HDMI_TX0N<29>

HDMI_CLKP<29> HDMI_CLKN<29>

APU_SVC<51>

APU_SVD<51>

APU_SVT<51>

1

APU_PWRGD

C465100P_0402_50V8J

C

1

49 0.1U_0402_16V7K

C

P

lace near APU

C61 0.1U_0402_16V7KHDMI@

C62 0.1U_0402_16V7KHDMI@

C63 0.1U_0402_16V7KHDMI@

C64 0.1U_0402_16V7KHDMI@

C65 0.1U_0402_16V7KHDMI@

C66 0.1U_0402_16V7KHDMI@

C67 0.1U_0402_16V7KHDMI@

C68 0.1U_0402_16V7KHDMI@

Route as differential with APU_VDD_SEN_L

1

53 0.1U_0402_16V7K

C

1

C

54 0.1U_0402_16V7K

1

C

55 0.1U_0402_16V7K

1

C

56 0.1U_0402_16V7K

1

C57 0.1U_0402_16V7K

1

C58 0.1U_0402_16V7K

1

C59 0.1U_0402_16V7K

1

C60 0.1U_0402_16V7K

1

APU_CLK<11>

APU_CLK#<11>

APU_DISP_CLK<11> APU_DISP_CLK#<11>

APU_PROCHOT#<11>

APU_VDD_SEN_L<51>

APU_VDDNB_SEN_H<51>

APU_VDD_SEN_H<51>

2

APU_SIC

APU_SID

APU_PWRGD

APU_THERMTRIP#

ALERT_L

APU_TDI APU_TDO

APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

D

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

THERMTRIP shutdown temperature: 125 degree

1K_0402_5%

APU_THERMTRIP#

+1.5V_APU

R12

1K_0402_5%

+1.5V_APU

1

2

R22

2

1

B

2

E

3

MMBT3904_NL_SOT23-3

f not used, pins are left unconnected (DG ref.)

I 20101111

M

L_VGA_AUXP

M

L_VGA_AUXN

D

P0_AUXP

D

P0_AUXN

+3VS

2

1

R23

R23 10K_0402_5%

10K_0402_5%

Q2

1

C

1

R13

10K_0402_5%

@

2

B

Q1

1

C

@

MMBT3904_NL_SOT23-3

1

R45 0_0402_5%

1

R28 0_0402_5%

1

R1449 0_0402_5%

@

E

3

2

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the FCH to transition the system to S5 immediately

E

2

R

8 1.8K_0402_5%

2

R

9 1.8K_0402_5%

2

10 1.8K_0402_5%

R

2

R

11 1.8K_0402_5%

1

R1456

R1456 10K_0402_5%

10K_0402_5%

@

2

H_PROCHOT# <36,44,51>

2

1

H_THERMTRIP# <13>

MAINPWON <36,44,46>

1

2

3

+1.5V_APU

1

R42 1K_0402_5%

1

R43 1K_0402_5%

1

R47 1K_0402_5%

1

R348 1K_0402_5%@

+1.5VS

1

R52 300_0402_5%

1

R56 300_0402_5%

1

R40 1K_0402_5%@

1

R35 1K_0402_5%@

1

R38 1K_0402_5%@

4

1

R49 1K_0402_5%

2

APU_SIC

APU_SID

ALERT_L

ALLOW_STOP

APU_RST#

APU_PWRGD

APU_SVT

APU_SVC

APU_SVD

ALLOW_STOP

A

CPU TSI interface level shift

C69 0.1U_0402_16V4Z

1

2

R33

+3VS

31.6K_0402_1%

G

2

B

3

S

BSH111 1N_SOT23-3

G

2

3

S

BSH111 1N_SOT23-3

APU_SID

APU_SIC

1

2

1

R34

30K_0402_1%

Q3

1

D

Q6

1

D

BSH111, the Vgs is: min = 0.4V Max = 1.3V

2

EC_SMB_DA2_SUS <36>

EC_SMB_CK2_SUS <36>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

To EC

2012/07/03 2013/07/03

C

+1.5V

2

R36

R36 1K_0402_5%

1K_0402_5%

1

APU_TRST#

Compal Secret Data

Deciphered Date

+1.5V

1

R46 10K_0402_5%

R48 10K_0402_5%

R50 10K_0402_5%

2

1

2

1

2

D

HDT Debug conn

JHDT1

1

3

5

7

9

11

13

15

17

19

SAMTE_ASP-136446-07-B

@

2

1

3

5

7

9

11

13

15

17

19

APU_TCK

2

4

APU_TMS

4

6

APU_TDI

6

8

APU_TDO

8

10

APU_PWRGD

10

12

APU_RST#

12

14

APU_DBRDY

14

16

APU_DBREQ#

16

18

1

R53 0_0402_5%

18

20

Title

Size Document Number Rev

Custom

Date: Sheet

1

20

R55 0_0402_5%

Compal Electronics, Inc.

1

R39 1K_0402_5%

1

R37 1K_0402_5%

1

R41 1K_0402_5%

1

R51 1K_0402_5%

2

APU_TEST19

2

APU_TEST18

FS1r2 Display/MISC/HDT

LA8642P M/B

E

+1.5V

2

4

0.1

of

7 57Thursday, November 01, 2012

of

7 57Thursday, November 01, 2012

of

7 57Thursday, November 01, 2012

Power Name

DD

V +APU_CORE

DDNB

V +APU_CORE_NB

VDDIO +1.5V

V

DDP / VDDR

+1.2VS

VDDA

1

+2.5VS

2

3

Consumption

5

A / 3.5A

VDDP decoupling

180P_0402_50V8J

C

107

106

1

2

180P_0402_50V8J

0A

6

29A

3

.2A

.5A

0

C

C 108

108

0.22U_0402_6.3V6K

1

2

A

+APU_CORE_NB

+1.2VS

0.22U_0402_6.3V6K

C

109

1

2

+1.5V_APU

+

APU_CORE

F8

DD_1

V

H6

V

DD_2

J1

DD_3

V

J14

V

DD_4

P6

V

DD_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

F3

VDD_18

L18

VDD_19

V6

VDD_20

W1

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

R1

VDD_27

P3

VDD_28

K10

VDD_29

H3

VDD_30

M19

VDD_31

C8

VDDNB_1

D10

VDDNB_2

B8

VDDNB_3

B12

VDDNB_4

C9

VDDNB_5

A9

VDDNB_6

A10

VDDNB_7

A8

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

J

CPU1E

DD_32

V

DD_33 DD_34

V V

DD_35

V

DD_36 VDD_37 VDD_38

VDD_39 VDD_40 VDD_41

VDD_42 VDD_43 VDD_44

VDD_45 VDD_46 VDD_47

VDD_48 VDD_49 VDD_50

VDD_51 VDD_52 VDD_53

VDD_54 VDD_55 VDD_56

VDD_57 VDD_58 VDD_59

VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15

VDDNB_16 VDDNB_17 VDDNB_18

VDDNB_19 VDDNB_20 VDDNB_21

VDDNB_22 VDDNB_23

VDDNB_CAP_1

VDDNB_CAP_2

VDDIO_19 VDDIO_20

VDDIO_21 VDDIO_22 VDDIO_23

VDDIO_24 VDDIO_25 VDDIO_26

VDDIO_27 VDDIO_28 VDDIO_29

VDDIO_30 VDDIO_31 VDDIO_32

VDDIO_33 VDDIO_34 VDDIO_35

VDDIO_36

VDDR_1 VDDR_2

VDDR_3 VDDR_4

B

+

APU_CORE

R11

T10 H8 G1

U11 W11 W13

W15 W17 W19

AB3 AD3 AD6

AE1 L1 Y6

M6 N11 N1

T3 T6 U19

U1 Y16 Y18

Y3 D4 F4

AF6 AF3 L11

C11 C12 D9

D8 D12 D11

B11 A12 B10

E12 B9

K13

K12

T23 T26

U22 U25 U28

Y26 T20 R28

R25 R22 V20

V23 V26 W22

W25 W28 Y24

G28

AG10 AH8

AH9 AH10

+APU_CORE_NB

+1.5V_APU

180P_0402_50V8J

C110

1

2

+

APU_CORE

0.22U_0402_6.3V6K

C70

1

2

+APU_CORE_NB

0.22U_0402_6.3V6K

C77

1

2

+1.5V_APU

+VDDNB_CAP

22U_0603_6.3V6M

C100

C105

C99

1

2

Northbridge Power Pins for Remote Decoupling

180P_0402_50V8J

1000P_0402_50V7K

C111

C112

1

2

C

0.01U_0402_16V7K

0.22U_0402_6.3V6K

C72

C71

C75

1

2

0.22U_0402_6.3V6K

C78

1

2

1

2

180P_0402_50V8J

C80

C79

1

2

180P_0402_50V8J

0.01U_0402_16V7K

C76

1

2

180P_0402_50V8J

C81

1

2

180P_0402_50V8J

C73

C74

1

2

D

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

22U_0603_6.3V6M

C83

22U_0603_6.3V6M

C84

1

2

180P_0402_50V8J

VDDR decoupling

C117

0.22U_0402_6.3V6K

C116

1

2

22U_0603_6.3V6M

4.7U_0603_6.3V6K

C86

22U_0603_6.3V6M

C85

1

2

4.7U_0603_6.3V6K

C87

1

2

4.7U_0603_6.3V6K

C88

C89

1

2

0.22U_0402_6.3V6K

4.7U_0603_6.3V6K

C90

1

2

+1.5V

C101

C91

1

2

+1.5V

0.22U_0402_6.3V6K

C92

C93

1

2

0.22U_0402_6.3V6K

C93

1

2

across VDDIO a nd VSS split

0.22U_0402_6.3V6K

180P_0402_50V8J

C102

C104

1

2

C114

1

0.22U_0402_6.3V6K

C95

C94

1

2

180P_0402_50V8J

1

2

J2

@

J2

@

PAD-OPEN 4x4m

0.22U_0402_6.3V6K

2

180P_0402_50V8J

0.22U_0402_6.3V6K

C97

C96

1

2

+1.5V_APU

330U_2.5V_M

C98

1

+

2

Need Short

+1.2VS

0.22U_0402_6.3V6K

1

2

E

CPU1F

J

J20

V

SS_1

L4

SS_2

V

R7

V

SS_3

W18

V

SS_4

A15

V

SS_5

AB17

V

SS_6

AC22

V

SS_7

AE21

V

SS_8

AF24

SS_9

V

AH23

SS_10

V

AH25

V

SS_11

B7

SS_12

V

C14

V

SS_13

C16

V

SS_14

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

V

SS_73 SS_74

V

SS_75

V

SS_76

V

SS_77

V

SS_78

V

SS_79

V

SS_80

SS_81

V

SS_82

V V

SS_83

SS_84

V V

SS_85

V

SS_86

VSS_87 VSS_88 VSS_89

VSS_90 VSS_91 VSS_92

VSS_93 VSS_94 VSS_95

VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101

VSS_102 VSS_103 VSS_104

VSS_105 VSS_106 VSS_107

VSS_108 VSS_109 VSS_110

VSS_111 VSS_112 VSS_113

VSS_114 VSS_115 VSS_116

VSS_117 VSS_118 VSS_119

VSS_120 VSS_121 VSS_122

VSS_123 VSS_124 VSS_125

VSS_126 VSS_127 VSS_128

VSS_129 VSS_130 VSS_131

VSS_132 VSS_133 VSS_134

VSS_135 VSS_136 VSS_137

VSS_138 VSS_139 VSS_140

VSS_141 VSS_142 VSS_143

A19 A21

A23 A25 A7

AA4 AA7 AB13

AB15 AB19 AB21

AB23 AB25 AB27

AB9 AC14 AC16

AC18 AC20 AC24

AC26 AC28 AC4

AC7 AD9 AE13

AE15 AE17 M9

N10 N4 N7

R10 R4 T11

T9 U10 U18

U4 U7 V11

AE19 AE23 AE25

AE27 AE4 AE7

AF14 AF16 AF18

AF20 AF22 AF26

AF28 AF9 AG4

AG7 AH13 AH15

AH17 AH19 AH21

P9 C18 D21

W14 P11 C7

E8 K18 W12

1

2

3

Demo Board Capacitor

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

CORE_NB_CAP 22uF x 2 180pF x 1

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

4

+2.5VS

L1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

2

3300P_0402_50V7K

C

119

118

1

2

Check

A

0.22U_0402_6.3V6K

40mil

+VDDA

4.7U_0402_6.3V6M

C120

1

2

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

D

VDDP

0.22uF x 2 180pF x 2

VDDR

0.22uF x 2 1nF x 4 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

FS1r2 PWR/GND

LA8642P M/B

E

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

of

8 57Thursday, November 01, 2012

of

8 57Thursday, November 01, 2012

of

8 57Thursday, November 01, 2012

4

0.1

A

B

C

D

E

1

2

3

+3VS

4

R251 10K_0402_5%

1

2

@

+3VS

C131

2.2U_0603_6.3V6K

D

DRA_SDQS1#<6>

DDRA_SDQS1<6>

DDRA_SDQS2#<6>

DDRA_SDQS2<6>

DDRA_CKE0<6>

DDRA_SBS2#<6>

DDRA_CLK0<6> DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6>

DDRA_SCS1#<6>

DDRA_SDQS4#<6> DDRA_SDQS4<6>

DDRA_SDQS6#<6> DDRA_SDQS6<6>

DDRA_SA0

1

2

VREF_DQ

+

R69 10K_0402_5%

1

C132

0.1U_0402_16V4Z

2

D

DRA_SDQ0

D

DRA_SDQ1

D

DRA_SDM0

DRA_SDQ2

D

DRA_SDQ3

D

DRA_SDQ8

D

DRA_SDQ9

D

DRA_SDQS1#

DRA_SDQS1

D

DDRA_SDQ10

DDRA_SDQ11

DDRA_SDQ16

DDRA_SDQ17

DDRA_SDQS2#

DDRA_SDQS2

DDRA_SDQ18

DDRA_SDQ19

DDRA_SDQ24

DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26

DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12

DDRA_SMA9

DDRA_SMA8

DDRA_SMA5

DDRA_SMA3

DDRA_SMA1

DDRA_CLK0

DDRA_CLK0#

DDRA_SMA10

DDRA_SBS0#

DDRA_SWE#

DDRA_SCAS#

DDRA_SMA13

DDRA_SCS1#

DDRA_SDQ32

DDRA_SDQ33

DDRA_SDQS4#

DDRA_SDQS4

DDRA_SDQ34

DDRA_SDQ35

DDRA_SDQ40

DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42

DDRA_SDQ43

DDRA_SDQ48

DDRA_SDQ49

DDRA_SDQS6#

DDRA_SDQS6

DDRA_SDQ50

DDRA_SDQ51

DDRA_SDQ56

DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58

DDRA_SDQ59

2

DDRA_SA0

1

R1450

R1450 10K_0402_5%

10K_0402_5%

2

1.5V

+

DIMM1

J

1

V

REF_DQ

3

SS2

V

5

D

Q0

7

D

Q1

9

V

SS4

11

D

M0

13

V

SS5

15

D

Q2

17

Q3

D

19

SS7

V

21

D

Q8

23

Q9

D

25

V

SS9

27

D

QS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

V

D

QS#0

D V

V

D

V

SS10

RESET#

VSS12

DQ14

DQ15

VSS14

DQ20

DQ21

VSS16

VSS17

DQ22

DQ23

VSS19

DQ28

DQ29

VSS21 DQS#3

DQS3

VSS24

DQ30

DQ31

VSS26

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36

DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47

VSS40

DQ52

DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

SS1

D

D SS3

QS0 SS6

D

D SS8

D

DM2

CK1

BA1

NC2

DM4

DM6

SDA

SCL

1.5V

+

2

4

D

Q4

Q5

Q6

Q7

Q12

Q13

M1

A15

A14

A11

A7

A6

A4

A2 A0

S0#

G2

DRA_SDQ4

6

D

DRA_SDQ5

8

10

D

DRA_SDQS0#

12

D

DRA_SDQS0

14

16

DRA_SDQ6

D

18

D

DRA_SDQ7

20

22

D

DRA_SDQ12

24

D

DRA_SDQ13

26

28

D

DRA_SDM1

30

EM_MA_RST#

M

32

34

DDRA_SDQ14

36

DDRA_SDQ15

38

40

DDRA_SDQ20

42

DDRA_SDQ21

44

46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

DDRA_SMA15

80

DDRA_SMA14

82

84

DDRA_SMA11

86

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94

96

DDRA_SMA2

98

DDRA_SMA0

100

102

DDRA_CLK1

104

DDRA_CLK1#

106

108

DDRA_SBS1#

110

DDRA_SRAS#

112

114

DDRA_SCS0#

116

DDRA_ODT0

118

120

DDRA_ODT1

122

124

126 128

130

DDRA_SDQ36

132

DDRA_SDQ37

134

136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172

174

DDRA_SDQ54

176

DDRA_SDQ55

178

180

DDRA_SDQ60

182

DDRA_SDQ61

184

186

DDRA_SDQS7#

188

DDRA_SDQS7

190

192

DDRA_SDQ62

194

DDRA_SDQ63

196

198

MEM_MA_EVENT#

200

202

204

206

+0.75VS

DRA_SDQS0# <6>

D

DRA_SDQS0 <6>

MEM_MA_RST# <6>

DDRA_SDQS3# < 6>

DDRA_SDQS3 < 6>

DDRA_CKE1 <6>

DDRA_CLK1 <6> DDRA_CLK1# <6>

DDRA_SBS1# <6>

DDRA_SRAS# <6>

DDRA_SCS0# <6>

DDRA_ODT0 <6>

DDRA_ODT1 <6>

+VREF_CA

DDRA_SDQS5# < 6>

DDRA_SDQS5 < 6>

DDRA_SDQS7# < 6> DDRA_SDQS7 < 6>

MEM_MA_EVENT# <6>

FCH_SDATA0 <10,13,30>

FCH_SCLK0 <10,13,30>

D

DRA_SDQ[0..63]

D

DRA_SDM[0..7]

DRA_SMA[0..15]

D

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

0.1U_0402_16V4Z

C121

1

C127

2

0.1U_0402_16V4Z

D

DRA_SDQ[0..63] <6>

D

DRA_SDM[0..7] <6>

D

DRA_SMA[0..15] <6>

2

C122

1

0.1U_0402_16V4Z

+VREF_DQ

1

2

1000P_0402_50V7K

2

1

C128

C123

0.1U_0402_16V4Z

2

C124

1

+1.5V

2

R65

1K_0402_1%

1

2

R67

R67 1K_0402_1%

1K_0402_1%

1

Place near DIMM1

2

C125

1

0.1U_0402_16V4Z

2

C126

1

+VREF_CA

1

2

+1.5V

2

R66

R66 1K_0402_1%

1K_0402_1%

15mil15mil

+VREF_CA

1

C129

2

0.1U_0402_16V4Z

1000P_0402_50V7K

1

2

1

C130

R68

R68 1K_0402_1%

2

1K_0402_1%

1

3

4

Security Classification

Issued Date

standard H:8mm

<Address: 00>

A

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDRIII SO-DIMM 1

LA8642P M/B

9 57Thursday, November 01, 2012

E

0.1

of

A

B

C

D

E

1.5V

DDRB_SA0

1

2

+

R72

10K_0402_5%

DIMM2

J

1

V

REF_DQ

3

SS2

V

5

D

Q0

7

D

Q1

9

V

SS4

11

D

M0

13

V

SS5

15

D

Q2

17

Q3

D

19

SS7

V

21

D

Q8

23

Q9

D

25

V

SS9

27

D

QS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

V

SS1

D D

V

SS3

D

QS#0

D

QS0

V

SS6

D D

SS8

V

D

Q12 Q13

D

V

SS10

D

RESET#

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22

DQ23

VSS19

DQ28

DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30

DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38

DQ39

VSS33

DQ44

DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46

DQ47

VSS40

DQ52

DQ53

VSS42

DM6

VSS43

DQ54

DQ55

VSS45

DQ60

DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63

VSS52

EVENT#

SDA

SCL

VTT2

VREF_DQ

+

D

DRB_SDQ0

D

DRB_SDQ1

D

DRB_SDM0

DRB_SDQ2

D

1

D

DRB_SDQS1#<6>

DDRB_SDQS1<6>

DDRB_SDQS2#<6>

DDRB_SDQS2<6>

DDRB_CKE0<6>

2

3

4

R253 10K_0402_5%

1

+3VS

@

DDRB_SBS2#<6>

DDRB_CLK0<6> DDRB_CLK0#<6>

DDRB_SBS0#<6>

DDRB_SWE#<6>

DDRB_SCAS#<6>

DDRB_SCS1#<6>

DDRB_SDQS4#<6> DDRB_SDQS4<6>

DDRB_SDQS6#<6> DDRB_SDQS6<6>

R71 10K_0402_5%

1

2

DDRB_SA0

2

DRB_SDQ3

D

DRB_SDQ8

D

DRB_SDQ9

D

DRB_SDQS1#

DRB_SDQS1

D

DDRB_SDQ10

DDRB_SDQ11

DDRB_SDQ16

DDRB_SDQ17

DDRB_SDQS2#

DDRB_SDQS2

DDRB_SDQ18

DDRB_SDQ19

DDRB_SDQ24

DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26

DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#

DDRB_SMA12

DDRB_SMA9

DDRB_SMA8

DDRB_SMA5

DDRB_SMA3

DDRB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRB_SMA10

DDRB_SBS0#

DDRB_SWE#

DDRB_SCAS#

DDRB_SMA13

DDRB_SCS1#

DDRB_SDQ32

DDRB_SDQ33

DDRB_SDQS4#

DDRB_SDQS4

DDRB_SDQ34

DDRB_SDQ35

DDRB_SDQ40 DDRB_SDQ41

DDRB_SDM5

DDRB_SDQ42

DDRB_SDQ43

DDRB_SDQ48

DDRB_SDQ49

DDRB_SDQS6#

DDRB_SDQS6

DDRB_SDQ50

DDRB_SDQ51

DDRB_SDQ56

DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58

DDRB_SDQ59

Standard H:4mm

<Address: 01>

A

1.5V

+

2

4

D

Q4 Q5

Q6 Q7

M1

A15

A14

A11

A7

A6

A4

A2

A0

S0#

G2

B

DRB_SDQ4

6

D

DRB_SDQ5

8

10

D

DRB_SDQS0#

12

D

DRB_SDQS0

14

16

DRB_SDQ6

D

18

D

DRB_SDQ7

20

22

D

DRB_SDQ12

24

D

DRB_SDQ13

26

28

D

DRB_SDM1

30

EM_MB_RST#

M

32

34

DDRB_SDQ14

36

DDRB_SDQ15

38

40

DDRB_SDQ20

42

DDRB_SDQ21

44

46

DDRB_SDM2

48

50

DDRB_SDQ22

52

DDRB_SDQ23

54

56

DDRB_SDQ28

58

DDRB_SDQ29

60

62

DDRB_SDQS3#

64

DDRB_SDQS3

66

68

DDRB_SDQ30

70

DDRB_SDQ31

72

74

DDRB_CKE1

76

78

DDRB_SMA15

80

DDRB_SMA14

82

84

DDRB_SMA11

86

DDRB_SMA7

88

90

DDRB_SMA6

92

DDRB_SMA4

94 96

DDRB_SMA2

98

DDRB_SMA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_SBS1#

110

DDRB_SRAS#

112 114

DDRB_SCS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122

124 126

128

130

DDRB_SDQ36

132

DDRB_SDQ37

134

136

DDRB_SDM4

138

140

DDRB_SDQ38

142

DDRB_SDQ39

144

146

DDRB_SDQ44

148

DDRB_SDQ45

150

152

DDRB_SDQS5#

154

DDRB_SDQS5

156

158

DDRB_SDQ46

160

DDRB_SDQ47

162

164

DDRB_SDQ52

166

DDRB_SDQ53

168

170

DDRB_SDM6

172 174

DDRB_SDQ54

176

DDRB_SDQ55

178 180

DDRB_SDQ60

182

DDRB_SDQ61

184 186

DDRB_SDQS7#

188

DDRB_SDQS7

190 192

DDRB_SDQ62

194

DDRB_SDQ63

196 198

MEM_MB_EVENT#

200

202 204

206

+0.75VS

DRB_SDQS0# <6>

D

DRB_SDQS0 <6>

MEM_MB_RST# <6>

DDRB_SDQS3# < 6> DDRB_SDQS3 < 6>

DDRB_CKE1 <6>

DDRB_CLK1 <6> DDRB_CLK1# <6>

DDRB_SBS1# <6> DDRB_SRAS# <6>

DDRB_SCS0# <6>

DDRB_ODT0 <6>

DDRB_ODT1 <6>

+VREF_CA

DDRB_SDQS5# < 6> DDRB_SDQS5 < 6>

DDRB_SDQS7# < 6>

DDRB_SDQS7 < 6>

MEM_MB_EVENT# <6>

FCH_SDATA0 <9,13,30> FCH_SCLK0 < 9,13,30>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

D

DRB_SDQ[0..63]

D

DRB_SDM[0..7]

DRB_SMA[0..15]

D

2012/07/03 2013/07/03

D

DRB_SDQ[0..63] <6>

D

DRB_SDM[0..7] <6>

D

DRB_SMA[0..15] <6>

Compal Secret Data

Deciphered Date

0.1U_0402_16V4Z

C143

0.1U_0402_16V4Z

D

+

VREF_DQ

0.1U_0402_16V4Z

+1.5V

1

5mil 15mil

VREF_DQ

+

1000P_0402_50V7K

C134

C133

1

2

0.1U_0402_16V4Z

2

C137

1

+0.75VS

2

1

0.1U_0402_16V4Z

2

C138

1

C144

4.7U_0603_6.3V6K

2

0.1U_0402_16V4Z

2

C139

1

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

+

VREF_CA

+

1000P_0402_50V7K

0.1U_0402_16V4Z

C135

1

2

C136

2

Place near DIMM2

0.1U_0402_16V4Z

2

C141

1

0.1U_0402_16V4Z

2

C142

1

+1.5V

1

+

C145

220U_6.3V_M

2

@

2

C140

1

SF000002Y00

Compal Electronics, Inc.

DDRIII SO-DIMM 2

LA8642P M/B

E

1

2

3

4

0.1

of

10 57Thursday, November 01, 2012

of

10 57Thursday, November 01, 2012

of

10 57Thursday, November 01, 2012

150P_0402_50V8J

1

2

VGA

WLAN

LAN

3

CLK_PCIE_CARD_FCH<40> CLK_PCIE_CARD_FCH#<40>

Card reader

LAN

4

25MHZ_10PF_X3G025000DC1H

CLK_PCIE_VGA<16>

CLK_PCIE_VGA#<16>

CLK_PCIE_WLAN<30>

CLK_PCIE_WLAN#<30>

CLK_PCIE_LAN<31> CLK_PCIE_LAN#<31>

CLK_LAN_25M<31>

C157

1

2

10P_0402_50V8J

C160

1

2

10P_0402_50V8J

A

146

C

1

2

U

MI_RXP0<5>

U

MI_RXN0<5> MI_RXP1<5>

U

MI_RXN1<5> MI_RXP2<5>

U U

MI_RXN2<5>

MI_RXP3<5>

U

MI_RXN3<5>

U

MI_TXP0<5>

U

MI_TXN0<5 >

U

MI_TXP1<5> UMI_TXN1<5> UMI_TXP2<5>

UMI_TXN2<5> UMI_TXP3<5> UMI_TXN3<5>

+VDDAN_11_PCIE

+1.1VS_CKVDD

1

SC

X1

O

C N

2

A

R

74/ C146 close to FCH

P

LT_RST#

1

R

74 33_0402_5%

1

2

C

153 0.1U_0402_16V7K

1

2

C

147 0.1U_0402_16V7K

1

2

C

148 0.1U_0402_16V7K

1

2

C

154 0.1U_0402_16V7K

1

2

C

149 0.1U_0402_16V7K

1

2

C

150 0.1U_0402_16V7K

1

2

151 0.1U_0402_16V7K

C

1

2

152 0.1U_0402_16V7K

C

1

R75 590_0402_1%

1

R76 2K_0402_1%

1

APU

APU_DISP_CLK<7>

APU_DISP_CLK#<7>

APU

Remove 0 ohm on PVT

1

R87 22_0402_5%@

4

C N

SC O

3

R89

R89 1M_0402_5%

1M_0402_5%

B

U

1A

UDSON-2

H

PCI CLKS

P

CICLK4/14M_OSC/GPO39

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPC

LDRQ1#/CLK_REQ6#/GPIO49

APU

S5 PLUS

CICLK0

P

CICLK1/GPO36 CICLK2/GPO37

P P

CICLK3/GPO38

P

CIRST#

D0/GPIO0

A

D1/GPIO1

A A

D2/GPIO2 D3/GPIO3

A

D4/GPIO4

A

D5/GPIO5

AD6/GPIO6

AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12

AD13/GPIO13 AD14/GPIO14 AD15/GPIO15

AD16/GPIO16 AD17/GPIO17 AD18/GPIO18

AD19/GPIO19 AD20/GPIO20 AD21/GPIO21

AD22/GPIO22 AD23/GPIO23 AD24/GPIO24

AD25/GPIO25 AD26/GPIO26 AD27/GPIO27

AD28/GPIO28 AD29/GPIO29 AD30/GPIO30

AD31/GPIO31

CBE0# CBE1#

CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#

PERR#

SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

GNT2#/SD_LED/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0

LPCCLK1

LAD0

LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

CLK_CALRN

25M_X1

25M_X2

AE2

CIE_RST#

P

AD5

A

_RST#

AE30

U

MI_TX0P

AE32

U

MI_TX0N

AD33

U

MI_TX1P

AD31

U

MI_TX1N

AD28

U

MI_TX2P

AD29

U

MI_TX2N

AC30

MI_TX3P

U

AC32

MI_TX3N

U

AB33

MI_RX0P

U

AB31

U

MI_RX0N

AB28

U

MI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21808-A0-BOLTON-M3_FCBGA656

B

2

R77

2

2K_0402_1%

APU_CLK<7> APU_CLK#<7>

A

_RST#

U

MI_RXP0_C

U

MI_RXN0_C

U

MI_RXP1_C

U

MI_RXN1_C

U

MI_RXP2_C MI_RXN2_C

U

MI_RXP3_C

U

MI_RXN3_C

CLK_LAN_25M_R

25M_X1

25M_X2

PCIE_CALRP PCIE_CALRN

PU_PCIE_RST#_C

A

C

AF3

AF1 AF5 AG2

AF6

AB5

AJ3

AL5 AG4 AL6

AH3 AJ5 AL1

AN5 AN6 AJ1

AL8 AL3 AM7

AJ6 AK7 AN8

AG9 AM11 AJ10

AL12 AK11 AN12

AG12 AE12 AC12

AE13 AF13 AH13

AH14 AD15 AC15

AE16 AN3 AJ8

AN10 AD12 AG10

AK9 AL10 AF10

AE10 AH1 AM9

AH8 AG15 AG13

AF15 AM17 AD16

AD13 AD21 AK17

AD19 AH9

AF18

AE18 AC16 AD18

B25

D25 D27

C28 A26 A29

A31 B27 AE27

AE19

G25 E28

APU_PROCHOT#_R

E26

APU_PWRGD_R

G26 F26

H7 F1 F3

E6

G2

32K_X1

G4

32K_X2

C

P

CI_CLK1 <15>

P

CI_CLK3 <15>

P

CI_CLK4 <15>

F

or PCIE device reset on FS1

(GFX,GLAN,WLAN,LVDS Travis)

APU_PCIE_RST #: Reset PCIE device on APU

APU_PCIE_RST#_C

R90/ C161 close to FCH

PCI_AD23 <15>

PCI_AD24 <15> PCI_AD25 <15> PCI_AD26 <15>

PCI_AD27 <15>

T26

T27

1

R124 33_0402_5%

+RTCBATT_R

2

LPC_CLK1 <15>

LPC_AD0 <30,36> LPC_AD1 <30,36> LPC_AD2 <30,36>

LPC_AD3 <30,36> LPC_FRAME# <30,36>

SERIRQ <36>

1

R86 0_0402_5%@

1

R73 0_0402_5%

APU_RST# <7>

RTC_CLK <15,36>

2012/07/03 2013/07/03

1

@

R84

0_0402_5%

2

W=20mils

R88 510_0402_5%

C158

Deciphered Date

R88 510_0402_5%

1

2

1U_0402_6.3V6K

Compal Secret Data

2

1

Need OPEN

D

MC74VHC1G08DFT2G SC70 5P

R90

1

2

33_0402_5%

1

@

C161

2

@

CLK_PCI_EC <15,36>

CLK_PCI_DB <30>

ALLOW_STOP <7>

APU_PROCHOT# <7>

APU_PWRGD <7,51>

+RTCBATT

2

for Clear CMOS

D

R91

@

150P_0402_50V8J

1

CLRP1

CLRP1 SHORT PADS

SHORT PADS

2

+

3VALW

C

159

@

159

@

1

2

0.1U_0402_16V4Z

5

2

P

B

4

Y

1

A

G

U2

2

1

8.2K_0402_5%

@

U2

2

R93

32K_X1

32K_X2

1

2

3

@

1

0_0402_5%

32.768KHZ_12.5PF_CM31532768DZFT

VGA,LAN,WLAN,Cardreader

APU_PCIE_RST# <16,30,31,40>

R92

R92 0_0402_5%

0_0402_5%

PLT_RST# <36>

Y1

Close to HUDSON-M2/3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

E

EC

1

20P_0402_50V8J

1

20M_0402_5%

2

20P_0402_50V8J

LA8642P M/B

E

DVT change

C155

R78

C156

11 57Thursday, November 01, 2012

1

2

3

4

0.1

of

A

B

C

D

E

4MB SPI ROM

PI_CLK_FCH

33_0402_5%

22P_0402_50V8J

2

SPI_CLK_FCH_R

2

SPI_SI_R

FWR#SPI_SI <36>

SPI_CLK <36>

2

12 57Thursday, November 01, 2012

S

1

R

94

@

2

162

C

1

2

3

4

0.1

of

@

+3VALW

3VALW

+

1

2

S

R

95

1

R

96

hare with EC

1B

U

1

S

SD

HDD

ODD

2

+AVDD_SATA

+3VS

3

4

A

S

ATA_FTX_C_DRX_P0<30>

S

ATA_FTX_C_DRX_N0<30>

SATA_FRX_C_DTX_N0<30>

SATA_FRX_C_DTX_P0<30>

SATA_FTX_C_DRX_P1<34> SATA_FTX_C_DRX_N1<34>

SATA_FRX_C_DTX_N1<34> SATA_FRX_C_DTX_P1<34>

SATA_FTX_C_DRX_P2<34>

SATA_FTX_C_DRX_N2<34>

SATA_FRX_C_DTX_N2<34> SATA_FRX_C_DTX_P2<34>

1

2

R1051K_0402_1%

1

2

R106931_0402_1%

1

BT_ON#<38>

BT_DISABLE#<30>

WL_OFF#<30>

ODD_EN<34>

R117 10K_0402_5%

R120 10K_0402_5%

R121 10K_0402_5%

2

1

R108 10K_0402_5%

SATA_CALRP

SATA_CALRN

BT_ON#

BT_DISABLE#

WL_OFF#

ODD_EN

2

T12

B

U

AK19

ATA_TX0P

S

AM19

S

ATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21808-A0-BOLTON-M3_FCBGA656

SERIAL ATA

UDSON-2

H

HW MONITOR

D_CLK/SCLK_2/GPIO73

S

D_CMD/SLOAD_2/GPIO74

S

D_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARD

GBE LANSPI ROM

VGA DAC

VGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCLK

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_GREEN

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P

AUX_VGA_CH_N

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXD3 GBE_RXD2 GBE_RXD1

GBE_RXD0

GBE_TXCLK

GBE_TXD3 GBE_TXD2

GBE_TXD1 GBE_TXD0

VGA_RED

VGA_BLUE

AUXCAL

NC1 NC2

NC3 NC4 NC5

C

AL14

AN14 AJ12 AH12

AK13 AM13 AH15 AJ14

AC4 AD3

AD9 W10 AB8

AH7 AF7 AE7

AD7 AG8 AD1

AB7 AF9 AG6

AE8 AD8 AB9

AC2 AA7 W9

GBE_PHY_INTR

V6 V5 V3

SPI_CLK_FCH_R

T6

SPI_SB_CS0#_R

V1

L30

L32

M29

M28 N30

M33

N32

K31

V28

V29

U28

AUXCAL

T31

T33 T29 T28

R32 R30 P29

P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10

A28 G27 L4

2012/07/03 2013/07/03

S need pop R245

SPI_SO_R

SPI_SI_R

SPI_WP#

1

R102 150_0402_1%

R103 150_0402_1%

R104 150_0402_1%

R107 715_0402_1%

R111 10K_0402_5%

R112 10K_0402_5%

R113 10K_0402_5%

R114 10K_0402_5%

R115 10K_0402_5%

R116 10K_0402_5%

R118 10K_0402_5%

R119 10K_0402_5%

2

1

2

1

2

CRT_HSYNC <28> CRT_VSYNC <28>

CRT_DDC_DATA <28>

CRT_DDC_CLK <28>

1

2

ML_VGA_AUXP_C <7> ML_VGA_AUXN_C <7>

1

R109 100_0402_1%

1

2

ML_VGA_TXP0 <7>

ML_VGA_TXN0 <7> ML_VGA_TXP1 <7> ML_VGA_TXN1 <7>

ML_VGA_TXP2 <7> ML_VGA_TXN2 <7>

ML_VGA_TXP3 <7> ML_VGA_TXN3 <7>

FCH_CRT_HPD <7>

2

@

2

@

2

@

2

@

2

@

2

Need to enable internal pull down to lea ve unconnected

Compal Secret Data

Deciphered Date

SPI_SB_CS0#_R SPI_SO_R

96

1

245

R

97

0_0402_5%

1

2

1

2

0_0402_5%

R98

DAC_RED < 28>

DAC_GRN <28>

DAC_BLU <28>

+VDDAN_11_ML

Module design FCH_CRT_HPD pull up 110K now 10 K

+FCH_VDDAN_33_DAC

2

D

PI_WP#

10K_0402_5%

2

S

PI_HOLD#

10K_0402_5%

2

S

PI_SB_CS0#

@

10K_0402_5%

U

3

SPI_WP#

1

CS#

2

SO/SIO1

HOLD#

3

WP#

4

GND

SI/SIO0

W25Q32BVSSIG SOIC 8P SPI ROM

1

R125 0_0402_5%@

R128 0_0402_5%@

R233 0_0402_5%@

R238 0_0402_5%@

2

1

2

1

2

1

2

SPI_SB_CS0# SPI_SO_L

SPI_SO_L SPI_SI

SPI_CLK_FCH SPI_SB_CS0#

Co-lay EC share ROM

1

R11010K_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet

+

3VALW

C

165

1

2

0.1U_0402_16V4Z

8

VCC

7

SPI_HOLD#

6

SPI_CLK_FCH

SCLK

5

SPI_SI

FRD#SPI_SO

FWR#SPI_SI

SPI_CLK

FSEL#SPICS#

GBE_PHY_INTR

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

R100 0_0402_5%

1

R99 0_0402_5%

FRD#SPI_SO <36 >

FSEL#SPICS# <36>

1

R101 10K_0402_5%

LA8642P M/B

E

3VALW

+

2

R

127

10K_0402_5%

@

1

CPPE#<40>

+3VALW

For FCH internal debug use

1

R129 2.2K_0402_5%@

1

R130 2.2K_0402_5%@

1

R131 2.2K_0402_5%@

2

3

4

R131 2.2K_0402_5%@

+3VALW

1

R137 10K_0402_5%

1

R136 10K_0402_5%

1

R135 10K_0402_5%

1

R145 10K_0402_5%@

1

R142 10K_0402_5%@

1

R141 10K_0402_5%

1

R139 10K_0402_5%

1

R230 10K_0402_5%@

1

R146 10K_0402_5%@

1

R147 100K_0402_5%@

1

R148 10K_0402_5%@

+3VS

1

R154 2.2K_0402_5%

1

R156 2.2K_0402_5%

1

R157 10K_0402_5%

1

R158 8.2K_0402_5%

1

R159 8.2K_0402_5%

1

R162 10K_0402_5%

1

R163 10K_0402_5%

1

R164 2.2K_0402_5%

1

R165 10K_0402_5%@

1

R168 10K_0402_5%@

1

R169 10K_0402_5%@

S

YS_RESET#

10K_0402_5%

2

R

175

A

2

1

R126 0_0402_5%@

ODD_DETECT#

ODD_DA#_FCH

USB_OC7#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

FCH_SCLK1

FCH_SDATA1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

PEG_CLKREQ#_R

A

+

3VS

G

2

Q71

1

3

D

S

D

S

2N7002K_SOT23-3

2

TEST0

TEST1

TEST2

Module design ODD_DETECT# without pull up need check chipset pin internal status

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB_OC5#

CPPE#_R

PEG_CLKREQ#<17>

HDA_BITCLK_AUDIO<35> HDA_SDOUT_AUDIO<35>

HDA_SDIN0<35>

HDA_SYNC_AUDIO<35>

HDA_RST_AUDIO#<35>

GPIO187 H: 2G Vram L: 1G Vram

VGA_GATE#<36>

+3VALW

1

@

R160

R161

2

1

PX@

2

R161

2

10K_0402_5%

GPIO189 GPIO190

1

PX@

R167

R166

2

10K_0402_5%

R364 10K_0402_5%X76@

+3VALW

R365 10K_0402_5%X76@

R366 10K_0402_5%

+3VALW

R367 10K_0402_5%

PXS_RST#<16> PXS_PWREN<18,47,49,50>

BOARD Config.

B

PCIE_RST2 : Reset PCIE device on Hudson2/3

T

13

F

CH_PWRGD

T

EST0

T

EST1

T

EST2

CPPE#_R

SYS_RESET#

WD_PWRGD

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1

PEG_CLKREQ#_R

USB_OC7#

USB_OC5#

USB_OC3#

USB_OC2#

USB_OC1#

USB_OC0#

10

01

13

HDA_BITCLK

HDA_SDOUT

HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO187

GPIO188

GPIO189 GPIO190

Function

PX5

Reserved

DIS

UMA

E

C_LID_OUT#<36>

P

M_SLP_S3#<36>

M_SLP_S5#<36>

P P

BTN_OUT#<36>

CH_PWRGD<36,51>

F

G

ATEA20<36>

KBRST#<36>

EC_SCI#<36>

EC_SMI#<36>

FCH_PCIE_WAKE#<30,31>

H_THERMTRIP#<7>

EC_RSMRST#<36>

LAN_CLKREQ#<31>

FCH_SPKR< 35>

FCH_SCLK0<9,10,30> FCH_SDATA0<9,10,30>

WLAN_CLKREQ#<30>

VGA_PWRGD<50>

1

2

R132 0_0402_5%@

ODD_DA#_FCH<34>

ODD_DETECT#<34>

USB_OC2#<40>

USB_OC1#<40>

USB_OC0#<39>

1

R138 33_0402_5%

R140 33_0402_5%

R143 33_0402_5%

R144 33_0402_5%

1

2

G

2

1

2

1

2

1

2

@

2

R150 0_0402_5%

2

R152 0_0402_5%

1

D

PX@

Q70

2N7002K_SOT23-3

S

3

GPIO189 GPIO190

0 0

1 1

B

1

U

SB_RCOMP

U

SB_FSD1N

SB_FSD0N

U

SB_HSD13P

SB_HSD13N

U

SB_HSD12P

USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P

USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP USBSS_CALRN

USB_SS_TX3P

USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P

USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P

USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202

KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205

KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

U

SB_RCOMP

H1 H3

H6 H5

H10

G10

K10

U

SB30_P12

J12

SB30_N12

U

G12 F12

K12

K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8

E8

C6 A6

C5 A5

C1

USB20_P1

C3

USB20_N1

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14

C14

C12 A12

D15

USB30_TX_P2

B15

USB30_TX_N2

E14

USB30_RX_P2

F14

USB30_RX_N2

F15

USB30_TX_P1

G15

USB30_TX_N1

H13

USB30_RX_P1

G13

USB30_RX_N1

J16

USB30_TX_P0

H16

USB30_TX_N0

J15

USB30_RX_P0

K15

USB30_RX_N0

H19

1

R149 10K_0402_5%

G19

1

R151 10K_0402_5%

G22

1

R153 10K_0402_5%

G21

1

R155 10K_0402_5%

E22 H22 J22

EC_PWM2

H21

K21

GPU_SEL

K22

F22 F24 E24

B23 C24 F18

USB30_P12

USB30_N12

USB20_P1

USB20_N1

D

R248 0_0402_5%

R249 0_0402_5%

R246 0_0402_5%

R247 0_0402_5%

C

U

1D

HUDSON-2

AB6

P

CIE_RST2#/PCI_PME#/GEVENT4#

R2

I#/GEVENT22#

R

W7

S

PI_CS3#/GBE_STAT1/GEVENT21#

T3

S

LP_S3#

W2

S

LP_S5#

J4

P

WR_BTN#

N7

P

WR_GOOD

T9

EST0

T

T10

EST1/TMS

T

V9

T

EST2

AE22

G

A20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21808-A0-BOLTON-M3_FCBGA656

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/07/03 2013/07/03

U

SBCLK/14M_25M_48M_OSC

USB MISC

U

SB_FSD1P/GPIO186

U

SB_FSD0P/GPIO185

USB 1.1

ACPI / WAKE UP EVENTS

USB 2.0

GPIO

USB OC

HD AUDIO

USB 3.0

SCL3_LV/GPIO195 SDA3_LV/GPIO196

EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

E

1

R

122 11.8K_0402_1%

2

R

USB30_P11 <39> USB30_N11 <39>

USB30_P10 <39> USB30_N10 <39>

USB20_P4 <38> USB20_N4 <38>

USB20_P3 <27> USB20_N3 <27>

USB20_P2 <30> USB20_N2 <30>

USB20_P0 <40>

USB20_N0 <40>

1

R133 1K_0402_1%

R134 1K_0402_1%

2

USBR3@

2

USBR3@

USBR2@

2

USBR2@

2

1

2

EC_PWM2 <1 5>

Date: Sheet

strap pin

1

Title

Size Document Number Rev

Custom

USB20_LP

USB20_LN

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

+FCH_VDD_11_SSUSB_S

USB30_TX_P2 <40> USB30_TX_N2 <40>

USB30_RX_P2 <40> USB30_RX_N2 <4 0>

USB30_TX_P1 <39> USB30_TX_N1 <39>

USB30_RX_P1 <39> USB30_RX_N1 <3 9>

USB30_TX_P0 <39> USB30_TX_N0 <39>

USB30_RX_P0 <39>

USB30_RX_N0 <39>

USB20_LP <4 0>

USB20_LN <40>

LA8642P M/B

LP2

LP1

BT

CMOS

WLAN

RP1

USB3.0 and USB2.0 Option

10K_0402_5%

GPU_SEL

10K_0402_5%

E

P2

+3VALW

PX@

R234

@

R235

13 57Thursday, November 01, 2012

RP2

LP2

LP1

Mars

1

2

1

2

of

Root

1

2

3

4

0.1

A

B

C

D

E

3VS

+

FCH_VDDAN_33_DAC

1

+3VS

FBMA-L11-201209-221LMA30T_0805

2

+3VALW

+VDDAN_33_USB

3

+3VS

4

2

L

0_0603_5%

1

2

220 ohm

1

R

2

172 0_0402_5%

L4

1

2

220 ohm

L6

1

MBK1608221YZF_2P

2

220 ohm

L77

1

220 ohm

L13

L14

2

MBK1608221YZF_2P

0_0603_5%

1

0_0603_5%

1

VDDPL_33_SYS

+

C166

1

2

+

VDDPL_33_MLDAC

C175

1

2

+FCH_VDDAN_33_DAC

30mil

2.2U_0603_6.3V6K

C195

1

2

+VDDPL_33_SSUSB_S

2.2U_0402_6.3V6M

C

C 205

205

1

2

+VDDPL_33_USB_S

C213

1

2

+VDDPL_33_PCIE

220 ohm

+VDDPL_33_SATA

220 ohm

A

2.2U_0402_6.3V6M

0.1U_0402_16V7K

C167

1

2

0.1U_0402_16V7K

C176

1

2

LDO_CAP: Internally generated 1.8V supply for the RGB outputs

+1.1VS

0.1U_0402_16V4Z

C196

1

2

+3VALW

0.1U_0402_16V7K

C206

1

2

0.1U_0402_16V7K

2.2U_0402_6.3V6M

C214

1

2

2.2U_0402_6.3V6M

C220

1

2

2.2U_0402_6.3V6M

C227

1

2

+1.1VALW

171

R

1

+

3VS

+VDDPL_33_MLDAC

L3

1

MBK1608221YZF_2P

220 ohm/2A

1

FBMA-L11-201209-221LMA30T_0805

220 ohm/2A

1

MBK1608221YZF_2P

+1.1VALW

1

MBK1608221YZF_2P

+FCH_VDD_11_SSUSB_S

40mils

2

L78

FBMA-L11-201209-221LMA30T_0805

42 ohm/4A

2

0_0603_5%

R

173 0_0402_5%

R174 0_0402_5%

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

2

R178 0_0402_5%

R179 0_0603_5%

L5

2

L9

2

220 ohm

L11

2

220 ohm

R185 0_0603_5%

R187 0_0603_5%

1

22U_0603_6.3V6M

C171

1

2

+

VDDPL_33_SYS

1

2

1

2

1

2

1

2

1

R182 0_0402_5%

10U_0603_6.3V6M

C201

C200

1

2

C209

2.2U_0402_6.3V6M

C208

1

2

10U_0603_6.3V6M

C216

C215

1

2

1

2

B

+

VDDIO_33_PCIGP

0.1U_0402_16V7K

C173

C174

C172

1

2

C188

1

2

10U_0603_6.3V6M

0.1U_0402_16V7K

C221

1

2

C228

1

2

C174

1

2

+

VDDPL_33_SYS

VDDPL_33_DAC

+

+VDDPL_33_ML

+FCH_VDDAN_33_DAC

+VDDPL_33_SSUSB_S

@

1

2

C184 2.2U_0603_6.3V6K

+VDDPL_11_DAC

+VDDAN_11_ML

0.1U_0402_16V7K

4.7U_0402_6.3V6M

0.1U_0402_16V7K

C190

C189

1

2

+VDDAN_33_USB

1U_0402_6.3V6K

C202

C203

1

2

+VDDAN_11_USB_S

+VDDCR_11V_USB

0.1U_0402_16V7K

C217

1

2

+VDDAN_11_SSUSB

0.1U_0402_16V7K

1U_0402_6.3V6K

C222

C223

1

2

+VDDCR_11_SSUSB

10U_0603_6.3V6M

1U_0402_6.3V6K

C229

1

2

1.1VS

1C

U

H

UDSON-2

102mA

AB17

0.1U_0402_16V7K

C204

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

C230

1

2

DDIO_33_PCIGP_1

V

AB18

V

DDIO_33_PCIGP_2

AE9

V

DDIO_33_PCIGP_3

AD10

V

DDIO_33_PCIGP_4

AG7

V

DDIO_33_PCIGP_5

AC13

V

DDIO_33_PCIGP_6

AB12

V

DDIO_33_PCIGP_7

AB13

DDIO_33_PCIGP_8

V

AB14

DDIO_33_PCIGP_9

V

AB16

V

DDIO_33_PCIGP_10

4

7mA

H24

V

DDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21808-A0-BOLTON-M3_FCBGA656

0.1U_0402_16V7K

C231

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

UDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

DDCR_11_1

V V

DDCR_11_2

V

DDCR_11_3

V

DDCR_11_4

V

DDCR_11_5

V

DDCR_11_6

V

DDCR_11_7 DDCR_11_8

V

CORE S0

DDCR_11_9

V

DDAN_11_CLK_1

V

DDAN_11_CLK_2

VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5

VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3

VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6

VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1

VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3

VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7

VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3

VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6

VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2012/07/03 2013/07/03

1007mA

C179

T14 T17

1

T20 U16 U18

2

V14 V17 V20

Y17

340mA

H26 J25

C181

K24 L22

1

M22

N21 N22

2

P22

1088mA

AB24 Y21 AE25

C185

AD24 AB23

1

AA22

AF26 AG27

2

1337mA

AA21

Y20 AB21

C191

AB22

AC22

1

AC21 AA20

AA18

2

AB20 AC19

59mA

N18 L19

C197

M18

V12

1

V13 Y12

Y13

2

W11

5mA

G24

C207

1

2

187mA

N20 M20

C211

1

2

70mA

J24

C218

1

2

12mA

M8

C224

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

VCC_VDDCR_11

+

0.1U_0402_16V7K

C168

C180

0.1U_0402_16V7K

1

2

+

1.1VS_CKVDD

0.1U_0402_16V7K

C183

C182

1

2

+VDDAN_11_PCIE

1U_0402_6.3V6K

0.1U_0402_16V7K

C186

C187

1

2

1U_0402_6.3V6K

0.1U_0402_16V7K

C192

C193

1

2

+VDDIO_33_S

1U_0402_6.3V6K

C199

C198

1

2

+VDDXL_3.3V

2.2U_0402_6.3V6M

+VDDCR_1.1V

1U_0402_6.3V6K

C212

1

2

+VDDPL_11_SYS_S

0.1U_0402_16V7K

2.2U_0402_6.3V6M

C219

1

2

+VDDAN_33_HWM

0.1U_0402_16V7K

2.2U_0402_6.3V6M

C225

1

@

2

+VDDIO_AZ

C226 2.2U_0402_6.3V6M

D

1U_0402_6.3V6K

C169

10U_0603_6.3V6M

1U_0402_6.3V6K

22U_0603_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1

10U_0603_6.3V6M

C170

1

2

+

1.1VS_CKVDD

22U_0603_6.3V6M

1U_0402_6.3V6K

C178

C177

1

2

+VDDAN_11_PCIE

+AVDD_SATA

22U_0603_6.3V6M

C194

1

2

1

R181 0_0402_5%

L7

0_0603_5%

1

R183 0_0603_5%

1

L12 0_0603_5%

1

R184 0_0402_5%

1

R186 0_0402_5%

2

1

R

170 0_0805_5%

2ohm @ 100MHz

4

1

R

176 0_0603_5%

42ohm @ 100MHz

1

R177 0_0805_5%

42ohm @ 100MHz

1

R180 0_0805_5%

2

220 ohm

2

220 ohm

2

+

2

+

1.1VS

2

+1.1VS

2

+1.1VS

2

+3VALW

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wa ke is supported; ot herwise, tie to +3.3V_S0 rail. Hudson-2 designs : Tie to +3.3V_ S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

FCH PWR

LA8642P M/B

14 57Thursday, November 01, 2012

E

of

1

2

3

4

0.1

A

B

C

D

E

1

2

3

M13

M16 M21 M25

A3

A33

B7

B13

D9

D13

E5

E12 E16 E29

F7

F9 F11 F13 F16 F17

F19 F23 F25

F29

G6

G16

G32 H12 H15

H29

J6

J9

J10 J13 J28

J32

K7 K16

K27 K28

L6

L12 L13 L15

L16 L21

N6 N11 N13

N23 N24 P12

P18 P20 P21

P31 P33

R4

R11 R25 R28

T11 T16 T18

N8

K25

H25

U

1E

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

UDSON-2

H

GROUND

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

VSS VSS VSS

VSS

T25 T27 U6

U14 U17 U20

U21 U30 U32

V11 V16 V18

W4 W6 W25

W28 Y14 Y16

Y18 AA6 AA12

AA13 AA14 AA16

AA17 AA25 AA28

AA30 AA32 AB25

AC6 AC18 AC28

AD27 AE6 AE15

AE21 AE28 AF8

AF12 AF16 AF33

AG30 AG32 AH5

AH11 AH18 AH19

AH21 AH23 AH25

AH27 AJ18 AJ28

AJ29 AK21 AK25

AL18 AM21 AM25

AN1 AN18 AN28

AN33

T21 L28

K33 N28

R6

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<11>

PCI_CLK3<11>

PCI_CLK4<11>

CLK_PCI_EC<11,36>

LPC_CLK1<11>

EC_PWM2<13>

RTC_CLK<11,36>

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

+3VS

1

2

1

@

2

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

+3VS

R188 10K_0402_5%

R189 10K_0402_5%

R190 10K_0402_5%

1

@

2

R201 10K _0402_5%

R200 10K _0402_5%

R202 10K _0402_5%

1

2

EC ENABLED

EC DISABLED

DEFAULT

+3VALW

R191 10K_0402_5%

1

@

2

R203 10K _0402_5%

1

2

+3VALW

1

2

1

@

2

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

+3VALW

R192 10K_0402_5%

@

R204 10K _0402_5%

D

EBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

+3VALW

R194 10K_0402_5%

R193 10K_0402_5%

1

2

R206 2.2K_040 2_5%

R205 2.2K_040 2_5%

1

@

2

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

PCI_AD27 PCI_AD26

USE PCI

PULL

PLL

HIGH

DEFAULT

BYPASS

PULL

PCI PLL

LOW

PCI_AD27<11>

PCI_AD26<11>

PCI_AD25<11>

PCI_AD24<11>

PCI_AD23<11>

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R195 2.2K_0402_5%

1

@

2

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

R196 2.2K_0402_5%

1

@

2

@

R197 2.2K_0402_5%

1

2

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

R198 2.2K_0402_5%

1

@

2

R199 2.2K_0402_5%

1

@

2

1

2

3

21808-A0-BOLTON-M3_FCBGA656

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

FCH-VSS/Strap

LA8642P M/B

15 57Thursday, November 01, 2012

E

of

4

0.1

A

P

CIE_CTX_GRX_P[7..0]<5>

P

CIE_CTX_GRX_N[7..0]<5>

1

2

3

CLK_PCIE_VGA<11>

CLK_PCIE_VGA#<11>

CIE_CTX_GRX_P[7..0]

P

CIE_CTX_GRX_N[7..0]

P

CIE_CTX_GRX_P0

P

CIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

2

PX@

R210 1K_0402_5%

GPU_RST#

1

2

1

PX@

R212

R212 100K_0402_5%

100K_0402_5%

A

W36

W38

AB35 AA36

AH16

AA30

U36

U38

R36

R38

N36

N38 M37

M35

H37

H35 G36

G38

A38

Y

Y35

V37

V35

T37

T35

P37

P35

L36

L38 K37

K35 J36

J38

F37

F35

E37

37

U

4A

PCIE_RX0P

PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P

PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P

PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

NC

NC NC

NC

NC NC

NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

B

P

ART 1 0F 9

PCI EXPRESS INTERFACE

MARS-XTX M2_FCBGA962PX@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC

NC NC

NC

NC NC

NC

NC NC

P

CIE_CRX_GTX_P[7..0]

P

CIE_CRX_GTX_N[7..0]

33

Y

P

CIE_CRX_C_GTX_P0

Y

32

P

CIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3

T33

PCIE_CRX_C_GTX_P4

T32

PCIE_CRX_C_GTX_N4

T30

PCIE_CRX_C_GTX_P5

T29

PCIE_CRX_C_GTX_N5

P33

PCIE_CRX_C_GTX_P6

P32

PCIE_CRX_C_GTX_N6

P30

PCIE_CRX_C_GTX_P7

P29

PCIE_CRX_C_GTX_N7

N33

N32

N30 N29

L33 L32

L30

L29

K33 K32

J33 J32

K30

K29

H33 H32

1

Y30

R209 1.69K_0402_1%PX@

1

Y29

R211 1K_0402_1%PX@

2

C

P

CIE_CRX_GTX_P[7..0] <5>

P

CIE_CRX_GTX_N[7..0] <5>

1

2

C

2340.1U_0402_16V7K PX@

1

2

C

2350.1U_0402_16V7K PX@

1

2

C2380.1U_0402_16V7K

1

2

C2390.1U_0402_16V7K PX@

1

2

C2360.1U_0402_16V7K

1

2

C2400.1U_0402_16V7K PX@

1

2

C2410.1U_0402_16V7K

1

2

C2370.1U_0402_16V7K PX@

1

2

C2420.1U_0402_16V7K

1

2

C2430.1U_0402_16V7K PX@

1

2

C2440.1U_0402_16V7K

1

2

C2450.1U_0402_16V7K PX@

1

2

C2460.1U_0402_16V7K

1

2

C2470.1U_0402_16V7K PX@

1

2

C2480.1U_0402_16V7K

1

2

C2490.1U_0402_16V7K PX@

+0.95VGS

PX@

P

CIE_CRX_GTX_P0

P

CIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2

PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

D

L

VDS Interface

U

4D

ART 7 0F 9

P

RSVD/VARY_BL

LVDS CONTROL

LVTMDP

PX@

PXS_RST#<13>

APU_PCIE_RST#<11,30,31,40>

RSVD/DIGON

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC#AG36

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

MARS-XTX M2_FCBGA962

+3VGS

5

2

B

1

A

3

A

K27

A

J27

AK35 AL36

AJ38

AK37

AH35 AJ36

AG38 AH37

AF35

NC#AF35

AG36

AP34 AR34

AW37 AU35

AR37

AU39

AP35 AR35

AN36

NC

AP37

NC

P

4

GPU_RST#

Y

G

PX@

U5

U5 MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

E

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/07/03 2013/07/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

ATI_MarsXTX_M2_PCIE/LVDS

LA8642P M/B

E

of

16 57Thursday, November 01, 2012

of

16 57Thursday, November 01, 2012

of

16 57Thursday, November 01, 2012

4

0.1

1

2

ACIN<36,45>

GPU_VID5<50>

GPU_VID1<50>

GPU_VID2<50>

PEG_CLKREQ#<13>

GPU_VID3<50>

GPU_VID4<50>

3

+1.8VGS

PX@

1

2

R231 499_0402_1%

PX@

1

2

R232 249_0402_1%

1

2

0.1U_0402_16V7K

C272

PX@

GPIO_28_FDO

H

L

4

+1.8VGS

PX@

1

BLM15BD121SN1D_0402

TSVDD MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

A

+VREFG_GPU

+3VGS

MLPS

Disable

Enable

+3VGS

L83

A

@

D1

RB751V_SOD323

1

R223 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

R259

R85 5.11K_0402_5%

R272 1K_0402_5%

R384 10K_0402_5%

R385 10K_0402_5%

+TSVDD

2

1

C279

2

PX@

20

T

21

T30

2

T17

T28

T29

1

2

T18

T25

@

1

2

4.7K_0402_5%

1

2

@

1

2

PX@

T19

1

2

@

1

2

PX@

(1.8V@13mA TSVDD)

1

C280

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

ENLK_CLK

G G

ENLK_VSYNC

GPU_SMB_CK2

GPU_SMB_DA2

GPU_GPIO0

GPU_GPIO5

GPU_VID5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO10

GPU_VID1

THM_ALERT#

GPU_VID2

GPU_GPIO21

GPU_GPIO22

PEG_CLKREQ#

GPU_VID3

GPU_VID4

+VREFG_GPU

PX_EN

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK

JTAG_TMS JTAG_TDO

THERM_D+

THERM_D-

GPIO_28_FDO

+TSVDD

1

C281

2

0.1U_0402_16V4Z

PX@

A A

A

AW5

AW6

AR10

AW10

AU10 AP10 AV11

AT11 AR12

AW12

AU12 AP12

AJ23

AH23

AK26 AJ26

AH20 AH18 AN16

AH17 AJ17 AK17

AJ13 AH15 AJ16

AK16 AL16 AM16

AM14 AM13 AK14

AG30 AN14 AM17

AL13 AJ14 AK13

AN13

AG32 AG33

AJ19 AK19 AJ20

AK20 AJ24 AH26

AH24

AC30

AK24

AH13

AL21

AD28

AM23 AN23 AK23

AL24 AM24

AF29

AG29

AK32

AL31

AJ32 AJ33

D29 C29

J21

K21

R8

A

U8

A

P8

W8

A

R3

A

R1

A

U1

A

U3

W3

AP6

AU5 AR6

AU6 AT7

AV7 AN7 AV9

AT9

U

4B

MUTI GFX

ENLK_CLK

G G

ENLK_VSYNC

S

WAPLOCKA WAPLOCKB

S

N

C

N D

BG_CNTL0

N

C

N

C

N

C

D

BG_DATA0

D

BG_DATA1

D

BG_DATA2

DBG_DATA3

DBG_DATA4 DBG_DATA5 DBG_DATA6

DBG_DATA7 DBG_DATA8 DBG_DATA9

DBG_DATA10 DBG_DATA11 DBG_DATA12

DBG_DATA13 DBG_DATA14 DBG_DATA15

DBG_DATA16 DBG_DATA17 DBG_DATA18

DBG_DATA19 DBG_DATA20 DBG_DATA21

DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON

GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK

GPIO_11 GPIO_12 GPIO_13

GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16

GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF

GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB

CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC

GENERICD GENERICE_HPD4 GENERICF_HPD5

GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK

JTAG_TMS JTAG_TDO

THERMAL

DPLUS

DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

PART 2 0F 9

DPA

DPB

DPC

DPD

DAC1

DDC/AUX

MARS-XTX M2_FCBGA962PX@

B

MLPS

B

AVSSN

HSYNC VSYNC

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCVGACLK

DDCVGADATA

RSET

PS_0

PS_1

PS_2

PS_3

C

U24

A

N

C

A

V23

N

C

A

T25

C

N

R24

A

N

C

A

U26

C

N

A

V25

N

C

T27

A

N

C

A

R26

N

C

A

R30

N

C

A

T29

N

C

A

V31

C

N

A

U30

N

C

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

R

AD37

AE36

G

AD35

AF37

B

AE38

AC36

HSYNC

AC38

VSYNC

AB34

R220 499_0402_1%PX@

AD34

+AVDD

AE34

AC33

+VDD1DI

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26 AN26

AM27 AL27

AM19

AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30

AJ31

T32

T33

1

2

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

PU_GPIO5

G

HM_ALERT#

T

JTAG_TRSTB

JTAG_TDI JTAG_TMS

JTAG_TCK

+VDD1DI

1

C269

2

PX@

0.1U_0402_16V7K

Internal VGA Thermal Sensor

0.1U_0402_16V4Z

THERM_D+

@

1

THERM_D-

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

R224 10K_0402_5%@

R225 10K_0402_5%@

R226 10K_0402_5%@

R227 10K_0402_5%@

+AVDD

1

C266

2

PX@

0.1U_0402_16V7K

1

C271

C270

2

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+3VGS

@

1

2

C18

2

C19

1000P_0402_50V7K

+3VGS

1

PX@

R228

2

STRAPS

+

3VGS

1

2

R

216 100K_0402_5%@

1

2

R

83 2.2K_0402_5%@

+3VGS

1

2

1

2

1

2

1

2

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+1.8VGS

1

2

L79

PX@

L79

PX@

BLM15BD121SN1D_0402

1

C267

C268

2

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VGS

1

2

L80

PX@

L80

PX@

BLM15BD121SN1D_0402

1

2

PX@

R229

10K_0402_5%

DMN66D0LDW-7 2N_SOT363-6

C

VDD1DI MarsC RB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

U6

1

VDD

2

D+

3

D-

4

THERM#

ADM1032ARMZ-2REEL_MSOP8

@

SMBus address: 4D

2

1

Q9A

DMN66D0LDW-7 2N_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

+3VGS

SDATA

ALERT#

6

PX@

4

SCLK

GND

8

7

6

5

Q9B

Close to U6

1

2

VGA_SMB_CK2

R207 0_0402_5%

VGA_SMB_DA2

R208 0_0402_5%

THM_ALERT#

EC_SMB_CK2 <33,36>

3

EC_SMB_DA2 <33,36>

PX@

2012/07/03 2013/07/03

PX@

2

PX@

GPU_SMB_CK2

1

GPU_SMB_DA2

Compal Secret Data

D

C

ONFIGURATION STRAPS

A

LLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

S

TRAPS

TX_PWRS_ENB

TX_DEEMPH_EN

B

IF_GEN3_EN_A

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:Tx de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

T

ransmitter Power Savings Enable

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture s ize If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST ) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistl er/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2

PS_3

@

C577

0.01U_0402_16V7K

Bits[3:1]

0 0 0

1 1

0 0 0

0 1

0 0 0

1 0

1 1

X X X

PX@

1

C578

2

@

PX@

1

2

0.01U_0402_16V7K

1

C580

C579

2

0.01U_0402_16V7K

0.082U_0402_16V7K

R_pu R_pd

NC 4.75K

NC

82 nF

NC

10 nF

NC

X

1

R24

X76@

R24

X76@

8.45K_0402_1%

4.75K_0402_1%

8.45K_0402_1%

2

1

R26

X76@

R26

X76@

PX@

4.75K_0402_1%

2

Title

ATI_MarsXTX_M2_Main_MSIC

Size Document Number R ev

C

Date: Sheet

4.75K

@

E

R

ECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

Mapping to VRAM type please refer to page 21

X

1

R44

R31

Compal Electronics, Inc.

8.45K_0402_1%

2

1

4.75K_0402_1%

2

R80

@

R80

@

R79

PX@

R79

PX@

LA8642P M/B

E

1

8.45K_0402_1%

2

1

4.75K_0402_1%

2

+1.8VGS

R82

@

R82

@

R81

PX@

R81

PX@

17 57Thursday, November 01, 2012

D

efault Setting

X

1

0

X

XX

X

XX

0

XXX

1

2

1

2

of

1

2

3

4

0.1

E

2

PX@

C282

C282 15P_0402_50V8J

15P_0402_50V8J

1

2

X

TALIN

XTALOUT

D

1

@

C404

0.1U_0402_16V7K

2

1

@

R276

51.1_0402_1%

2

PX@

C283

15P_0402_50V8J

1

2

1

2

1

20 1M_0402_5%PX@

R

Y

2

4

N

C

1

TALIN

X

2

1

@

C403

0.1U_0402_16V7K

@

R275

51.1_0402_1%

OSC

27MHZ 10PF +-20PPM X3G027000DA1H

PX@

2

3

X

TALOUT

O

SC

2

NC

+MPV18

+SPV18

+SPLL_VDDC

C

AM10

AN10

AF30 AF31

AN9

H7 H8

U

4C

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

PX@

P

ART 9 0F 9

PLLS/XTAL

MARS-XTX M2_FCBGA962

XTALIN

XTALOUT

XO_IN

XO_IN2

CLKTESTA

CLKTESTB

V33

A

AU34

AW34

AW35

AK10

AL10

1.8VGS

L

1

MBK1608221YZF_2P

+1.8VGS

L25

1

BLM15BD121SN1D_0402

+0.95VGS

L86

1

BLM15BD121SN1D_0402

B

+

MPV18

(

85

PX@

85

PX@

2

PX@

2

PX@

2

MPLL_PVDD:1.8V@130mA )

1

C383

C382

2

1U_0402_6.3V6K

PX@

1U_0402_6.3V6K

PX@

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPV18

(SPLL_PVDD:1.8V@75mA )

1

C385

C386

2

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

C401

C398

2

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

1

C384

2

PX@

1

C387

2

PX@

1

C402

2

PX@

A

PLL_PVDD MarsCRB Design

M

1

2

220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

+

<+3VS TO +3VGS>

3

PXS_PWREN<13,47,49,50>

4

A

PXS_PWREN

+3VALW

1

@

R241

R241 100K_0402_5%

100K_0402_5%

2

PXS_PWREN#

1

@

OUT

Q17

2

IN

B

Q17 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

GND

3

PXS_PWREN# <42 >

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

+5VALW

R242

PX@

R242

PX@

20K_0402_5%

1

D

PXS_PWREN

2012/07/03 2013/07/03

2

G

S

3

Compal Secret Data

Deciphered Date

Need OPEN

+3VS

R243

PX@

R243

PX@

20K_0402_5%

PX@

Q18

Q18 2N7002K_SOT23-3

2N7002K_SOT23-3

3

2

1

2

D

+3VGS

1

10U_0603_6.3V6M

PX@

Q15

LP2301ALT1G_SOT23-3

PX@

C1024

0.1U_0402_16V4Z

1U_0603_10V6K

1

C290

C289

PX@

2

PXS_PWREN#

2

@

R240

470_0603_5%

2

1

D

2

G

@

S

3

Q16

Q16 2N7002K_SOT23-3

2N7002K_SOT23-3

@

1

2

R244

0_0402_5%

Title

ATI_MarsXTX_M2_BACO POWER

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA8642P M/B

18 57Thursday, November 01, 2012

E

3

4

0.1

of

LENOVO Y485P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual