LENOVO X270 Schematics

WV

5

4

-4 SIT LOGIC SCHEMATICS

WV-

1

4

3

2

6/27/2016

001.T

002.POW

D

003.CPU(1/16) :

004.CP

ITLE PAGE

ER SEQUENCE

DDI/EDP

U(2/16) : DDR4

005.CPU(3/16) : DDR4

006.C

PU(4/16) : MISC/JTAG

007.CPU(5/16) : LPC/SPI/SMBUS/C-LINK

008.CPU(6/16) :

009.CPU(7/

010.CP

U(8/16) : PCIE/USB/SATA

011.CPU(9/16)

PU

C

012.C

(10/16) : CLOCK SIGNALS

013.CPU(11/16)

014.CPU(12/16) :

16) : AUDIO/SDXC

LPSS/ISH

: CSI-2/EMMC

: SYSTEM PM

CPU POWER

015.CPU(13/16) : CPU POWER

016.CPU(14/16) : PCH POWER

017.CP

018.CP

019.XDP

020.RT

021.SPI

B

022.DDR4

023.T

024.TYPE-C_MU

025.BL

026.

027.BL

028.DP

029.D

030.BL

U(15/16) : GND U(16/16) : CFG/RESERVED

CONNECTOR

C BATTERY

FLASH

SO DIMM

YPE_C_ CONTROLLER

X

ANK ANK

BL

ANK

SWITCH

P DEMUX

ANK

031.BLANK

A

032.BLANK

033.BLANK

034.BLANK

035.BLANK

5

036.BLANK

037.R

03

039.BL

04

041.DISPL

042.BL

043.SAT

04

F COMPONENT

8.LCD/LID/MIC/CAMERA/PWR SW

ANK

0.HDMI CONNECTOR

AY PORT CONNECTOR

ANK

A HDD CONN

4.USB POWER/CONN

045.USB POWER/CONN

046.GBE

047.GBE

048.GBE

049.RJ45

P

050.

CLARKVILLE

LAN SWITCH

MAGNETICS

CONNECTOR

CIE MINI CARD SLOT

051.MEDIA CARD CONTROLLER

052.MED

053.S

054.AUDIO AL

055.AU

056.A

057.AUDIO E

058.AUDIO

IA CARD INTERFACE

M

ART CARD I/F

C3245-GRT

DIO CONNECTOR

UDIO JACK SENSE

XT MIC I/F

SPEAKER

059.AUDIO BEEP

060.D

061.M

062.M

OCKING CONNECTOR

EC1653(1/3) EC1653(2/3)

063.MEC1653(3/3)

4.KEYBOARD/TRACK POINT

06

065.T

066.BL

067.FA

068.G-SENSO

OUCH PAD/NFC/FPR

ANK

N CONNECTOR

R

069.TPM

070.SMBUS SW/LPC DEBUG PORT

4

3

071.THINK ENG

INE(1/2)

072.THINK ENGINE(2/2)

073.DC-IN

074.BA

075.

TTERY INPUT

TTERY CHARGER(BQ25700)

BA

076.BLANK

077.BLANK

078.DC

/DC VCC5M/VCC3M(TPS51285B)

079.DC/DC IMVP8(NCP81208)

080.DC/DC CPUCORE(NCP81382)

081.DC/

082.DC

083.DC

084.BL

085.DC

DC VCCGFXCORE_I(NCP81381)

/DC VCCSA(NCP81380)

/DC VCC1R0_SUS(TPS51367R)

ANK

/DC VCC1R2A(TPS51716)

086.DC/DC VCC1R8_SUS(RT8068A)

087.BL

088.D

089.BLOCK

ANK

C/DC VCC2R5A(RT8068A)

DIAGRAM

090.BLANK

091.BL

092.L

09

ANK

OAD SW PCH SUS/TRACK POINT

3.LOAD SW LAN

094.LOAD SW CPU

095.LO

09

097.BL

098.

AD SW B

6.LOAD SW WWAN & WLAN

ANK

H FOR SCREW HOLES

PT

099.BLOCK DIAGRAM

100.NEC

Se

cu

rity Classification

Secu

cu

rity Classification

Se

Is

ued Date

s

ued Date

Iss

ued Date

s

Is

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

I

TH

I

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

TH

I

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

TH

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

LED BOARD

LC

Future Center Secret Data

LC

3

Future Center Secret Data

2

2016/

2/

Deciphered Date

2015/8/10

t

le

Ti

le

t

le

t

Ti

TI

PAGE

TLE

PAGE

TITLE

TLE

PAGE

TI

e

z

Si

e

z

Si

z

e

ument Number Rev

Doc

oc

D

oc

ument Number Rev

D

C

us

tom

us

C

us

tom

C

Date: Sheet

ues

day, December 20, 2016

T

day, December 20, 2016

ues

T

day, December 20, 2016

ues

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

1

1 100

of

1 100

of

1 100

of

D

C

B

A

0

.3

0

.3

0

5

4

3

2

1

D

C

Voltage Rails

B

State

S5 S4/AC Only

A

S5 S4 Battery only

( O --> Means ON , X --> Means OFF )

Power Plane

S0

S3

VSYS

VCC3SW

O

VCC1R0_SUS(Deep Sleep)

VCC3B VCCST_CPU(Deep Sleep)

VCCSTG_CPU

VCC3M

VCC1R2A

VCC5M

+VCCSA VCCCPUIO VCCCPUC VCC1R8_SUS(Deep Sleep)

VCC3_SUS(Deep Sleep)

VCCMPHY_GATE VCCGFXCORE_I VCCSTG

OO O

OO

O

X

XX

X

ORE

EC SMBus1 address

Device

G-

Senor (KX023)

Address

001

1 110Xb

PCH SM Bus address

Device

CH-

A

Tou ch Pa d

DDR

DIMM0 (J21)

Address

1001 0000b

$2C

EC SMBus0 address

Device

in Battery

Ma

Address

0x16

EC SMBus5 address

vice

De

T

ype C controller

EC SMBus2 address

Device

BATTERY Charger PU101

Address

0x12H (0001001bX)

PCH SM Bus0 address

vice

De

In

tel Lan_I219

NF

C

Address

0XC8

??

???

EC SMBus7 address

Device

Se

cond Battery

Address

000B

Address

0 X16

BOM Structure Table

BOM

Structure BTO Item

@ I3

@ I5@ I7

@ VPRO@ NVPRO@ TI@ PA

@

ME@

CONN@

RF

@ RF_NS@

EMC_

NS@

EMC@ KA

BYU@ SKYU@

SK

YI3@

SK

YI5@

SKYI7@

SKYi5

VPRO@

SKYi7

VPRO@

i5

VPRO@

i7

VPRO@

Not stuff CPU I3 KABYlake U CPU I5 KABYlake U

CPU I7 KABYlake U For VPRO part For NVPRO part For TI TUSB546 Type C Switch For Parade 8743 Type C Switch ME part(connector, hole)

ME part(connector, hole)

RF component RF reserved components EMC reserved components EMC

For

Kabylake use

For

skylake U use

CPU I3 SKYlake U CPU I5 SKYlake U CPU I7 SKYlake U

For

I5 VPRO SKYLAKE CPU

For

I7 VPRO SKYLAKE CPU

For

I7 VPRO KABYLAKE CPU

components

I5 VPRO KABYLAKE CPU

D

C

B

A

S5 S4 AC & Battery don't exist

XX

5

Ti

tle

Title

curity Classification

Security Classification

Se

sued Date

Is

sued Date

Is

X

4

sued Date

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

014/08/10

2014/08/10

LC

Future Center Secret Data

LC

ciphered Date

De

ciphered Date

De

ciphered Date

2

2015/08/10

Title

BLOCK DIAGRAM

BLO

CK DIAGRAM

BLOCK DIAGRAM

Size

Si

ze

Si

Do

cument Number Rev

Do

Document Number Rev

Date: Sheet of

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

Tu

esday, December 20, 2016

Tu

esday, December 20, 2016

Tu

1

2100

0.

3C

0.

0.3C

of

D

Type

1 t

C

C DDI

o 3 DP HUB

5

0 Test_Point_40MIL

TP8

DD

IP2_CTRLCLK30

IP2_CTRLDATA30

D

4

3

2

CPU

V

CCPUIO

C

3_SUS

VCC

RC1

24.9_0201_1%

2

1

IP1_0N

DD

IP1_0P

DD

IP1_1N

DD

D

IP1_1P

D

IP1_2N

DD

IP1_2P

DD

D

IP1_3N

D

IP1_3P

D

IP1_CTRLCLK

DD

D

IP1_CTRLDATA

D

IP2_CTRLCLK

DD

IP2_CTRLDATA

EDP_

COMP

E55

F5

E58

F58

F53

G53

F56

G56

C50

D50

C52 D52

A50

B50

D51

C51

L13 L12

N11

N12

E52

5

N7

N8

DDI

DDI1_T

DDI1_T DDI1_T

DDI1_T DDI2_T

DDI

DDI DDI2_T

DDI2_T

GP GPP

GPP GPP

ED

REV = 1

U1A

SKYL

1_T

XN[0]

1_T

XP[0]

XN[1]

1_T

XP[1]

XN[2]

XP[2] XN[3]

XP[3] XN[0]

XP[0]

2_T

XN[1]

2_T

XP[1]

XN[2]

XP[2]

XN[3]

XP[3]

_E18/DDPB_CTRLCLK

P

_E19/DDPB_CTRLDATA

_E20/DDPC_CTRLCLK _E21/DDPC_CTRLDATA

_E22/DDPD_CTRLCLK _E23/DDPD_CTRLDATA

P_RCOMP

AKE-U_BGA1356

SKYLAKE_U

DDI

DIS

PLAY SIDEBANDS

?

LT

TXN0

EDP_

C47

TXN[0]

EDP_

C46

P_

TXP[0]

ED

D46

ED

TXN[1]

P_

C45

ED

TXP[1]

P_

A45

EDP_

TXN[2]

B45

TXP[2]

EDP_

A47

EDP_

TXN[3]

B4

TXP[3]

EDP_

E4

EDP_

EDP

GPP

GPP GPP

GP

F 20

1 O

ED

P_

ED

DISP_UTIL

P_

DDI

1_A

DDI1_A

2_A

DDI DDI

2_A

DDI3_A

_E13/DDPB_HPD0

_E14/DDPC_HPD1 _E15/DDPD_HPD2

P

_E16/DDPE_HPD3

_E17/EDP_HPD

GPP

BKLTEN

EDP_

P_

BKLTCTL

ED

EDP_

AUXN

AUXP

UXN

UXP

UXN UXP UXN

UXP

VDDEN

?

100K_0201_5%

F4

B52 G50

F50

E48

F48

G4 F46

L9 L7 L6 N9 L10

R12

R11 U13

TXP0

EDP_

TXN1

EDP_

P_

TXP1

ED

7

AUXN

EDP_

5

AUXP

EDP_

5

DD

IP1_AUXN

DD

IP1_AUXP

D

IP2_AUXN

D

DD

IP2_AUXP

6

DD

IP1_HPD

IP2_HPD

DD

P_

HPD

ED

A_

BLON

VG

EL

_BKLT_CTRL

PAN

_POWER_ON

EL

RC1

RC5

1

RC2

1

100K_0201_5%

2

RC3

1

100K

_0201_5%

2

RC4

1

2

_0201_5%

1

100K

2

6

_0201_5% 100K

P_

TXN0 38

ED

P_

TXP0 38

ED

EDP_

TXN1 38

ED

TXP1 38

P_

ED

AUXN 38

P_

AUXP 38

EDP_

DD

IP1_AUXN 24

IP1_AUXP 24

DD

IP2_AUXN 30

DD

IP2_AUXP 30

D

IP1_HPD 23,24

D

DD

IP2_HPD 30

EDP_

HPD 38

VG

BLON 61

A_

PAN

_BKLT_CTRL 38

EL

PANEL

_POWER_ON 72

2

7

RC11

2.2K

_0402_1%

1

D

IP1_0N24

D

IP1_0P24

D

IP1_1N24

D D

IP1_1P24

D

DD

IP1_2N24

DD

IP1_2P24

IP1_3N24

DD

IP1_3P24

D

IP2_0N30

D

IP2_0P30

DD

IP2_1N30

DD

IP2_1P30

DD

IP2_2N30

IP2_2P30

DD

IP2_3N30 IP2_3P30

DD

1

@

1

PCB

ZZZ

NM-B

061

DAZ1

2F00100

D

C

B B

2/

3

U1

S IC FJ

8067702739633 SR340 H0 2.6G 01 !, A.3

SA00

0086M10

i5 VPRO@

U1

S IC

8066201924931 SR2F0 D1 2.4G BGA 1356 01 !, A.3

FJ

0

007GN20

SA0

SKYi5 VPRO@

LC

Future Center Secret Data

LC

Future Center Secret Data

LC

Future Center Secret Data

Deciphered Date

2

2015/08/10

U1

FJ

8067702739738 SR2ZW H0 2.4G 01 !, A.5

S IC

0080720

SA00

I3@

U1

S IC FJ

A

8066201931106 QLB3 D1 2G BGA 1356, A.3

5

SA0

SKYI3@

0

0082E20

U1

S IC

8067702739739 SR2ZU H0 2.5G 01 !, A.4

FJ

0

0080320

SA0

I5@

U1

S IC

8066201930409 SR2EY D1 2.3G 01 !, A.3

FJ

SA0

007GP30

0

SKYI5@

4

U1

S IC FJ

8067702739740 SR2ZV H0 2.7G 01 !, A.4

SA00

0080420

I7@

U1

S IC FJ

8066201930408 SR2EZ D1 2.5G 01 !, A.3

0

007GM30

SA0

SKYI7@

cu

rity Classification

Se

Secu

rity Classification

Se

rity Classification

cu

ued Date

Iss

ued Date

s

Is

T

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

T

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

T

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/2/

2016/

2016/2/

U1

S IC FJ

8067702739628 SR33Z H0 2.8G 01 !, A.3

0086N10

SA00

i7 VPRO@

U1

FJ

8066201924950 SR2F1 D1 2.6G 01 !, A.5

S IC

0

007GL30

SA0

SKYi7 VPRO@

t

le

Tit

Ti

Tit

le

CPU(

1

/16) : DDI/EDP

1

/16) : DDI/EDP

CPU(1

Size

e

Siz

c

ument Number Rev

Do

Doc

ument Number Rev

c

Cu

Cus

tom

s

tom

Cus

Date: Sheet

T

ues

day, December 20, 2016

ues

T

day, December 20, 2016

ues

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

1

3100

0.

0.3

3

0.3

of

A

5

M_A_

DQ[63:0]22

D

C

LOGIC

B

4

M_A_

DQ0

M_A_DQ1 M_A_DQ2 M_A_DQ3

M_A_DQ4

M_A_DQ5 M_A_DQ6

M_A_DQ7 M_A_DQ8

A_DQ9

M_ M_A_DQ10

A_DQ11

M_

M_A_DQ12

A_DQ13

M_

M_A_

DQ14

M_

A_DQ15

M_A_DQ16

M_A_DQ17

M_

A_DQ18

M_A_DQ19

M_

A_DQ20

M_A_DQ21 M_A_DQ22

M_A_DQ23

M_A_DQ24 M_A_DQ25 M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29 M_A_DQ30

A_DQ31

M_

A_DQ32

M_

A_DQ33

M_

A_DQ34

M_ M_A_DQ35

A_DQ36

M_ M_

A_DQ37

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_

A_DQ41

M_A_DQ42

M_A_DQ43

M_A_DQ44

A_DQ45

M_

M_A_DQ46 M_A_DQ47 M_A_DQ48

A_DQ49

M_

M_A_DQ50

M_A_DQ51

M_A_DQ52

A_DQ53

M_

M_A_DQ54

A_DQ55

M_

A_DQ56

M_

A_DQ57

M_ M_A_DQ58

M_A_DQ59

M_

A_DQ60

M_A_DQ61

M_

A_DQ62

M_A_DQ63

DDR_VTT_PG_CTRL85

U1B

AL71

D

DR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

71

AN

DR0_DQ[7]

D

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

70

AU

DDR0_DQ[14]

AU

69

0_DQ[15]

DDR

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DR1_DQ[4]/DDR0_DQ[20]

D

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

D

DR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DR1_DQ[12]/DDR0_DQ[28]

D

AF69

DR1_DQ[13]/DDR0_DQ[29]

D

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH

69

D

DR1_DQ[15]/DDR0_DQ[31]

BB65

D

DR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DR0_DQ[19]/DDR0_DQ[35]

D

5

BA6

DR0_DQ[20]/DDR0_DQ[36]

D

5

AY6

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA6

1

DDR0_DQ[24]/DDR0_DQ[40]

A

W61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

1

AY6

D

DR0_DQ[29]/DDR0_DQ[45]

BA59

D

DR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DR1_DQ[18]/DDR0_DQ[50]

D

65

AN

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DR1_DQ[20]/DDR0_DQ[52]

D

AP66

D

DR1_DQ[21]/DDR0_DQ[53]

AT

65

DDR1_DQ[22]/DDR0_DQ[54]

AU

65

D

DR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU

61

DR1_DQ[25]/DDR0_DQ[57]

D

0

AP6

DDR1_DQ[26]/DDR0_DQ[58]

60

AN

DDR1_DQ[27]/DDR0_DQ[59]

AN61

D

DR1_DQ[28]/DDR0_DQ[60]

AP61

D

DR1_DQ[29]/DDR0_DQ[61]

AT60

D

DR1_DQ[30]/DDR0_DQ[62]

AU60

D

DR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-U_BGA1356

REV = 1

?

SKYLAKE_UL

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

A

DDR CH -

2

0.1U_0402_16V7-K

SN74AUP1G07DCKR_SC-70

3

T

DDR0_CKN[0]

DDR0_CKP[0]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CK

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_ODT[0]

1

VCC1R2A

U3

6

4

Y

DDR0_V

DDR1_V

DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

D

DR0_DQSN[0]

DDR0_DQSP[0]

DR0_DQSN[1]

D

DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA

REF_DQ

DDR_V

TT_CNTL

100K_0201_5%

5

@

C

NC

VC

D

A

GN

3

1 2

A[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_M DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_M

A[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_M

A[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSN[2] D

DR1_DQSN[1]/DDR0_DQSN[3]

D

DR1_DQSP[1]/DDR0_DQSN[3]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DR0_DQSP[3]/DDR0_DQSP[5]

D

DR1_DQSN[2]/DDR0_DQSN[6]

D

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

D

DR1_DQSP[3]/DDR0_DQSP[7]

OF 20

DDR_VTT_PG_CTRL

C7

09

2

@

AU53

AT53 AU55

AT55 BA56

BB56

W56

A

E[2]

AY5

6

AU45

AU43

AT45 AT43

BA51 BB54 BA52 AY52

AW52

AY55

AW54 BA54 BA55

AY54 AU46

AU48 AT46

AU50

AU52 AY51

AT48

AT50 BB50

AY50

BA50

2

BB5

AM70 AM6

9

AT

69

AT70

AH66

AH65

G69

A

AG70

BA64

AY64

0

AY6

BA60 AR66

65

AR

AR61

AR

60

AW50

AT52

7

AY6

8

BA6

7

AW67

?

VCC3B

2

RC1

69

@

1

DTC015TMT2L_VMT3

QC

2

-M_A_

DDRCLK0_1866M

M_A_DDRCLK0_1866M

-M_A_DDRCLK1_1866M

M_A_DDRCLK1_1866M

M_A_CKE0

M_A_CKE1

-M_A_CS0

-M_A_CS1

-M_A_ODT0

-M_A_ODT1

M_

A_A5

M_A_A9 M_

A_A6

M_A_A8

M_A_A7

M_A_BG0

M_A_A12 M_

A_A11

M_A_ACT_N

M_A_A13

-M_A_CAS

A_WE

-M_

-M_A_RAS A_BS0

M_

M_A_A2

A_BS1

M_

A_A10

M_

A_A1

M_ M_

A_A0

M_A_A3

M_

A_A4 -M_A_DQS4

-M_A_DQS0

M_A_DQS0

-M_

A_DQS1

M_

A_DQS1

-M_

A_DQS2

M_A_DQS2

DQS3

-M_A_

M_A_DQS3

-M_

A_DQS4

M_A_DQS4

-M_A_DQS5

A_DQS5

M_

-M_A_DQS6

A_DQS6

M_

-M_A_DQS7

M_A_DQS7

A_ALERT_N

M_

A_PARITY

M_

1

@

VCC3M

2

RC8

100K_0201_5%

1

3

2

RC9

10K

TP

VC

_0201_5%

DDR_PG_CTRL

1

M_A_BG0 22

M_A_ACT_N 22

M_A_BG1 22

-M_A_CAS 22

-M_A_WE 22

-M_A_ M_

M_

DDR4_VREF_CA_M3 22

17 Test_Point_40MIL

C1R2A

2

@

1

-M_A_DDRCLK0_1866M 22 M_A_DDRCLK0_1866M 22

-M_A_DDRCLK1_1866M 22 M_A_DDRCLK1_1866M 22

M_A_CKE0 22

M_A_CKE1 22

-M_A_CS0 22

-M_A_CS1 22

-M_A_ODT0 22

-M_A_ODT1 22

RAS 22

A_BS0 22

A_BS1 22

A_ALERT_N 22

A_PARITY 22

M_

A_A0

M_A_A1

M_A_A2

M_A_A3 M_A_A4 M_

A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9M_A_BG1

M_A_A10

M_A_A11

M_A_A12

M_A_A13

-M_A_DQS0

A_DQS1

-M_

-M_A_DQS2

-M_A_DQS3

-M_

A_DQS5

-M_A_DQS6

-M_A_DQS7

M_A_DQS0 M_A_DQS1

M_

A_DQS2

M_A_DQS3

M_A_DQS4

M_

A_DQS5

M_A_DQS6

M_

A_DQS7

1

M_A_A[0..13] 22

A_DQS[0..7] 22

-M_

M_A_DQS[0..7] 22

D

C

B

A

LOGIC

5

4

Security Classification

Se

curity Classification

Security Classification

Issued Date

Is

sued Date

Issued Date

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2016/2/3

LC Future Center Secret Data

2/3

Deciphered Date

2

2015/08/10

tle

Ti

tle

Title

e

Siz

Size

e

Siz

stom

Cu

stom

Cu

Custom

Date: Sheet

2/16) : DDR4

CPU(

CPU(2/16) : DDR4

cument Number Rev

Do

Document Number Rev

cument Number Rev

Do

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

Tuesday, December 20, 2016

T

uesday, December 20, 2016

Tuesday, December 20, 2016

LOGIC

4100

of

4100

1

of

A

3

0.

3

0.

0.3

5

D

C

4

AY39 AW3

AY37 AW3

BB39 BA39

BA37

BB3

AY35

AW3 AY33

AW33

BB35

BA35

BA3

BB33 AU4

AT40

AT37

AU

AR4

AP40

AP37

AR3

AT3

AU33

AU3

AT

AR33

AP3 AR

AP3 AY31

AW3

AY29

AW2

BB3

BA3

BA2

BB29

AY2

AW2

AY25

AW25

BB2

BA27 BA25

BB25

AU2

AT AT25 AU

AP2

AN2

AN

AP25

AT2 AU2

AU21

AT AN

AP2

AP21

AN

9

7

7 5

3

0

37

0

7

3

0

3

0

3 0

3

0

1

9

1

9

7

2

5

2

7

5

2

2 2

1

2 2

2

1

U1C

DD

R0_DQ[32]/DDR1_DQ[0]

DD

R0_DQ[33]/DDR1_DQ[1]

DD

R0_DQ[34]/DDR1_DQ[2]

R0_DQ[35]/DDR1_DQ[3]

DD

R0_DQ[36]/DDR1_DQ[4]

DD

R0_DQ[37]/DDR1_DQ[5]

DD

D

R0_DQ[38]/DDR1_DQ[6]

D

DD

R0_DQ[39]/DDR1_DQ[7]

DD

R0_DQ[40]/DDR1_DQ[8]

DD

R0_DQ[41]/DDR1_DQ[9]

DD

R0_DQ[42]/DDR1_DQ[10]

R0_DQ[43]/DDR1_DQ[11]

DD

R0_DQ[44]/DDR1_DQ[12]

DD

R0_DQ[45]/DDR1_DQ[13]

DD

R0_DQ[46]/DDR1_DQ[14]

DD

R0_DQ[47]/DDR1_DQ[15]

DD

R1_DQ[32]/DDR1_DQ[16]

R1_DQ[33]/DDR1_DQ[17]

DD

R1_DQ[34]/DDR1_DQ[18]

DD

D

R1_DQ[35]/DDR1_DQ[19]

D

R1_DQ[36]/DDR1_DQ[20]

DD

D

R1_DQ[37]/DDR1_DQ[21]

D DD

R1_DQ[38]/DDR1_DQ[22]

DD

R1_DQ[39]/DDR1_DQ[23]

R1_DQ[40]/DDR1_DQ[24]

DD

R1_DQ[41]/DDR1_DQ[25]

R1_DQ[42]/DDR1_DQ[26]

DD DD

R1_DQ[43]/DDR1_DQ[27]

R1_DQ[44]/DDR1_DQ[28]

DD

R1_DQ[45]/DDR1_DQ[29]

D

R1_DQ[46]/DDR1_DQ[30]

D

DD

R1_DQ[47]/DDR1_DQ[31]

R0_DQ[48]/DDR1_DQ[32]

DD

R0_DQ[49]/DDR1_DQ[33]

DD

R0_DQ[50]/DDR1_DQ[34]

DD

R0_DQ[51]/DDR1_DQ[35]

DD DD

R0_DQ[52]/DDR1_DQ[36]

D

R0_DQ[53]/DDR1_DQ[37]

D

R0_DQ[54]/DDR1_DQ[38]

D

R0_DQ[55]/DDR1_DQ[39]

DD

R0_DQ[56]/DDR1_DQ[40]

DD

R0_DQ[57]/DDR1_DQ[41]

DD

R0_DQ[58]/DDR1_DQ[42]

DD

R0_DQ[59]/DDR1_DQ[43]

DD

R0_DQ[60]/DDR1_DQ[44]

D

R0_DQ[61]/DDR1_DQ[45]

D

R0_DQ[62]/DDR1_DQ[46]

D

DD

R0_DQ[63]/DDR1_DQ[47]

R1_DQ[48]

DD DD

R1_DQ[49]

DD

R1_DQ[50]

D

R1_DQ[51]

D

DD

R1_DQ[52]

D

R1_DQ[53]

D

R1_DQ[54]

DD

D

R1_DQ[55]

D

R1_DQ[56]

D

R1_DQ[57]

DD

D

R1_DQ[58]

D

R1_DQ[59]

D

R1_DQ[60]

D

DD

R1_DQ[61]

R1_DQ[62]

DD

D

R1_DQ[63]

D

SKYLAKE-U_BGA1356

REV = 1

?

LT

SKYLAKE_U

DDR1_MA

[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA

[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA

[6]/DDR1_CAA[2]/DDR1_MA[6]

[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA

A

[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_M

R1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DD

[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA DDR1_MA

[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_M

[15]/DDR1_CAA[8]/DDR1_ACT#

A

DD

R1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA

[13]/DDR1_CAB[0]/DDR1_MA[13]

S

#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_CA

D

R1_WE#/DDR1_CAB[2]/DDR1_MA[14]

D

DDR1_RAS

#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_B

[0]/DDR1_CAB[4]/DDR1_BA[0]

A

DDR1_MA

[2]/DDR1_CAB[5]/DDR1_MA[2] [1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA

DDR1_MA

[10]/DDR1_CAB[7]/DDR1_MA[10]

A

[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1_M

A

[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_M

R0_DQSN[4]/DDR1_DQSN[0]

DD

R0_DQSP[4]/DDR1_DQSP[0]

DD

R0_DQSN[5]/DDR1_DQSN[1]

DD

R0_DQSP[5]/DDR1_DQSP[1]

D

R1_DQSN[4]/DDR1_DQSN[2]

D D

R1_DQSP[4]/DDR1_DQSP[2]

D

R1_DQSN[5]/DDR1_DQSN[3]

D

R1_DQSP[5]/DDR1_DQSP[3]

DD

R0_DQSN[6]/DDR1_DQSN[4]

DD

R0_DQSP[6]/DDR1_DQSP[4]

DD

R0_DQSN[7]/DDR1_DQSN[5]

DD

R0_DQSP[7]/DDR1_DQSP[5]

DDR

CH

- B

F 20

3 O

DDR1_CKN[ DDR1_CKN[

DDR1_CKP

DDR1_CKP[1]

DDR1_CKE

DDR1_CS#[

R1_ODT[0]

DD

R1_ODT[1]

DD

DDR1_MA

R1_DQSN[6]

D

R1_DQSP[6]

DD

R1_DQSN[7]

DD

R1_DQSP[7]

DDR1_ALE

DDR1_PA

DRAM

_RESET#

R_RCOMP[0]

D

R_RCOMP[1]

D

R_RCOMP[2]

DD

3

AN4

5

0]

AN46

1]

AP45

[0]

AP46

AN56

[0]

AP55

[1]

AN5

5

[2]

AP5

3

[3]

BB42

0]

AY42

1]

BA42

W42

A AY48

AP50 BA48

BB48

AP48

2

AP5

0

AN5

AN48 AN53 AN52

3

BA4 AY43

AY44

AW4

4

BB44 AY4

7

BA4

4

6

AW4

AY46

6

BA4 BB46

[3]

BA47

[4]

BA38

AY3

8

AY34

BA34

AT38

8

AR3

AT3

2

AR3

2

0

BA3

AY30 AY26

BA26

5

AR2

2

7

AR

2

AR2 AR2

1

RC16

AN4

3

RT#

3

AP4

R

1

3

AT

8

AR1

SM

8

AT1

SM_

AU18

SM

?

6

ace near to CPU

Pl

_

RCOMP0

RCOMP1

_

RCOMP2

RC1

RC12

RC13

1

0_0201_5%

1

2

1

2

121_0201_1%

2

1

2

6_0201_1%

80.

100_0201_1%

VC

6 CC7

@

2

1R2A

C

2

RC10 470_0201_5%

1

2

1

_0201_6.3V6K

0.1U

RC1

2

1

0_0201_5%

5

4

-DRA

MRS

T 22

1

D

C

B

A

t

le

Ti

t

le

Ti

t

rity Classification

Secu

rity Classification

Secu

rity Classification

Secu

ued Date

Iss

Is

ued Date

s

Is

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

T

HIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

LC

Future Center Secret Data

LC

Future Center Secret Data

LC

Deciphered Date

2/

3

2/

3

2/

3

Deciphered Date

2

2015/08/10

le

CPU(

3

/16) : DDR4

CPU(3

/16) : DDR4

CPU(

/16) : DDR4

3

Siz

e

Siz

Size

c

ument Number Rev

Do

c

ument Number Rev

Do

Doc

ument Number Rev

tom

s

Cu

s

tom

Cu

s

tom

Cu

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

T

ues

day, December 20, 2016

T

day, December 20, 2016

ues

day, December 20, 2016

Tues

1

5100

of

5100

of

5100

of

B

A

3

0.

3

0.

3

0.

5

4

3

2

1

Update description

D

For DCI debug RC113 OP, RC148 short(XDP_TDO→ PCH_TDO)

D

RC138 OP, RC145 short(XDP_TMS→ PCH_TMS) RC137 OP, RC147 short(XDP_TRST→ PCH_TRST) RC142 OP, RC143 short(XDP_TCK0→ JTAGX) RC139 OP, RC146 short(XDP_TDI→ PCH_TDI)

C

VCCSTG

2

4

RC1

1K_0201_5%

1

PEC

I62

ROCHOT61,62,75,79

-P

B

RC1

RC18

RC1

RC20

RC16

7

9

1

510_0201_5%

1 2 1

1

2

9_0201_1%

49.

9_0201_1%

49.

9_0201_1%

49.

9_0201_1%

49.

CST

VC

2

RC1 1K_0201_5%

1

Test_Point_40MIL

5

TP50

-PROCHOT_R

D63

1

A5

C65

C63

A65 C55

D55

B54

C56

A6

A7

BA5

AY5

AT

AU16

H66

H65

D

CATERR#

4

PEC

I

P

ROCHOT#

TH

ERMTRIP#

KTOCC#

S

BPM#[0]

[1]

BPM#

BPM#[2]

[3]

BPM# GP

P_E3/CPU_GP0

P_E7/CPU_GP1

GP

P_B3/CPU_GP2

GP

P_B4/CPU_GP3

GP

16

ROC_POPIRCOMP

P

CH_OPIRCOMP

OPCE_RCOMP OP

C_RCOMP

SKYLAKE-U_BGA1356

REV = 1

JTAG

XD

B6

U MISC

CP

4 OF 20

PROC_TCK

P

PROC_TDO

P

ROC_TMS

PROC_TRST#

CH_JTAG_TCK

P

PCH_JTAG_TDI PCH_JTAG_TDO P

CH_JTAG_TMS

PCH_TRST#

?

ROC_TDI

JTAGX

1

D60 A61

C60 B5

9

B5

6

D59

A56

C59

C61

A5

9

51_0201_5%

RC21

1

RC1

42

@

1

RC137 51_0201_5%

@

2

51_0201_5%

2

P_TCK0

XDP_TDI XDP_TDO

XD

P_TMS

-X

DP_TRST

PCH_TCK

P_

CK0 19

T

XD

P_TDI 19 P_TDO 19

XD

XDP_TMS 19

-XDP_TRST 19

PC

H_TCK 19

@

?

SKYLAKE_ULT

U1

C

B

A

Ti

tle

Title

Security Classification

Is

sued Date

Issued Date

Is

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2016/2/3

LC Future Center Secret Data

LC

Future Center Secret Data

LC Future Center Secret Data

2/3

Deciphered Date

2

2015/08/10

Title

CPU(4/16) : MISC/JTAG

CPU(

4/16) : MISC/JTAG

CPU(

4/16) : MISC/JTAG

Siz

e

Siz

e

Size

cument Number Rev

Do

cument Number Rev

Do

Document Number Rev

stom

Cu

Custom

Date: Sheet

Date: Sheet of

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

T

uesday, December 20, 2016

T

Tuesday, December 20, 2016

6100

1

6100

of

A

3

0.

0.3

5

C

3_SUS

VC

4

3

2

1

D

VCC

3_SUS

VCC

RC22

_0201_5%

3B

2

@

RC23

10K

1

-CL_

SPI_C

SPI_M

IO2

SPI_

SPI_IO3

-SP

I_CS0

I_CS2

-SP

DOCK

DOCK DOCK

DOCK

CL_

CLK_WLAN

CL

DATA_WLAN

_

RST_WLAN

2

@

1 1K_0201_5%

1

RC15

LK

ISO_IO1

OSI_IO0

ID1

ID2 ID3

ID0

_0201_5%

1

0 1K_0201_5% 5

RC1

U1

E

M2 M3

J4

V1

V2

M1

G3

G2 G1

2

1

SPI0_ SPI0_

S

I0_MOSI

P

I0_IO2

SP

I0_IO3

SPI0_

GPP

_D1/SPI1_CLK

GPP

_D2/SPI1_MISO

P

_D3/SPI1_MOSI

GP

P

_D21/SPI1_IO2

GP GP

_D22/SPI1_IO3

P

GPP

_D0/SPI1_CS#

CL_CLK

CL_DA

CL_RS

GP

_A0/RCIN#

P

_A6/SERIRQ

GPP

SKYL

REV = 1

SPI - FLASH

CLK MISO

CS0#

CS1#

CS2#

SPI

- TOUCH

C LINK

A

T

#

T

AKE-U_BGA1356

AV2

AW3

AV3

AW2

AU4 AU3

AU

AW13

AY1

2

@

1

SKYLAKE_

?

LT

U

BU

S, SMLINK

SM

GPP

_C0/SMBCLK

_C1/SMBDATA

GPP

_C2/SMBALERT#

GPP

P

_C3/SML0CLK

GP

P

_C4/SML0DATA

GP

_C5/SML0ALERT#

P

_C6/SML1CLK

GPP

LPC

GPP

_A14/SUS_STAT#/ESPI_RESET#

GPP

5

F 20

O

_C7/SML1DATA

_B23/SML1ALERT#/PCHHOT#

GPP

_A1/LAD0/ESPI_IO0

GPP

_A2/LAD1/ESPI_IO1

P

_A3/LAD2/ESPI_IO2

GP

_A4/LAD3/ESPI_IO3

GPP

_A5/LFRAME#/ESPI_CS#

GPP

_A9/CLKOUT_LPC0/ESPI_CLK

_A10/CLKOUT_LPC1

GPP

_A8/CLKRUN#

GPP

?

2

@

1

LK21,69

SPI_C

ISO_IO121,69

SPI_M

OSI_IO021,69

SPI_M

SPI_IO221

IO321

SPI_

P

I_CS021

-S

I_CS269

-SP

C

70

TA

LE : Functional Strap

B

0 1K_0201_5%

RC14

DOCK

-DOCK

-NFC_

CL_

-CL_

-KB IRQSER61,

1 1K_0201_5%

1

8.

2K

RC14

ID[3:0]60

_CAP_ID60

DTCT65

CLK_WLAN50

DATA_WLAN50

RST_WLAN50

RC61

SPI0_IO2 (Consent Strap)

HIGH

Ena

bled (Default)

Disabled

LOW

R7

R8

R10

R9 W2

W1 W3

V3

AM7

AY1 BA13 BB1

AY1

BA1

AW9 AY9 AW11

LPC

3

LP

3

LP

2

1

LPC

3_SUS

VCC

2

_0201_5% 1K

4

1

RC2

CLK

SMB_

DATA

SMB_

0_CLK

SML

0_DATA

_

SCL2

EC

SDA2

EC_

_AD0

_AD1

C

_AD2

C

_AD3

C

CLK_EC_24M_R

CLK_DEBUG_24M_R

2

1

2

499_0201_1%

5

1

RC2

RC3

499_0201_1% 6

RC2

1

0

1

2

1

_0201_5%

4.7K

RC27

2

0_0402_5%

2

_0201_5% .7K

4

1 2

RC28

22_0201_5%

VCC

2

1

3B

_0201_5% .2K

8

9 RC2

CLK 70

SMB_

DATA 70

SMB_

L

0_CLK 46

SM

L

0_DATA 46

SM

_

SCL2 62

EC EC_

SDA2 62

LP

_AD[3:0] 61,70

C

C_FRAME 61,70

-LP

-SUS

_STAT 61,70

LPC

CLK_EC_24M 61

CLK_DEBUG_24M 70

LPC

RUN 61,70

-CLK

D

C

TABLE : Functional Strap

SPI0_IO3 (A0 Personality Strap)

HI

GH

Disabled (Default) Enabled

B

LOW

TABLE : Functional Strap

SPI

0_MOSI (Boot Halt)

HIGH

Disabled (Default) Enabled

LOW

TAB

LE : Functional Strap

GP

P_C5/SML0ALERT # (LPC or eSPI)

HI

GH

eSPI is selected LPC is selected (Default)

LOW

LOG

B

IC

TAB

LE : Functional Strap

SPI

0_MISO (JTAG ODT Disable)

HIGH

Enabled (Default) Disabled

LOW

A

Se

rity Classification

cu

rity Classification

Se

Secu

rity Classification

ued Date

Iss

Is

ued Date

s

ued Date

s

Is

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

T

HIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2016/2/

3

2/

3

LE : Functional Strap

TAB

GP

P_C2/SMBALERT# (TLS Confidentiality)

HI

GH

Enable ME Crypto TLS with Confidentiality Disable ME Crypto TLS (Default)

LOW

Future Center Secret Data

LC

Future Center Secret Data

LC

Future Center Secret Data

LC

Deciphered Date

2

2015/08/10

LOG

IC

le

t

Ti

le

Tit

le

U(5/16) : LPC/SPI/SMBUS/C-LINK

CP

C

U(5/16) : LPC/SPI/SMBUS/C-LINK

P

CPU(5/16) : LPC/SPI/SMBUS/C-LINK

Size

e

Siz

e

Siz

Do

ument Number Rev

c

Do

ument Number Rev

c

Do

c

ument Number Rev

Cu

Cus

tom

s

Cu

s

tom

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

day, December 20, 2016

Tues

ues

T

ues

day, December 20, 2016

1

A

0.

0.3

3

0.

7100

of

7100

of

3

2

VCC1

4

R8_SUS

5

VCC3_SUS

1

D

NFC_DLREQ65

C_DATA_CPU

I2C_CLK_CPU

-INT_MIC_DTCT38

WWAN_ WWAN_CFG150

INT#_TYPEC_CPU

-WWAN_RESET

CFG050

C

INT#_TYPEC_CPU23

-EC_SCI61

-EC_WAKE61

I2C0_DATA65

I2C0_CLK65

I2

C_DATA_CPU23 C_CLK_CPU23

I2

ADD net name -WWAN_RESET to WWAN on 2016 0317

I2

WAN_RESET50

-W

-INT_MIC_DTCT

WWAN_CFG0

10K

2

1

_0201_5%

2

10K_0201_5%

1

RC32

R486

@

10K_0201_5%

RC33

2

@

1

2

1

1K_0201_5%

RC34

@

2

@

1K_0201_5%

1

RC152

NFC_DLREQ

-E

C_SCI

-E

C_WAKE

-MIC_HW_EN

2

0_0201_5%

RC35

1

U1

AN8

GP

P_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

7

AR

GPP_B18/GSPI0_MOSI

AM5

P_B19/GSPI1_CS#

GP

AN7

GPP_B20/GSPI1_CLK

AP5

GP

P_B21/GSPI1_MISO

AN

5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

P_C10/UART0_RTS#

GP

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GP

P_C21/UART2_TXD

AD

3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GP

P_C16/I2C0_SDA

U6

GP

P_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

P_F5/I2C2_SCL

GP

AH11

GP

P_F6/I2C3_SDA

AH12

GP

P_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

12

AF

P_F9/I2C4_SCL

GP

SKYLAKE-U_BGA1356

REV = 1

?

AKE_ULT

F

LPSS ISH

SKYL

GP

P_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

6 OF 20

GPP_D9

GPP_D10 GPP_D11

GPP_D12

P_D5/ISH_I2C0_SDA

GP

P_D6/ISH_I2C0_SCL

GP

P_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

P_C12/UART1_RXD/ISH_UART1_RXD

GP

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GP

P_A18/ISH_GP0

GPP_A19/ISH_GP1 GPP_A20/ISH_GP2

P_A21/ISH_GP3

GP

GPP_A22/ISH_GP4

GPP_A23/ISH_GP5

P_A12/BM_BUSY#/ISH_GP6

GP

D

P2

P3 P4

P1 M4

N3 N1

N2

AD11

AD12

U1 U2

U3

U4

AC1

2

AC

AC3 AB4

AY8

BA8 BB7

BA7

AY7

AW7

3

AP1

?

WWAN_CFG2 50

WWAN_CFG3 50

C

B

A

tle

Ti

tle

Security Classification

curity Classification

Se

curity Classification

Se

Is

sued Date

Issued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2/3

Future Center Secret Data

LC

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Ti

CPU(6/16) : LPSS/ISH

Siz

e

Siz

Size

cument Number Rev

Do

Document Number Rev

Do

cument Number Rev

stom

Cu

stom

Cu

stom

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

T

uesday, December 20, 2016

T

Tuesday, December 20, 2016

8100

1

8100

of

B

A

3

0.

3

0.

3

5

4

3

2

1

D

VC

3_SUS

C

1

6

8-J

47P_0201_25V

2

1K_0201_5%

VC

3_SUS

C

1

CC5

2

1

@

A

CE ON TOP SIDE

PL

Check

@

2

0_0603_5%

TP2 Te

st_Point_40MIL

1

33_0201_5% 33_0201_5%

33_0201_5%

1

0_0201_5%

RC37

TP1

@

st_Point_40MIL

Te

1

RC39

1

RC40 33_0201_5%

1

RC41

1

RC42

CTIVE65

NFC_A

VCC

3_SUS

2

RC38 1K_0201_5%

1

HDA_

SYNC_R

HDA_

BCLK_R

HDA

SDO_R

_

-HDA

RST_R

_

33

R91

NFC_A

CTIVE_R

2

@

_SPKR

PCH

BA22 AY22 BB2

BA21 AY2

AW22

AY20

A

W2

AK10

A

AK7

AK6 AK9

2

1

J5

0

H5

D7

D8

C8

W5

U1G

HDA_S

YNC/I2S0_SFRM LK/I2S0_SCLK

HDA_B

A_SDO/I2S0_TXD

HD

_S

DI0/I2S0_RXD

HDA

DI1/I2S1_RXD

HDA_S

T#/I2S1_SCLK

HDA_RS

GPP

_D23/I2S_MCLK

I2S1

_SFRM

_TXD

I2S1

_F1/I2S2_SFRM

GPP GPP

_F0/I2S2_SCLK

GP

_F2/I2S2_TXD

P

_F3/I2S2_RXD

GPP

_D19/DMIC_CLK0

GP

_D20/DMIC_DATA0

P

GPP

_D17/DMIC_CLK1

_D18/DMIC_DATA1

GPP

GP

_B14/SPKR

P

SKYL

AKE-U_BGA1356

D

IO

AU

SKYLAKE_

REV = 1

?

ULT

I

O/SDXC

SD

P

_G0/SD_CMD

GP

GPP

_G1/SD_DATA0

_G2/SD_DATA1

GPP GP

_G3/SD_DATA2

P

_G4/SD_DATA3

GPP

P

_G5/SD_CD#

GP

_G6/SD_CLK

GPP

P

_G7/SD_WP

GP

O

F 20

7

GP

_A17/SD_PWR_EN#/ISH_GP7

P

GPP

_A16/SD_1P8_SEL

SD

_RCOMP

GPP

?

_F23

AB1

AB13

AB12

W12

W1

W10

W8

W7

BA9

BB9

AB7

AF13

1

2

200_0201_1%

DTCT 65

C_

-S

-SC_

RC43

DTCT

RC3

TES

T PAD BOTTOM SIDE DO NOT MOVE AFTER FIX

SYNC54

HDA_

BCLK54

HDA_

SDO54

HDA_

SDIN054

-HDA

RST54

_

C

_

PRIORITY130

DDI DDI

PRIORITY230

_

PC

H

_SPKR59

@

EMC

CC5 for EMC request on 2016/3/17

Add

D

C

B

A

le

Tit

t

le

Tit

cu

rity Classification

Se

rity Classification

cu

Secu

rity Classification

Iss

ued Date

Iss

ued Date

Iss

HIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

T

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/2/

2016/

LC

Future Center Secret Data

LC

Future Center Secret Data

Deciphered Date

3

2/

3

Deciphered Date

2

2015/08/10

Ti

/16) : AUDIO/SDXC

CPU(7

CPU(

CPU(7

/16) : AUDIO/SDXC

7

Siz

Size

e

Siz

Do

c

ument Number Rev

c

Do

Cus

tom

Cu

s

tom

s

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

ues

day, December 20, 2016

T

ues

day, December 20, 2016

ues

1

9100

of

9100

of

B

A

0.3

0.

3

5

U1H

PC

IE0_RXN51

PCIE0_RXP51 PCIE0_TXN51 PCIE0_TXP51

D

USB3P3_RXN_SYS45

B3P3_RXP_SYS45

US

USB3P3_TXN_SYS45

USB3P3_TXP_SYS45

PCIE2_RXN50

PCIE2_RXP50

PCIE2_TXN50 PCIE2_TXP50

PCIE3_RXN46

PCIE3_RXP46

PCIE3_TXN46 PCIE3_TXP46

PC

IE1_RXN50

IE1_RXP50

PC

PCIE1_TXN50

IE1_TXP50

PC

PCIE4_L1_RXN43

PCIE4_L1_RXP43

PCIE4_L1_TXN43

PCIE4_L1_TXP43

PCIE4_L0_SATA1_RXN43 PCIE4_L0_SATA1_RXP43

PCIE4_L0_SATA1_TXN43

PCIE4_L0_SATA1_TXP43

C

-XDP_PRDY19

-X

DP_PREQ19

-TPM_IRQ69

PCIE10_L1_RXN50

IE10_L1_RXP50

PC

IE10_L1_TXN50

PC

IE10_L1_TXP50

PC

PCIE10_L0_SATA2_RXN50 PC

IE10_L0_SATA2_RXP50

PCIE10_L0_SATA2_TXN50 PC

IE10_L0_SATA2_TXP50

Card Reader

JUSB3 CONN J42

WLAN

LAN

WIGIG

HDD

VCC3_SUS

RC4

1 2

100_0201_1%

53 10K_0201_5% RC1

Optane

9

1

IE_RCOMPP

PC

2

PCIE_RCOMPN

-XDP_PRDY DP_PREQ

-X

-T

PM_IRQ

PCIE10_L1_RXN

PCIE10_L1_RXP

IE10_L1_TXN

PC

IE10_L1_TXP

PC

PCIE10_L0_SATA2_RXN

PC

IE10_L0_SATA2_RXP

PC

IE10_L0_SATA2_TXN

IE10_L0_SATA2_TXP

PC

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

3

G1

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

6

C1

PCIE2_TXP/USB3_6_TXP

H16

IE3_RXN

PC

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

IE4_RXN

PC

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

IE5_RXN

PC

E1

6

PCIE5_RXP

C19

PCIE5_TXN

D19

IE5_TXP

PC

8

G1

IE6_RXN

PC

F1

8

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

IE7_RXN/SATA0_RXN

PC

E20

PC

IE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

1

A2

PCIE7_TXP/SATA0_TXP

G21

IE8_RXN/SATA1A_RXN

PC

F21

PCIE8_RXP/SATA1A_RXP

D2

1

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

IE9_RXP

PC

3

B2

PCIE9_TXN

A23

PC

IE9_TXP

F25

IE10_RXN

PC

E2

5

PCIE10_RXP

D2

3

PCIE10_TXN

3

C2

PCIE10_TXP

F5

IE_RCOMPN

PC

E5

PC

IE_RCOMPP

6

D5

PR

OC_PRDY#

D61

PROC_PREQ#

1

BB1

P_A7/PIRQA#

GP

E28

PCIE11_RXN/SATA1B_RXN

E27

IE11_RXP/SATA1B_RXP

PC

D24

PC

IE11_TXN/SATA1B_TXN

C24

IE11_TXP/SATA1B_TXP

PC

E3

0

PCIE12_RXN/SATA2_RXN

0

F3

PCIE12_RXP/SATA2_RXP

A2

5

PC

IE12_TXN/SATA2_TXN

B25

PC

IE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1

4

?

SKYLAKE_ULT

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1

GP

8 OF 20

B3_2_RXN/SSIC_1_RXN

US

USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

US

B3_3_RXP/SSIC_2_RXP

B3_3_TXN/SSIC_2_TXN

US

USB3_3_TXP/SSIC_2_TXP

USB2_VBUSSENSE

P_E9/USB2_OC0#

GP

E10/USB2_OC1#

GPP_ GPP_E11/USB2_OC2#

GP

P_E12/USB2_OC3#

GPP_E4/DEVSLP0

GP

GPP_E6/DEVSLP2

P_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN

USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN

USB3_4_RXP

B3_4_TXN

US

USB3_4_TXP

USB2N_1

USB2P_1

US

B2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

B2N_5

US

USB2P_5

USB2N_6

USB2P_6

USB2N_7

B2P_7

US

USB2N_8

B2P_8

US

USB2N_9

US

B2P_9

USB2N_10

USB2P_10

US

B2_COMP

B2_ID

US

P_E5/DEVSLP1

?

H8

G8 C13

D13 J6

H6

B13 A13

J10

H10

B15

5

A1

E10

F10 C15 D1

5

AB9

AB10 AD

6

AD7 AH3

AJ3

AD9

10

AD

AJ1

AJ2

AF6

AF7

AH1 AH2

AF8 AF9

AG1 AG2

7

AH

AH8

AB6

AG3 AG4

US

A9

-U

C9

-USB_PORT1_OC1

D9

-USB_PORT2_OC2

B9 J1

J2

SAT

J3

H2 H3 G4

H1

US

BCOMP B2_ID

US

B2_VBUSSENSE

SB_PORT0_OC0

NFC_INT

A1_DEVSLP

TP3

@

1

Te

3

st_Point_12MIL

RC1 56 1K_0201_5%

2

USB3P0_RXN 44

US

B3P0_RXP 44

USB3P0_TXN 44 USB3P0_TXP 44

USB3P1_RXN 24

USB3P1_RXP 24

USB3P1_TXN 24

B3P1_TXP 24

US

USB3P3_RXN_DOCK 60

USB3P3_RXP_DOCK 60

USB3P3_TXN_DOCK 60

USB3P3_TXP_DOCK 60

BP0- 44

US

USBP0+ 44

USBP

1- 23

USBP1+ 23

US

BP2- 50

USBP2+ 50

USBP3-_DOCK 60

USBP3+_DOCK 60

USBP4- 65

BP4+ 65

US

BP3-_SYS 45

US USBP3+_SYS 45

BP6- 50

US US

BP6+ 50

USBP7- 38

USBP7+ 38

US

BP8- 65

USBP8+ 65 USBP9- 38

BP9+ 38

US

RC157 0_0201_5%

RC4 8 113_0201_1%

2

VCC3_SUS

2

1

-W

2

_0201_5%

10K

1

5

RC44

RC4

WAN_SATA_DTCT

PCIe Port Assignment

Media Carfd Controller

0

1

USB3.0 system port(3rd)

2

M.2 WLAN Slot Port 0(WLAN)

3

GbE PHY

4

PCIE SSD

6

Reserved M.2 WLAN Slot Port 1(WIGIG)

7 8

Optane

Reserved

1110Reserved

VCC3_SUS

2

_0201_5% 10K

1

7

35 10K_0201_5%

RC4

R2745 10K_0201_5%

RC1

NF

C_ON

2

-U

SB_PORT0_OC0 44 SB_PORT1_OC1 45

-U

NF

C_INT 65

C_ON 65

NF

SATA1_DEVSLP 43

SATA2_DEVSLP 50

-PE_DTCT 43

-WWAN_SATA_DTCT 50

Flex

I/O High Speed Signals Configuration Net Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16

0 1 2 3 4 5 6 7 8 9

ible I/O Configuration

USB3 1

2/SSIC1

USB3 USB3 3/SSIC2

USB3 4

USB3 5/PCIE 1 USB3 6/PCIE 2 PCIE 3 (WLAN)

PCIE 4 (GbE)

PCIE 5 (WIGIG)

PCIE 6

PCIE 7/SATA 0 PCIE 8/SATA 1A

PCIE 9 PCIE 9

PCIE 10

PCIE 11/SATA 1B PCIE 12/SATA 2

USB P

ort Assignment

USB 2.0 System Port (AOU) USB Type-C

M.2 WWAN Slot USB 2.0 System Port (Docking ) Smart Card Slot USB 2.0 System Port (3rd Port) NGFF WLAN Slot USB Camera Fingerprint Reader Touch Panel

1

USB3 1 US

B3 2 USB3 3 USB3P1 USB3 4

PCIE 1 PCIE 2 PCIE 3 PCIE 4 PCIE 5 PCIE 6

PCIE 7 (x2) GPIO STRAP

PCIE 10 PCIE 11

PCIE 12

USB3P

NA

USB3P3_DOCK

PCIE0

USB3P3_SYS

PCIE2 PCIE3

NA NA

PCIE4_L1

PCIE4_L0_SATA1

NA NA

IE10_L1

PC

PCIE10_L0_SATA2

0

D

C

1

B

USB 3.0 Port Assignment

0

USB 3.0 System Port (AOU)

NA

1 2

USB Type-C

3

USB 3.0 System Port Docking

4

CIE 1)

(P

5

USB 3.0 System Port (3rd Port)

A

5

SATA Port Assignment

0

(PCI

E 7)PCIE SSD

1A

SATA HDD

1B

Optane PCIE1

2

Optane PCIE2

4

curity Classification

Se

curity Classification

Security Classification

sued Date

Is

sued Date

Is

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

TH

IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

TH

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

016/2/3

2016/2/3

2

016/2/3

LC Future Center Secret Data

Future Center Secret Data

LC

LC Future Center Secret Data

ciphered Date

De

ciphered Date

De

2

2015/08/10

tle

Title

Ti

tle

PU(8/16) : PCIE/USB/SATA

010_C

010_CPU(8/16) : PCIE/USB/SATA

ze

Si

ze

Size

Do

cument Number Rev

Document Number Rev

Do

cument Number Rev

C

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

esday, December 20, 2016

Tu

esday, December 20, 2016

10

1

10

of

B

A

3

0.

3

0.

3

100

5

4

3

2

1

D

PLANAR

Kab

ylake

AKE_

ULT

SKYL

I

U1

-2

CSI

A36

CSI

2_DN0

B3

6

CSI

2_DP0

C38

CSI

2_DN1

D38

CSI

2_DP1

C36

I

2_DN2

CS

D36

I

2_DP2

CS

A3

8

CSI

2_DN3

B38

CSI

2_DP3

C31

CS

2_DN4

I

D31

CSI

2_DP4

C

C33

CSI

2_DN5

D33

2_DP5

CSI

1

A3

2_DN6

CSI

B3

1

CS

2_DP6

I

A33

CSI

2_DN7

3

B3

2_DP7

CSI

9

A2

2_DN8

CSI

B2

9

2_DP8

CSI

C28

2_DN9

CSI

D28

I

2_DP9

CS

A27

2_DN10

CSI

B27

CSI

2_DP10

C27

2_DN11

CSI

D27

CSI

2_DP11

SKYL

AKE-U_BGA1356

REV = 1

?

9

O

F 20

P

_D4/FLASHTRIG

GP

M

MC

E

GP

_F13/EMMC_DATA0

P

GP

P

_F14/EMMC_DATA1

GP

_F15/EMMC_DATA2

P

_F16/EMMC_DATA3

GP

GPP

_F17/EMMC_DATA4

P

_F18/EMMC_DATA5

GP

P

_F19/EMMC_DATA6

GP

_F20/EMMC_DATA7

P

GP

_F21/EMMC_RCLK

P

_F22/EMMC_CLK

GPP

P

_F12/EMMC_CMD

GP

EM

CSI

2_CLKN0

CSI

2_CLKP0 2_CLKN1

CSI

2_CLKP1

2_CLKN2

CSI

I

2_CLKP2

CS

CSI

2_CLKN3

CS

2_CLKP3

I

CS

I2_COMP

MC_RCOMP

?

C37 D37

C32 D32

C29

D29

B2

A26 E13

B7

AP2

AP1

AP3

AN3 AN

AN

AM4

AM1

AM2

AM3

AP4

AT1

SDV

FVT

SIT

-I

NT

SVT

RUDER_PCH

EL

LEV

6

@

1

KABYU@

1

@

2

0_0201_5%

2

0_0201_5%

2

0_0201_5%

2

0_0201_5%

RC5

PLAN

PL

1

2

PLAN

1

ARID1

RC52

ARID2

AN

RC53

ARID3

AN

RC54

ARID0

1

B

0

ID[3..0]

0000

0001

001

0

1

001

-INT

3

RC

3 RC52

5

NA

ASM ASM

SKYLA

KE

SIT

RUDER_PCH 13

PL

ID

ANAR

2

RC51

NA

NA NA

ASM ASM

PLANAR

ID[3..0]

1

101

10

RC54

D

C

B

A

t

le

Ti

le

t

Ti

le

Se

rity Classification

cu

rity Classification

Se

rity Classification

Secu

Iss

ued Date

Iss

ued Date

Iss

ued Date

THIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

HIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS

SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2/

3

2/

3

2/

Future Center Secret Data

LC

Future Center Secret Data

LC

Future Center Secret Data

LC

Deciphered Date

2

2015/08/10

t

CPU(

/16) : CSI-2/EMMC

9

/16) : CSI-2/EMMC

CPU(9

CPU(

/16) : CSI-2/EMMC

9

e

Siz

e

Size

Doc

ument Number Rev

Do

c

ument Number Rev

Do

ument Number Rev

c

Cus

tom

Cus

tom

Cu

s

tom

T

Tues

Date: Sheet

T

ues

day, December 20, 2016

ues

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

1

11 100

of

11 100

of

A

0.3

0.

3

5

4

3

2

1

D

VCC1R0_SUS

12

RC57

2.7K_0402_0.5%

?

SKYL

U1J

CIE0_CLK_100M51

-P PCIE0_CLK_100M51

-CLKREQ_PCIE051

-PCIE1_CLK_100M50

PC

IE1_CLK_100M50

-CLKREQ_PCIE150

-PCIE2_CLK_100M50 PCIE2_CLK_100M50

-CLKREQ_PCIE250

CIE3_CLK_100M46

C

-P PCIE3_CLK_100M46

-CLKREQ_PCIE346

-PCIE4_CLK_100M43 PCIE4_CLK_100M43

KREQ_PCIE443

-CL

CIE5_CLK_100M50

-P

PC

IE5_CLK_100M50

-CLKREQ_PCIE550

D42

CLKOUT_PCIE_N0

C42

LKOUT_PCIE_P0

C

AR

10

GP

P_B5/SRCCLKREQ0#

B4

2

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

LKOUT_PCIE_P2

C

AT8

GP

P_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

10

AT

P_B8/SRCCLKREQ3#

GP

0

B4

LKOUT_PCIE_N4

C

0

A4

CLKOUT_PCIE_P4

AU

8

GPP_B9/SRCCLKREQ4#

E4

0

C

LKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1

AKE_ULT

CLOCK SIGNALS

10 OF 20

C

LKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

X

TAL24_OUT

XCLK_BIASREF

RT RTCX2

SRTCRST#

RTCRST#

F43

E43

BA17

XT

AL24_IN

E37

XT

AL24_OUT

E35

XC

LK_BIASREF

E42

8

AM1

RTCX1

CX1

0

AM2

RTCX

2

AN18

AM16

?

SUSCLK_32K 50,61

2

1

-SRTCRST 20

-RT

CRST 17,20

5

RC5

1M_0201_5%

RC56

1

RC58

10M_0201_5%

2

0_0201_5%

2

1

Y1 24MHZ_10PF_8Y24000011

XTAL24_OUT_R

1

2

0

CC1

12P_0201_25V8-J

1

Change CC12, CC13 to 6.8pF

1

2

6.

8P_0201_25V8-C

2

CC1

2

Y2

32.768KHZ 9PF 20PPM 9H03280012

1

2

CC13

Change CC12, CC13 to 6.8pF

6.

8P_0201_25V8-C

GND1

2

3

GND2

4

CC1

12P_0201_25V8J

2

1

D

C

Y2 32.768KHZ

LCFC P/N

SJ100069400

0000IX00

SJ1

10000J900

SJ

KD

SEIKO

TXC

S

Intel ESR spec

50K ohm Max

ohm Max

50K

ohm Max

50K

Vendor

B

Vendor P/N

1TJF090DJ1A000B

X1A000141000200

3280012

9H

Vendor ESR spec

50K ohm Max

ohm Max

50K

ohm Max

50K

B

Y1 24MHZ

ndor P/N

Vendor

TXC

KDS

I

ntel ESR spec

ohm Max

50

ohm Max SJ10000P100

50

LCFC P/N

SJ

10000HH0J

Ve

8Y24000011

ZHAE24000BC0D

1Z

Vendor ESR spec

ohm Max

50 50 ohm Max

A

tle

Ti

Title

Ti

curity Classification

Se

Security Classification

Se

curity Classification

Issued Date

sued Date

Is

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/

2016/2/3

2016/

LC

Future Center Secret Data

LC Future Center Secret Data

2/3

Deciphered Date

2

2015/08/10

tle

CPU(

CPU(10/16) : CLOCK SIGNALS

10/16) : CLOCK SIGNALS

CPU(

10/16) : CLOCK SIGNALS

e

Siz

Size

Document Number Rev

cument Number Rev

Do

cument Number Rev

stom

Cu

Custom

stom

Cu

Date: Sheet

Date: Sheet of

T

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

uesday, December 20, 2016

12 100

1

12 100

of

A

3

0.

0.3

3

0.

1

D

C

VCC

OUT_

SG17FE_SON5

TC7

4

UC3

1

NC

2

A

IN_

3

GND

Y

1

RC65

BPWRG

VCC

6

RC6

RC67

RC68

1

3M

RC6

1

RC70

1

9

1K

_0201_5%

4.7K

2

_0201_5%

-PL

TP4

1Test_Point_40MIL

0_0201_5%

2

0_0201_5%

2

0_0201_5%

2

-IN

TRUDER_PCH11

TRST

U1

1

0

AN

GPP

B5

SYS_

AY17

RC20

RS

A6

8

PRO

B65

VCC

OK

B6

SYS_PWR

0

BA2

PCH

BB20

DS

AR1

3

GP

AP11

GP

BB1

5

WAKE#

15

AM

GPD2

AW1

7

GP

AT15

GP

SKYL

REV = 1

VCC

1R8_SUS

2

0

@

_0201_5% 10K

1

U_

PWRGD

CP

ST_PWRGD

VCC

@

SYS_PWR

H

_PWROK

PC

DSW

PWROK

U

SWARN

-S

SUSAC

K

5

VC

3M

C

D

UCORE

5

4

-XD

P_DBR17,19

MRST19,62

-RS

BPWRG54,

_PWRGD79

MP

W

RG62,72

-PC

IE_WAKE50,71

A

NWAKE46

-L

LA

N

PHYPC46

1

CC15 100P

RC5

9

1

RC60

_0201_25V

2

33_0201_5%

2

33_0201_5%

8J

62,65,70,72

CP

TRST_NEAR51,70

-PL

TRST_FAR43,46,50,61,69,71

-PL

1

CC14

_0201_25V

8J

100P

C

2

3

POWER MANAGEMENT

SYSTEM

SKYL

7

RC1

1

K

_B13/PLTRST#

R

ESET#

RST#

M

CPWRGD

ST_PWRGD

OK

_PWROK

W

_PWROK

P

_A13/SUSWARN#/SUSPWRDNACK _A15/SUSACK#

P

/LAN_WAKE#

D1

1/LANPHYPC /RSVD

D7

AKE-U_BGA1356

AKE_

SPVR3

0

?

ULT

10100_4P

2

0_0201_5%

2

CV

CC

RT

AT1

/SLP_S3# /SLP_S4#

0/SLP_S5# SLP_

SUS#

SLP_

/SLP_A#

/PWRBTN#

/BATLOW#

RUDER#

LAN#

1

AP15

6

BA1

AY1

6

15

AN

AW15

BB17

6

AN1

5

BA1

AY15

1

3

AU

1

AP16

-IN

TRUDER

0

AM1 AM

1

?

RC71

@

_0201_25V7K

1000P

2

1

0_0201_5%

GP

_B12/SLP_S0#

P

GPD4 GP

D5

GP

D1

/SLP_WLAN#

GPD9

GPD6

GPD3

D1

/ACPRESENT

GP

GPD0

P

_A11/PME#

GP

INT

GP

_B11/EXT_PWR_GATE#

P

_B2/VRALERT#

F 20

11 O

GPP

3

2

S1

4

1

RC62 1M_0201_5%

1 2

2

7 CC1

1

O

DI

VCC

3M

2

RC6

4

_0201_5%

10K

@

1

DC1

2

1

PMEG4002EL SOD882, A.1

H_SLP_S0 17,94

-PC

C

H_SLP_S3 17,62,71,72

-P

H_SLP_S4 17,62,71,85

C

-PC

H_SLP_S5 17,71

H_SLP_SUS 62

-PC

H_SLP_LAN 63

-PC

H_SLP_WLAN 62

-PC H_SLP_M 17,71

-PC

-P

RSW_EC 62

W

AC_

PRESENT 62

-B

TLOW 63

A

T_PWR_GATE 16

X

-E

-I

TRUDER_EC 63

N

3_SUS

B

CP

UCORE

_ON71,79

A

5

VCC

2

RC72

10K_0201_5%

1

D

QC2

2

G

K

3541G1ET2L 1N VMT3

LS

S

3

4

VC

1R0_SUS

C

2

3

RC7

10K

_0201_5%

1

VC

ST_PWRGD

C

1

D

QC3

2

G

K

3541G1ET2L 1N VMT3

LS

S

3

Ti

le

t

Tit

le

t

le

urity Classification

Sec

c

urity Classification

Se

c

urity Classification

Is

ued Date

s

ued Date

Iss

Is

ued Date

s

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

I

TH

S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CO NTAINS CONFIDENTIAL

I

TH

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

016/2/3

2016/2/3

016/2/3

2

LC

Future Center Secret Data

LC

Future Center Secret Data

De

hered Date

cip

hered Date

Decip

hered Date

2

2015/08/10

Ti

U(1

1/16) : SYSTEM PM

CP

1/16) : SYSTEM PM

U(1

1/16) : SYSTEM PM

CP

e

Siz

e

z

Si

z

e

Si

Do

ument Number Rev

c

ument Number Rev

Doc

ument Number Rev

c

Do

C

Tu

Date: Sheet

!"#$%&'(%)*+,-

!"#$%&'(%)*+,-!"#$%&'(%)*+,-

sday, December 20, 2016

e

sday, December 20, 2016

e

sday, December 20, 2016

1

13

of

13 100

13

of

B

A

3

0.

0.3

3

0.

100

5

4

3

2

1

D

1

2

VCCSTG_CPU

VCCST

56_0201_5%

@

6

1 2

RC7

2

100_0201_1%

7

1

RC7

RC161 100_0201_1%

C_SENSE 79

VC

VSS_

SENSE 79

-SVID_ALERT 79

SVID_CLK 79

SVID_DATA 79

VCCSTG

CCPUCORE

VC

2

9 CC7

CC78

1

1U_0201_6.3V6

C

2

CC81

CC80

1

1U_0201_6.3V6

2

3 CC8

CC82

1

1U_0201_6.3V6

4 CC8

2

5 CC8

1

1U_0201_6.3V6

TP

TP20Test_Point_40MIL

TP

TP TP

37Test_Point_40MIL @

22Test_Point_40MIL

18Test_Point_40MIL @ 19Test_Point_40MIL

VCCCPUCORE

?

SKYL

A30

EOPIO_AG62

AKE_ULT

CPU POWER 1 OF 4

12 OF 20

VCC_G32

VCC_G33

VCC_G35

VCC_G37

VCC_G38

VCC_G40 VCC_G42

VC

C_J30

VCC_J33

VCC_J37

C_J40

VC

VCC_K33

VCC_K35 VCC_K37

VC

C_K38 C_K40

VC

VCC_K42 VCC_K43

VC

C_SENSE

VSS_

SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33

G35 G3

G3

G4

G42

J30

J33

J37

J4

K33

K35 K37

K3 K4

K42 K43

E32

E33

B63

A6 D64

G2

?

U1L

A30

VCC_

4

A3

VCC_A34

A39

C_A39

VC

A44

VC

C_A44

AK33

VCC_AK33

AK3

5

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

33

AL

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VC

C_AM32

AM3

3

VC

C_AM33

AM35

VC

C_AM35

AM37

C_AM37

VC

8

AM3

VCC_AM38

0

G3

CC_G30

V

K32

VCCG0

AK3

2

VCCG1

2

AB6

AC63

AE6 AE6

A

AL

AJ

2

P6

2

V6

H63

G61

3 2

G62

63

62

VCCOPC_AB62

V VCCOPC_V62

VCC_OPC_1P8_H63 V

VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO_AE62

VCC

VCCEOPIO_SENSE

VSSEOPIO_SENSE

CCOPC_P62

CC_OPC_1P8_G61

SKYLAKE-U_BGA1356

1

TP23Test_Point_40MIL

@

1

@

21Test_Point_40MIL

@

1

@

1

@

7

8

0

8 0

3

0

VC

C_SENSE

VSS_

SENSE

VID_ALERT_R

-S

SVID

_CLK

SVID_DATA

VCCCPUCORE

VCCSTG_CPU

RC79

2

1

220_0201_5%

1

RC7

4

VCCCPUCORE

1

2

1

2

100_0201_1% 5 RC7

RC82 100_0201_1%