Lenovo THINKPAD YOGA 900-13ISK Schematic

5

Yog

4

3

a4 SKL-U CS SIT2 Schematic Block Diagram

2

1

D D

EDP

SPI

USB2.0

I2C

USB2.0

C

I2

SML

LCD

SPI

BIOS

ERA

CAM

TO

UCHPANEL

DC-IN CONNECTOR

TO

UCH PAD

ink

NFC

PAGE 24

PAGE 9

PAGE 24

PAGE 24

PAGE 30

PAGE 26

PAGE 33

Right IO Bo

LPDDR3

NGFF SSD

WiFi/BT

ard

PAGE 17-19

PAGE 21

PAGE 20

USB3.0 Port

HP/MIC COMBO JACK

C C

ft IO Board

Le

USB3.1 Port

Typc-C Port TPS65982

PS8740

CARD READER OZ620

LPDDR3 Channel A&B
1600

SATA/PCIE

PCIE

C298

AL

MHz

for WiFi & USB2.0 for BT

USB3.0 & USB2.0

I2S/mHDA

USB3.0 & USB2.0

USB3.0 & USB2.0 & DDI

x1

PCIE

SKL-U

PAGE 2--15

MCP

3V/5V

PAGE 29

1.00V

PAGE 29

0.

6V/1.2V

PAGE 29

5V

1.

PAGE 29

SWITCH POW

PAGE 31

WALKPORT

PAGE 29

CPU_CORE
GTX_CORE

PAGE 32

ER

CHARGER

G-SENSOR I2C

2nd

B B

Sen

sor Board

E-Compass

GYRO

PAGE 23

I2C

I2C

EC

PAGE 22

LPC

BUSI2C

SMBUS

80 Port

Battery

PAGE 33

PAGE 33

PAGE 30

G-SENSOR

ALS I2C

A A

5

C

I2

4

KB

PAGE 33

3

WIN

8 BTN

PAGE 24

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

1 37Monday,

1 37Monday,

1 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

le

Title

Title

Tit

ADWELL Block Diagram

ADWELL Block Diagram

ADWELL Block Diagram

BRO

BRO

BRO

Size Document Number

Size Document Number

Size Document Number

C

C

C

A4

A4

A4

YOG

YOG

YOG

Date: Sheet of

Date: Sheet of

Date: Sheet of
"PROPERTY NOTE: this document cont ains information confidential and

"PROPERTY NOTE: this document cont ains information confidential and

"PROPERTY NOTE: this document cont ains information confidential and
property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

2

July 27, 2015

July 27, 2015

July 27, 2015

5

DD

I1_DN033
I1_DP033

DD
DDI1_DN133
DD

I1_DP133
I1_DN233

D D

C C

DD
DDI1_DP233
DD

I1_DN333
I1_DP333

DD

DD

PB_CLK
PB_DATA

DD

EC_IRQ33

COD

TOUCH_RST_N24

EDP_COM

E55
F55
E58
F58
F53
G53
F56
G56

C50
D50
C52
D52
A50
B50
D51
C51

L13
L12

N7
N8

N11
N12

P

E52

4

U95A

DDI1_TXN[0]
DD

I1_TXP[0]
I1_TXN[1]

DD
DDI1_TXP[1]
DD

I1_TXN[2]
I1_TXP[2]

DD
DDI1_TXN[3]
DD

I1_TXP[3]

DDI2_TXN[0]
DD

I2_TXP[0]
I2_TXN[1]

DD
DD

I2_TXP[1]
I2_TXN[2]

DD

I2_TXP[2]

DD
DD

I2_TXN[3]
I2_TXP[3]

DD

GPP_E18/DDPB_CTRLCLK
GP

P_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK
GP

P_E21/DDPC_CTRLDATA

GPP_E22/DDPD_CTRLCLK
GP

P_E23/DDPD_CTRLDATA

E

DP_RCOMP

SKL_ULT

REV = 1

SKL_

ULT

DDI

DISPLAY SIDEBANDS

3

?

1 OF

EDP

20

EDP_TXN[0]
E

DP_TXP[0]
DP_TXN[1]

E
EDP_TXP[1]
E

DP_TXN[2]
DP_TXP[2]

E
EDP_TXN[3]
E

DP_TXP[3]

EDP_AUXN
E

DP_AUXP

E

DP_DISP_UTIL

I1_AUXN

DD
DD

I1_AUXP
I2_AUXN

DD

I2_AUXP

DD
DD

I3_AUXN
I3_AUXP

DD

GP

P_E13/DDPB_HPD0
P_E14/DDPC_HPD1

GP
GPP_E15/DDPD_HPD2
GP

P_E16/DDPE_HPD3

P_E17/EDP_HPD

GP

E

DP_BKLTEN

DP_BKLTCTL

E

E

DP_VDDEN

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

DP_UT

IL

DDPB_HPD 33

KBSMI_N 22

SCI_N 22

EDP_HPD 24

LCD_BL_PWM_PCH 22

LCD

EDP_VDD

?

TP4TEST

PAD

_BL_EN 24

_EN 22,24

EDP_TX0_DN 24
EDP_TX0_DP 24
EDP_TX1_DN 24
EDP_TX1_DP 24
EDP_TX2_DN 24
EDP_TX2_DP 24
EDP_TX3_DN 24
EDP_TX3_DP 24

EDP_AUX_DN 24
EDP_AUX_DP 24

1

I1_AUX_DN 33

DD

I1_AUX_DP 33

DD

2

EDP_COM

P

1 2

R1 24.9_0402_1%

COM

PENSATION PU FOR DP

+VCC

1

IO

+3V

_N

SCI

KBSMI_N

PB_HPD

DD

402_5%

402_5%

12

R12610K_0

12

R9510K_0

1 2

R157 100K_

0402_5%

+3V

DD
DD

PB_CLK
PB_DATA

2 3
1 4

2.2K_0404_

RP30

4P2R_5%

B B

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

2 37Monday,

2 37Monday,

2 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP (DDI,EDP)

BROADWELL MCP (DDI,EDP)

BROADWELL MCP (DDI,EDP)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

15:0]17

M_B_DQ[

M_B_DQ[

47:32]18

M_A_DQ[

15:0]18

M_A_DQ[

47:32]17

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47

D D

C C

U95B

AL71

DDR0_DQ[0]

AL68

DD

R0_DQ[1]

AN68

R0_DQ[2]

DD

AN69

DDR0_DQ[3]

AL70

DD

R0_DQ[4]

AL69

R0_DQ[5]

DD

AN70

DD

R0_DQ[6]

AN71

R0_DQ[7]

DD

AR70

R0_DQ[8]

DD

AR68

DD

R0_DQ[9]

AU71

R0_DQ[10]

DD

AU68

R0_DQ[11]

DD

AR71

DD

R0_DQ[12]

AR69

R0_DQ[13]

DD

AU70

DDR0_DQ[14]

AU69

DD

R0_DQ[15]

BB65

R0_DQ[16]/DDR0_DQ[32]

DD

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DD

R0_DQ[18]/DDR0_DQ[34]

AY63

R0_DQ[19]/DDR0_DQ[35]

DD

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DD

R0_DQ[21]/DDR0_DQ[37]

BA63

R0_DQ[22]/DDR0_DQ[38]

DD

BB63

DD

R0_DQ[23]/DDR0_DQ[39]

BA61

R0_DQ[24]/DDR0_DQ[40]

DD

AW61

R0_DQ[25]/DDR0_DQ[41]

DD

BB59

DD

R0_DQ[26]/DDR0_DQ[42]

AW59

R0_DQ[27]/DDR0_DQ[43]

DD

BB61

R0_DQ[28]/DDR0_DQ[44]

DD

AY61

DD

R0_DQ[29]/DDR0_DQ[45]

BA59

R0_DQ[30]/DDR0_DQ[46]

DD

AY59

R0_DQ[31]/DDR0_DQ[47]

DD

AY39

DD

R0_DQ[32]/DDR1_DQ[0]

AW39

R0_DQ[33]/DDR1_DQ[1]

DD

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DD

R0_DQ[35]/DDR1_DQ[3]

BB39

R0_DQ[36]/DDR1_DQ[4]

DD

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DD

R0_DQ[38]/DDR1_DQ[6]

BB37

R0_DQ[39]/DDR1_DQ[7]

DD

AY35

DD

R0_DQ[40]/DDR1_DQ[8]

AW35

DD

R0_DQ[41]/DDR1_DQ[9]

AY33

R0_DQ[42]/DDR1_DQ[10]

DD

AW33

DD

R0_DQ[43]/DDR1_DQ[11]

BB35

R0_DQ[44]/DDR1_DQ[12]

DD

BA35

R0_DQ[45]/DDR1_DQ[13]

DD

BA33

DD

R0_DQ[46]/DDR1_DQ[14]

BB33

R0_DQ[47]/DDR1_DQ[15]

DD

AY31

R0_DQ[48]/DDR1_DQ[32]

DD

AW31

DD

R0_DQ[49]/DDR1_DQ[33]

AY29

R0_DQ[50]/DDR1_DQ[34]

DD

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DD

R0_DQ[52]/DDR1_DQ[36]

BA31

R0_DQ[53]/DDR1_DQ[37]

DD

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DD

R0_DQ[55]/DDR1_DQ[39]

AY27

R0_DQ[56]/DDR1_DQ[40]

DD

AW27

DD

R0_DQ[57]/DDR1_DQ[41]

AY25

DD

R0_DQ[58]/DDR1_DQ[42]

AW25

R0_DQ[59]/DDR1_DQ[43]

DD

BB27

DD

R0_DQ[60]/DDR1_DQ[44]

BA27

DD

R0_DQ[61]/DDR1_DQ[45]

BA25

R0_DQ[62]/DDR1_DQ[46]

DD

BB25

DD

R0_DQ[63]/DDR1_DQ[47]

SKL_ULT

REV = 1

SKL_

4

?

ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DD

R0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
R0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

DD
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DD

R0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

R0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DD
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DD

R0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

R0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DD
DD

R0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

R0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DD

DD

R0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

R0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DD

R0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DD

DD

R0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

R0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DD

R0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DD

DD

R0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

R0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DD

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

R0_DQSN[2]/DDR0_DQSN[4]

DD
DD

R0_DQSP[2]/DDR0_DQSP[4]
R0_DQSN[3]/DDR0_DQSN[5]

DD

R0_DQSP[3]/DDR0_DQSP[5]

DD
DD

R0_DQSN[4]/DDR1_DQSN[0]
R0_DQSP[4]/DDR1_DQSP[0]

DD

R0_DQSN[5]/DDR1_DQSN[1]

DD
DD

R0_DQSP[5]/DDR1_DQSP[1]
R0_DQSN[6]/DDR1_DQSN[4]

DD
DDR0_DQSP[6]/DDR1_DQSP[4]
DD

R0_DQSN[7]/DDR1_DQSN[5]
R0_DQSP[7]/DDR1_DQSP[5]

DD

DDR CH - A

20

2 OF

DD
DDR0_CKP[0]
DD
DD

DD
DD
DD
DD

DD

DD
DD
DD

DD
DD

DD

R0_DQSN[0]
R0_DQSP[0]

DD
DD

R0_DQSN[1]

DD

R0_DQSP[1]

DD

R0_ALERT#

DD

DD

R_VREF_CA

R0_VREF_DQ

DD
DD

R1_VREF_DQ

R_VTT_CNTL

DD

R0_CKN[0]

R0_CKN[1]
R0_CKP[1]

R0_CKE[0]
R0_CKE[1]
R0_CKE[2]
R0_CKE[3]

R0_CS#[0]
R0_CS#[1]
R0_ODT[0]
R0_ODT[1]

R0_MA[3]
R0_MA[4]

R0_PAR

3

M_A_DQ[31:16]17

M_A_DQ16

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

DD

R_PG_CTRL_R

+V_DD
+V_DD
+V_DD

M_A_CLK_DD

R0_DN 17,19
R0_DP 17,19

M_A_CLK_DD
M_A_CLK_DDR1_DN 17,19
M_A_CLK_DD

R1_DP 17,19

M_A_CKE0 17,19
M_A_CKE1 17,19
M_A_CKE2 17,19
M_A_CKE3 17,19

M_A_CS0_N 17,19
M_A_CS1_N 17,19

0 17,19

M_A_ODT

1

1
1

1
1

TP68 TEST

M_A_CAA0 17,19
M_A_CAA1 17,19
M_A_CAA2 17,19
M_A_CAA3 17,19
M_A_CAA4 17,19
M_A_CAA5 17,19
M_A_CAA6 17,19
M_A_CAA7 17,19
M_A_CAA8 17,19
M_A_CAA9 17,19

M_A_CAB0 17,19
M_A_CAB1 17,19
M_A_CAB2 17,19
M_A_CAB3 17,19
M_A_CAB4 17,19
M_A_CAB5 17,19
M_A_CAB6 17,19
M_A_CAB7 17,19
M_A_CAB8 17,19
M_A_CAB9 17,19

TP61 TEST
TP62 TESTPAD

M_A_DQS_DN0 17
M_A_DQS_DP0 17
M_A_DQS_DN
M_A_DQS_DP1 17
M_A_DQS_DN
M_A_DQS_DP4 17
M_A_DQS_DN
M_A_DQS_DP5 17
M_B_DQS_DN
M_B_DQS_DP0 18
M_B_DQS_DN
M_B_DQS_DP1 18
M_B_DQS_DN
M_B_DQS_DP4 18
M_B_DQS_DN5 18
M_B_DQS_DP5 18

TP10 TEST
TP53 TESTPAD

R_CA_VREF 19
R_VREFDQ0 19
R_VREFDQ1 19

PAD

PAD

PAD

1 17

4 17

5 17

0 18

1 18

4 18

M_B_DQ[

M_B_DQ[

M_A_DQ[

31:16]18

63:48]18

63:48]17

M_A_DQ17

M_A_DQ18

M_A_DQ19

M_A_DQ20

M_A_DQ21

M_A_DQ22

M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ31

M_A_DQ48

M_A_DQ49

M_A_DQ50

M_A_DQ51

M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60

M_A_DQ61

M_A_DQ62

M_A_DQ63

M_B_DQ16

M_B_DQ17

M_B_DQ18

M_B_DQ19

M_B_DQ20

M_B_DQ21

M_B_DQ22

M_B_DQ23

M_B_DQ24

M_B_DQ25

M_B_DQ26

M_B_DQ27

M_B_DQ28

M_B_DQ29

M_B_DQ30

M_B_DQ31

M_B_DQ48

M_B_DQ49

M_B_DQ50

M_B_DQ51

M_B_DQ52

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ56

M_B_DQ57

M_B_DQ58

M_B_DQ59

M_B_DQ60

M_B_DQ61

M_B_DQ62

M_B_DQ63

?

2

U95C

AF65

DD

R1_DQ[0]/DDR0_DQ[16]

AF64

R1_DQ[1]/DDR0_DQ[17]

DD

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DD

R1_DQ[3]/DDR0_DQ[19]

AF66

R1_DQ[4]/DDR0_DQ[20]

DD

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DD

R1_DQ[6]/DDR0_DQ[22]

AK66

R1_DQ[7]/DDR0_DQ[23]

DD

AF70

DD

R1_DQ[8]/DDR0_DQ[24]

AF68

R1_DQ[9]/DDR0_DQ[25]

DD

AH71

R1_DQ[10]/DDR0_DQ[26]

DD

AH68

DD

R1_DQ[11]/DDR0_DQ[27]

AF71

R1_DQ[12]/DDR0_DQ[28]

DD

AF69

R1_DQ[13]/DDR0_DQ[29]

DD

AH70

DD

R1_DQ[14]/DDR0_DQ[30]

AH69

R1_DQ[15]/DDR0_DQ[31]

DD

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DD

R1_DQ[17]/DDR0_DQ[49]

AP65

R1_DQ[18]/DDR0_DQ[50]

DD

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DD

R1_DQ[20]/DDR0_DQ[52]

AP66

R1_DQ[21]/DDR0_DQ[53]

DD

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DD

R1_DQ[23]/DDR0_DQ[55]

AT61

R1_DQ[24]/DDR0_DQ[56]

DD

AU61

DD

R1_DQ[25]/DDR0_DQ[57]

AP60

R1_DQ[26]/DDR0_DQ[58]

DD

AN60

R1_DQ[27]/DDR0_DQ[59]

DD

AN61

DD

R1_DQ[28]/DDR0_DQ[60]

AP61

R1_DQ[29]/DDR0_DQ[61]

DD

AT60

R1_DQ[30]/DDR0_DQ[62]

DD

AU60

DD

R1_DQ[31]/DDR0_DQ[63]

AU40

R1_DQ[32]/DDR1_DQ[16]

DD

AT40

R1_DQ[33]/DDR1_DQ[17]

DD

AT37

DD

R1_DQ[34]/DDR1_DQ[18]

AU37

R1_DQ[35]/DDR1_DQ[19]

DD

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DD

R1_DQ[37]/DDR1_DQ[21]

AP37

R1_DQ[38]/DDR1_DQ[22]

DD

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DD

R1_DQ[40]/DDR1_DQ[24]

AU33

R1_DQ[41]/DDR1_DQ[25]

DD

AU30

DD

R1_DQ[42]/DDR1_DQ[26]

AT30

DD

R1_DQ[43]/DDR1_DQ[27]

AR33

R1_DQ[44]/DDR1_DQ[28]

DD

AP33

DD

R1_DQ[45]/DDR1_DQ[29]

AR30

R1_DQ[46]/DDR1_DQ[30]

DD

AP30

R1_DQ[47]/DDR1_DQ[31]

DD

AU27

DD

R1_DQ[48]

AT27

R1_DQ[49]

DD

AT25

R1_DQ[50]

DD

AU25

DD

R1_DQ[51]

AP27

R1_DQ[52]

DD

AN27

DDR1_DQ[53]

AN25

DD

R1_DQ[54]

AP25

R1_DQ[55]

DD

AT22

DDR1_DQ[56]

AU22

DD

R1_DQ[57]

AU21

R1_DQ[58]

DD

AT21

DD

R1_DQ[59]

AN22

DD

R1_DQ[60]

AP22

R1_DQ[61]

DD

AP21

DD

R1_DQ[62]

AN21

DD

R1_DQ[63]

SKL_ULT

REV = 1

?

ULT

SKL_

R1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DD
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DD

R1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
R1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DD
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DD

R1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

R1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DD
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DD

R1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
R1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DD

R1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DD

R1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DD

DD

R1_WE#/DDR1_CAB[2]/DDR1_MA[14]

R1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DD

R1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DD

DD

R1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

R1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DD
R1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DD

DD

R1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
R1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DD

DDR1_DQSN[0]/DDR0_DQSN[2]
DD

R1_DQSP[0]/DDR0_DQSP[2]
R1_DQSN[1]/DDR0_DQSN[3]

DD
DD

R1_DQSP[1]/DDR0_DQSP[3]

DD

R1_DQSN[2]/DDR0_DQSN[6]
R1_DQSP[2]/DDR0_DQSP[6]

DD
DD

R1_DQSN[3]/DDR0_DQSN[7]
R1_DQSP[3]/DDR0_DQSP[7]

DD

R1_DQSN[4]/DDR1_DQSN[2]

DD
DD

R1_DQSP[4]/DDR1_DQSP[2]
R1_DQSN[5]/DDR1_DQSN[3]

DD

R1_DQSP[5]/DDR1_DQSP[3]

DD

DD
DD
DDR1_DQSN[7]
DD

DDR1_ALERT#

DR
DD
DD

DDR CH - B

3 OF

20

DD

DD

R1_CKN[0]
R1_CKN[1]

DD
DDR1_CKP[0]
DD

R1_CKP[1]

DDR1_CKE[0]
DD

R1_CKE[1]
R1_CKE[2]

DD
DD

R1_CKE[3]

R1_CS#[0]

DD
DD

R1_CS#[1]

R1_ODT[0]

DD

R1_ODT[1]

DD

DDR1_MA[3]
DD

R1_MA[4]

R1_DQSN[6]
R1_DQSP[6]

R1_DQSP[7]

DD

R1_PAR
AM_RESET#
R_RCOMP[0]
R_RCOMP[1]
R_RCOMP[2]

1

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

SM_RC
SM_RC
SM_RC

OMP_0
OMP_1
OMP_2

M_B_CLK_DDR0_DN 18,19
M_B_CLK_DD

R1_DN 18,19
R0_DP 18,19

M_B_CLK_DD
M_B_CLK_DDR1_DP 18,19

M_B_CKE0 18,19
M_B_CKE1 18,19
M_B_CKE2 18,19
M_B_CKE3 18,19

M_B_CS0_N 18,19
M_B_CS1_N 18,19
M_B_ODT

0 18,19

1

TP70 TEST

M_B_CAA0 18,19
M_B_CAA1 18,19
M_B_CAA2 18,19
M_B_CAA3 18,19
M_B_CAA4 18,19
M_B_CAA5 18,19
M_B_CAA6 18,19
M_B_CAA7 18,19
M_B_CAA8 18,19
M_B_CAA9 18,19

M_B_CAB0 18,19
M_B_CAB1 18,19
M_B_CAB2 18,19
M_B_CAB3 18,19
M_B_CAB4 18,19
M_B_CAB5 18,19
M_B_CAB6 18,19
M_B_CAB7 18,19
M_B_CAB8 18,19
M_B_CAB9 18,19

1

TP63 TEST

1

1
1
1

PAD
PAD

TP64 TEST

M_A_DQS_DN
M_A_DQS_DP2 17
M_A_DQS_DN
M_A_DQS_DP3 17
M_A_DQS_DN
M_A_DQS_DP6 17
M_A_DQS_DN
M_A_DQS_DP7 17
M_B_DQS_DN
M_B_DQS_DP2 18
M_B_DQS_DN
M_B_DQS_DP3 18
M_B_DQS_DN
M_B_DQS_DP6 18
M_B_DQS_DN
M_B_DQS_DP7 18

TP66 TEST

PAD
PAD

TP65 TEST
TP67 TESTPAD

PAD

2 17

3 17

6 17

7 17

2 18

3 18

6 18

7 18

?

B B

10V6K

4

+3V

1 2

R192
100K_0402_5%

DD

R_VTT_PG_CTRL 29

SM_RC

12

R183 200_0

1 2

R291 80.6_0402_

R186 162_0

3

2

402_1%

12

402_1%

OMP_0

OMP_1

SM_RC

1%

OMP_2

SM_RC

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

3 37Monday,

3 37Monday,

3 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Tit

le

Title

Title

BROADWELL MCP ( PROCESSOR LPDDR3)

BROADWELL MCP ( PROCESSOR LPDDR3)

BROADWELL MCP ( PROCESSOR LPDDR3)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

July 27, 2015

July 27, 2015

July 27, 2015

+1.2VSUS

2

U17

1

R_PG_CTRL_R

DD

A A

5

2

3

NC

A

GND

74AUP1G0

V

1

NC

7FW4-7_DFN1010-6_1X1

6

cc

5

2

4

Y

1

C28

0.1u_0201_

5

2_WLAN_WAKE_CTRL_N20

M.

M.

2_WLAN_WIFI_WAKE_R_N20

_KILL_N_WIFI_NGFF20

RF

M.2_WIFI_RST_N20

D D

PAD
PAD
PAD
PAD

C C

+3V

12

R68

0402_5%

B B

100K_

12

@

R75
100K_0402_5%

BOARD_I
BOARD_I
BOARD_I
BOARD_I

TP58TEST
TP79TEST
TP80TEST
TP81TEST

I2C0_SDA
I2C

0_SCL

I2C1_SDA
I2C

1_SCL

I2C2_SDA
I2C

2_SCL

I2C

3_SDA_R

I2C

3_SCL_R

12

R69
100K_

12

@

R76
100K_0402_5%

D0
D1
D2
D3

0402_5%

TP40
TP41
TP39
TP25

UAR
UAR
UAR
UART2_CTS_N

12

R70
100K_

@

12

R77
100K_0402_5%

1
1
1
1

T2_RXD
T2_TXD
T2_RTS_N

0402_5%

4

12

12

U95F

AN8

GP

AP7

GP

AP8

GP

AR7

GP

AM5

GPP_B19/GSPI1_CS#

AN7

GP

AP5

GP

AN5

GPP_B22/GSPI1_MOSI

AB1

GP

AB2

GPP_C9/UART0_TXD

W4

GP

AB3

GP

AD1

GP

AD2

GP

AD3

GP

AD4

GP

U7

GP

U6

GP

U8

GP

U9

GPP_C19/I2C1_SCL

AH9

GP

AH10

GPP_F5/I2C2_SCL

AH11

GP

AH12

GPP_F7/I2C3_SCL

AF11

GP

AF12

GP

SKL_ULT

REV = 1

0.1u_0201_

3_SCL_R

I2C

3_SDA_R

I2C

I2C

1_SDA

1_SCL

I2C

R71

0402_5%

100K_

@

R78
100K_

0402_5%

?

ULT

LPSS ISH

P_B15/GSPI0_CS#
P_B16/GSPI0_CLK
P_B17/GSPI0_MISO
P_B18/GSPI0_MOSI

P_B20/GSPI1_CLK
P_B21/GSPI1_MISO

P_C8/UART0_RXD

P_C10/UART0_RTS#
P_C11/UART0_CTS#

P_C20/UART2_RXD
P_C21/UART2_TXD
P_C22/UART2_RTS#
P_C23/UART2_CTS#

P_C16/I2C0_SDA
P_C17/I2C0_SCL

P_C18/I2C1_SDA

P_F4/I2C2_SDA

P_F6/I2C3_SDA

P_F8/I2C4_SDA
P_F9/I2C4_SCL

+1.8V

1

C629

10V6K

2

+3V

12

R73

0402_5%

100K_

@

SKL_

U8

1

CCA

V

2

S

CLA

3

S

DAA

GND4OE

TCA9517DGKR_3X3

U16

1

VCCA

2

1

A

3

A

2

GND4OE

TXS0102DQER_1P4X1

D0

BOARD_I

D1

BOARD_I

BOARD_I

D2

BOARD_ID3

D4

BOARD_I

GP

GP

6 OF 20

8

CCB

V

7

S

CLB

6

S

DAB

5

8

VCCB

7

1

B

6

B

2

5

12

R79
100K_

0402_5%

3

P_D9

GP

GP

P_D10
P_D11

GP

P_D12

GP

P_D5/ISH_I2C0_SDA

GP
GPP_D6/ISH_I2C0_SCL

P_D7/ISH_I2C1_SDA

GP
GPP_D8/ISH_I2C1_SCL

P_F10/I2C5_SDA/ISH_I2C2_SDA

GP

GP

P_F11/I2C5_SCL/ISH_I2C2_SCL

P_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

P_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

+3VDX_TOU

+3VDX_TCH_PAD

P_D15/ISH_UART0_RTS#

GP

GP

P_D16/ISH_UART0_CTS#/SML0BALERT#

P_C12/UART1_RXD/ISH_UART1_RXD

GP
GP

P_C13/UART1_TXD/ISH_UART1_TXD

P_C14/UART1_RTS#/ISH_UART1_RTS#

GP
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

CHPANEL

TOU

CHPANEL_PWR_EN

CHPAD_PWR_EN

TOU

SIV

P_A18/ISH_GP0

GP
GPP_A19/ISH_GP1
GP

P_A20/ISH_GP2
P_A21/ISH_GP3

GP
GPP_A22/ISH_GP4
GP

P_A23/ISH_GP5

P_A12/BM_BUSY#/ISH_GP6

GP

1

C628

0.1u_0201_10V6K

2

SDV

BOARD_ID4

0

0

0

0

0

0

BOARD_ID4

I2C3_SCL 24

I2C

I2C

I2C

0 1

0 1

P2

R545 0_040

P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

?

3_SDA 24

1_SDA_TCD 4,26

1_SCL_TCD 4,26

1 2

@

BOARD_ID4

1 2

R549 0_040

@

BOARD_ID1 BOARD_ID0 DescriptionBOARD_ID3 BOARD_ID2

0

0

10 0

0

10 0

BOARD_ID1 BOARD_ID0 DescriptionBOARD_ID3 BOARD_ID2

2_5%

U_I2C_SDA_OUT_PCH 23

MC
MC

U_I2C_SCL_OUT_PCH 23

2_5%

_RST_N 33

CR
FPBACK 24
EC_SENSOR_I

SENSOR_PWR

IO_PWR_EN 31

AUD
SD_PWR_EN 22,33
TOU

CHPANEL_PWR_EN 31
ERA_PWR_EN 31

CAM
SATA_PWR_EN 29
SE_P

WR_EN 25

2

N8_BUTTON_INT_N 22,24

WI

_EN 26

FP_PWR

C_DWL_REQ 25,33

NF

DP_X2MODE_EN 33

NT 22

_EN 31

0000

Elpida LPDDR3 16Gb 1600

10

Sam

sung LPDDR3 16G 1600

0

Elpida LPDDR3 8Gb 1600

1

Micron LPDDR3 32Gb 1866

0

Hynix LPDDR3 16Gb 1600

10

Samsung LPDDR3 8Gb 1600

I2C

I2C

I2C

I2C

I2C

I2C2_SCL

+3VDX_TC

+3VDX_TOU

0_SDA

0_SCL

1_SDA

1_SCL

2_SDA

+3V

H_PAD

+1.8V_AUD

+1.8V

+VCCPGPPA

CHPANEL

R23 0_0402_5%

R24 0_040

R29 0_040

R27 0_040

R25 0_040

R26 0_040

12

12

2_5%

12

2_5%@

12

2_5%@

12

2_5%@

12

2_5%@

R43 2.2K_0402_

R44 2.2K_0402_

R80 2.2K_0402_

R66 2.2K_0402_

1 2

R65 10K_0

1 2

R67 10K_0

R91 2.2K_0402_

R90 2.2K_0402_5%

R62 2.2K_0402_

R63 2.2K_0402_

RP5

@
1 8
2 7
3 6
4 5

10K_8P4R_5%

@

RP6

1 8
2 7
3 6
4 5

P4R_5%

10K_8

UAR
UAR

UAR
UAR

12

12

12

12

12

12

12

12

T2_RXD
T2_TXD

T2_RTS_N
T2_CTS_N

5%

5%

5%

5%

402_5%@

402_5%@

5%

5%

5%

WR_EN

SE_P
SATA_PWR_EN
CAM

ERA_PWR_EN
IO_PWR_EN

AUD

CHPANEL_PWR_EN

TOU

_EN

SD_PWR
SENSOR_PWR

CHPAD_PWR_EN

TOU

R249 49.9K_0402
R250 49.9K_0402

R251 49.9K_0402
R252 49.9K_0402

1

0_SDA_HUB 22

I2C

I2C

0_SCL_HUB 22

I2C

1_SDA_TCD 4,26

1_SCL_TCD 4,26

I2C

2_SDA_AUD 33

I2C

I2C

2_SCL_AUD 33

I2C

1_SDA

1_SCL

I2C

I2C1_SDA_TCD

1_SCL_TCD

I2C

2_SDA_AUD

I2C

I2C

2_SCL_AUD

3_SDA_R

I2C

I2C

3_SCL_R

3_SDA

I2C

3_SCL

I2C

_EN

CHPAD_PWR_EN 6,31

TOU

12

_1%

12

_1%

12

_1%

12

_1%

+3VAUX

+3V

0

0

A A

5

4

0

0

0

0 1 1 00

3

1 0

10 0 1 1

1 1 100

1

01 0

0110

Micron 16Gb x32 LPDDR3 1866

1

10

ix 16Gb x32 LPDDR3 1866

Hyn

0

01 0

Samsung 16Gb x32 LPDDR3 1866

1

Hynix 8Gb x32 LPDDR3 1866

01

Samsung 8Gb x32 LPDDR3 1866

Hyn

ix 32Gb x32 LPDDR3 1866

Micron 8Gb x32 LPDDR3 1866

sung 32Gb x32 LPDDR3 1866

Sam

2

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

4 37Monday,

4 37Monday,

4 37Monday,

Rev

Rev

Rev

of

of

of

Title

Title

Title

BROADWELL MCP ( PCIE USB GPIO)

BROADWELL MCP ( PCIE USB GPIO)

BROADWELL MCP ( PCIE USB GPIO)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

July 27, 2015

July 27, 2015

July 27, 2015

V1.0

V1.0

V1.0

5

+3V

0IX_R_N

1 2

R48 10K_0

+1.8VAUX

1 2

R64 10K_0

D D

402_5%@

402_5%@

Car

C C

SAT

PM_SLP_S

Wla

n

d Reader

0_N8,22,28,31

PM_SLP_S

A PORT2

R500
0_040

PCIE5_WLAN_RX_DN20

PCI
PCIE5_WLAN_TX_DN20
PCI

PCI

PCIE6_SD_RX_DP33
PCI
PCI

1 2

@

2_5%

E5_WLAN_RX_DP20

E5_WLAN_TX_DP20

E6_SD_RX_DN33

E6_SD_TX_DN33
E6_SD_TX_DP33

PCIE9_RN21

PCI

E9_TN21

PCI

PCIE9_TP21

PCI

PCI

E10_TN21

PCI

E10_TP21

PCI

PCIE11_RN21

PCI

E11_TN21

PCI

PCIE11_TP21

SATA2_RN21

SATA2_RP21
SATA2_TN21
SATA2_TP21

E9_RP21

E10_RN21
E10_RP21

R298 100_0

TP11TEST

PAD
PAD

TP12TEST

E11_RP21

12

402_1%

E_COMP

PCI

1
1

PM_SLP_S0IX_R_N

4

U95H

PCIE/USB3/SATA

H13

P

CIE1_RXN/USB3_5_RXN

G13

CIE1_RXP/USB3_5_RXP

P

B17

PCIE1_TXN/USB3_5_TXN

A17

P

CIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

P

CIE2_RXP/USB3_6_RXP

D16

CIE2_TXN/USB3_6_TXN

P

C16

PCIE2_TXP/USB3_6_TXP

H16

CIE3_RXN

P

G16

P

CIE3_RXP

D17

CIE3_TXN

P

C17

CIE3_TXP

P

G15

CIE4_RXN

P

F15

CIE4_RXP

P

B19

P

CIE4_TXN

A19

CIE4_TXP

P

F16

P

CIE5_RXN

E16

CIE5_RXP

P

C19

PCIE5_TXN

D19

P

CIE5_TXP

G18

PCIE6_RXN

F18

P

CIE6_RXP

D20

CIE6_TXN

P

C20

P

CIE6_TXP

F20

CIE7_RXN/SATA0_RXN

P

E20

P

CIE7_RXP/SATA0_RXP

B21

CIE7_TXN/SATA0_TXN

P

A21

CIE7_TXP/SATA0_TXP

P

G21

CIE8_RXN/SATA1A_RXN

P

F21

CIE8_RXP/SATA1A_RXP

P

D21

P

CIE8_TXN/SATA1A_TXN

C21

CIE8_TXP/SATA1A_TXP

P

E22

P

CIE9_RXN

E23

CIE9_RXP

P

B23

PCIE9_TXN

A23

P

CIE9_TXP

F25

P

CIE10_RXN

E25

P

CIE10_RXP

D23

CIE10_TXN

P

C23

P

CIE10_TXP

F5

CIE_RCOMPN

P

E5

P

CIE_RCOMPP

D56

ROC_PRDY#

P

D61

P

ROC_PREQ#

BB11

P_A7/PIRQA#

GP

E28

P

CIE11_RXN/SATA1B_RXN

E27

CIE11_RXP/SATA1B_RXP

P

D24

PCIE11_TXN/SATA1B_TXN

C24

P

CIE11_TXP/SATA1B_TXP

E30

CIE12_RXN/SATA2_RXN

P

F30

P

CIE12_RXP/SATA2_RXP

A25

P

CIE12_TXN/SATA2_TXN

B25

CIE12_TXP/SATA2_TXP

P

SKL_ULT

REV = 1

3

?

SKL_

ULT

USB2

8 OF

20

SSIC / USB3

US

B3_2_RXN/SSIC_1_RXN
B3_2_RXP/SSIC_1_RXP

US
USB3_2_TXN/SSIC_1_TXN

US

B3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
US

B3_3_RXP/SSIC_2_RXP
B3_3_TXN/SSIC_2_TXN

US

US

B3_3_TXP/SSIC_2_TXP

B2_VBUSSENSE

US

P_E9/USB2_OC0#

GP

P_E10/USB2_OC1#

GP
GP

P_E11/USB2_OC2#
P_E12/USB2_OC3#

GP

GP
GP
GPP_E6/DEVSLP2

P_E0/SATAXPCIE0/SATAGP0

GP
GP

P_E1/SATAXPCIE1/SATAGP1

GP

P_E2/SATAXPCIE2/SATAGP2

GP

P_E8/SATALED#

B3_1_RXN

US

USB3_1_RXP
US

B3_1_TXN
B3_1_TXP

US

B3_4_RXN

US

US

B3_4_RXP
B3_4_TXN

US

B3_4_TXP

US

B2N_1

US
USB2P_1

B2N_2

US
USB2P_2

B2N_3

US
USB2P_3

B2N_4

US
US

B2P_4

B2N_5

US
US

B2P_5

B2N_6

US
US

B2P_6

B2N_7

US
US

B2P_7

USB2N_8
US

B2P_8

USB2N_9
US

B2P_9

US

B2N_10

US

B2P_10

US

B2_COMP

B2_ID

US

P_E4/DEVSLP0
P_E5/DEVSLP1

?

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6
AG3
AG4

A9
C9
D9
B9

J1
J2
J3

H2
H3
G4

H1

USB2_COMP

R299 113_0

USB_OC_N0 33
USB_OC_N1 30

C_IRQ_MGP5 25,33

NF

USB_OC_N3 33

1 2

R491 0_040

SSD_SATA_PCI

402_5%

12

2_5%@

E_DET_N 21

402_1%

USB2_ID 33
USB2_VBUS_SE

PCH_NFC_VEN 31,33

SATA2_DEVSLP 21

12

R4910K_0

2

USB3_RX1_N 33
USB3_RX1_P 33

USB3_TX1_N 33
USB3_TX1_P 33

USB3_RX2_N 33
USB3_RX2_P 33

USB3_TX2_N 33
USB3_TX2_P 33

USB3_RX3_N 33
USB3_RX3_P 33

USB3_TX3_N 33
USB3_TX3_P 33

USB_PN1 33
USB_PP1 33

USB_PN2 22,33
USB_PP2 22,33

USB_PN3 24
USB_PP3 24

USB_PN4 30
USB_PP4 30

USB_PN5 26
USB_PP5 26

USB_PN6 24
USB_PP6 24

USB_PN7 20
USB_PP7 20

USB_PN8 33
USB_PP8 33

NSE 33

+3V

USB3.0 PORT (RIO1)

USB3.0 PORT (LIO)

USB3.0 PORT (LIO Type-c)

USB3.0 PORT (RIO1)

USB3.0 PORT (LIO)

TOUCHPANEL

DC_IN USB2.0 PORT

Finger Print

CAMERA

BT

USB3.0 PORT (LIO Type-C)

YPECBUS

R456

0402_1%

200K_

R459

%

1M_0402_5

1

+3VAUX

USB_OC_N1
USB_OC_N0

USB_OC_N3

C_IRQ_MGP5

NF

R20

02_5%

+3VAUX+T

@

PQ7

N65D8LFB-7B

DM

@

USB2_ID

12

1

2

3

PQ9

R548

1 2

1K_04

12

@

R547

0402_5%

100K_

2

12

@

1 2

R81 10K_0402_5%

1 2

R82 10K_0

1 2

R87 10K_0

1 2

R86 10K_0

R450 100K_

@

1

DM

P58D0LFB-7B

3

USB2_VBUS_SE

1 2

@

12

0_040

2_5%
R105
330K_

0402_5%

@

402_5%

402_5%
402_5%

12

0402_5%@

NSE

SKL_

REV = 1

ULT

?

C37

I2_CLKN0

CS

D37

CS

I2_CLKP0

C32

CS

I2_CLKN1

D32

I2_CLKP1

CS

C29

CS

I2_CLKN2

D29

I2_CLKP2

CS

B26

CSI2_CLKN3

A26

CS

EMMC

GP
GP
GP
GP
GP
GP
GP
GP

GPP_F21/EMMC_RCLK

GP

9 OF

20

I2_CLKP3

CSI2_COMP

GP

P_D4/FLASHTRIG

P_F13/EMMC_DATA0
P_F14/EMMC_DATA1
P_F15/EMMC_DATA2
P_F16/EMMC_DATA3
P_F17/EMMC_DATA4
P_F18/EMMC_DATA5
P_F19/EMMC_DATA6
P_F20/EMMC_DATA7

GP

P_F22/EMMC_CLK

P_F12/EMMC_CMD

E

MMC_RCOMP

?

CSI

2_COMP

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

C_COMP

EMM

AT1

3

12

R300 100_0402_1%

12

R191 200_0

402_1%

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

5 37Monday,

5 37Monday,

5 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Tit

le

Title

Title

BROADWELL MCP ( PCIE USB GPIO)

BROADWELL MCP ( PCIE USB GPIO)

BROADWELL MCP ( PCIE USB GPIO)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

2

July 27, 2015

July 27, 2015

July 27, 2015

B B

A A

5

4

U95I

CSI-2

A36

I2_DN0

CS

B36

CS

I2_DP0

C38

CS

I2_DN1

D38

I2_DP1

CS

C36

CS

I2_DN2

D36

I2_DP2

CS

A38

CSI2_DN3

B38

CS

I2_DP3

C31

CSI2_DN4

D31

CS

I2_DP4

C33

I2_DN5

CS

D33

CSI2_DP5

A31

CS

I2_DN6

B31

I2_DP6

CS

A33

CS

I2_DN7

B33

CS

I2_DP7

A29

CS

I2_DN8

B29

CS

I2_DP8

C28

I2_DN9

CS

D28

CS

I2_DP9

A27

I2_DN10

CS

B27

CSI2_DP10

C27

CS

I2_DN11

D27

I2_DP11

CS

SKL_ULT

5

D D

A_BCLK_I2S0_SCLK_R

HD

A_SYNC_I2S0_SFRM_R

HD

A_SDO_I2S0_TXD_R

HD

A_RST_N_R

HD

LK

C C

I2S0_MC

HD

A_SDO_I2S0_TXD_R

RP2

1 8
2 7
3 6
4 5

04_8P4R_5%

22_08

1 2

R28 0_040

1 2

R30 0_040

@

R379 1K_04

12

2_5%@

2_5%@

02_5%

A_BCLK_I2S_SCLK 33

HD

HD

A_SYNC_I2S_SFRM 33

A_SDO_I2S_TXD 33

HD

HDA_RST_N_R_I2S0_MCLK 33

+VCC

PAZIO

+3V

PCH

_BEEP

@

1 2

R177 100K_

0402_5%

4

U95G

A_SYNC_I2S0_SFRM_R

HD
HD

A_SDO_I2S0_TXD_R22

HD

HD

A_SDI_I2S_RXD33

1 2

IC_CLK24,33

DM
DM

IC_DATA24,33

R31 0_0402_5%@

1 2

R32 0_040

_BEEP33

PCH

A_BCLK_I2S0_SCLK_R

A_RST_N_R

HD
I2S0_MCLK

PCH

PCH

2_5%@

1

TP32

_DMIC_CLK

_DMIC_DATA

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK10

AW5

J5

AK7
AK6
AK9

H5
D7

D8
C8

HD
HD
HD
HD
HD
HD
GP
I2S1_SFRM
I

2S1_TXD

GPP_F1/I2S2_SFRM
GP
GP
GPP_F3/I2S2_RXD

GP
GP

GP
GP

GP

SKL_ULT

AUDIO

A_SYNC/I2S0_SFRM
A_BLK/I2S0_SCLK
A_SDO/I2S0_TXD
A_SDI0/I2S0_RXD
A_SDI1/I2S1_RXD
A_RST#/I2S1_SCLK
P_D23/I2S_MCLK

P_F0/I2S2_SCLK
P_F2/I2S2_TXD

P_D19/DMIC_CLK0
P_D20/DMIC_DATA0

P_D17/DMIC_CLK1
P_D18/DMIC_DATA1

P_B14/SPKR

REV = 1

3

?

ULT

SKL_

SDIO/SDXC

P_G0/SD_CMD

GP

GP

P_G1/SD_DATA0
P_G2/SD_DATA1

GP
GPP_G3/SD_DATA2
GP

P_G4/SD_DATA3

P_G5/SD_CD#

GP
GPP_G6/SD_CLK

GP

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

P_G7/SD_WP

GP

P_A16/SD_1P8_SEL

S

?

D_RCOMP

GP

P_F23

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

SD_COM

P

2

CHPAD_PWR_EN 4,31

TOU

12

R184 200_0402_1%

1

B B

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

6 37Monday,

6 37Monday,

6 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP ( RTC AZLIA SATA PCH JTAG)

BROADWELL MCP ( RTC AZLIA SATA PCH JTAG)

BROADWELL MCP ( RTC AZLIA SATA PCH JTAG)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

4

3

2

1

+3V

RP3

D D

C C

B B

1 8
2 7
3 6
4 5

10K_8

1 2

R36 10K_0

1 2

R37 10K_0

VCC

RTC

R111 20K_0

R112 20K_0

P4R_5%

1 2

1 2

SRC

CLKREQ0_N

SRC

CLKREQ2_N

CK_REQ_SD_N
SRC

CLKREQ5_N

402_5%

402_5%

402_1%

402_1%

CK_REQ_WLAN_N

CK_REQ_SSD_N

SRTC_RST_N

1

C11
1U_0201_1

2

C_RST_N

RT

1

C12
1U_0201_1

2

0V6K

0V6K

CLK_SRC1_M.2_SSD_DN21
CLK_SRC

1_M.2_SSD_DP21

CK_REQ_SSD_N21

_DN20

CK_WLAN

CK_WLAN_DP20

CK_REQ_WLAN

_N20

CK_SD_D

N33

P33

CK_SD_D

CK_REQ_SD_N33

ME

RESET
SAVE ME = PU (Default)
CLEAR ME = PD

CMOS RESET

TP87

SAVE CMOS = PU (Default)

PAD

TEST

CLEAR CMOS = PD

TP88

PAD

TEST

SRCCLKREQ0_N

CLKREQ2_N

SRC

SRCCLKREQ5_N

U95J

D42

KOUT_PCIE_N0

CL

C42

CL

KOUT_PCIE_P0

AR10

P_B5/SRCCLKREQ0#

GP

B42

CL

KOUT_PCIE_N1

A42

KOUT_PCIE_P1

CL

AT7

GPP_B6/SRCCLKREQ1#

D41

KOUT_PCIE_N2

CL

C41

CLKOUT_PCIE_P2

AT8

GP

P_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CL

KOUT_PCIE_P3

AT10

P_B8/SRCCLKREQ3#

GP

B40

KOUT_PCIE_N4

CL

A40

KOUT_PCIE_P4

CL

AU8

GP

P_B9/SRCCLKREQ4#

E40

KOUT_PCIE_N5

CL

E38

CL

KOUT_PCIE_P5

AU7

P_B10/SRCCLKREQ5#

GP

SKL_ULT

REV = 1

10P_0

402_50V8J

ULT

SKL_

CLOCK SIGNALS

C13

1

2

?

CLKOUT_ITPXDP_N
CL

10 OF

20

R114 1M_0402_5

Y2

1423

24MHZ_8PF_EXS00A-CS07257

KOUT_ITPXDP_P

GPD8/SUSCLK

TAL24_IN

X

XTAL24_OUT

CLK_BIASREF

X

RT
RT

S

RTCRST#

CRST#

RT

12

XCLK_BIASREF

SUS_CLK

F43
E43

BA17

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

C_X1

RT

AM18

CX1

RT

C_X2

AM20

CX2

?

%

AN18
AM16

C_RST_N

SRT
RT

C_RST_N

XTAL24_OUTXTAL24_IN

1

C14
10P_0

402_50V8J

2

TP90
TP89

TEST
TEST

PAD
PAD

SUS_CLK 20,21

8.2P_0402_50V8J

1 2

C4

32.768KHZ_9PF_CM8V-T1A

C6

1 2

8.2P_0402_

R121 2.7K_0402_0.5%

R143 1K_04

12

Y1

50V8J

1 2

12

12

R83
10M_0402_

CLK5

+VCC

02_5%@

C_X1

RT

5%

RT

C_X2

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

7 37Monday,

7 37Monday,

7 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

le

Title

Title

Tit

BROADWELL MCP (CLK)

BROADWELL MCP (CLK)

BROADWELL MCP (CLK)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

4

3

2

1

+3VAUX

402_5%

402_5%

402_1%

402_5%@

+3VAUX

12

R148 8.2K_0402_

1 2

R149 10K_0

1 2

D D

R150 100K_

1 2

R151 10K_0402_5%@

+3V

1 2

R182 10K_0

DPW

ROK

RST_N22

PM_RSM

PM_BATLOW_N_R

5%

AC_PRESENT

402_5%

PM_PCH

0402_5%@

SYS_

PWROK

RESET_N

SYS_

402_5%

1 2

R142 0_040

1 2

R144 0_040

1 2

R145 10K_0

_PWROK

_R

2_5%
2_5%
402_5%

?

SKL_

U95K

SYSTEM POWER MANAGEMENT

PLT_RST

_N_R

SYS_

RESET_N

RST_N

RSM

PUPWRGD

H_C

1

H_VCCST_PWRGD

PCI

E_WAKE_N20,21,33

RSM

RST_N

TP69

1 2

R193 60.4_0402_

PWROK_R

SYS_
PCH_PWROK

ROK

DPW

SUS_PWR_ACK
SUSACK_N

SMC

_WAKE_SCI_N

PM_LANPHY_ENABLE MPH

1

TP73

AN10

P_B13/PLTRST#

GP

B5

SYS_RESET#

AY17

RS

MRST#

A68

P

ROCPWRGD

B65

1%

CCST_PWRGD

V

B6

S

YS_PWROK

BA20

CH_PWROK

P

BB20

W_PWROK

DS

AR13

P_A13/SUSWARN#/SUSPWRDNACK

GP

AP11

GPP_A15/SUSACK#

BB15

AKE#

W

AM15

GPD2/LAN_WAKE#

AW17

GP

D11/LANPHYPC

AT15

D7/RSVD

GP

SKL_ULT

REV = 1

ULT

SLP_S

5_N

US_N
AN_N

_N

PM_BATLOW_N

SM_INTRUDER_N

Y_EXT_PWR_GATEB

0_N

SLP_S

3_N 22,28
4_N 22

SLP_S

SLP_WLAN_N 31

PCH

AC_PRESENT

_R

GP_V

RALERTB 32,34

1

TP15

1

TP47

1

TP16

1

TP14

1

_PWRBTN_N 22

_R 22

1

TP74

TP54

11 OF

20

GPP_B12/SLP_S0#

GP

D4/SLP_S3#
D5/SLP_S4#

GP

GPD10/SLP_S5#

D9/SLP_WLAN#

GP

GP

D3/PWRBTN#

GP

D1/ACPRESENT

GP

GP

D0/BATLOW#

GP

P_A11/PME#

NTRUDER#

I

GP

P_B11/EXT_PWR_GATE#

P_B2/VRALERT#

GP

LP_SUS#

S
S

LP_LAN#

D6/SLP_A#

AT11
AP15
BA16

SLP_S

AY16

SLP_S

AN15

SLP_L

AW15
BB17

SLP_A

AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

?

PCI

E_WAKE_N

SMC

_WAKE_SCI_N

RALERTB

GP_V

MPH

Y_EXT_PWR_GATEB

SLP_WLAN_N

1 2

R140 1K_0402_5%

1 2

R12 10K_0

1 2

R42 10K_0

1 2

R113 20K_0

1 2

R45 10K_0

C C

SUS_PWR

SYS_PWROK22

PM_PCH

PM_SLP_S

PCH

_ACK_R22

_PWROK22

0_N5,22,28,31

_SUSACK_N22

@

R138

402_5%

10K_0

1 2

RTC

VCC

R85 330K_

B B

1 2

R136 0_040

1 2

R137 0_040

1 2

R147 0_040

1 2

R131 0_040

+3VAUX+1.8VAUX

R132

402_5%

10K_0

1 2

1 2

R135 0_0402_5%

12

0402_5%

2_5%

2_5%

2_5%@

PLT_RST_N20,21,22,33

R141

100K_

0402_5%

1 2

PWROK_R

SYS_

_PWROK

PCH

SLP_S

0_N

SUSACK_N

2_5%@

U18

@

R133

2_5%

0_040

1 2

_ACK

SUS_PWR

ALL_S

YS_PWRGD_PMIC22,28,31,32,34

1.00V_PWRGD_R

12

R211

2_5%

0_040

12

R213

@

0_0402_5%

NC11Vcc

2

A

NC

3

GND

74AUP1G0

7FW4-7_DFN1010-6_1X1

1

C110

2
2U_0402_4V6M

2

NTRUDER_N

SM_I

U9

+3V

6

U93

@

cc
V

A

4

Y

NC

B

Gnd

74AUP1G08FW4-7_DFN1010-6_1X1

3

1 2

R166 0_0402_5%

2
5
1

2

@

C251

0.1u_0201_10V6K

1

PLT_RST

_N_R

1.00V_PWRGD

+3VAUX

_R

1

2

1.00V_PWRGD

+3VAUX

C43
1U_0201_1

NCX2200GF3_SOT891

0V6K

_R

@

6

V

OUT

5

V

CC

2

CC

V

1

V

5

NC

6

V

AZV3001FZ4-7

3

-I

N

1

V

EE

4

N

+I

U10

4

N

OUT

-I

2

EE

V

3

+I

N

CC

2

Y

6

5

4

VCC

ST_PWRGD_IN-

100K_

VCC

ST_PWRGD_IN+

VCC

ST_PWRGD_IN-

ST_PWRGD_IN+

VCC

10K_0

0402_1%

+3VAUX

402_1%

R201

2

1

+1.00VAUX

R198

1 2

C44

0.1u_0201_

1 2

2

1

10V6K

+VCC

ST_CPU

12

R19
1K_04

C41

V6K

0.068U_0201_10

R205 1K_04

R206 1K_04

1

C42

2
.2U_0402_6.3V6M

2

02_5%

ST_PWRGD

H_VCC

12

02_5%

+VCC

12

02_5%@

+VCC

STG

ST_CPU

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

8 37Monday,

8 37Monday,

8 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP (PM)

BROADWELL MCP (PM)

BROADWELL MCP (PM)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

+3VAUX

1 2

R527 0_040

D D

_SCE0_N

PCH

PCH

_SO_R

PCH

_WP_R_N

PCH_SCE0_N
PCH

C C

B B

_SO_R
_WP_R_N

PCH

_SCK22

PCH

_SO22

PCH

_SI22

PCH

_WP_N

PCH

PCH

_HOLD_N

PCH_SCE0_N
PCH
PCH
PCH_SI

U6

1

2

3

4

W25Q64FVSSIG_SO8

U7

1

CS

2

SO(IO1)

3

W

4

SS

V

W25Q64FVZPIQ_WSON8_6x5

R164 33_0402_5%

R167 33_04

R169 33_0402_5%
R170 10K_0

+3VAUX_SPI

R171 20K_0402_1%
R172 33_04

+3VAUX_SPI

R174 20K_0
R175 33_04

R56 10K_0

_SO

R59 10K_0

_SCK

R60 10K_0
R61 10K_0

CS

DO

P

W

GND

#

P#(IO2)

1 2

1 2
1 2
1 2
1 2

@

V

HOLD

HOLD#(IO3)

S

12

12
12

+3VAUX_SPI

2_5%

+3VAUX_SPI

2

C16

0.1u_0201_

10V6K

1

8

CC

K

CL

DI

CC

V

S

CLK

I(IO0)

12

12

12
12

7

6

5

02_5%

402_1%

02_5%

8
7
6
5

02_5%

402_5%@

402_5%@
402_5%@
402_5%@
402_5%@

PCH

PCH

PCH

+3VAUX_SPI

PCH
PCH
PCH

+3VAUX_SPI

_HOLD_R_N

_SCK_R

_SI_R

_HOLD_R_N
_SCK_R
_SI_R

PCH

PCH

PCH

_WP_R_N

PCH

PCH

_HOLD_R_N

_SCK_R

_SO_R

_SI_R

4

U95E

_SCK

PCH
PCH

_SO
_SI

PCH
PCH_WP_N
PCH

_SCE0_N22

PCH

T_SERIRQ22

IN

_HOLD_N

1

TP18

1

TP19

1

TP20

1

TP21

SML0_ALE

AW13

RT_N

CIN_N22

H_R

AV2

S

AW3

S

AV3

S

AW2

S

AU4

S

AU3

S

AU2

S

AU1

S

M2

GP

M3

GP

J4

GPP_D3/SPI1_MOSI

V1

GP

V2

GP

M1

GPP_D0/SPI1_CS#

G3

CL

G2

CL

G1

CL

GP

AY11

GP

REV = 1

SPI - FLASH

PI0_CLK
PI0_MISO
PI0_MOSI
PI0_IO2
PI0_IO3
PI0_CS0#
PI0_CS1#
PI0_CS2#

SPI - TOUCH

P_D1/SPI1_CLK
P_D2/SPI1_MISO

P_D21/SPI1_IO2
P_D22/SPI1_IO3

C LINK

_CLK
_DATA
_RST#

P_A0/RCIN#

P_A6/SERIRQ

SKL_ULT

SML0_CLK

SML0_DAT

+3VAUX

1 2

1 2

+3VAUX

A

R374
10K_0

R176
20K_0

3

@

402_5%

@

402_1%

SKL_

1

2

3

?

ULT

SMBUS, SMLINK

LPC

GP

5 OF 20

PI OR LPC

ES
HIGH: ESPI IS SELECTED FOR EC
LOW: LPC SELECTED
WEAK INTERNAL PD

@

U39

V

V

CCA

CCB

A1

B1

2

2

A

B

GND4OE

TXS0102DQER_1P4X1

GP

GP

P_C1/SMBDATA

P_C2/SMBALERT#

GP

GP

P_C4/SML0DATA

GP

GP

P_C5/SML0ALERT#

GPP_C6/SML1CLK

GP

P_C7/SML1DATA

P_B23/SML1ALERT#/PCHHOT#

GP

P_A1/LAD0/ESPI_IO0

GP
GP

P_A2/LAD1/ESPI_IO1

GP

P_A3/LAD2/ESPI_IO2
P_A4/LAD3/ESPI_IO3

GP

GP

P_A5/LFRAME#/ESPI_CS#

P_A14/SUS_STAT#/ESPI_RESET#

P_A9/CLKOUT_LPC0/ESPI_CLK

GP

GPP_A10/CLKOUT_LPC1

GP

P_A8/CLKRUN#

C

+3VDX_NF

8

7

6

5

P_C0/SMBCLK

P_C3/SML0CLK

R7
R8
R10

R9
W2
W1

W3
V3
AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

?

2

+3V

12

SMB_CLK

A

SMB_DAT
SMB_ALERT_N

SML0_CLK
SML0_DAT

A

RT_N

SML0_ALE

SML1_ALERT_N

@

1 2

R697 0_040

@

1 2

R698 0_040

SML1_CLK 22
SML1_DATA 22

2_5%
2_5%

R322 0_040

+1.8V

R328 0_040

NF

C_SML_CLK 9,25,33
C_SML_DAT 9,25,33

NF

2_5%

12

2_5%@

R517~R520 should be changed to 15ohm when use eSPI mode.

1 2

R517 0_040

1 2

R518 0_0402_5%

1 2

R519 0_040

1 2

R520 0_040

CK_LPC_0_R

C_SML_CLK 9,25,33

NF

NF

C_SML_DAT 9,25,33

2_5%

2_5%
2_5%

LPC_FR

SUS_STAT

_N_ESPI_RST_N 22

1 2

R118 22_04

PM_CLKRUN_N 22

LPC_AD0_ESPI_IO0 22
LPC_AD1_ESPI_IO1 22
LPC_AD2_ESPI_IO2 22
LPC_AD3_ESPI_IO3 22

AME_N_ESPI_CS_N 22

02_1%

CLK_PCI

_LPC_ESPI_CLK 22

PM_CLKR

UN_N

CIN_N

H_R

T_SERIRQ

IN

SMB_CLK
SMB_DAT

A

SMB_ALERT_N

SML0_CLK
SML0_DAT

A

SML1_CLK

A

SML1_DAT

RT_N

SML1_ALE

SML1_ALE

RT_N

NFC_SML_CLK
NF

C_SML_DAT

R158 1K_04
R159 1K_0402_5%
R589 2.2K_0402_

R155 499_0
R156 499_0

R161 1K_04
R162 1K_04

R400 150K_

R373 150K_0402_5%

R377 10K_0

1

1

C79

0V6K

1U_0201_1

2

1 2

5%

402_5%

12
12
12

12
12

12
12

1 2

1 2

1 2

R181 499_0
R180 499_0402_1%@

12
12

12
12

R1348.2K_0402_

R3410K_0402_5%
R3510K_0

02_5%

402_1%
402_1%

02_5%
02_5%

0402_5%@

402_5%@

402_1%@

VCC

5%

GPPA_S0

VCC

+3VAUX

+3V

+3VDX_NF

GPPA_S0

C

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

9 37Monday,

9 37Monday,

9 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP (LPC SPI SMB CLINK)

BROADWELL MCP (LPC SPI SMB CLINK)

BROADWELL MCP (LPC SPI SMB CLINK)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

+VCC

ST_CPU

12

12

12

1%@

R10651_04

R10751_0402_5%

R10851_04

PCH_THRMTRIP_N

ATERR_N

H_C

CH_PANEL_INTR_N_LS

TOU

_JTAG_TDO_CPU

PCH

PCH

_JTAG_TDI_CPU

PCH_JTAG_TMS_CPU

12

02_1%

12

402_1%

+VCC

H_PROCHOT_R_N

12

R9 1K_04

D D

H_PROC

+3VDX_TOU

+VCC

HOT_N22,29,30,32,34

R239 49.9_0402_

CHPANEL

R7 100K_

STG

12

12

02_5%

02_5%

02_1%

0402_5%

R17 1K_04
R160 499_0

4

接到

EC

1.00V GPIO

H_C

_EC22

PECI

RF

_KILL_N_BT_NGFF20

STG

ATERR_N

HOT_R_N

H_PROC
PCH

_THRMTRIP_N

1 2

R212 0_040

1

TP31

1

TP27

1

TP23

1

TP24

TOU

CH_PANEL_INTR_N_R
CHPAD_INTR_N_R

TOU

_POPIRCOMP

CPU
PCH

_POPIRCOMP
OPCE_RC
OPC_RC

3

?

SKL_

TERR#

P_E3/CPU_GP0

P_B3/CPU_GP2
P_B4/CPU_GP3

C_RCOMP

CPU MISC

ULT

JTAG

PCH_JTAG_TCK

P
CH_JTAG_TDO

P

PCH_JTAG_TMS

4 OF

20

ROC_TCK

P

P

ROC_TDI

P

ROC_TDO
ROC_TMS

P

P

ROC_TRST#

CH_JTAG_TDI

P

CH_TRST#

JT

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

AGX

?

U95D

D63

CA

A54

PECI

C65

P

ROCHOT#

C63

HERMTRIP#

T

A65

2_5%

OMP

OMP

AU16

AT16

C55
D55
B54
C56

A6

A7
BA5
AY5

H66
H65

S

KTOCC#

PM#[0]

B
B

PM#[1]
PM#[2]

B

PM#[3]

B

GP
GPP_E7/CPU_GP1
GP
GP

P

ROC_POPIRCOMP
CH_OPIRCOMP

P
OPCE_RCOMP
OP

SKL_ULT

REV = 1

2

PCH

_TCK_JTAGX_CPU
_JTAG_TDI_CPU

PCH

_JTAG_TDO_CPU

PCH
PCH

_JTAG_TMS_CPU

ST_CPU_N

XDP_TR

PCH

_JTAG_TCK
_JTAG_TDI_CPU

PCH
PCH_JTAG_TDO_CPU
PCH

_JTAG_TMS_CPU

ST_CPU_N

XDP_TR
PCH

_TCK_JTAGX_CPU

1

1

1

TP33 TEST

TP35 TEST

PAD

PAD

02_5%

OPCE_RC

OMP

OMP

OPC_RC
CPU_POPIRCOMP
PCH

_POPIRCOMP

PCH_THRMTRIP_N

CH_PANEL_INTR_N_LS24

TOU

TOU

CHPAD_INTR_N26

CH_PANEL_INTR_N_LS

TOU

TOUCHPAD_INTR_N

+3VDX_TOUCHPANEL

2

61

PQ46

A

AO5804EL_SC89-6

H_PAD

+3VDX_TC

5

34

B

PQ46
AO5804EL_SC89-6

1 2

R253 0_040

1 2

R255 0_040

+3VAUX

12

R8
100K_

0402_5%

R214 0_040

+3VAUX

12

R10
100K_

0402_5%

R215 0_040

TOU

2_5%@

TOUCHPAD_INTR_N_R

2_5%@

1 2

1 2

CH_PANEL_INTR_N_R

2_5%

2_5%

CH_PANEL_INTR_N_R

TOU

TOU

CHPAD_INTR_N_R

1 2

H_T

HRMTRIP_N22

C C

B B

R240 0_040

PCH_TCK_JTAGX_CPU

R241 49.9_0402_1%
R242 49.9_0402_
R237 49.9_0402_
R238 49.9_0402_1%

2_5%@

1 2

R185 51_04

12
12

1%

12

1%

12

A A

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

10 37Monday,

10 37Monday,

10 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP (MISC THERM CPU JTAG)

BROADWELL MCP (MISC THERM CPU JTAG)

BROADWELL MCP (MISC THERM CPU JTAG)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

5

4

3

2

July 27, 2015

July 27, 2015

July 27, 2015

5

_VR

+V_EDRAM

R245

402_1%

100_0

1 2

VCC

OPC_SENSE

VSSO

D D

100_0

402_1%

R246

100_0

PC_SENSE

100_0

1 2

HSW IP - STUFF R226 EMPTY R210
SKL A0 STUFF R210 EMPTY R226

+1.00VSUS

1 2

R210 0_0402_5%

+1.00VDX

1 2

R226 0_040

1 2

R227 0_040

C C

VR_SVID

_DATA

H_C

PU_SVIDALRT_N

B B

H_C

PU_SVIDCLK

2_5%@

2_5%

ST_CPU

+VCC

12

R302
100_0

R202 220_0

ST_CPU

+VCC

1 2

402_1%

PR170

45.3_0402_1%

+V_EOP

R247

402_1%

R248

402_1%

ST_CPU

+VCC

+VCC

STG

12

R204 0_040

IO_VR

1 2

1 2

402_5%

1 2

+VCC

VCC

EOPIO_SENSE

OPIO_SENSE

VSSE

ST_CPU

1 2

1

2

1

2

R225
56_0402_5%

2_5%

C253

1
U_0201_10V6K

+V_EOP

C31

1
0U_0402_6.3V6M

1

2

1

2

C36

1
0U_0402_6.3V6M

IO_VR

C35

1
0U_0402_6.3V6M

VR_SVID

+VCCIO +1.00VSUS

R307

402_1%

100_0

1 2

IO_SENSE

VCC
VSSIO_SENSE

R308

402_1%

100_0

1 2

A A

5

+V_EDRAM

1

C269

1
U_0201_10V6K

2

_DATA 32,34

VR_SVID

VR_SVID

4

_VR

1

C273

1
U_0201_10V6K

2

_ALERT_N 32,34

_CLK 32,34

4

CPU

_CORE

1

TP84

1

TP85

+1.8V

VCC

OPC_SENSE

PC_SENSE

VSSO

VCC

EOPIO_SENSE

OPIO_SENSE

VSSE

Note：Layout need to follow
CRB to do an Inductor

1U_0201_1

0.1u_0201_

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

G30

K32

AK32

AB62

P62
V62

H63

G61

AC63
AE63

AE62
AG62

AL63

AJ62

C274

0V6K

1U_0201_1

1U_0201_1

U95L

CC_A30

V
V

CC_A34
CC_A39

V
VCC_A44
V

CC_AK33
CC_AK35

V
VCC_AK37
V

CC_AK38
CC_AK40

V
VCC_AL33
V

CC_AL37
CC_AL40

V
VCC_AM32
V

CC_AM33
CC_AM35

V
V

CC_AM37
CC_AM38

V

CC_G30

V

VD_K32

RS

RS

VD_AK32

VCCOPC_AB62
V

CCOPC_P62
CCOPC_V62

V

V

CC_OPC_1P8_H63

VCC_OPC_1P8_G61

CCOPC_SENSE

V
V

SSOPC_SENSE

CCEOPIO

V
V

CCEOPIO

CCEOPIO_SENSE

V
V

SSEOPIO_SENSE

SKL_ULT

REV = 1

+1.2VSUS

1

1

2

2

+VCC

ST_CPU

1

C275

0V6K

2

STG

+VCC

1

C276

0V6K

2

+1.2V_VCC

2

C189

10V6K

1

SKL_

CPU POWER 1 OF 4

C37
10U_0402_

PLLOC

ULT

6.3V6M

3

CPU

AU23
AU28
AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

AL23

3

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

A18

A22

K20
K21

U95N

CPU POWER 3 OF 4

DDQ_AU23

V
VDDQ_AU28
V

DDQ_AU35
DDQ_AU42

V
V

DDQ_BB23

V

DDQ_BB32
DDQ_BB41

V
V

DDQ_BB47

V

DDQ_BB51

V

DDQC

V

CCST

VCCSTG_A22

CCPLL_OC

V

V

CCPLL_K20
CCPLL_K21

V

SKL_ULT

REV = 1

_CORE

H_CPU_SVIDALRT_N
H_C

PU_SVIDCLK

_DATA

VR_SVID

+VCCSTG

?

SKL_

ULT

14 OF

CCIO_SENSE

V
V

SSIO_SENSE

SSSA_SENSE

V
V

CCSA_SENSE

20

CCIO

V
VCCIO
V

CCIO
CCIO

V
V

CCIO

V

CCIO
CCIO

V

V

CCSA
CCSA

V
V

CCSA

V

CCSA
CCSA

V
V

CCSA
CCSA

V
VCCSA
V

CCSA
CCSA

V
VCCSA
V

CCSA
CCSA

V
VCCSA

CPU

_CORE

R233

100_0

402_1%

1 2

VCC

_SENSE 32

SENSE 32

VSS_

R236

100_0

402_1%

1 2

GFX_COR

R235

100_0

402_1%

VCC

GT_SENSE32

T_SENSE32

VSSG

R304

100_0

402_1%

+VCC

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

VCC

IO_SENSE

AM23

VSSIO_SENSE

AM22

VSSS

A_SENSE

H21

SA_SENSE

VCC

H20

?

?

CC_G32

V
V

CC_G33
CC_G35

V
VCC_G37
V

CC_G38
CC_G40

V
VCC_G42

V

CC_J30
CC_J33

V
VCC_J37
V

CC_J40

CC_K33

V
VCC_K35
V

CC_K37
CC_K38

V
V

CC_K40
CC_K42

V

CC_K43

V

CC_SENSE

V

SS_SENSE

V

IDALERT#

V

VIDSCK

V

IDSOUT

VCCSTG_G20

20

12 OF

?

+1.2VSUS

1

2

C281

C190

1

0

U_0201_10V6K

.1u_0201_10V6K

2

1

2

GFX_COR

E

E

1 2

AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70

L71
M62
N63
N64
N66
N67
N69

J70

J69

U95M

CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
V

CCGT

V

CCGT
CCGT

V

CCGT_SENSE

V

SSGT_SENSE

V

SKL_ULT

REV = 1

SKL_

ULT

CPU POWER 2 OF 4

?

13 OF

VCCGTX_AK42
V

CCGTX_AK43
CCGTX_AK45

V
VCCGTX_AK46
V

CCGTX_AK48
CCGTX_AK50

V
VCCGTX_AK52
V

CCGTX_AK53
CCGTX_AK55

V
V

CCGTX_AK56
CCGTX_AK58

V

CCGTX_AK60

V
V

CCGTX_AK70
CCGTX_AL43

V

CCGTX_AL46

V
V

CCGTX_AL50
CCGTX_AL53

V

CCGTX_AL56

V
V

CCGTX_AL60

CCGTX_AM48

V
VCCGTX_AM50
V

CCGTX_AM52
CCGTX_AM53

V
VCCGTX_AM56
V

CCGTX_AM58
CCGTX_AU58

V
V

CCGTX_AU63

V

CCGTX_BB57
CCGTX_BB66

V

CCGTX_SENSE

V

SSGTX_SENSE

V

20

V

CCGT
CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
VCCGT
V

CCGT
CCGT

V
V

CCGT
CCGT

V

CCGT

V
V

CCGT
CCGT

V

CCGT

V

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

?

1 2

100_0

R309

402_1%

+VCCSA

IO

1

GFX_COR

E

VCC

GTX

GTX

VCC

R243

100_0

402_1%

1 2

VCC

GTX_SENSE 34

TX_SENSE 34

VSSG

R244

100_0

402_1%

1 2

1 2

SA

+VCC

VCC

VSSS

SA_SENSE32

A_SENSE32

R310

100_0402_1%

1 2

LENOVO.CRDN

LENOVO.CRDN

1

LENOVO.CRDN

11 37Monday,

11 37Monday,

11 37Monday,

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of

Title

Title

Title

BROADWELL MCP (PROCESSOR POWER)

BROADWELL MCP (PROCESSOR POWER)

BROADWELL MCP (PROCESSOR POWER)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

2

July 27, 2015

July 27, 2015

July 27, 2015

5

4

3

2

1

+3VAUX

12

?

SKL_ULT

U95O

+VCCPRIM_1P0

+VCC

+1.00VAUX

1 2

L15

30SN1D_2P

BLM15PX3

SA

D D

+VCC

L17
BLM15PX3

1 2

30SN1D_2P

@

1

C73
1U_0201_1

2

+VCC

PRIM_CORE

0V6K

2.57A

1U_0201_1

+VCCDSW_1P0

0V6K

PRIM_CORE

1

MPHYAON_1P0

+VCC

C7

+VCC

MPHYAON_1P0_C

2

MPHYGT_1P0

+VCC

+VCCAMPHYPLL_1P0

+VCCAPLL_1P0

+1.00VAUX

+1.00VAUX

+VCC

0V6K

+VCC

MPHYAON_1P0

+VCCAPLL_1P0

10V6K

+VCC

+VCC

12

PRIM_1P0

+VCCFHV

DTS_1P0

19P2_1P0

2_5%@

1 2

L16

21SN1D_2P

BLM15PX1

R375 0_040

L39

1 2

BLM15GA7

50SN1D_2P

C C

R381 0_0402_5%

R415 0_040

R416 0_040

1

C66
47U_0603_

4V

2

+VCCMPHYAON_1P0_C +VCCMPHYAON_1P0

1

C55

0V6K

1U_0201_1

2

12

2_5%

12

12

2_5%

12

2_5%

1

C54
1U_0201_1

2

2

C94

0.1u_0201_

1

R396 0_040

+VCC

+VCC

+VCC

+VCC

+VCC

+VCC

+VCC

PDSW_3P3

PAZIO

PSPI

SRAM_1P0

PRIM_3P3

FHV

APLLEBB_1P0

RT

C_VCC

R84
1K_04

AB19
AB20

AF18
AF19

N15
N16
N17

AB17

AD17
AD18
AJ17

AJ19

AJ16

AF20
AF21

AJ21

AK20

N18

02_5%

P18

V20
V21

AL1

K17

L1

P15
P16

K15
L15

V15

Y18

T19
T20

1 2

+VCC

MPHYGTAON_1P0_LS

B B

1 2

L8
BLM15PX330SN1D_2P

1

C198

1
U_0201_10V6K

2

12

R376 0_040

1 2

L9

21SN1D_2P

BLM15PX1

R401 0_0402_5%

A A

2_5%

1

C56

0V6K

1U_0201_1

2

1

C71

0V6K

1U_0201_1

2

12

1

C72
1U_0201_10V6K

2

5

1

C70
47U_0603_

2

+VCC

4V

+VCC

+VCC

+VCC

MPHYGT_1P0

AMPHYPLL_1P0

SRAM_1P0

APLLEBB_1P0

+3VAUX

L38

1 2

BLM15GA7

1 2

BLM15GA7

50SN1D_2P

L40

50SN1D_2P

+1.8VAUX

+3VAUX

1 2

L10

21SN1D_2P

BLM15PX1

4

CCPRIM_1P0

V

CCPRIM_1P0

V
V

CCPRIM_1P0

VCCPRIM_CORE
V

CCPRIM_CORE
CCPRIM_CORE

V
VCCPRIM_CORE

PDSW_1P0

DC

V

CCMPHYAON_1P0
CCMPHYAON_1P0

V

V

CCMPHYGT_1P0_N15
CCMPHYGT_1P0_N16

V
V

CCMPHYGT_1P0_N17
CCMPHYGT_1P0_P15

V

CCMPHYGT_1P0_P16

V

CCAMPHYPLL_1P0

V

CCAMPHYPLL_1P0

V

CCAPLL_1P0

V

V

CCPRIM_1P0_AB17
CCPRIM_1P0_Y18

V

V

CCDSW_3P3_AD17
CCDSW_3P3_AD18

V
VCCDSW_3P3_AJ17

CCHDA

V

CCSPI

V

V

CCSRAM_1P0
CCSRAM_1P0

V

CCSRAM_1P0

V
V

CCSRAM_1P0

CCPRIM_3P3_AJ21

V

CCPRIM_1P0_AK20

V

V

CCAPLLEBB

SKL_ULT

REV = 1

+3VALW

D1 SDM

BAT_D

@

CPU POWER 4 OF 4

2 1

2 1

D2

1

C85
1U_0201_1

2

2

C77

0.1u_0201_

1

15 OF 20

10U45LP-7_DFN1006-2-2

10U45LP-7_DFN1006-2-2

SDM

10V6K

+VCC

PDSW_3P3

0V6K

+VCC

V

GP
GP

PAZIO

CCPGPPA

V
V

CCPGPPB
CCPGPPC

V
VCCPGPPD

V

CCPGPPE
CCPGPPF

V

VCCPGPPG

CCPRIM_3P3_V19

V

CCPRIM_1P0_T1

VCCATS_1P8

CCRTCPRIM_3P3

V

CCRTC_AK19

V

CCRTC_BB14

V

DC

V

CCCLK1

VCCCLK2

CCCLK3

V

V

CCCLK4

VCCCLK5

CCCLK6

V

P_B0/CORE_VID0
P_B1/CORE_VID1

3

PRTC

?

1

2

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

C5
1U_0201_10V6K

+3VAUX

R318 0_0402_5%

+3VAUX

R316 0_040

TP77
TP78

VCC

+VCC

RTC

PGPPA

+VCC
+VCC

PGPPB

+VCC

PGPPC
PGPPD

+VCC
+VCC

PGPPE
PGPPF

+VCC
+VCCPGPPG

+VCC

PRIM_3P3

DTS_1P0

+VCC

+VCC

ATS_1P8

PRTCPRIM_3P3

VCC

RTCEXT

19P2_1P0

+VCC

+VCCCLK2

CLK3

+VCC

+VCC

CLK4

CLK6

+VCC

1
1

2

C93

0.1u_0201_10V6K

1

12

12

2_5%

1

C58
1U_0201_1

2

VCC

+VCC

RTC

2

1

CLK5

0V6K

C430

0.1u_0201_

+VCC

+VCC

10V6K

PRIM_3P3

PSPI

2

R323 0_040

R325 0_040

R326 0_040

R327 0_040

R329 0_0402_5%

R330 0_040

1

C65

4V

47U_0603_

2

+1.8VAUX

R324 0_040

R332 0_040

R333 0_040

+3VAUX

R334 0_040

+1.00VAUX

R417 0_0402_5%

R423 0_0402_5%

R428 0_0402_5%

R429 0_040

R438 0_040

2_5%

12

2_5%

12

2_5%

12

2_5%

12

12

2_5%

12

2_5%@

12

2_5%

12

2_5%

12

2_5%

12

12

12

12

2_5%

12

2_5%

Tit

le

Title

Title

BROADWELL MCP (PCH POWER)

BROADWELL MCP (PCH POWER)

BROADWELL MCP (PCH POWER)

Size Document Number

Size Document Number

Size Document Number

C

C

C

YOGA4

YOGA4

YOGA4

Date: Sheet

Date: Sheet

Date: Sheet
"PR

"PR

"PR

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

OPERTY NOTE: this document contains information confidential and

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents

property to LENOVO PND and shall not be reproduced or transf erred to other documents
or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was

or disclosed to others or used for any purpose other than that for which it was
obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

obtained without the expressed written consent of LENOVO PND."

1

C74
1U_0201_1

2

1

C75
1U_0201_1

2

1

C76
1U_0201_1

2

1

C81
1U_0201_1

2

1

C236

1
U_0201_10V6K

2

1

C82
1U_0201_1

2

July 27, 2015

July 27, 2015

July 27, 2015

PGPPA

+VCC

+VCC

PGPPB

0V6K

+VCC

PGPPC

0V6K

+VCC

PGPPE

0V6K

+VCCPGPPD

PGPPG

+VCC

+VCC

PGPPA

+VCCPGPPF

+VCCATS_1P8

0V6K

2

C310

0
.1u_0201_10V6K

1

0V6K

1

+VCC

PRTCPRIM_3P3

+VCC

+VCCCLK3

+VCCCLK4

+VCC

+VCCPGPPA

CLK2

+VCC

CLK6

LENOVO.CRDN

LENOVO.CRDN

LENOVO.CRDN

12 37Monday,

12 37Monday,

12 37Monday,

CLK5

Rev

Rev

Rev

V1.0

V1.0

V1.0

of

of

of