Lenovo Thinkpad T490s Schematic

5

www.teknisi-indonesia.com

4

3

2

1

T490S/X390 Logic Schematics

1.TITLE PAGE

2.BLOCK DIAGRAM

3.CPU (1/16): DDI/TYPE-C

D D

4.CPU (2/16): DDR (1/2)

5.CPU (3/16): DDR (2/2)

6.CPU (4/16): MISC/JTAG

7.CPU (5/16): ESPI/SPI/SMBUS/C-LINK

8.CPU (6/16): LPSS/ISH

9.CPU (7/16): AUDIO/SDXC

10.CPU (8/16): PCIE/USB/SATA

11.CPU (9/16): CSI-2/EMMC/CNVI

12.CPU (10/16): CLOCK SIGNALS

13.CPU (11/16): SYSTEM PM

14.CPU (12/16): CPU POWER (1/2)

15.CPU (13/16): CPU POWER (2/2)

16.CPU (14/16): PCH POWER

C C

17.CPU (15/16): GND

18.CPU (16/16): CFG/RESERVED

19.XDP CONNECTOR

20.RTC BATTERY

21.SPI FLASH

22.BLANK

23.BLANK

24.BLANK

25.BLANK

26.BLANK

27.BLANK

28.BLANK

B B

29.BLANK

30.BLANK

31.BLANK

32.BLANK

33.DDR4 SUB CHANNEL-A

34.DDR4 SUB CHANNEL-B

35.DDR4 SUB CHANNEL-C

36.DDR4 SUB CHANNEL-D

37.BLANK

38.BLANK

39.BLANK

40.BLANK

41.BLANK

42.BLANK

43.BLANK

44.BLANK

45.BLANK

46.BLANK

47.BLANK

48.BLANK

49.BLANK

50.BLANK

51.LCD INTERFACE

52.LID/CAMERA/MIC/TOUCH INTERFACE

53.BLANK

54.HDMI CONNECTOR

55.ALPINE RIDGE (1/2)

56.ALPINE RIDGE (2/2)

57.BLANK

58..BLANK

59.USB PD CONTROLLER

60.BLANK

61.Type-C Switch

62.DOCKING CONNECTOR

63.THUNDERBOLT CONNECTOR

64.M.2 SOCKET 3 MODULE I/F

65.BLANK

66.M.2 TYPE 2230

67.M.2 SOCKET 2 MODULE I/F

68.DDI DEMUX/HDMI LEVEL SHIFTE

69.USB TYPE-A CONNECTOR

70.USB TYPE-A CONN

BASE LOGIC 1 : Lightsaber-3 Pass-1 VER 0.25 Jul/10/2017 BASE LOGIC 2 : Finn-1 SIT VER 2.01 Jun/28/2017

71.BLANK

72.Smart card reader/FRP/NEC LED

73.GBE JACKSONVILLE

74.BLANK

75.BLANK

76.MEDIA CARD CONTROLLER

77.MEDIA CARD INTERFACE

78.AUDIO ALC3287

79.AUDIO CONNECTOR

80.AUDIO JACK SENSE

81.AUDIO EXT MIC I/F

82.AUDIO SPEAKER

83.AUDIO BEEP

84.AUDIO Debug port

85.MEC1663(1/3)

86.MEC1663(2/3)

87.MEC1663(3/3)

88.KEYBOARD/TRACK POINT

89.TOUCH PAD/NFC

90.FAN CONNECTOR

91.APS G-SENSOR

92.BLANK

93.SMBUS SWITCH

94.THINK ENGINE-3 (1/2)

95..THINK ENGINE-3 (2/2)

96.BLANK

97.BLANK

98.DISCRETE TPM 2.0

Jazz/Sideswipe VER 1.0 Jun/12/2018

99.SCREW HOLES

100.DC-IN

101.BATTERY INPUT

102.BATTERY CHARGER(BQ25700A)

103.DC/DC VCC5M (NB690)

104.DC/DC VCC5M_PD (NB693)

105.DC/DC VCC3M (TPS51393)

106.BLANK

107.DC/DC VCC1R8_SUS (BU90104)

108.DC/DC IMVP8 (MP2949AGQKT)

109.DC/DC VCCCPUCORE (MP86901C)

110.DC/DC VCCGFXCORE_I (MP86901

111.DC/DC VCCSA (MP86901A)

112.DC/DC VCC1R2A(NB687)

113.BLANK

114.DC/DC VCC1R05_SUS(NB693)

115.BLANK

116.LOAD SW VCCST & VCCSTG

117.LOAD SW LAN

118.LOAD SW B

119.LOAD SW WLAN

120.LOAD SW PCH SUS

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2

2018/01/12

LC Future Center Secret Data

Deciphered Date

2018/01/12

Title

TITLE PAGE

Size Document Number Re v

Custom

Date: Sheet of

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

1 125

0.1

5

www.teknisi-indonesia.com

4

3

2

1

LCD CON N eDP 13" FHD/FHD Touch 14" FHD/FHD Touch /WQHD

D D

HDMI Conn

TYPE-C Conn

USB2. 0 Smart Cart

USB 2.0 TYPE- C

USB3.1 Gen1 AOU (USB1)

C C

USB3.1 Gen1 CON N

USB 2.0 Side Dock Port

USB2. 0 Touch Panel

USB2. 0 M.2 WWAN Slot

USB2. 0 IR Camera

USB2. 0 Fingerp rint

54

I2C

63

USB2.0 CH1

72

USB2.0 CH2

61

USB3.0 CH3 USB2.0 CH3

70

USB3.0 CH4 USB2.0 CH4

69

USB2.0 CH5

62

USB2.0 CH6

51

USB2.0 CH7

67

USB2.0 CH8

52

USB2.0 CH9

72

HDIMI

DP++ DEMUX PS8337 BQFN

USB-C SW PS8747B

USB x 1 0 ports

RTC Battery

FAN

G-Sensor

LIS2DWLTR_LGA12_2X2

51

68

XBAR_D DI2x4

61

20

90

91

EDPx4

DDI2x4

USB3.0 CH2

10

CPU

Intel

Whiskey Lake U

Platform

BGA15 28

15W

3,4,5,6,7, 8,9,1 0,11, 12 13,14,15 ,16,1 7,18

LPC Bus 33MHz

Channel A

DDR4 2400MHz

Channel B DDR 4

DDR4 2400MHz

XDP

SM Bus

10

SPI

TPM 2.0

ST33HTPH2E32AHB4 _VQFN32_5X5

DDR4 / 1.2V

DDR 4 SUB

MD

SUB

MD

CPU XDP

NFC

CNVi

PCI Express x 8 p orts

HDA

SPI Flash

32MB (SPI1)

MX25L25673GM2I-08G

98

19

89

21

33,34

35,36

Stereo Speaker

1GB x 4 ; 2GB x 4

82

Microphone Headphone

79

Blueto oth

ALC328 7 HDA CODEC

ALC3287-CG_MQFN48_6X 6

Extern al

Mic

JAZZ/SIDESWIPE Block Diagram

Project Code: FT491/FX390

Antenn a

(M.2 WLAN )

9560PD2WGPLQ_146P

66

Intel GbE PHY JACKSO NVILLE

78

WGI219LM-QREF-A0_QFN48_6 X6

Internal

Mic

81

52

Port 8 (X1)

73

SM Bus

2018 Feb ' 20

DDI1 X4

ALPINE RIDGE_LP

JHL6240 _BGA337

SPI

SPI Flash TBT

8MB

W25Q80DVSSIG_SO8

Antenn a

(M.2 WWAN Card)

Type-B M.2 Card

Micro SIM Card Slot

Port 7 (X1)

Port 5,6 (X2)

55.56

67

Port 1

77

SBU SW TS3DS102 24

PD Conntroller TI TPS65988

SN170101 2RJTR

SPI

55

(X1)

Port 9~12 (X4)

60

59

Multi-Media Contro ller

Real tek RTS52 32S- GR

M.2 Slot SSD

228 0 224 2

I2C

SD Card Slot

Side Dock (CS18)

77

62

76

64

B B

USB2. 0

Port 9

Fingerp rint Reader

89

A A

Sub-Board

USB3.1 Gen1 AOU (USB1)

Sub-B

5

FPC

Thermal Sensor

PECI 3.0

LED for ThinkPad Logos

SMB-MB/SB

SM Bus

ClickP ad

Power Button

Keyboard

Embedded

Controller MEC1 663

MEC1663-WC_WFBGA144

8888

85,86, 87 94,95

Power Button

FFC

51

4

Lenovo ASIC THINK ENGINE-3

BD4179MWV_UQFN56_7X 7

50

Audio Combo Jack

Sub Board

Difference with Kolar

External Connector/Socket

Internal Connector/Socket

Internal Switch

3

TABLE: Chip Capacitor Thermal Characteristics

Code

-55 to 150degC

-55 to 125degC

-55 to 105degC

-55 to 85degC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+/-30ppm/ degC +/-30ppm/ degC

+/-15% +/-22% +/-15%

2018/01/12

NPO

C0G

X7R X6S X5R

LC Future Center Secre t Data

2

TABLE: Chip Capacitor Tolerance

Tolera nce

+/-0.25pF +/-0.5pF

+/-5% +/-10% +/-20% +80/-20%

Deciphered Date

2018/01/12

Code

C D

J K M

Z

TABLE: Chip Pa rt Dimension

Size [mm]

0.40 x 0.20

0.60 x 0.30

1.00 x 0.50

1.60 x 0.80

2.00 x 1.25

2.00 x 1.60

2.50 x 2.00

3.20 x 1.60

3.20 x 2.50

4.50 x 1.60

4.50 x 2.50

4.50 x 3.20

5.00 x 2.50

6.40 x 3.20

Title

BLOCK DIAGRAM

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet of

mm Size Code Inch Size Code

0402 0603 1005 1608 2125 2016 2520 3216 3225 4516 4525 4532 5025 6432

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

01005 0201 0402 0603 0805 0806 1008 1206 1210 1806 1810 1812 2010 2512

LOGIC

2 125

0.1

5

www.teknisi-indonesia.com

4

3

2

1

TABLE : Fu nctional Strap

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD (DDP1 I2C / TBT LSX #0 PI NS VCCIO CONFIGURATION)

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD (DDP2 I2C / TBT LSX #1 PI NS VCCIO CONFIGURATION)

GPP_D10/DDP3_CTRLDATA/TBT_LSX2_RXD (DDP3 I2C / TBT LSX #2 PINS VCCIO CONFIGURATION)

GPP_D12/DDP4_CTRLDATA/TBT_LSX3_RXD (DDP4 I2C / TBT LSX #3 PINS VCCIO CONFIGURATION)

D D

HIGH

LOW

3.3V

1.8V

VCC3_SUS

1 2

DDIP1_0N55

DDIP1_0P55 DDIP1_1N55

DDIP1_1P55

DDIP1_2N55

DDIP1_2P55

DDIP1_3N55

DDIP1_3P55

DDIP2_0N68

DDIP2_0P68

DDIP2_1N68 DDIP2_1P68

DDIP2_2N68

C C

B B

DDIP2_2P68

DDIP2_3N68 DDIP2_3P68

DDIP2_CTRLCLK68

DDIP2_CTRLDATA68

DDIP1_0N DDIP1_0P

DDIP1_1N DDIP1_1P

DDIP1_2N DDIP1_2P

DDIP1_3N

DDIP1_3P

DDIP2_0N

DDIP2_0P DDIP2_1N

DDIP2_1P DDIP2_2N

DDIP2_2P DDIP2_3N

DDIP2_3P

DDIP2_CTRLCLK

DDIP2_CTRLDATA

VCCIO

12

R0307

GPP_H17

1/20W_24.9_1%_0201

EDP_COMP

GPP_E19

?

UCPU1A

AL5

DDI1_TXN_0

AL6

DDI1_TXP_0

AJ5

DDI1_TXN_1

AJ6

DDI1_TXP_1

AF6

DDI1_TXN_2

AF5

DDI1_TXP_2

AE5

DDI1_TXN_3

AE6

DDI1_TXP_3

AC4

DDI2_TXN_0

AC3

DDI2_TXP_0

AC1

DDI2_TXN_1

AC2

DDI2_TXP_1

AE4

DDI2_TXN_2

AE3

DDI2_TXP_2

AE1

DDI2_TXN_3

AE2

DDI2_TXP_3

GPP_E13/DDPB_HPD0/DISP_MISC0

GPP_E14/DDPC_HPD1/DISP_MISC1

GPP_E15/DPPD_HPD2/DISP_MISC2

GPP_E16/DPPE_HPD3/DISP_MISC3

GPP_E17/EDP_HPD/DISP_MISC4

AM6

DISP_RCOMP

CC8

GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#

CC9

GPP_E19/DPPB_CTRLDATA

CH4

GPP_E20/DPPC_CTRLCLK

CH3

GPP_E21/DPPC_CTRLDATA

CP4

GPP_E22/DPPD_CTRLCLK

CN4

GPP_E23/DPPD_CTRLDATA

CR26

GPP_H16/DDPF_CTRLCLK

CP26

GPP_H17/DDPF_CTRLDATA

@

1 of 20

WHISKEYLAKE-U_BGA1528

EDP_TXN_0

EDP_TXP_0

EDP_TXN_1

EDP_TXP_1

EDP_TXN_2

EDP_TXP_2

EDP_TXN_3

EDP_TXP_3

EDP_AUX_N

EDP_AUX_P

DISP_UTILS

DDI1_AUX_N

DDI1_AUX_P

DDI2_AUX_N

DDI2_AUX_P

DDI3_AUX_N

DDI3_AUX_P

EDP_BKLTEN

EDP_VDDEN

EDP_BKLTCTL

AG4

AG3

AG2

AG1

AJ4

AJ3

AJ2

AJ1

AH4

AH3

AM7

AC7

AC6

AD4

AD3

AG7

AG6

CN6

CM6

CP7

CP6

CM7

CK11

CG11

CH11

EDP_TXN0

EDP_TXP0 EDP_TXN1

EDP_TXP1 EDP_TXN2

EDP_TXP2 EDP_TXN3

EDP_TXP3

EDP_AUXN

EDP_AUXP

DDIP1_AUXN

DDIP1_AUXP

DDIP2_AUXN

DDIP2_AUXP

DDIP1_HPD

DDIP2_HPD

PANEL_POWER_ON_CPU

@

1 2

1/20W_100K_5%_0201

R0303

R0304

1 2

1/20W_100K_5%_0201

R0302

1 2

1/20W_100K_5%_0201

R0305

LCD_SELF_TEST_ON51,87

1/20W_100K_5%_0201

PANEL_POWER_ON_CPU

LCD_SELF_TEST_ON

1 2

1/20W_100K_5%_0201

R0306

EDP_TXN0 51

EDP_TXP0 51 EDP_TXN1 51

EDP_TXP1 51 EDP_TXN2 51

EDP_TXP2 51 EDP_TXN3 51

EDP_TXP3 51

EDP_AUXN 51

EDP_AUXP 51

DDIP1_AUXN 55

DDIP1_AUXP 55 DDIP2_AUXN 68

DDIP2_AUXP 68

DDIP1_HPD 55

DDIP2_HPD 68

-WWAN_PERST 67

EDP_HPD 51

VGA_BLON 85

PANEL_BKLT_CTRL_CPU 51

RB520CM-30T2R_VMN2M2

12

D0301

RB520CM-30T2R_VMN2M2

12

D0302

12

R0308 1/20W_100K_5%_0201

PANEL_POWER_ON 95

R0301

1/20W_2.2K_5%_0201

UCPU1

WHL_i7

SA00009GY10

VCC3_SUS

12

GPP_H17

R0309

@

1/20W_20K_5%_0201

12

R0310

@

1/20W_20K_5%_0201

5

4

A A

i7_NVMP@

UCPU1

WHL_i5

SA00009Z900

i5_V@

UCPU1

WHL_i5

SA00009GZ10

i5_NVMP@

CPU Config

UCPU1

WHL_i7

SA00009Z800

i7_V@

UCPU1

WHL_i7

SA00009GY00

i7_NV@

UCPU1

WHL_i3

SA00009H010

i3_NVMP@

3

PCB

zzz1

NM-B891

DAZ1BR00100

SVT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (1/16): DDI/TYPE-C

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Wednesday, January 02, 2019

1

3 125

of

0.1

5

www.teknisi-indonesia.com

4

3

2

1

D D

C C

B B

M_A_DQ[15:0]33

M_A_DQ[47:32]33

M_B_DQ[15:0]35

M_B_DQ[47:32]35

M_A_DQ4

M_A_DQ6 M_A_DQ1

M_A_DQ7 M_A_DQ2

M_A_DQ0 M_A_DQ5

M_A_DQ3 M_A_DQ12

M_A_DQ14 M_A_DQ9

M_A_DQ13 M_A_DQ10

M_A_DQ8 M_A_DQ11

M_A_DQ15 M_A_DQ34

M_A_DQ32 M_A_DQ39

M_A_DQ35 M_A_DQ38

M_A_DQ36 M_A_DQ37

M_A_DQ33 M_A_DQ46

M_A_DQ40 M_A_DQ47

M_A_DQ45 M_A_DQ42

M_A_DQ44 M_A_DQ43

M_A_DQ41 M_B_DQ4

M_B_DQ6 M_B_DQ5

M_B_DQ1 M_B_DQ2

M_B_DQ0 M_B_DQ3

M_B_DQ7 M_B_DQ10

M_B_DQ14 M_B_DQ15

M_B_DQ13 M_B_DQ12

M_B_DQ8 M_B_DQ11

M_B_DQ9 M_B_DQ34

M_B_DQ32 M_B_DQ37

M_B_DQ33 M_B_DQ36

M_B_DQ38 M_B_DQ35

M_B_DQ39 M_B_DQ42

M_B_DQ46 M_B_DQ47

M_B_DQ45 M_B_DQ40

M_B_DQ44 M_B_DQ43

M_B_DQ41

?

UCPU1B

A26

DDR0_DQ_0/DDR0_DQ_0

D26

DDR0_DQ_1/DDR0_DQ_1

D28

DDR0_DQ_2/DDR0_DQ_2

C28

DDR0_DQ_3/DDR0_DQ_3

B26

DDR0_DQ_4/DDR0_DQ_4

C26

DDR0_DQ_5/DDR0_DQ_5

B28

DDR0_DQ_6/DDR0_DQ_6

A28

DDR0_DQ_7/DDR0_DQ_7

B30

DDR0_DQ_8/DDR0_DQ_8

D30

DDR0_DQ_9/DDR0_DQ_9

B33

DDR0_DQ_10/DDR0_DQ_10

D32

DDR0_DQ_11/DDR0_DQ_11

A30

DDR0_DQ_12/DDR0_DQ_12

C30

DDR0_DQ_13/DDR0_DQ_13

B32

DDR0_DQ_14/DDR0_DQ_14

C32

DDR0_DQ_15/DDR0_DQ_15

H37

DDR0_DQ_16/DDR0_DQ_32

H34

DDR0_DQ_17/DDR0_DQ_33

K34

DDR0_DQ_18/DDR0_DQ_34

K35

DDR0_DQ_19/DDR0_DQ_35

H36

DDR0_DQ_20/DDR0_DQ_36

H35

DDR0_DQ_21/DDR0_DQ_37

K36

DDR0_DQ_22/DDR0_DQ_38

K37

DDR0_DQ_23/DDR0_DQ_39

N36

DDR0_DQ_24/DDR0_DQ_40

N34

DDR0_DQ_25/DDR0_DQ_41

R37

DDR0_DQ_26/DDR0_DQ_42

R34

DDR0_DQ_27/DDR0_DQ_43

N37

DDR0_DQ_28/DDR0_DQ_44

N35

DDR0_DQ_29/DDR0_DQ_45

R36

DDR0_DQ_30/DDR0_DQ_46

R35

DDR0_DQ_31/DDR0_DQ_47

AN35

DDR0_DQ_32/DDR1_DQ_0

AN34

DDR0_DQ_33/DDR1_DQ_1

AR35

DDR0_DQ_34/DDR1_DQ_2

AR34

DDR0_DQ_35/DDR1_DQ_3

AN37

DDR0_DQ_36/DDR1_DQ_4

AN36

DDR0_DQ_37/DDR1_DQ_5

AR36

DDR0_DQ_38/DDR1_DQ_6

AR37

DDR0_DQ_39/DDR1_DQ_7

AU35

DDR0_DQ_40/DDR1_DQ_8

AU34

DDR0_DQ_41/DDR1_DQ_9

AW35

DDR0_DQ_42/DDR1_DQ_10

AW34

DDR0_DQ_43/DDR1_DQ_11

AU37

DDR0_DQ_44/DDR1_DQ_12

AU36

DDR0_DQ_45/DDR1_DQ_13

AW36

DDR0_DQ_46/DDR1_DQ_14

AW37

DDR0_DQ_47/DDR1_DQ_15

BA35

DDR0_DQ_48/DDR1_DQ_32

BA34

DDR0_DQ_49/DDR1_DQ_33

BC35

DDR0_DQ_50/DDR1_DQ_34

BC34

DDR0_DQ_51/DDR1_DQ_35

BA37

DDR0_DQ_52/DDR1_DQ_36

BA36

DDR0_DQ_53/DDR1_DQ_37

BC36

DDR0_DQ_54/DDR1_DQ_38

BC37

DDR0_DQ_55/DDR1_DQ_39

BE35

DDR0_DQ_56/DDR1_DQ_40

BE34

DDR0_DQ_57/DDR1_DQ_41

BG35

DDR0_DQ_58/DDR1_DQ_42

BG34

DDR0_DQ_59/DDR1_DQ_43

BE37

DDR0_DQ_60/DDR1_DQ_44

BE36

DDR0_DQ_61/DDR1_DQ_45

BG36

DDR0_DQ_62/DDR1_DQ_46

BG37

DDR0_DQ_63/DDR1_DQ_47

WHISKEYLAKE-U_BGA1528

@

DDR0_CKN_0/DDR0_CKN_0

DDR0_CKP_0/DDR0_CKP_0

DDR0_CKN_1/DDR0_CKN_1

DDR0_CKP_1/DDR0_CKP_1

DDR0_CKE_0/DDR0_CKE_0

DDR0_CKE_1/DDR0_CKE_1

DDR0_CKE_2/NC

DDR0_CKE_3/NC

DDR0_CS#_0/DDR0_CS#_0

DDR0_CS#_1/DDR0_CS#_1

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1

DDR0_CAB_9/DDR0_MA_0

DDR0_CAB_8/DDR0_MA_1

DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4

DDR0_CAA_0/DDR0_MA_5

DDR0_CAA_2/DDR0_MA_6

DDR0_CAA_4/DDR0_MA_7

DDR0_CAA_3/DDR0_MA_8

DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10

DDR0_CAA_7/DDR0_MA_11

DDR0_CAA_6/DDR0_MA_12

DDR0_CAB_0/DDR0_MA_13

DDR0_CAB_2/DDR0_MA_14

DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_3/DDR0_MA_16

DDR0_CAB_4/DDR0_BA_0

DDR0_CAB_6/DDR0_BA_1

DDR0_CAA_5/DDR0_BG_0

DDR0_CAA_8/DDR0_ACT#

DDR0_CAA_9/DDR0_BG_1

DDR0_DQSN_0/DDR0_DQSN_0

DDR0_DQSP_0/DDR0_DQSP_0

DDR0_DQSN_1/DDR0_DQSN_1

DDR0_DQSP_1/DDR0_DQSP_1

DDR0_DQSN_2/DDR0_DQSN_4

DDR0_DQSP_2/DDR0_DQSP_4

DDR0_DQSN_3/DDR0_DQSN_5

DDR0_DQSP_3/DDR0_DQSP_5

DDR0_DQSN_4/DDR1_DQSN_0

DDR0_DQSP_4/DDR1_DQSP_0

DDR0_DQSN_5/DDR1_DQSN_1

DDR0_DQSP_5/DDR1_DQSP_1

DDR0_DQSN_6/DDR1_DQSN_4

DDR0_DQSP_6/DDR1_DQSP_4

DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_7/DDR1_DQSP_5

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA

DDR0_VREF_DQ_0

DDR0_VREF_DQ_1

DDR1_VREF_DQ

DDR_VTT_CNTL

2 of 20

V32

V31

T32

T31

U36

U37

U34

U35

AE32

AF32

AE31

AF31

AC37

AC36

AC34

AC35

AA35

AB35

AA37

AA36

AB34

W36

Y31

W34

AA34

AC32

AC31

AB32

Y32

W32

AB31

V34

V35

W35

C27

D27

D31

C31

J35

J34

P34

P35

AP35

AP34

AV34

AV35

BB35

BB34

BF34

BF35

W37

W31

F36

D35

D37

E36

C35

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7 M_A_A8

M_A_A9 M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_A15

M_A_A16

DDR_PG_CTRL

-M_A_DDRCLK0_1200M

M_A_DDRCLK0_1200M

M_A_CKE0

-M_A_CS0

M_A_ODT0

-M_A_DQS0

M_A_DQS0

-M_A_DQS1

M_A_DQS1

-M_A_DQS4

M_A_DQS4

-M_A_DQS5

M_A_DQS5

-M_B_DQS0

M_B_DQS0

-M_B_DQS1

M_B_DQS1

-M_B_DQS4

M_B_DQS4

-M_B_DQS5

M_B_DQS5

-M_A_ALERT M_A_PARITY

M_A_BS0

M_A_BS1

M_A_BG0

-M_A_ACT

M_A_BG1

VCC3M

-M_A_DDRCLK0_1200M 33,34

M_A_DDRCLK0_1200M 33,34

M_A_CKE0 33,34

-M_A_CS0 33,34

M_A_ODT0 33,34

M_A_BS0 33,34 M_A_BS1 33,34

M_A_BG0 33,34

-M_A_ACT 33,34

M_A_BG1 33

-M_A_ALERT 33,34

M_A_PARITY 33,34 M_A_VREF_CA_CPU 34

M_B_VREF_CA_CPU 36

M_A_A[16:0] 33,34

-M_A_DQS[7:0] 5,33

M_A_DQS[7:0] 5,33

-M_B_DQS[7:0] 5,35

M_B_DQS[7:0] 5,35

R0402

1/20W_100K_5%_0201

1 2

VCC1R2A

2

DDR_VTT_PG_CTRL

1

Q0401 DTC015TMT2L NPN VMT3

DDR_VTT_PG_CTRL 112

3

R0401 1/20W_10K_5%_0201

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

@

Title

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (2/16): DDR (1/2)

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

4 125

of

0.1

5

www.teknisi-indonesia.com

4

3

2

1

D D

C C

B B

M_A_DQ[31:16]33

M_A_DQ[63:48]33

M_B_DQ[31:16]35

M_B_DQ[63:48]35

M_A_DQ20

M_A_DQ22

M_A_DQ21

M_A_DQ17

M_A_DQ18

M_A_DQ16

M_A_DQ23 M_A_DQ19

M_A_DQ26 M_A_DQ24

M_A_DQ31 M_A_DQ29

M_A_DQ30 M_A_DQ28

M_A_DQ27 M_A_DQ25

M_A_DQ50 M_A_DQ48

M_A_DQ53 M_A_DQ49

M_A_DQ54 M_A_DQ52

M_A_DQ51 M_A_DQ55

M_A_DQ62 M_A_DQ58

M_A_DQ63 M_A_DQ61

M_A_DQ56 M_A_DQ60

M_A_DQ57 M_A_DQ59

M_B_DQ16 M_B_DQ20

M_B_DQ19 M_B_DQ23

M_B_DQ22 M_B_DQ18

M_B_DQ17

M_B_DQ21

M_B_DQ26 M_B_DQ30

M_B_DQ31 M_B_DQ29

M_B_DQ28 M_B_DQ24

M_B_DQ27 M_B_DQ25

M_B_DQ48

M_B_DQ50 M_B_DQ51

M_B_DQ55 M_B_DQ52

M_B_DQ54

M_B_DQ49 M_B_DQ53

M_B_DQ60 M_B_DQ56

M_B_DQ58 M_B_DQ62

M_B_DQ63

M_B_DQ61

M_B_DQ57

M_B_DQ59

?

UCPU1C

J22

DDR1_DQ_0/DDR0_DQ_16

H25

DDR1_DQ_1/DDR0_DQ_17

G22

DDR1_DQ_2/DDR0_DQ_18

H22

DDR1_DQ_3/DDR0_DQ_19

F25

DDR1_DQ_4/DDR0_DQ_20

J25

DDR1_DQ_5/DDR0_DQ_21

G25

DDR1_DQ_6/DDR0_DQ_22

F22

DDR1_DQ_7/DDR0_DQ_23

D22

DDR1_DQ_8/DDR0_DQ_24

C22

DDR1_DQ_9/DDR0_DQ_25

C24

DDR1_DQ_10/DDR0_DQ_26

D24

DDR1_DQ_11/DDR0_DQ_27

A22

DDR1_DQ_12/DDR0_DQ_28

B22

DDR1_DQ_13/DDR0_DQ_29

A24

DDR1_DQ_14/DDR0_DQ_30

B24

DDR1_DQ_15/DDR0_DQ_31

G31

DDR1_DQ_16/DDR0_DQ_48

G32

DDR1_DQ_17/DDR0_DQ_49

H29

DDR1_DQ_18/DDR0_DQ_50

H28

DDR1_DQ_19/DDR0_DQ_51

G28

DDR1_DQ_20/DDR0_DQ_52

G29

DDR1_DQ_21/DDR0_DQ_53

H31

DDR1_DQ_22/DDR0_DQ_54

H32

DDR1_DQ_23/DDR0_DQ_55

L31

DDR1_DQ_24/DDR0_DQ_56

L32

DDR1_DQ_25/DDR0_DQ_57

N29

DDR1_DQ_26/DDR0_DQ_58

N28

DDR1_DQ_27/DDR0_DQ_59

L28

DDR1_DQ_28/DDR0_DQ_60

L29

DDR1_DQ_29/DDR0_DQ_61

N31

DDR1_DQ_30/DDR0_DQ_62

N32

DDR1_DQ_31/DDR0_DQ_63

AJ29

DDR1_DQ_32/DDR1_DQ_16

AJ30

DDR1_DQ_33/DDR1_DQ_17

AM32

DDR1_DQ_34/DDR1_DQ_18

AM31

DDR1_DQ_35/DDR1_DQ_19

AM30

DDR1_DQ_36/DDR1_DQ_20

AM29

DDR1_DQ_37/DDR1_DQ_21

AJ31

DDR1_DQ_38/DDR1_DQ_22

AJ32

DDR1_DQ_39/DDR1_DQ_23

AR31

DDR1_DQ_40/DDR1_DQ_24

AR32

DDR1_DQ_41/DDR1_DQ_25

AV30

DDR1_DQ_42/DDR1_DQ_26

AV29

DDR1_DQ_43/DDR1_DQ_27

AR30

DDR1_DQ_44/DDR1_DQ_28

AR29

DDR1_DQ_45/DDR1_DQ_29

AV32

DDR1_DQ_46/DDR1_DQ_30

AV31

DDR1_DQ_47/DDR1_DQ_31

BA32

DDR1_DQ_48/DDR1_DQ_48

BA31

DDR1_DQ_49/DDR1_DQ_49

BD31

DDR1_DQ_50/DDR1_DQ_50

BD32

DDR1_DQ_51/DDR1_DQ_51

BA30

DDR1_DQ_52/DDR1_DQ_52

BA29

DDR1_DQ_53/DDR1_DQ_53

BD29

DDR1_DQ_54/DDR1_DQ_54

BD30

DDR1_DQ_55/DDR1_DQ_55

BG31

DDR1_DQ_56/DDR1_DQ_56

BG32

DDR1_DQ_57/DDR1_DQ_57

BK32

DDR1_DQ_58/DDR1_DQ_58

BK31

DDR1_DQ_59/DDR1_DQ_59

BG29

DDR1_DQ_60/DDR1_DQ_60

BG30

DDR1_DQ_61/DDR1_DQ_61

BK30

DDR1_DQ_62/DDR1_DQ_62

BK29

DDR1_DQ_63/DDR1_DQ_63

WHISKEYLAKE-U_BGA1528

@

DDR1_CKN_0/DDR1_CKN_0

DDR1_CKP_0/DDR1_CKP_0

DDR1_CKN_1/DDR1_CKN_1

DDR1_CKP_1/DDR1_CKP_1

DDR1_CKE_0/DDR1_CKE_0

DDR1_CKE_1/DDR1_CKE_1

DDR1_CKE_2/NC

DDR1_CKE_3/NC

DDR1_CS#_0/DDR1_CS#_0

DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

NC/DDR1_ODT_1

DDR1_CAB_9/DDR1_MA_0

DDR1_CAB_8/DDR1_MA_1

DDR1_CAB_5/DDR1_MA_2

NC/DDR1_MA_3

NC/DDR1_MA_4

DDR1_CAA_0/DDR1_MA_5

DDR1_CAA_2/DDR1_MA_6

DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9

DDR1_CAB_7/DDR1_MA_10

DDR1_CAA_7/DDR1_MA_11

DDR1_CAA_6/DDR1_MA_12

DDR1_CAB_0/DDR1_MA_13

DDR1_CAB_2/DDR1_MA_14

DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_3/DDR1_MA_16

DDR1_CAB_4/DDR1_BA_0

DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2

DDR1_DQSP_0/DDR0_DQSP_2

DDR1_DQSN_1/DDR0_DQSN_3

DDR1_DQSP_1/DDR0_DQSP_3

DDR1_DQSN_2/DDR0_DQSN_6

DDR1_DQSP_2/DDR0_DQSP_6

DDR1_DQSN_3/DDR0_DQSN_7

DDR1_DQSP_3/DDR0_DQSP_7

DDR1_DQSN_4/DDR1_DQSN_2

DDR1_DQSP_4/DDR1_DQSP_2

DDR1_DQSN_5/DDR1_DQSN_3

DDR1_DQSP_5/DDR1_DQSP_3

DDR1_DQSN_6/DDR1_DQSN_6

DDR1_DQSP_6/DDR1_DQSP_6

DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_7/DDR1_DQSP_7

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#

DDR_COMP_0

DDR_COMP_1

DDR_COMP_2

3 of 20

AF28

AF29

AE28

AE29

T28

T29

V28

V29

AL37

AL35

AL36

AL34

AG36

AG35

AF34

AG37

AE35

AF35

AE37

AC29

AE36

AB29

AG34

AC28

AB28

AK35

AJ35

AK34

AJ34

AJ37

AJ36

W29

Y28

W28

H24

G24

C23

D23

G30

H30

L30

N30

AL31

AL30

AU31

AU30

BC31

BC30

BH31

BH30

Y29

AE34

BU31

BN28

BN27

BN29

DDR_RCOMP0

DDR_RCOMP1 DDR_RCOMP2

-M_B_DDRCLK0_1200M

M_B_DDRCLK0_1200M

M_B_CKE0

-M_B_CS0

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7 M_B_A8

M_B_A9 M_B_A10

M_B_A11 M_B_A12

M_B_A13

M_B_A14

M_B_A15

M_B_A16

R0501 1/20W_121_1%_0201

R0503 1/20W_100_1%_0201

M_B_ODT0

-M_A_DQS2

M_A_DQS2

-M_A_DQS3

M_A_DQS3

-M_A_DQS6

M_A_DQS6

-M_A_DQS7

M_A_DQS7

-M_B_DQS2

M_B_DQS2

-M_B_DQS3

M_B_DQS3

-M_B_DQS6

M_B_DQS6

-M_B_DQS7

M_B_DQS7

-M_B_ALERT

M_B_PARITY

1 2

R0502 1/20W_80.6_1%_0201

1 2

M_B_BS0

M_B_BS1

M_B_BG0

M_B_BG1

-M_B_ACT

-M_B_ALERT 35,36

M_B_PARITY 35,36

-M_B_DDRCLK0_1200M 35,36 M_B_DDRCLK0_1200M 35,36

M_B_CKE0 35,36

-M_B_CS0 35,36

M_B_ODT0 35,36

M_B_BS0 35,36

M_B_BS1 35,36

M_B_BG0 35,36

M_B_BG1 35

-M_B_ACT 35,36

VCC1R2A

12

R0504 1/20W_470_5%_0201

-DRAMRST

-DRAMRST 33,35

M_B_A[16:0] 35,36

-M_A_DQS[7:0] 4,33

M_A_DQS[7:0] 4,33

-M_B_DQS[7:0] 4,35

M_B_DQS[7:0] 4,35

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (3/16): DDR (2/2)

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

5 125

of

0.1

5

www.teknisi-indonesia.com

4

3

2

1

D D

C C

B B

TABLE : GT3e RCOMP Resistor

CPU SKU

Pin A14 Reserved

Pin B14

TABLE : Fu nctional Strap

ITP_PMODE (DFX Test Mode)

HIGH

LOW

TABLE : Fu nctional Strap

GPP_E6 (JTAG ODT Disable)

HIGH

LOW

TABLE : Fu nctional Strap

GPP_H2/CNV_BT_I2S_SDO (eSPI Flash Sharing Mode)

HIGH

LOW

U43e

OPCE_RCOMP

OPC_RCOMP

DFX Test Mode Disabled (Default)

DFX Test Mod e Enabled

Enabl ed

Disabled

Slave Attached Flash Sharing (SAFS) Enabled

Master Attached Flash Sharing (MAFS) Enabled (Default)

U42

Reserved

-PROCHOT86,87,102,108

-WWAN_DISABLE67 -XDP_PRDY 19

-TBT_PLUG_EVENT55

PECI

-PROCHOT

VCCSTG

R0603

1/20W_1K_5%_0201

1 2

R0601 1/20W_499_1%_0201

R0602 1/20W_0_5%_0201

12

1 2

R0606 1/20W_49.9_1%_0201

1 2

R0607 1/20W_49.9_1%_0201

1 2

R0608 1/20W_49.9_1%_0201@

1 2

R0609 1/20W_49.9_1%_0201@

VCCST VCCST

R0605

1/20W_1K_5%_0201

1 2

-PROCHOT_CPU

-THRMTRIP

-WWAN_DISABLE_R

PROC_POPIRCOMP PCH_OPIRCOMP

OPCE_RCOMP OPC_RCOMP

1 2

R0604

1/20W_1K_5%_0201

?

AA4

-CATERR

AR1

Y4

BJ1

U1

U2

U3

U4

CE9

CN3

CB34

CC35

BP27

BW25

L5

N5

@

UCPU1D

CATERR#

PECI

PROCHOT#

THRMTRIP#

PROC_TRST#

BPM#_0

BPM#_1

BPM#_2

BPM#_3

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

GPP_B3/CPU_GP2

GPP_B4/CPU_GP3

PROC_POPIRCOMP

PCH_OPIRCOMP

RSVD35

RSVD36

WHISKEYLAKE-U_BGA1528

4 of 20

PCH_TRST#

PCH_JTAGX

PROC_PREQ#

PROC_PRDY#

PROC_TCK

PROC_TDI

PROC_TDO

PROC_TMS

PCH_TCK

PCH_TDI

PCH_TDO

PCH_TMS

PCH_TCK_R

R0610 1/20W_51_5%_0201

1 2

PROC_TCK

PROC_TDI

PROC_TDO PROC_TMS

PROC_TRST

T6

U6

Y5

T5

AB6

W6

U5

W5

P5

Y6

P6

W2

W1

1 2

R0611 1/20W_0_5%_0201DCI@

1 2

R0612 1/20W_0_5%_0201DCI@

1 2

R0613 1/20W_0_5%_0201DCI@

1 2

R0614 1/20W_0_5%_0201DCI@

1 2

R0615 1/20W_0_5%_0201DCI@

1 2

R0616 1/16W_0_5%_0402@

-XDP_PREQ

-XDP_PRDY

XDP_TCK0

XDP_TDI

XDP_TDO XDP_TMS

-XDP_TRST

XDP_TCK0 19

XDP_TDI 19PECI86

XDP_TDO 19

XDP_TMS 19

-XDP_TRST 19

PCH_TCK 19

-XDP_PREQ 19

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (4/16): MISC/JTAG

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

6 125

1

of

0.1

3

www.teknisi-indonesia.com

GPP_C5

4

VCC3_SUS

R0719

1/20W_1K_5%_0201

1 2

@

12

R0720

@

1/20W_20K_5%_0201

5

SPI_IO2

SPI_IO3

SPI_MOSI_IO0

D D

1 2

R0721 1/20W_100K_5%_0201

1 2

R0722 1/20W_100K_5%_0201

1 2

R0723 1/20W_100K_5%_0201

VCC3_SUS_SPI

GPP_C2

12

R0718

@

1/20W_20K_5%_0201

2

1

GPP_C2

PCHHOT

LPC_AD0 LPC_AD1

LPC_AD2 LPC_AD3

LPCCLK_0 LPCCLK_1

VCC3_SUS

R0711

1 2

GPP_C5

1/20W_1K_5%_0201

R0707

1 2

1/20W_499_1%_0201

1 2

R0702 1/20W_22_5%_0201EMC@

1 2

R0701 1/20W_0_5%_0201@

22PC_25VC_JC_NPOC_0201

VCC3B

12

R0703 1/20W_8.2K_5%_0201

R0709

R0710

1 2

1/20W_499_1%_0201

C0702

RF_NS@

1

2

R0708

1 2

1/20W_4.7K_5%_0201

LPC_AD[3:0] 85,93

-LPC_FRAME 85,93

-SUS_STAT 85,93

LPCCLK_EC_24M 85

LPCCLK_DEBUG_24M 93

1

C0701 22PC_25VC_JC_NPOC_0201

RF@

2

1 2

1/20W_4.7K_5%_0201

DCI Use

SMB_CLK

SMB_DATA

SML0_CLK

SML0_DATA

EC_SCL2

EC_SDA2

PCHHOT

R0717 1/20W_4.7K_5%_0201

DCI@

1 2

SMB_CLK 93 SMB_DATA 93

SML0_CLK 73 SML0_DATA 73

EC_SCL2 86 EC_SDA2 86

-CLKRUN 85,93

VCC3_SUS

VCC3B

R0712,R0713,R0714,R0715,R0 716

EVT FVT SIT SVT

Resistor

R-short

SPI_CLK21,98

C C

SPI_MISO_IO121,98 SPI_MOSI_IO021,98

SPI_IO221 SPI_IO321

B B

V V

V

1 2

R0712 0_0201_SP

1 2

R0713 0_0201_SP

1 2

R0714 0_0201_SP

1 2

R0715 0_0201_SP

1 2

R0716 0_0201_SP

R0712 R0713

R0714 R0715

R0716

CL_CLK_WLAN66

CL_DATA_WLAN66

12

R0704 1/20W_8.2K_5%_0201

?

UCPU1E

CH37

R0712 R0713

R0714

R0715

-SPI_CS021

-SPI_CS298

-NFC_DTCT89

-CL_RST_WLAN66

-KBRC85

IRQSER85,93

R0716

CL_CLK_WLAN

CL_DATA_WLAN

-CL_RST_WLAN

R0705

1/20W_1K_5%_0201

1 2

@

SPI0_CLK

CF37

SPI0_MISO

CF36

SPI0_MOSI

CF34

SPI0_IO2

CG34

SPI0_IO3

CG36

SPI0_CS0#

CG35

SPI0_CS1#

CH34

SPI0_CS2#

CF20

GPP_D1/SPI1_CLK/BK1/SBK1

CG22

GPP_D2/SPI1_MISO_IO1/BK2/SBK2

CF22

GPP_D3/SPI1_MOSI_IO0/BK3/SBK3

CG23

GPP_D21/SPI1_IO2

CH23

GPP_D22/SPI1_IO3

CG20

GPP_D0/SPI1_CS0#/BK0/SBK0

CH7

CL_CLK

CH8

CL_DATA

CH9

CL_RST#

BV29

GPP_A0/RCIN#/TIME_SYNC1

BV28

GPP_A6/SERIRQ

WHISKEYLAKE-U_BGA1528

@

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1

GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

5 of 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A8/CLKRUN#

CK14

CH15

CJ15

CH14

CF15

CG15

CN15

CM15

CC34

CA29

BY29

BY27

BV27

CA28

CA27

BV32

BV30

BY30

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (5/16): ESPI/SPI/SMBUS/C-LINK

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

7 125

of

0.1

1 2

www.teknisi-indonesia.com

12

R0807 1/20W_1K_5%_0201

12

R0808 1/20W_20K_5%_0201

1

VCC3_SUS

12

R0809

@

1/20W_20K_5%_0201

12

R0810

@

1/20W_20K_5%_0201

3

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D11/ISH_SPI_MISO/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_H10/I2C5_SDA/ISH_I2C2_SDA

GPP_H11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#

6 of 20

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1

GPP_A20/ISH_GP2

GPP_A21/ISH_GP3

GPP_A22/ISH_GP4

GPP_A23/ISH_GP5

CN22

CR22

CM22

CP22

CK22

CH20

CH22

CJ22

CJ27

CJ29

CM24

CN23

CM23

CR24

CG12

CH12

CF12

CG14

BW35

BW34

CA37

CA36

CA35

CA34

BW37

R0806

1 2

1/20W_10K_5%_0201

GPP_B18

GPP_B22

R0801

1/20W_100K_5%_0201

4

-IR_CAM_DTCT

1 2

@

1 2

R0802 1/20W_10K_5%_0201

-MIC_HW_EN

1 2

VCC3_SUS

1 2

R0804 1/20W_1K_5%_0201

R0803 1/20W_10K_5%_0201

@

GPP_B17

R0805 1/20W_0_5%_0201

?

UCPU1F

CC27

GPP_B15/GSPI0_CS0#

CC32

GPP_A7/PIRQA#/GSPI0_CS1#

CE28

GPP_B16/GSPI0_CLK

CE27

GPP_B17/GSPI0_MISO

CE29

GPP_B18/GSPI0_MOSI

CA31

GPP_B19/GSPI1_CS0#

CA32

GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#

CC29

GPP_B20/GSPI1_CLK

CC30

GPP_B21/GSPI1_MISO

CA30

GPP_B22/GSPI1_MOSI

CK20

GPP_F5/CNV_BRI_RSP

CG19

GPP_F6/CNV_RGI_DT

CJ20

GPP_F4/CNV_BRI_DT

CH19

GPP_F7/CNV_RGI_RSP

CR12

GPP_C20/UART2_RXD

CP12

GPP_C21/UART2_TXD

CN12

GPP_C22/UART2_RTS#

CM12

GPP_C23/UART2_CTS#

CM11

GPP_C16/I2C0_SDA

CN11

GPP_C17/I2C0_SCL

CK12

GPP_C18/I2C1_SDA

CJ12

GPP_C19/I2C1_SCL

CF27

GPP_H4/I2C2_SDA

CF29

GPP_H5/I2C2_SCL

CH27

GPP_H6/I2C3_SDA

CH28

GPP_H7/I2C3_SCL

CJ30

GPP_H8/I2C4_SDA

CJ31

GPP_H9/I2C4_SCL

WHISKEYLAKE-U_BGA1528

@

TABLE : Fu nctional Strap

GPP_B14/SPKR (Top Swap Override)

Enable "Top Swap" Mode

HIGH

LOW

TABLE : Fu nctional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

Enable "No Reboot" Mode

HIGH

LOW

Disable "No Reboot" Mode (Default)

D D

TABLE : Fu nctional Strap

GPP_B23/SML1ALERT# (CPUNSSC Clock Freq uency)

HIGH

19.2MHz (from Internal Divider)

LOW

38.4MHz (Direct form Crystal) (Default)

C C

GPP _C18 IR NARROW: L RGB :H

LCD siza contro l Low:14" JAZZ High:13" SIDESWIPE

B B

5

LOGICDisable "Top Swap" Mode (Default)

NFC_DLREQ89

-TPM_IRQ98

-WWAN_PEWAKE67

BRI_RSP_CNVI66 RGI_DT_CNVI66

BRI_DT_CNVI66 RGI_RSP_CNVI66

EPRIVACY_ON51 TBT_FORCE_PWR55

-EC_SCI85

-EC_WAKE85

I2C0_DATA89 I2C0_CLK89

-IR_CAM_DTCT52

Size CTL51

-INT_MIC_DTCT52

WWAN_CFG067

WWAN_CFG167

-TPM_IRQ

2

VCC3_SUS

R0814

1/20W_100K_5%_0201

GPP_D12

VCC3_SUS

@

GPP_B18 GPP_B22

@

GPP_D12

WWAN_CFG2 67 WWAN_CFG3 67

-FULL_CARD_POWER_OFF 67

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (6/16): LPSS/ISH

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

8 125

1

8 125

0.1

TABLE : Fu nctional Strap

www.teknisi-indonesia.com

HDA_SDO/I2S0_TXD

Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Fla sh Descriptor Security (Default)

D D

5

4

VCC3_SUS

3

2

1

PLACE ON BOTTOM SIDE

1 2

R0904 1/20W_1K_5%_0201

VCC3_SUS

R0903

1/20W_1K_5%_0201

1 2

HDA_SYNC78

HDA_BCLK78

C C

HDA_SDO78

HDA_SDIN078

22PC_25VC_JC_NPOC_0201

DDI_PRIORITY168

PCH_SPKR83

TOP_SWAP_EN87

C0902

NFC_ACTIVE89

EMC@

1

2

R0901 1/20W_33_5%_0201

1 2

R0907 1/20W_33_5%_0201EMC@

1 2

R0902 1/20W_33_5%_0201

1

C0901 22PC_25VC_JC_NPOC_0201

EMC@

2

-CNV_RF_RESET66

CNV_CLKREQ66

D_S_control N_Y_control

1 2

R0913 0_0201_SP

HDA_SYNC_CPU HDA_BCLK_CPU

HDA_SDO_CPU

@

-CNV_RF_RESET

R0905 1/20W_0_5%_0201@

CNV_CLKREQ

1 2

R

@

R0908 1/10W _0_5%_0603

TP0901

Test_Point_20MIL

1

@

TEST PAD BOTTOM SIDE DO NOT MOVE AFTER FIX

1 2

TP0902

Test_Point_20MIL

1

@

NFC_ACTIVE_R

PCH_SPKR

?

UCPU1G

BN34

HDA_SYNC/I2S0_SFRM

BN37

HDA_BCLK/I2S0_SCLK

BN36

HDA_SDO/I2S0_TXD

BN35

HDA_SDI0/I2S0_RXD

BL36

HDA_SDI1/I2S1_RXD/SNDW1_DATA

BL35

HDA_RST#/I2S1_SCLK/SNDW1_CLK

CK23

GPP_D23/I2S_MCLK

BL37

I2S1_SFRM/SNDW2_CLK

BL34

I2S1_TXD/SNDW2_DATA

CJ32

GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#

CH32

GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK

CH29

GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ

CH30

GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO

CP24

GPP_D19/DMIC_CLK0/SNDW4_CLK

CN24

GPP_D20/DMIC_DATA0/SNDW4_DATA

CK25

GPP_D17/DMIC_CLK1/SNDW3_CLK

CJ25

GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35

GPP_B14/SPKR

WHISKEYLAKE-U_BGA1528

@

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

7 of 20

GPP_G0/SD_CMD

GPP_G1/SD3_DATA0

GPP_G2/SD3_DATA1

GPP_G3/SD3_DATA2

GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_1P8_RCOMP

SD_3P3_RCOMP

CH36

CL35

CL36

CM35

CN35

CH35

CK36

CK34

BW36

BY31

CK33

CM34

SD_RCOMP

1 2

R0906 1/20W_200_1%_0201

TBT_RTD3_PWR_EN 55

TBT_FORCE_USB_PWR 55

-TBT_PERST 55

-TBT_PCIE_WAKE 55

-WWAN_ANTENNA 67

-SC_DTCT 72

VCC3_SUS VCC3_SUS

NEC@

YMT@

1 2

1/20W_100K_5%_0201

R0911

1 2

1/20W_100K_5%_0201

R0910

H: DRIFT L:JAZ Z/SI DEW IPE

5

B B

H:N EC L:Y MT

A A

@

1 2

D_S_controlN_Y_control

1/20W_100K_5%_0201

R0912

1 2

1/20W_100K_5%_0201

R0909

R0913

EVT FVT SIT SVT

Resistor

R-short

V V

V

4

V

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (7/16): AUDIO/SDXC

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

9 125

0.1

Descriptor

www.teknisi-indonesia.com

for PCIe

4x1 LaneR eversal

Disabled

4x1 LaneR eversal

Disabled

4x1 LaneR eversal

Enabl ed

R1006

1/20W_10K_5%_0201

NFC_ON 89

SATA1_DEVSLP 64

BDC_ON 66

-SATA_DTCT 64

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

PCI

Device Function

10 125

1

of

PCIe Port Assignment PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 7

PCIE 8

PCIE 9

D D

PCIE 13

PCIE 14

C C

B B

A A

Media Card Controller

Alpine Ridge-DP

(x4)

WWAN

GBE

(x4)

WLAN

(x1)

NVMe SSD

(x1)

5

USB 2.0 Port Assignment

USB2_1

Smart Card

USB2_2

Type-C Port C

USB2_3

Type-A Port (AOU)

USB2_4

Type-A Port (DCI)

TBT Port B

USB2_5

Touch Panel

USB2_6

USB2_7

WWAN Card

USB2_8

RGB / IR Hybrid Camera

USB2_9

Fingerprint Reader

WLAN

USB2_10

USB 3.0 Port Assignment

USB3_1

USB3_2

USB3_3

USB3_4

USB3_5

USB3_6

PCIE5_L0_RXN55

PCIE5_L0_RXP55

PCIE5_L0_TXN55

PCIE5_L0_TXP55

PCIE5_L1_RXN55

PCIE5_L1_RXP55

PCIE5_L1_TXN55

PCIE5_L1_TXP55

PCIE7_RXN67 PCIE7_RXP67

PCIE7_TXN67 PCIE7_TXP67

PCIE8_RXN73 PCIE8_RXP73

PCIE8_TXN73 PCIE8_TXP73

PCIE9_RXN66 PCIE9_RXP66

PCIE9_TXN66 PCIE9_TXP66

PCIE13_L3_RXN64 PCIE13_L3_RXP64

PCIE13_L3_TXN64 PCIE13_L3_TXP64

PCIE13_L2_RXN64 PCIE13_L2_RXP64

PCIE13_L2_TXN64 PCIE13_L2_TXP64

PCIE13_L1_RXN64 PCIE13_L1_RXP64

PCIE13_L1_TXN64 PCIE13_L1_TXP64

PCIE13_L0_SATA1_RXN64 PCIE13_L0_SATA1_RXP64

PCIE13_L0_SATA1_TXN64 PCIE13_L0_SATA1_TXP64

4

Type-C Port C

Type-A Port (AOU)

Type-A Port (Gen2)

4

SATA Port Assignment

SATA 0

SATA 1B

SATA 2

R1007 1/20W_100_1%_0201

1 2

PCIE_RCOMP_P

SATA SSDSATA 1A

PCIE_RCOMP_N

?

UCPU1H

BW9

PCIE5_RXN/USB31_5_RXN

BW8

PCIE5_RXP/USB31_5_RXP

BW4

PCIE5_TXN/USB31_5_TXN

BW3

PCIE5_TXP/USB31_5_TXP

BU6

PCIE6_RXN/USB31_6_RXN

BU5

PCIE6_RXP/USB31_6_RXP

BU4

PCIE6_TXN/USB31_6_TXN

BU3

PCIE6_TXP/USB31_6_TXP

BT7

PCIE7_RXN

BT6

PCIE7_RXP

BU2

PCIE7_TXN

BU1

PCIE7_TXP

BU9

PCIE8_RXN

BU8

PCIE8_RXP

BT4

PCIE8_TXN

BT3

PCIE8_TXP

BP5

PCIE9_RXN

BP6

PCIE9_RXP

BR2

PCIE9_TXN

BR1

PCIE9_TXP

BN6

PCIE10_RXN

BN5

PCIE10_RXP

BR4

PCIE10_TXN

BR3

PCIE10_TXP

BN10

PCIE11_RXN/SATA0_RXN

BN8

PCIE11_RXP/SATA0_RXP

BN4

PCIE11_TXN/SATA0_TXN

BN3

PCIE11_TXP/SATA0_TXP

BL6

PCIE12_RXN/SATA1A_RXN

BL5

PCIE12_RXP/SATA1A_RXP

BN2

PCIE12_TXN/SATA1A_TXN

BN1

PCIE12_TXP/SATA1A_TXP

BK6

PCIE13_RXN

BK5

PCIE13_RXP

BM4

PCIE13_TXN

BM3

PCIE13_TXP

BJ6

PCIE14_RXN

BJ5

PCIE14_RXP

BL2

PCIE14_TXN

BL1

PCIE14_TXP

BG5

PCIE15_RXN/SATA1B_RXN

BG6

PCIE15_RXP/SATA1B_RXP

BL4

PCIE15_TXN/SATA1B_TXN

BL3

PCIE15_TXP/SATA1B_TXP

BE5

PCIE16_RXN/SATA2_RXN

BE6

PCIE16_RXP/SATA2_RXP

BJ4

PCIE16_TXN/SATA2_TXN

BJ3

PCIE16_TXP/SATA2_TXP

CE6

PCIE_RCOMP_N

CE5

PCIE_RCOMP_P

CR28

GPP_H12/M2_SKT2/CFG_0

CP28

GPP_H13/M2_SKT2/CFG_1

CN28

GPP_H14/M2_SKT2/CFG_2

CM28

GPP_H15/M2_SKT2/CFG_3

WHISKEYLAKE-U_BGA1528

@

3

PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN

PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP

PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN

PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP

GPP_E9/USB2_OC0#/GP_BSSB_CLK

GPP_E10/USB2_OC1#/GP_BSSB_DI

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1

GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#/SPI1_CS1#

8 of 20

3

Flexible I/O Configuration

PCIE1_RXN/USB31_1_RXN

PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN

PCIE1_TXP/USB31_1_TXP

PCIE3_RXN/USB31_3_RXN

PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN

PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN

PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN

PCIE4_TXP/USB31_4_TXP

USB2_1N

USB2_1P

USB2_2N

USB2_2P

USB2_3N

USB2_3P

USB2_4N

USB2_4P

USB2_5N

USB2_5P

USB2_6N

USB2_6P

USB2_7N

USB2_7P

USB2_8N

USB2_8P

USB2_9N

USB2_9P

USB2_10N

USB2_10P

USB2_COMP

USB2_VBUSSENSE

GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0

GPP_E5/DEVSLP1

GPP_E6/DEVSLP2

HSIO Port High Speed Signals

ICE Lake PCH-LP Premium - U

Port 1

USB3 1 / PCIE 1

Port 2

USB3 2 / PCIE 2

Port 3

USB3 3 / PCIE 3

Port 4

USB3 4 / PCIE 4

Port 5

USB3 5 / PCIE 5

Port 6

USB3 6 / PCIE 6

Port 7

PCIE 7 (GbE)

Port 8

PCIE 8 (GbE)

Port 9

PCIE 9 (GbE)

Port 10

PCIE 10

Port 11

PCIE 11 / SATA 0

Port 12

PCIE 12 / SATA 1A

Port 13

PCIE 13 (GbE)

Port 14

PCIE 14 (GbE)

Port 15

PCIE 15 / SATA 1B

Port 16

PCIE 16 / SATA 2

CB5

CB6

CA4

CA3

BY8

BY9

CA2

CA1

BY7

BY6

BY4

BY3

BW6

BW5

BW2

BW1

CE3

CE4

CE1

CE2

CG3

CG4

CD3

CD4

CG5

CG6

CC1

CC2

CG8

CG9

CB8

CB9

CH5

CH6

CC3

CC4

USB2_COMP

CC5

USB2_ID

CE8

USB2_ID

USB2_VBU

CC6

CK6

CK5

CK8

CK9

CP8

CR8

CM8

CN8

CM10

CP10

CN7

AR3

RSVD37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

R1001

VCC3_SUS

12

1/20W_10K_5%_0201

2018/01/12

X2

12

1 2

2

PCI

Device Function

0h

X4

R1002 1/20W_10K_5%_0201

R1003 1/20W_113_1%_0201

R1004 1/20W_0_5%_0201

R1005 1/20W_1K_5%_0201

R1008

1/20W_10K_5%_0201

1h

1Ch

2h

3h

4h

5h

1Ch

6h

7h

0h

1h

1Dh

2h

3h

4h

5h

1Dh

6h

7h

1 2

NFC_INT

LC Future Center Secre t Data

Deciphered Date

2

HSIO Configurati on

PCIE 1

USB3 3

USB3 4

PCIE 5*2 L0

PCIE 5*2 L1

PCIE 7

PCIE 8

PCIE 9

PCIE 9 x4 L3 Storage Lane 3

PCIE 9 x4 L2

PCIE 9 x4 L1

PCIE 9 x4 L0 / SATA1

NFC_INT 89

-USB_PORT4_OC2 69

-USB_PORT3_OC3 70

2018/01/12

Device

Media Card Controller

Type-A Port (Gen2)

Type-A Port (AOU)

Alpine Ridge - DP

Storage Lane 2

Storage Lane 1

Storage Lane 0 / SATA

PCIE1_RXN 76

PCIE1_RXP 76 PCIE1_TXN 76

PCIE1_TXP 76

USB3P2_RXN 61 USB3P2_RXP 61

USB3P2_TXN 61 USB3P2_TXP 61

USB3P3_RXN 70

USB3P3_RXP 70 USB3P3_TXN 70

USB3P3_TXP 70

USB3P4_RXN 69

USB3P4_RXP 69 USB3P4_TXN 69

USB3P4_TXP 69

USBP1- 72

USBP1+ 72

USBC_USB2N 63 USBC_USB2P 63

USBP3- 70

USBP3+ 70

USBP4- 69

USBP4+ 69

TBT_USB5N 62 TBT_USB5P 62

USBP6- 51

USBP6+ 51

USBP7- 67

USBP7+ 67

USBP8- 52

USBP8+ 52

USBP9- 72

USBP9+ 72

USB2_10N 66 USB2_10P 66

VCC3_SUS

NFC_ON

Title

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

CS19 T14/T15/P53s

1 2

CPU (8/16): PCIE/USB/SATA

0.1

5

www.teknisi-indonesia.com

4

3

2

1

VCC3_SUSVCC3_SUS

R1113

1 2

GPP_H23 XTAL_FREQ_SELECT

1/20W_4.7K_5%_0201

D D

R1114

1 2

@

1/20W_10K_5%_0201

?

CNV_WR_D0N66

C C

R1101

1 2

B B

CNV_WR_D0P66

CNV_WR_D1N66 CNV_WR_D1P66

CNV_WT_D0N66

CNV_WT_D0P66

CNV_WT_D1N66 CNV_WT_D1P66

CNV_WR_CLKN66 CNV_WR_CLKP66

CNV_WT_CLKN66 CNV_WT_CLKP66

CNV_WT_RCOMP

-WWAN_RESET67

1/20W_150_1%_0201

CNV_WR_D0N CNV_WR_D0P

CNV_WR_D1N CNV_WR_D1P

CNV_WT_D0N CNV_WT_D0P

CNV_WT_D1N CNV_WT_D1P

CNV_WR_CLKN CNV_WR_CLKP

CNV_WT_CLKN CNV_WT_CLKP

CML_ME_DET

A4WP_PRESENT

1 2

1/20W_100K_5%_0201

R1117

UCPU1I

CR30

CNV_WR_D0N

CP30

CNV_WR_D0P

CM30

CNV_WR_D1N

CN30

CNV_WR_D1P

CN32

CNV_WT_D0N

CM32

CNV_WT_D0P

CP33

CNV_WT_D1N

CN33

CNV_WT_D1P

CN31

CNV_WR_CLKN

CP31

CNV_WR_CLKP

CP34

CNV_WT_CLKN

CN34

CNV_WT_CLKP

CP32

CNV_WT_RCOMP_0

CR32

CNV_WT_RCOMP_1

CP20

GPP_F0/CNV_PA_BLANKING

CK19

GPP_F1

CG17

GPP_F2

CR14

GPP_C8/UART0_RXD

CP14

GPP_C9/UART0_TXD

CN14

GPP_C10/UART0_RTS#

CM14

GPP_C11/UART0_CTS#

CJ17

GPP_F8/CNV_MFUART2_RXD

CH17

GPP_F9/CNV_MFUART2_TXD

CF17

GPP_F23/A4WP_PRESENT

WHISKEYLAKE-U_BGA1528

@

GPP_H18/CPU_C10_GATE#

GPP_H19/TIMESYNC_0

GPP_H21 / XTAL_FREQ_SELECT

GPP_D4/IMGCLKOUT0/BK4/SBK4

GPP_H20/IMGCLKOUT_1

GPP_F12/EMMC_DATA0

GPP_F13/EMMC_DATA1

GPP_F14/EMMC_DATA2

GPP_F15/EMMC_DATA3

GPP_F16/EMMC_DATA4

GPP_F17/EMMC_DATA5

GPP_F18/EMMC_DATA6

GPP_F19/EMMC_DATA7

GPP_F20/EMMC_RCLK

GPP_F21/EMMC_CLK

GPP_F11/EMMC_CMD

GPP_F22/EMMC_RESET#

EMMC_RCOMP

9 of 20

GPP_H22

GPP_H23

GPP_F10

GPD7

GPP_F3

CN27

CM27

XTAL_FREQ_SELECT

CF25

CN26

GPP_H23

CM26

CK17

BV35

GPD7

CN20

CG25

CH25

CR20

CM20

CN19

CM19

CN18

CR18

CP18

CM18

CM16

CP16

CR16

CN16

EMMC_RCOMP

CK15

1 2

R1119 1/20W_200_1%_0201

PLANARID1 PLANARID2

PLANARID3

MEMORYID0 MEMORYID1

MEMORYID2 MEMORYID3

MEMORYID4

PLANARID0

-CPU_C10_GATE 15,95,120

CML_ME_DET

-INTRUDER_PCH 13

GPD7

R1115

1 2

@

1/20W_10K_5%_0201

R1116

1 2

@

1/20W_10K_5%_0201

VCC3M

1 2

VCC3_SUS

@

R1120

1 2

@

R1121

1 2

R1118

1/20W_100K_5%_0201

1/20W_4.7K_5%_0201

1/20W_10K_5%_0201

MEMORYID0

MEMORYID1 MEMORYID2

MEMORYID3

MEMORYID4

TABLE: MEMORYID

MEMORYID[4:0]

00h (00000b)

01h (00001b)

02h (00010b)

03h (00011b)

04h (00100b)

05h (00101b)

06h (00110b)

A A

07h (00111b)

08h (01000b)

09h (01001b)

10h (01010b)

U3301, U3302, U3303, U3304, U3501, U3502, U3503,U3504

Vendo r

Micron

Samsung

SK hynix

Samsung

5

Part Number Componen t Qty Channel- 0 Channel-1 Tota l

SA00008F920

SA000090M 00

SA00008PE1 0

SA00008WC10

SA000090T00

SA00009TE00

8Gbit SDP

16Gbit DDP

8Gbit SDP

16Gbit DDP

8Gbit SDP

16Gbit DDP

32Gbit DDP

4pcs

4GB 0GB

8pcs

4GB 8GB

8pcs

8GB 8GB

4pcs

8pcs

8GB 8GB

4pcs

8pcs

4GB 8GB

8pcs

4pcs

16GB 0G B 16GB

8pcs

16GB 16G B 32GB

4

Capacit y

4GB

0GB4G B

4GB4G B 8GB

0GB4G B

4GB

16GB

4GB

16GB

4GB

16GB8GB8GBSA00008AD10

R1106

X76@

R1107

1 2

1/20W_0_5%_0201

X76@

3

R1108

X76@

R1109

R1110

1 2

1/20W_0_5%_0201

1 2

1/20W_0_5%_0201

X76@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

R1102

1/20W_0_5%_0201

1 2

@

LC Future Center Secre t Data

Deciphered Date

2

R1103 1/20W_0_5%_0201

1 2

@

R1104 1/20W_0_5%_0201

1 2

@

2018/01/12

PLANARID3 PLANARID2

PLANARID1 PLANARID0

R1105 1/20W_0_5%_0201

1 2

@

TABLE: PLANARID

PLANARID[3:0]

0h (0000b)

1h (0001b)

2h (0010b)

Fh (1111b)

Title

CPU (9/16): CSI-2/EMMC/CNVI

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

PHASE

EVT

EVT2

FVT

SIT

SVT

11 125

of

0.1

5

www.teknisi-indonesia.com

D D

4

3

2

1

C C

?

UCPU1J

AW2

-PCIE1_CLK_100M76

PCIE1_CLK_100M76

-CLKREQ_PCIE176

-PCIE5_CLK_100M55

PCIE5_CLK_100M55

-CLKREQ_PCIE555

-PCIE13_CLK_100M64

-CLKREQ_PCIE1364

-PCIE7_CLK_100M67

PCIE7_CLK_100M67

-CLKREQ_PCIE767

-PCIE8_CLK_100M73

PCIE8_CLK_100M73

-CLKREQ_PCIE873

-PCIE9_CLK_100M66 PCIE9_CLK_100M66

-CLKREQ_PCIE966

B B

A A

CLKOUT_PCIE_N_0

AY3

CLKOUT_PCIE_P_0

CF32

GPP_B5/SRCCLKREQ0#

BC1

CLKOUT_PCIE_N_1

BC2

CLKOUT_PCIE_P_1

CE32

GPP_B6/SRCCLKREQ1#

BD3

CLKOUT_PCIE_N_2

BC3

CLKOUT_PCIE_P_2

CF30

GPP_B7/SRCCLKREQ2#

BH3

CLKOUT_PCIE_N_3

BH4

CLKOUT_PCIE_P_3

CE31

GPP_B8/SRCCLKREQ3#

BA1

CLKOUT_PCIE_N_4

BA2

CLKOUT_PCIE_P_4

CE30

GPP_B9/SRCCLKREQ4#

BE1

CLKOUT_PCIE_N_5

BE2

CLKOUT_PCIE_P_5

CF31

GPP_B10/SRCCLKREQ5#

WHISKEYLAKE-U_BGA1528

@

10 of 20

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL_IN

XTAL_OUT

CLK_BIASREF

CLKIN_XTAL

SRTCRST#

RTCRST#

RTCX1

RTCX2

R1201 R1202

Resistor

R-short

AU1

AU2

BT32

XTAL24_IN

CK3

R1201 0_0201_SP

XTAL24_OUT

CK2

R1202 0_0201_SP

CLK_BIASREF

CJ1

CNV_REFCLK_R

CM3

BN31

BN32

BR37

BR34

EVT FVT SIT SVT

V V

V

1 2

RTCX1 RTCX2

2

R1208

C1205

1/20W_10K_5%_0201

6.8PC_25VC_C_NPOC_0201

1

1 2

@

V

SUSCLK_32K 66,85

1 2

R1207 1/20W_0_5%_0201

-SRTCRST 20

-RTCRST 17,20

XTAL24_OUT_R_R

1 2

1/20W_60.4_1%_0201

R1204

XTAL24_IN_R

TXC KDS

R1203

1 2

1/20W_10M_5%_0201

TABLE of Y1202

P/NVendor

1TJF090DJ1A000B

12

R1205 1/20W_200K_1%_0201

CNV_REFCLK 66PCIE13_CLK_100M64

1 2

C1201 6.8P_25V_C_NPO_0201

Y1202

32.768KHZ_9PF_9H03280012

1 2

C1204 6.8P_25V_C_NPO_0201

LCFC P/N

SJ10000J9009H03280012 SJ100069400

R1206

1 2

1/20W_0_5%_0201

XTAL24_OUT_R

1

C1202 15P_25V_J_NPO_0201

2

Y1201 24MHZ_12PF_8Y24000034

3

1

4 2

1

C1203 15P_25V_J_NPO_0201

2

5

4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (10/16): CLOCK SIGNALS

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

12 125

of

0.1

5

www.teknisi-indonesia.com

D D

4

3

TABLE of U1301

ON

TI

P/NVendor

NL17SZ17XV5T 2G

SN74LVC1G17DRLR

LCFC P/N

SA00005OU00 SA00005MG00

2

VCC3M

1

U1301

1

NC

-PLTRST

VCC3M

C C

R1307,R1308,R1309,R131 0

EVT FVT SIT SVT

Resistor

VVV V

R-short

B B

@

1 2

R1317 1/20W_10K_5%_0201

@

1 2

R1318 1/20W_10K_5%_0201

@

1 2

R1319 1/20W_10K_5%_0201

CPUCORE_PWRGD

MPWRG

BPWRG

V

-XDP_DBR17,19

-RSMRST19,94

BPWRG86,89, 93,95

CPUCORE_PWRGD108 MPWRG94,95

-PCIE_WAKE55,66,67,76,94

-LANWAKE73 LANPHYPC73

MPWRG

VCC3_SUS

Check list Suggest

TABLE : Fu nctional Strap

INPUT3VSEL (VCCDSW_3P3)

HIGH

3.0V

LOW

3.3V

TABLE : Fu nctional Strap

INTRUDER# (SPI Voltage Configuration)

A A

HIGH

SPI Voltage is 1.8V (Default)

LOW

SPI Voltage is 3.3V

CPUCORE_ON94,108

CPUCORE_ON

1

1/20W_1K_5%_0201

R1305

1 2

1/20W_4.7K_5%_0201

R1313

1/20W_10K_5%_0201

1 2

Q1302

32

Q1302

LSK3541G1ET2L_VMT3

R1306

TP1301Test_Point_20MIL

-SUSWARN

CPU_PWRGD

1

VCCST_PWRGD

1 2

R1307 0_0201_SP

1 2

R1308 0_0201_SP

1 2

R1309 0_0201_SP

1 2

R1310 0_0201_SP

-INTRUDER_PCH11

VCCST

VCC1R05_SUS

12

R1321

@

1/16W_1K_5%_0402

R1314

1 2

1/20W_10K_5%_0201

VCCST_PWRGD_R VCCST_PWRGD

32

Q1301

1

LSK3541G1ET2L_VMT3

1 2

?

BJ35

CN10

BR36

AR2

BJ2

BPWRG_R

CR10

CPUCORE_PWRGD_R

BP31

MPWRG_R

BP30

BV34

-SUSWARN_N

BY32

BU30

BU32

BU34

R1311 0_0201_SP

R1322 1/20W_62_5%_0201

UCPU1K

GPP_B13/PLTRST#

SYS_RESET#

RSMRST#

PROCPWRGD

VCCST_PWRGOOD

SYS_PWROK

PCH_PWROK

DSW_PWROK

GPP_A13/SUSWARN#/SUSPWRDACK

GPP_A15/SUSACK#

WAKE#

GPD2/LAN_WAKE#

GPD11/LANPHYPC

WHISKEYLAKE-U_BGA1528

@

1 2

2

IN A

3

GND

TC7SZ17FE_SON-5

11 of 20

-INTRUDER_PCH_R

5

Vcc

4

OUT

GPP_B12/SLP_S0#

GPD4/SLP_S3#

GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

INPUT3VSEL

-INTRUDER_R

S1301 SPVR310200_4P

3 4

2 1

INPUT3VSEL

SLP_SUS#

SLP_LAN#

VCC3_SUS

@

BJ37

BU36

BU27

BT29

BU29

BT31

BT30

BU37

BU28

BU35

BV36

BR35

CC37

CC36

BT27

R1315

1 2

R1316

1 2

U1301

-INTRUDER

GPP_B11

INPUT3VSEL

1 2

R1312 0_0201_SP

1/20W_4.7K_5%_0201

12

R13011/20W _33_5%_0201

12

R13021/20W _33_5%_0201

RTCVCC

12

1

C1303 1000P_25V_K_X7R_0201

2

@

GPP_B11

2

C1302

1

100P_25V_J_NPO_0201

R1303 1/20W_1M_5%_0201

VCC3_SUS

R1320

1 2

1/20W_100K_5%_0201

2

C1301

1

100P_25V_J_NPO_0201

VCC3M

R1304

1/20W_10K_5%_0201

1 2

@

-PLTRST_FAR 64,66,67,73,85,93,94

-PLTRST_NEAR 55,76,98

-PCH_SLP_S0 17,108,120

-PCH_SLP_S3 17,55,86,94,95

-PCH_SLP_S4 17,86,94,112

-PCH_SLP_S5 17,94

-PCH_SLP_SUS 86,95

-PCH_SLP_LAN 94

-PCH_SLP_WLAN 86

-PCH_SLP_M 17,94

-PWRSW_EC 64,86

AC_PRESENT 86

-BATLOW 55,87

R1311,R1312

Resistor

R-short

V V

SVTSITFVTEVT

V

TABLE : Fu nctional Strap

GPD7 (XTAL Inp ut Mode)

HIGH

XTAL Input is Single Ended

LOW

XTAL is Attached (Default)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (11/16): SYSTEM PM

Size Document Number Re v

Custom

C

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

Date: Sheet o f

1

13 125

0.1

5

www.teknisi-indonesia.com

VCCCPUCORE

1

2

1

2

C1401

C1402

D D

1U_6.3V_M_X5R_0201

2

1

2

1

1U_6.3V_M_X5R_0201

C1403

1U_6.3V_M_X5R_0201

C1405

C1408

C1407

C1404

C1406

1U_6.3V_M_X5R_0201

VCCCPUCORE

1

2

C1409

1

2

1

C1410

1U_6.3V_M_X5R_0201

C1412

C1411

2

1

2

22U_6.3V_M_X5R_0603

@

10U_6.3V_M_X5R_0402

@

VccGT

47uF_08 05

22uF_06 03

10uF_04 02

1uF_0402/ 0201

VccCORE

47uF_08 05

22uF_06 03

10uF_04 02

1uF_0402/ 0201

4

LCFCPDG

4

HW:0/PWR :0

15

HW:2/PWR :24

HW:1/PWR :10

15

11

HW:10/PWR :10

PDGPDG

18

HW:0/PWR :0

9

HW:0/PWR :24

22 HW:0/PWR :10

42

HW:0/PWR :10

3

2

1

VCCGT58

VCCGT59

VCCGT60

VCCGT61

VCCGT64

VCCGT69

VCCGT70

VCCGT71

VCCGT72

VCCGT65

VCCGT66

VCCGT67

VCCGT68

VCCGT73

VCCGT74

VCCGT75

VCCGT76

VCCGT77

VCCGT78

VCCGT79

VCCGT87

VCCGT88

VCCGT89

VCCGT90

VCCGT80

VCCGT81

VCCGT82

VCCGT83

VCCGT84

VCCGT85

VCCGT86

VCCGT95

VCCGT96

VCCGT91

VCCGT92

VCCGT93

VCCGT94

VCCGT98

VCCGT97

VCCGT100

VCCGT101

VCCGT99

VCCGT102

VCCGT104

VCCGT105

VCCGT106

VCCGT103

VCCGT107

VCCGT108

VCCGT109

VCCGT111

VCCGT112

VCCGT110

VCCGT114

VCCGT113

VCCCORE100

VCCGT116

VCCGT117

VCCGT118

VCCCORE101

VCCGFXCORE_IVCCCPUCORE

D15

D17

D18

D20

E4

F5

F6

F7

F8

F11

F14

F17

F20

G11

G12

G14

G15

G17

G18

G20

H5

H6

H7

H8

H11

H12

H14

H15

H17

H18

H20

J7

J8

J11

J14

J17

J20

K2

K11

L7

L8

L10

M9

N7

N8

N9

N10

P2

P8

R9

T8

T9

T10

U8

U10

V2

V9

W8

W9

Y8

E3

D2

VCCCPUCORE

VCCGFXCORE_I

12

R1409 1/20W_100_1%_0201

12

R1410 1/20W_100_1%_0201

VCCGT_SENSE

VSSGT_SENSE

3

VCCCPUCORE

VCCGT_SENSE 108 VSSGT_SENSE 108

?

UCPU1L

AN9

VCCCORE5

AN10

VCCCORE1

AN24

VCCCORE2

AN26

VCCCORE3

AN27

VCCCORE4

AP2

VCCCORE6

AP9

VCCCORE9

AP24

VCCCORE7

AP26

VCCCORE8

AR5

VCCCORE13

AR6

VCCCORE14

AR7

VCCCORE15

AR8

VCCCORE16

AR10

VCCCORE10

AR25

VCCCORE11

AR27

VCCCORE12

AT9

VCCCORE19

AT24

VCCCORE17

AT26

VCCCORE18

AU5

VCCCORE24

AU6

VCCCORE25

AU7

VCCCORE26

AU8

VCCCORE27

AU9

VCCCORE28

AU24

VCCCORE20

AU25

VCCCORE21

AU26

VCCCORE22

AU27

VCCCORE23

AV2

VCCCORE30

AV5

VCCCORE32

AV7

VCCCORE33

AV10

VCCCORE29

AV27

VCCCORE31

AW5

VCCCORE39

AW6

VCCCORE40

AW7

VCCCORE41

AW8

VCCCORE42

AW9

VCCCORE43

AW10

VCCCORE34

BB9

RSVD3

BC24

RSVD4

AY9

RSVD1

BB24

RSVD2

WHISKEYLAKE-U_BGA1528

@

VCCCPUCORE

AW24

VCCCORE35

AW25

VCCCORE36

AW26

VCCCORE37

AW27

VCCCORE38

AY24

VCCCORE44

AY26

VCCCORE45

BA5

VCCCORE48

BA7

VCCCORE49

BA8

VCCCORE50

BA25

VCCCORE46

BA27

VCCCORE47

BB2

VCCCORE51

BB26

VCCCORE52

BC5

VCCCORE56

BC6

VCCCORE57

BC7

VCCCORE58

BC9

VCCCORE59

BC10

VCCCORE53

BC26

VCCCORE54

BC27

VCCCORE55

BD5

VCCCORE63

BD8

VCCCORE64

BD10

VCCCORE60

BD25

VCCCORE61

BD27

VCCCORE62

BE9

VCCCORE69

BE24

VCCCORE65

BE25

VCCCORE66

BE26

VCCCORE67

BE27

VCCCORE68

BF2

VCCCORE70

BF9

VCCCORE73

BF24

VCCCORE71

BF26

VCCCORE72

BG27

VCCCORE74

AN6

VCC_SENSE

AN5

VSS_SENSE

AA3

VIDALERT#

AA1

VIDSCK

AA2

VIDSOUT

Y3

RSVD5

VCCSTG1

12 of 20

VCCSTG

BG3

VCCCPUCORE

12

R1406 1/20W_100_1%_0201

1 2

R1407 1/20W_220_5%_0201

12

R1408 1/20W_100_1%_0201

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2

2018/01/12

VCCST

R1404

12

R1403

1/20W_56_5%_0201

1/20W_100_5%_0201

@

LC Future Center Secret Data

Deciphered Date

R1405 1/20W_100_5%_0201

VCC_SENSE VSS_SENSE

-SVID_ALERT

SVID_CLK

SVID_DATA

VCC_SENSE 108

VSS_SENSE 108

-SVID_ALERT 108

SVID_CLK 108

SVID_DATA 108

2018/01/12

Title

CPU (12/16): CPU POWER (1/2)

Size Document Number Re v

Custom

Date: Sheet of

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

14 125

VCCGFXCORE_I

?

UCPU1M

A5

VCCGT8

A6

VCCGT9

A8

VCCGT10

A11

VCCGT1

A12

VCCGT2

C C

B B

A A

5

4

A14

VCCGT3

A15

VCCGT4

A17

VCCGT5

A18

VCCGT6

A20

VCCGT7

AA9

VCCCORE75

AB2

VCCCORE76

AB8

VCCCORE77

AB9

VCCCORE78

AB10

VCCCORE79

AC8

VCCCORE80

AD9

VCCCORE81

AE8

VCCCORE82

AE9

VCCCORE83

AE10

VCCCORE84

AF2

VCCCORE85

AF8

VCCCORE86

AF10

VCCCORE87

AG8

VCCCORE88

AG9

VCCCORE89

AH9

VCCCORE90

AJ8

VCCCORE91

AJ10

VCCCORE92

AK2

VCCCORE93

AK9

VCCCORE94

AL8

VCCCORE95

AL9

VCCCORE96

AL10

VCCCORE97

AM8

VCCCORE98

B3

VCCGT39

B4

VCCGT40

B6

VCCGT41

B8

VCCGT42

B11

VCCGT35

B14

VCCGT36

B17

VCCGT37

B20

VCCGT38

C2

VCCGT49

C3

VCCGT51

C6

VCCGT52

C7

VCCGT53

C8

VCCGT54

C11

VCCGT43

C12

VCCGT44

C14

VCCGT45

C15

VCCGT46

C17

VCCGT47

C18

VCCGT48

C20

VCCGT50

D4

VCCGT62

D7

VCCGT63

D11

VCCGT55

D12

VCCGT56

D14

VCCGT57

Y10

VCCCORE99

WHISKEYLAKE-U_BGA1528

@

13 of 20

VCCGT_SENSE

VSSGT_SENSE

0.1

5

www.teknisi-indonesia.com

4

3

2

1

VCCIO

2

C1501

C1502

1

D D

1UC_6.3VC_KC_X5RC_0402

VCC1R2A

1

2

C1533

C1534

22U_6.3V_M_X5R_0603

C C

B B

-CPU_C10_GATE11,95,120

VCCIO

2

C1503

1

@

1UC_6.3VC_KC_X5RC_0402

1

2

C1538

22U_6.3V_M_X5R_0603

A_ON94,112,120

1

C1505

C1504

1

2

C1506

C1507

22U_6.3V_M_X5R_0603

@

10U_6.3V_M_X5R_0402

@

1UC_6.3VC_KC_X5RC_0402

2

C1536

1

C1540

C1539

1

10U_6.3V_M_X5R_0402

C1542

1

10U_6.3V_M_X5R_0402

1 2

D1501 RB521CM-30T2R_VMN2M-2@

1 2

D1502 RB521CM-30T2R_VMN2M-2@

VCCSA

2

1

R1506

2

1

C1511

2

1

C1513

10U_6.3V_M_X5R_0402

22U_6.3V_M_X5R_0603

VCC1R2A

ON

2

1

C1515

10U_6.3V_M_X5R_0402

2

1

C1512

C1518

10U_6.3V_M_X5R_0402

VCCSFR_OC

2

C1546

1

1UC_6.3VC_KC_X5RC_0402

R1501

Resistor

R-short

1

C1548

@

10U_6.3V_M_X5R_0402

2

10U_6.3V_M_X5R_0402

2

1

C1516

C1514

C1517

10U_6.3V_M_X5R_0402

EVT FVT SIT SVT

V V

V

1 2

R1501 0_1%_0603_LE

A2

B2

C2

D2

@

A1

VOUT1

VIN1

B1

VIN2

VOUT2

C1

PG

CT

D1

GND

ON

U1501 TPS22971YZPT_DSBGA8

2

1

C1510

10U_6.3V_M_X5R_0402

2

C1543

C1544

C1545

1

22U_6.3V_M_X5R_0603

VCC3M

12

@

1/16W_10K_1%_0402

V

VCCSFR_OC

VCCSA

1

2

C1520

2

1

C1519

1U_6.3V_M_X5R_0201

1

C1547

@

0.1UC_6.3VC_KC_X7RC_0402

2

1

2

C1521

2

1

C1523

C1522

1U_6.3V_M_X5R_0201

VCCSFR_OC

VCCSA

2

C1527

1

C1528

1

@

1U_6.3V_M_X5R_0201

?

UCPU1N

AD36

VDDQ1

AH32

VDDQ2

AH36

VDDQ3

AM36

VDDQ4

AN32

VDDQ5

AW32

VDDQ6

AY36

VDDQ7

BE32

VDDQ8

BH36

VDDQ9

R32

VDDQ10

Y36

VDDQ11

BC28

RSVD1

BP11

VCCST1

BP2

VCCST2

BG1

VCCSTG1

BG2

VCCSTG2

BL27

VCCPLL_OC1

BM26

VCCPLL_OC2

BR11

VCCPLL1

BT11

VCCPLL2

WHISKEYLAKE-U_BGA1528

@

2

C1529

1

1U_6.3V_M_X5R_0201

14 of 20

1

2

1

1U_6.3V_M_X5R_0201

VCCSTG

C1526

C1524

1

C1525

@

1U_6.3V_M_X5R_0201

VCC1R2A

VCCST

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCIO9

VCCIO10

VCCIO11

VCCIO12

VCCIO13

VCCIO14

VCCIO15

VCCIO16

VCCSA2

VCCSA1

VCCSA3

VCCSA5

VCCSA6

VCCSA4

VCCSA9

VCCSA7

VCCSA8

VCCSA13

VCCSA14

VCCSA10

VCCSA11

VCCSA12

VCCSA15

VCCSA16

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

VCCST VCCSTG

2

C1531

C1530

1

1UC_6.3VC_KC_X5RC_0402

VCCIO

AK24

AK26

AL24

AL25

AL26

AL27

AM25

AM27

BH24

BH25

BH26

BH27

BJ24

VCCSA

BJ26

BP16

BP18

BG8

BG10

BH9

BJ8

BJ9

BJ10

BK8

BK25

BK27

BL8

BL9

BL10

BL24

BL26

BM24

BN25

VCCIO_SENSE

BP28

VSSIO_SENSE

BP29

BE7

BG7

2

C1532

1

1UC_6.3VC_KC_X5RC_0402

VCCIO

12

R1502 1/20W_100_1%_0201

12

R1504

1/20W_100_1%_0201

12

R1505 1/20W_100_1%_0201

VCCSA

12

R1503 1/20W_100_1%_0201

VSSSA_SENSE VCCSA_SENSE

VSSSA_SENSE 108

VCCSA_SENSE 108

VccSA

47uF_0 805 2

22uF_0 805 0 HW:2/PW R:8

10uF_0 402 13 HW: 5/PWR: 7

1uF_04 02 0 HW:6/P WR:7

VDDQ

47uF_0 805 0

22uF_0 805 1 HW:7/PW R:6

10uF_0 402 9 HW:4/PW R:0

1uF_04 02 4 HW:6/P WR:0

VccIO

47uF_0 805 0

22uF_0 805 0 HW:0/PW R:4

10uF_0 402 6 HW:0/PW R:0

1uF_04 02 4 HW:3/P WR:0

0.1uF_0 20111

PDG LCFC

HW:0/PW R:0

PDG LCFC

HW:0/PW R:0

PDG LCFC

HW:0/PW R:0

PDG LCFCVccPL L

HW:2/PW R:01uF_04 02

HW:0/PW R:0

PDG LCFCVccPLL _OC

HW:1/PW R:01uF_04 02 1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (13/16): CPU POWER (2/2)

Size Document Number Re v

Custom

C

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

15 125

0.1

3

www.teknisi-indonesia.com

VCC3M_PCH

1

2

47UC_6.3VC_MC_X5RC_0805C_H1.25

2

1

C1617

0.1UC_6.3VC_KC_X7RC_0402

C1608

C1609

1

2

0.1U_6.3V_K_X5R_0201

1UC_6.3VC_KC_X5RC_0402

VCCRTCEXT

2

1

2

C1616

C1612

0.1U_6.3V_K_X5R_0201

1

1UC_6.3VC_KC_X5RC_0402

VCCDSW_1P05

4

VCC1R05_SUS_PRIM VCC1R8_SUS_PRIM

2

C1605

1

1UC_6.3VC_KC_X5RC_0402

1

C1602

C1601

2

47UC_6.3VC_MC_X5RC_0805C_H1.25

VCC3_SUS_PRIM RTCVCC

1

2

C1603

C1606

2

47UC_6.3VC_MC_X5RC_0805C_H1.25

C1607

1

1UC_6.3VC_KC_X5RC_0402

5

VCC3M

R1601

1 2

VCC3_SUS

VCC1R8_SUS

D D

VCC1R05_SUS VCCPRIM_CORE

0_1%_0603_LE

R1602

1 2

0_1%_0603_LE

R1603

1 2

0_1%_0603_LE

R1604

1 2

0_1%_0603_LE

R1605

1 2

0_1%_0603_LE

VCC3M_PCH

VCC3_SUS_PRIM

VCC1R8_SUS_PRIM

VCC1R05_SUS_PRIMVCC1R05_SUS

R1601,R1602,R1603,R1604,R1 605

Resistor

V

R-short

V V

SVTSITFVTEVT

V

2

1

VCC1R05_SUS VCC1R05_SUS_XTAL

1 2

L1601 M MZ0603AFY560VT_2P

@

R1606

1 2

0_1%_0603_LE

C C

VCC1R05_SUS VCC1R05_SUS_AMP

1 2

L1602 M MZ0603AFY560VT_2P

@

R1607

1 2

0_1%_0603_LE

R1606,R1607

EVT FVT SIT SVT

Resistor

V

R-short

B B

V V

V

2

1

C1610

@

C1613

@

C1611

1

2

47U_6.3V_M_X5R_0603

1UC_6.3VC_KC_X5RC_0402

VCCPRIM_CORE

1

2

C1614

2

1

47U_6.3V_M_X5R_0603

1UC_6.3VC_KC_X5RC_0402

2

1

VCC1R05_SUS_PRIM

C1615

1UC_6.3VC_KC_X5RC_0402

VCC3_SUS_PRIM

VCCPRIM_CORE

VCC1R05_SUS_AMP

VCC3M_PCH

VCC1R8_SUS_PRIM

VCC3_SUS_PRIM

VCC1R05_SUS_PRIM

VCCDSW_1P05

?

VCC1R05_SUS_PRIM

BP20

BW16

BW18

BW19

BY16

CA14

CC15

CD15

CD16

CP17

CB22

CB23

CC22

CC23

CD22

CD23

CP29

BU15

BU22

BV15

BV16

BV18

BV19

BV20

BV22

BW20

BW22

CA12

CA16

CA18

CA19

CA20

CB12

CB14

CB15

BT24

BU14

BV12

BW12

BW14

BY12

BY14

BV2

BR15

CC12

BR24

BT20

BV23

BT18

BT19

BU18

BU19

BT22

BP22

BV14

UCPU1P

VCCPRIM_1P051

VCCPRIM_1P059

VCCPRIM_1P0510

VCCPRIM_1P0511

VCCPRIM_1P0512

VCCPRIM_1P0514

VCCPRIM_1P81

VCCPRIM_1P84

VCCPRIM_1P85

VCCPRIM_1P88

VCCPRIM_3P34

VCCPRIM_3P35

VCCPRIM_3P36

VCCPRIM_3P37

VCCPRIM_3P38

VCCPRIM_3P39

VCCPRIM_3P310

VCCPRIM_CORE1

VCCPRIM_CORE2

VCCPRIM_CORE3

VCCPRIM_CORE4

VCCPRIM_CORE5

VCCPRIM_CORE6

VCCPRIM_CORE7

VCCPRIM_CORE8

VCCPRIM_CORE9

VCCPRIM_CORE10

VCCPRIM_CORE11

VCCPRIM_CORE12

VCCPRIM_CORE13

VCCPRIM_CORE14

VCCPRIM_CORE15

VCCPRIM_CORE16

VCCPRIM_CORE17

VCCPRIM_CORE18

VCCDSW_1P05

VCCAPLL_1P054

VCCPRIM_MPHY_1P051

VCCPRIM_MPHY_1P053

VCCPRIM_MPHY_1P054

VCCPRIM_MPHY_1P055

VCCPRIM_MPHY_1P056

VCCAMPHYPLL_1P05

VCCAPLL_1P052

VCCDUSB_1P05

VCCDSW_3P31

VCCHDA

VCCSPI

VCCPRIM_1P054

VCCPRIM_1P055

VCCPRIM_1P057

VCCPRIM_1P058

VCCPRIM_1P056

VCCPRIM_1P052

VCCPRIM_MPHY_1P052

WHISKEYLAKE-U_BGA1528

@

16 of 20

VCCPRIM_3P33

VCCRTC

VCCPRIM_1P0513

DCPRTC

VCCPRIM_1P053

VCCAPLL_1P053

VCCA_BCLK_1P05

VCCAPLL_1P051

VCCA_SRC_1P05

VCCA_XTAL_1P05

VCCDPHY_1P242

VCCDPHY_1P244

VCCDPHY_1P241

VCCDPHY_1P243

VCCDPHY_EC_1P24

VCCDSW_3P32

VCCA_19P2_1P05

VCCPRIM_1P82

VCCPRIM_1P83

VCCPRIM_1P86

VCCPRIM_1P87

VCCPRIM_1P89

VCCPRIM_3P32

VCCPRIM_3P31

GPP_B0/CORE_VID0

GPP_B1/CORE_VID1

VCC3_SUS_PRIM

CB16

BR23

BY20

BP24

BR20

BT12

BP14

BR14

BU12

CP5

VCCLDOSRAM_1P24

BY24

CA24

BY23

CA23

CP25

BT23

BR12

CC18

CC19

CD18

CD19

CP23

BW23

BP23

CB36

CB35

VCC1R05_SUS_PRIM

VCCDPHY_1P24

VCC1R8_SUS_PRIM

RTCVCC

VCC1R05_SUS_XTAL

VCC3M_PCH

VCC3_SUS_PRIM

VCCRTCEXT

VCC1R05_SUS_PRIM

VCCDPHY_1P24

2

C1604

4.7U_6.3V_M_X5R_0402

1

near CP25 pin

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (1/16): DDI/TYPE-C

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

16 125

0.1

5

www.teknisi-indonesia.com

4

3

2

1

APS/PETS Interface

VCC3M

VCC3_SUS

D D

-PCH_SLP_S013,108,120

-XDP_DBR13,19

-PWRSWITCH51,62,93,94

-RTCRST12,20

-PCH_SLP_M13,94

-PCH_SLP_S413,86,94,112

-PCH_SLP_S513,94

-PCH_SLP_S313,55,86,94,95

?

1

CR34

TP1701Test_Point_16MIL

C C

1

CN1

TP1704Test_Point_16MIL

1

D1

TP1707Test_Point_16MIL

1

TP1706Test_Point_16MIL

1

A36

TP1705Test_Point_16MIL

B B

UCPU1R

CR34

VSS_1

BT5

VSS_2

BY5

VSS_3

CP35

VSS_4

CM37

VSS_5

CK37

VSS_6

AW1

VSS_7

CM1

VSS_8

BD6

VSS_9

AY4

VSS_10

B34

VSS_11

E35

VSS_12

A4

VSS_13

AE24

VSS_14

AE26

VSS_15

AF25

VSS_16

AG24

VSS_17

AG26

VSS_18

AH24

VSS_19

AH25

VSS_20

B2

VSS_21

B36

VSS_22

C36

VSS_23

C37

VSS_24

CN1

VSS_25

CN2

VSS_26

CN37

VSS_27

CP2

VSS_28

D1

VSS_29

A32

VSS_30

F33

VSS_31

A3

VSS_32

BJ7

VSS_33

CJ36

VSS_34

A36

VSS_35

BK10

VSS_36

CJ4

VSS_37

AB27

VSS_38

BK2

VSS_39

CK1

VSS_40

AB3

VSS_41

BK28

VSS_42

AB30

VSS_43

BK3

VSS_44

CK4

VSS_45

AB33

VSS_46

BK33

VSS_47

CK7

VSS_48

AB36

VSS_49

BK4

VSS_50

CL2

VSS_51

AB4

VSS_52

BK7

VSS_53

CM13

VSS_54

AB7

VSS_55

BL25

VSS_56

CM17

VSS_57

AC10

VSS_58

BL28

VSS_59

CM21

VSS_60

AC27

VSS_61

BL29

VSS_62

CM25

VSS_63

AC30

VSS_64

BL30

VSS_65

CM29

VSS_66

BL31

VSS_67

CM31

VSS_68

AD33

VSS_69

BL32

VSS_70

CM33

VSS_71

AD35

VSS_72

17 of 20

WHISKEYLAKE-U_BGA1528

@

VSS_73

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

BL7

AE25

BM33

CM5

AE27

BM35

CM9

AE30

BM36

CN13

AE7

BM9

CN17

AF27

BN30

CN21

AF3

BN7

CN25

AF30

CN29

AF33

BP15

AF36

AF4

CN5

AF7

BP25

CN9

AG10

BP3

CP1

BP32

CP11

AH27

BP33

CP13

AH28

BP4

CP15

AH29

BP7

CP19

AH30

CP21

AH31

BR19

CP27

AH33

BR25

AH35

CP37

AJ25

BT15

AJ28

BT16

CP9

AJ7

CR2

AK3

CR36

AK33

D21

AK36

BT25

D25

AK4

BT28

AL28

BT33

D5

AL29

1

CP1

TP1703 Test_Point_16MIL

1

CR36

TP1702 Test_Point_16MIL

UCPU1S

BT35

VSS_145

D6

VSS_146

AL32

VSS_147

BT36

VSS_148

D8

VSS_149

AL7

VSS_150

D9

VSS_151

AM10

VSS_152

BU11

VSS_153

E23

VSS_154

AM28

VSS_155

E27

VSS_156

AM33

VSS_157

BU23

VSS_158

E29

VSS_159

AM35

VSS_160

BU24

VSS_161

E31

VSS_162

BU25

VSS_163

E33

VSS_164

AN25

VSS_165

BU7

VSS_166

E9

VSS_167

AN28

VSS_168

BV11

VSS_169

F12

VSS_170

AN29

VSS_171

F15

VSS_172

AN30

VSS_173

F18

VSS_174

AN31

VSS_175

BV3

VSS_176

F2

VSS_177

AN7

VSS_178

BV31

VSS_179

F21

VSS_180

AN8

VSS_181

BV33

VSS_182

F24

VSS_183

BV4

VSS_184

F3

VSS_185

AP3

VSS_186

BW11

VSS_187

F4

VSS_188

AP33

VSS_189

BW15

VSS_190

G21

VSS_191

AP36

VSS_192

G27

VSS_193

AP4

VSS_194

G33

VSS_195

AR28

VSS_196

G35

VSS_197

G36

VSS_198

AT33

VSS_199

BW24

VSS_200

G9

VSS_201

AT35

VSS_202

H21

VSS_203

AT36

VSS_204

BW7

VSS_205

H27

VSS_206

AT4

VSS_207

BY11

VSS_208

AU10

VSS_209

BY15

VSS_210

H9

VSS_211

AU28

VSS_212

BY22

VSS_213

J12

VSS_214

AU29

VSS_215

J15

VSS_216

WHISKEYLAKE-U_BGA1528

@

18 of 20

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

VSS_239

VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247

VSS_248

VSS_249

VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

VSS_255

VSS_256

VSS_257

VSS_258

VSS_259

VSS_260

VSS_261

VSS_262

VSS_263

VSS_264

VSS_265

VSS_266

VSS_267

VSS_268

VSS_269

VSS_270

VSS_271

VSS_272

VSS_273

VSS_274

VSS_275

VSS_276

VSS_277

VSS_278

VSS_279

VSS_280

VSS_281

VSS_282

VSS_283

VSS_284

VSS_285

VSS_286

VSS_287

VSS_288

VSS_289

BY25

J18

AU32

BY28

J21

AV25

BY33

J24

AV28

BY35

J33

AV3

BY36

J36

AV33

J6

AV36

C1

K21

AV4

C21

K22

AV6

C25

K24

AV8

C29

K25

AW28

C33

K27

AW29

C4

K28

AW3

C9

K29

AW30

CA11

K3

AW31

CA15

K30

AY33

CA22

K31

AY35

K32

B12

K4

B15

CA25

K9

B18

CB11

L27

B21

L33

B23

L35

B25

CB18

L36

B27

CB19

L6

B29

CB2

N25

B31

CB20

N27

CB25

?

UCPU1T

N6

VSS_290

B37

VSS_291

CB3

VSS_292

P10

VSS_293

B5

VSS_294

CB33

VSS_295

P3

VSS_296

B7

VSS_297

CB4

VSS_298

P33

VSS_299

B9

VSS_300

CB7

VSS_301

1

C1

Test_Point_16MIL

TP1708

P36

VSS_302

BA10

VSS_303

CC11

VSS_304

P4

VSS_305

BA28

VSS_306

P7

VSS_307

BA3

VSS_308

CC20

VSS_309

R27

VSS_310

BB3

VSS_311

CC25

VSS_312

R28

VSS_313

BB33

VSS_314

CC28

VSS_315

R29

VSS_316

BB36

VSS_317

CC31

VSS_318

R30

VSS_319

BB4

VSS_320

CC7

VSS_321

R31

VSS_322

BC25

VSS_323

CD11

VSS_324

T27

VSS_325

CD12

VSS_326

T30

VSS_327

BC29

VSS_328

CD14

VSS_329

T33

VSS_330

T35

VSS_331

BC32

VSS_332

CD24

VSS_333

T36

VSS_334

CD25

VSS_335

T7

VSS_336

BC8

VSS_337

CE33

VSS_338

U26

VSS_339

BD28

VSS_340

CE35

VSS_341

U7

VSS_342

BD33

VSS_343

CE36

VSS_344

V26

VSS_345

BD35

VSS_346

CE7

VSS_347

V27

VSS_348

BD36

VSS_349

CF11

VSS_350

V3

VSS_351

BE10

VSS_352

CF14

VSS_353

V30

VSS_354

BE28

VSS_355

CF19

VSS_356

V33

VSS_357

BE29

VSS_358

CF2

VSS_359

V36

VSS_360

BE3

VSS_361

19 of 20

WHISKEYLAKE-U_BGA1528

@

VSS_362

VSS_363

VSS_364

VSS_365

VSS_366

VSS_367

VSS_368

VSS_369

VSS_370

VSS_371

VSS_372

VSS_373

VSS_374

VSS_375

VSS_376

VSS_377

VSS_378

VSS_379

VSS_380

VSS_381

VSS_382

VSS_383

VSS_384

VSS_385

VSS_386

VSS_387

VSS_388

VSS_389

VSS_390

VSS_391

VSS_392

VSS_393

VSS_394

VSS_395

VSS_396

VSS_397

VSS_398

VSS_399

VSS_400

VSS_401

VSS_402

VSS_403

VSS_404

VSS_405

VSS_406

VSS_407

VSS_408

VSS_409

VSS_410

VSS_411

VSS_412

VSS_413

VSS_414

VSS_415

VSS_416

VSS_417

VSS_418

VSS_419

VSS_420

VSS_421

VSS_422

VSS_423

VSS_424

VSS_425

VSS_426

VSS_427

VSS_428

VSS_429

VSS_430

VSS_431

VSS_432

VSS_433

CF23

V4

BE30

CF28

W10

BE31

CF3

W27

CF4

W30

BF3

CG33

W7

BF33

CG7

BF36

Y26

BF4

CH31

Y27

BG25

Y30

BG28

CJ11

Y33

CJ14

Y35

BH28

CJ19

Y7

BH29

CJ23

BH32

CJ28

BH33

CJ33

BH35

CJ35

BP19

BR16

BY18

BY19

CC16

BU16

CC14

BR22

BU20

CD20

BT14

BP12

CB24

CC24

J5

U24

BD7

AR4

AU4

AW4

BA6

BC4

BE4

BE8

BA4

BD4

BG4

CJ2

CJ3

AM5

CM4

AC5

AG5

CR6

J1701 FCI_10051922-1810ELF

18

NC1

17

NC2

16

NC3

15

SLP_S0#

14

GND1

13

SYS_RESET#

12

GND2

11

PWRBTN#

10

GND3

9

RTCRST#

8

GND4

7

+V3.3DS

6

SLP_A#

5

SLP_S4#

4

SLP_S5#

3

VccDSW3_3

2

SLP_S3#

1

VccSus3_3

ME@

PEG2

PEG1

20

19

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (15/16): GND

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Drift/Ironhide

Drift/IronhideDrift/Ironhide

Friday, December 28, 2018

1

17 125

of

0.1

2

www.teknisi-indonesia.com

?

UCPU1O

K12

RSVD46

K14

RSVD47

K15

RSVD48

K17

RSVD49

K18

RSVD50

K20

RSVD51

L25

RSVD52

M24

RSVD53

M26

RSVD54

P24

RSVD55

P26

RSVD56

R24

RSVD57

R25

RSVD58

R26

RSVD59

W25

RSVD60

V24

RSVD61

Y25

RSVD62

Y24

RSVD63

RSVD38

RSVD39

RSVD40

RSVD41

RSVD42

RSVD43

RSVD44

RSVD45

RSVD64

RSVD65

AA24

AA26

AB25

AC24

AC25

AC26

AD24

AD26

V25

T25

RSVD84

1 2

3

1

TP1801Test_Point_20MIL

12

R1802 1/20W_1K_5%_0201

@

R1805

1 2

1/20W_49.9_1%_0201

ITP_PMODE_R

CFG9

4

?

CGF_RCOMP

UCPU1Q

T4

CFG_0

R4

CFG_1

T3

CFG_2

R3

CFG_3

J4

CFG_4

M4

CFG_5

J3

CFG_6

M3

CFG_7

R2

CFG_8

N2

CFG_9

R1

CFG_10

N1

CFG_11

J2

CFG_12

L2

CFG_13

J1

CFG_14

L1

CFG_15

L3

CFG_16

N3

CFG_18

L4

CFG_17

N4

CFG_19

AB5

CFG_RCOMP

W4

ITP_PMODE

CG2

RSVD25

CG1

RSVD24

H4

RSVD34

H3

RSVD33

BV24

RSVD22

BV25

RSVD23

G3

RSVD69

G4

RSVD70

BK36

RSVD17

BK35

RSVD16

W3

RSVD35

AM4

RSVD7

AM3

RSVD71

A35

RSVD1

D34

RSVD30

G2

RSVD32

G1

RSVD31

WHISKEYLAKE-U_BGA1528

@

20 of 20

RSVD_TP5

RSVD_TP4

IST_TRIG

RSVD_TP3

RSVD72

RSVD73

RSVD74

RSVD75

RSVD76

RSVD77

RSVD29

RSVD26

RSVD27

RSVD78

RSVD79

RSVD8

RSVD9

RSVD11

RSVD10

RSVD80

RSVD81

RSVD82

RSVD83

VSS_392

RSVD68

RSVD_TP1

RSVD67

RSVD84

RSVD66

RSVD85

SKTOCC#

F37

F34

CP36

CN36

BJ36

BJ34

BK34

TP1

BR18

TP3

BT9

BT8

BP8

BP9

CR4

CP3

CR3

AU3

AT3

AN1

AN2

AN4

AN3

AL2

AL1

AL4

AL3

BP34

TP2

BP36

BP35

TP5

C34

A34

B35

CR35

AH26

AJ27

E1

SKTOCC

R1807 1/20W_0_5%_0201

5

D D

R1803,R1806

Resistor

V V V

R-short

C C

B B

SVTSITFVTEVT

V

CFG319

1 2

R1803 0_0201_SP

12

@

R1801

1/20W_1K_5%_0201

1 2

ITP_PMODE19

R1806 0_0201_SP

CFG3_R

CFG4

12

R1804

1/20W_1K_5%_0201

1

15 of 20

WHISKEYLAKE-U_BGA1528

@

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

CPU (16/16): CFG/RESERVED

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

18 125

of

0.1

5

www.teknisi-indonesia.com

D D

4

3

2

1

VCCSTG

@

R1907

1 2

XDP_TCK06

PCH_TCK6

XDP_TMS6 XDP_TDI6

-XDP_TRST6

XDP_TDO6

C C

B B

-XDP_DBR13,17

ITP_PMODE18

-RSMRST13,94

CFG318

-XDP_PRDY6

-XDP_PREQ6

XDP_TCK0

PCH_TCK

XDP_TMS

XDP_TDI

-XDP_TRST

XDP_TDO

-XDP_DBR

ITP_PMODE

-RSMRST

-XDP_PRDY

-XDP_PREQ

1 2

R1904 1/20W_0_5%_0201@

@

R1909

1 2

1/20W_51_5%_0201

VCC1R05_SUSVCCSTG

@

R1901

R1906

1 2

@

1/20W_1.5K_5%_0201

1/20W_51_5%_0201

R1908

1 2

1/20W_51_5%_0201

VCC3B

R1902

1 2

1/20W_1K_5%_0201

1 2

R1905 1/20W_1K_5%_0201@

VCCSTG VCC1R05_SUS

R1903

1 2

1/20W_100_1%_0201

XDP_TCK1

R1905

2

C1901

0.1U_6.3V_K_X5R_0201

1

@

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

@

JXDP1

26

25

GND2

GND1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

MOLEX_52435-2671

28

27

Logic

Page 6

Page 18

Page 19

Ref Des

R0610

R1801

JXDP1

C1901

R1903

R1902

R1901

R1905

R1904

Merge d

ASM

DCI 2.0

NO_ASM

ASM

NO_ASM

LOGIC

TABLE

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

XDP CONNECTOR

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

19 125

of

0.1

2

www.teknisi-indonesia.com

VCC3SW

D2001 RB520CM-30T2R_VMN2M2

1 2

3

RTCVCC

5

D D

C C

4

1

D2001

D2003

R2001 1/20W_1K_5%_0201

1 2

JRTC1

1

R2001

1

2

3

B B

HIGHS_WS23020-S0291-HF

A A

ME@

GND1

GND2

4

12

RB520CM-30T2R_VMN2M2

2

C2001 1U_6.3V_M_X5R_0201

1

@

1 2

R2002 1/20W_20K_5%_0201

2

1

1 2

R2003 1/20W_20K_5%_0201

2

1

C2002 1U_6.3V_K_X5R_0201

C2003 1U_6.3V_K_X5R_0402

-RTCRST

-SRTCRST

JCMOS SHORT PADS

1 2

@

JME SHORT PADS

1 2

@

-RTCRST 12,17

-SRTCRST 12

5

4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

RTC BATTERY

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Wednesday, January 02, 2019

1

20 125

0.1

5

www.teknisi-indonesia.com

D D

4

3

2

1

C C

VCC3_SUS_SPI

2

1

SPI_IO37

SPI_CLK7,98

SPI_MOSI_IO07,98

B B

A A

SPI_IO3

SPI_CLK

SPI_MOSI_IO0

1 2

12

R21031/20W_51_5%_0201

R21051/20W_51_5%_0201

R21061/20W_51_5%_0201

C2101

0.1U_6.3V_K_X5R_0201

SPI_IO3_0_R

SPI_CLK_0_R

SPI_MOSI_IO0_0_R

R2110 1/20W_33_5%_0201

EMC_NS@

1 2

2

C2103 10P_50V_J_NPO_0402

1

EMC_NS@

VCC3_SUS

D2101 RB520CM-30T2R_VMN2M2

1 2

2

C2102

0.1U_6.3V_K_X5R_0201

1

8

VCC

7

/HOLD(IO3)

6

CLK

5

DI(IO0)

W25Q256JVEIQ_WSON8_8X6

Use SA00008WZ00 Footprint (WSON8) But PN is SA00008J400

U2101

DO(IO1)

/WP(IO2)

/CS

GND

TABLE of TPM (U2101)

MXIC FL 256M MX25L25673GM2I-08G

WINBOND

FL 256M W25Q256JVEIQ WSON

256M GD25B256DYIGR WSONGigaDevi ce

1

SPI_MISO_IO1_0_R

2

3

4

32MB (256Mb) 200MIL SOI C8 MACRONIX MX25L25673GM2I-08G MACRONIX MX25L25673GM2I-10G

32MB (256Mb) 8x6mm WSON8 (Optional) WINBOND W25Q256JVEIQ

SPI_IO2_0_R

LCFC P/NP/NVendor

SA00008J400

SA00008WZ00

SA00009R800

1 2

-SPI_CS0-SPI_CS0_R

12

R21011/20W_0_5%_0201

SPI_MISO_IO1

12

R21021/20W_51_5%_0201

SPI_IO2

R21041/20W_51_5%_0201

-SPI_CS0 7

SPI_MISO_IO1 7,98

SPI_IO2 7

5

4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

SPI FLASH

Size Document Number Re v

Custom

Date: Sheet o f

Date: Sheet

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

21 125

of

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

22 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

23 125

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF L C FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secret Data

Deciphered Date

2

2018/01/12

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

24 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

25 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

26 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

27 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

C

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

28 125

0.1

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

BLANK

Size Document Number Rev

Custom

Date : Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

29 125

0.1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

2

LC Future Center Secret Data

Deciphered Date

2018/01/12

5

www.teknisi-indonesia.com

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/01/12

LC Future Center Secre t Data

Deciphered Date

2

2018/01/12

Title

BLANK

Size Document Number Re v

Custom

Date: Sheet o f

Jazz/Sideswipe

Jazz/SideswipeJazz/Sideswipe

Friday, December 28, 2018

1

30 125

0.1

Lenovo Thinkpad T490s Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual